Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329213446

1

T5

3114

T1

216960

T6

3168

auto[1]

405868

1

T6

664

T4

224

T17

428

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329226118

1

T5

3114

T1

216960

T6

3390

auto[1]

393196

1

T6

442

T4

190

T17

392

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329108598

1

T5

3114

T1

216960

T6

3134

auto[1]

510716

1

T6

698

T4

236

T17

504

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305823228

1

T5

3114

T1

216960

T6

540

auto[1]

23796086

1

T6

3292

T4

1828

T17

684

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195615234

1

T5

2610

T1

122540

T6

3100

auto[1]

134004080

1

T5

504

T1

94420

T6

732

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

178824046

1

T5

2610

T1

122540

T6

96

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

126647356

1

T5

504

T1

94420

T6

192

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

29098

1

T17

14

T18

36

T20

98

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7714

1

T6

36

T18

74

T49

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

16192672

1

T6

2418

T4

1328

T17

424

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7239106

1

T6

206

T4

180

T18

274

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53130

1

T6

88

T4

44

T17

20

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13286

1

T6

8

T9

96

T46

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47386

1

T17

20

T18

12

T102

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1962

1

T6

18

T9

58

T80

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10848

1

T17

120

T18

50

T102

52

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3636

1

T6

72

T80

62

T12

40

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10638

1

T9

140

T46

2

T49

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2956

1

T4

40

T11

18

T12

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19882

1

T9

510

T46

52

T49

56

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4882

1

T12

56

T26

48

T159

42

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

72456

1

T17

60

T18

24

T20

26

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4390

1

T6

8

T9

88

T136

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32550

1

T17

50

T18

70

T102

56

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8362

1

T6

64

T136

66

T11

86

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

28652

1

T6

92

T4

22

T17

32

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6888

1

T6

48

T18

50

T9

164

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

54278

1

T6

54

T4

64

T17

110

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12134

1

T6

80

T9

192

T46

38

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

73178

1

T6

54

T17

54

T18

40

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6094

1

T17

44

T102

20

T9

88

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42874

1

T17

56

T18

150

T20

66

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11278

1

T102

42

T49

40

T136

50

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

44266

1

T6

36

T4

20

T17

40

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11400

1

T4

14

T18

56

T20

44

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

79280

1

T6

262

T4

116

T17

58

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

22636

1

T18

74

T9

228

T46

38