Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 316797814 1 T6 1526 T1 130138 T7 3812
auto[1] 377622 1 T1 2310 T7 638 T16 764


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 316788360 1 T6 1526 T1 130190 T7 4080
auto[1] 387076 1 T1 1794 T7 370 T16 796


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 316714342 1 T6 1526 T1 130117 T7 3666
auto[1] 461094 1 T1 2516 T7 784 T16 994


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 299355362 1 T6 1526 T1 108804 T7 936
auto[1] 17820074 1 T1 215650 T7 3514 T16 1658


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 179400500 1 T6 1394 T1 400796 T7 4424
auto[1] 137774936 1 T6 132 T1 902898 T7 26


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 165253702 1 T6 1394 T1 185504 T7 490
auto[0] auto[0] auto[0] auto[0] auto[1] 133773662 1 T6 132 T1 901548 T7 26
auto[0] auto[0] auto[0] auto[1] auto[0] 26804 1 T1 200 T7 140 T16 20
auto[0] auto[0] auto[0] auto[1] auto[1] 7526 1 T16 30 T108 36 T176 90
auto[0] auto[0] auto[1] auto[0] auto[0] 13582108 1 T1 212564 T7 2888 T16 798
auto[0] auto[0] auto[1] auto[0] auto[1] 3897160 1 T1 660 T16 124 T18 82
auto[0] auto[0] auto[1] auto[1] auto[0] 49058 1 T1 246 T7 32 T16 86
auto[0] auto[0] auto[1] auto[1] auto[1] 11900 1 T1 60 T82 6 T179 14
auto[0] auto[1] auto[0] auto[0] auto[0] 63022 1 T1 48 T7 10 T18 18
auto[0] auto[1] auto[0] auto[0] auto[1] 1346 1 T156 6 T180 2 T67 6
auto[0] auto[1] auto[0] auto[1] auto[0] 10558 1 T1 152 T7 80 T106 82
auto[0] auto[1] auto[0] auto[1] auto[1] 1616 1 T156 44 T180 56 T67 52
auto[0] auto[1] auto[1] auto[0] auto[0] 10490 1 T1 132 T16 26 T71 14
auto[0] auto[1] auto[1] auto[0] auto[1] 2754 1 T179 14 T142 18 T13 66
auto[0] auto[1] auto[1] auto[1] auto[0] 17538 1 T1 64 T138 74 T140 68
auto[0] auto[1] auto[1] auto[1] auto[1] 5098 1 T179 54 T142 58 T15 76
auto[1] auto[0] auto[0] auto[0] auto[0] 48712 1 T1 66 T7 12 T16 30
auto[1] auto[0] auto[0] auto[0] auto[1] 4098 1 T18 8 T176 38 T181 8
auto[1] auto[0] auto[0] auto[1] auto[0] 28512 1 T1 230 T7 132 T16 66
auto[1] auto[0] auto[0] auto[1] auto[1] 7348 1 T18 54 T176 44 T141 66
auto[1] auto[0] auto[1] auto[0] auto[0] 27920 1 T1 218 T7 196 T16 86
auto[1] auto[0] auto[1] auto[0] auto[1] 7226 1 T1 26 T16 42 T106 56
auto[1] auto[0] auto[1] auto[1] auto[0] 50518 1 T1 456 T7 164 T18 96
auto[1] auto[0] auto[1] auto[1] auto[1] 12106 1 T1 122 T179 70 T140 76
auto[1] auto[1] auto[0] auto[0] auto[0] 69084 1 T1 226 T7 46 T16 64
auto[1] auto[1] auto[0] auto[0] auto[1] 6208 1 T16 12 T107 30 T108 40
auto[1] auto[1] auto[0] auto[1] auto[0] 42492 1 T1 70 T16 124 T18 162
auto[1] auto[1] auto[0] auto[1] auto[1] 10672 1 T16 74 T107 54 T108 78
auto[1] auto[1] auto[1] auto[0] auto[0] 40598 1 T1 196 T7 144 T16 132
auto[1] auto[1] auto[1] auto[0] auto[1] 9724 1 T1 196 T18 26 T82 2
auto[1] auto[1] auto[1] auto[1] auto[0] 79384 1 T1 424 T7 90 T16 364
auto[1] auto[1] auto[1] auto[1] auto[1] 16492 1 T1 286 T82 40 T182 46

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