Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319268394

1

T7

3288

T5

113212

T8

2572

auto[1]

459846

1

T7

788

T5

130

T26

274

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319293592

1

T7

3266

T5

113152

T8

2572

auto[1]

434648

1

T7

810

T5

190

T26

284

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319176598

1

T7

3242

T5

113152

T8

2572

auto[1]

551642

1

T7

834

T5

190

T26

368

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295212042

1

T7

584

T5

111690

T8

2572

auto[1]

24516198

1

T7

3492

T5

1652

T26

2972

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171175574

1

T7

3710

T5

112040

T8

2572

auto[1]

148552666

1

T7

366

T5

1302

T26

148

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

152136708

1

T7

252

T5

110304

T8

2572

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

142703504

1

T7

74

T5

1302

T26

46

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

34490

1

T7

18

T5

14

T26

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8332

1

T7

32

T31

8

T2

22

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

18386512

1

T7

2572

T5

1532

T26

2590

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5725464

1

T7

68

T26

68

T31

182

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

58500

1

T7

78

T26

18

T31

154

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13680

1

T7

10

T31

6

T1

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50100

1

T7

30

T32

2

T2

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1638

1

T1

8

T12

20

T141

50

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12902

1

T32

64

T2

66

T74

56

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3306

1

T12

58

T141

58

T13

62

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11794

1

T7

56

T31

28

T32

102

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2830

1

T72

52

T165

30

T33

24

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21760

1

T7

52

T31

48

T32

50

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5078

1

T165

38

T33

72

T12

114

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58994

1

T31

12

T32

32

T1

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5050

1

T7

18

T31

4

T32

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37884

1

T31

130

T32

92

T1

64

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9996

1

T7

62

T31

54

T1

44

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31998

1

T7

30

T26

2

T31

76

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8212

1

T1

8

T2

18

T23

42

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

60796

1

T7

52

T26

82

T31

302

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13472

1

T2

40

T24

62

T33

56

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

76920

1

T7

52

T5

4

T26

16

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6396

1

T1

28

T2

36

T23

54

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53152

1

T7

46

T5

66

T26

56

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12670

1

T1

36

T2

138

T23

74

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50870

1

T7

118

T5

70

T26

68

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11404

1

T7

18

T26

34

T31

54

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

92194

1

T7

354

T5

50

T26

110

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21634

1

T7

84

T31

68

T32

62