Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333530816 1 T8 3334 T9 3490 T10 3494
auto[1] 435222 1 T9 1086 T10 174 T28 156


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333555290 1 T8 3334 T9 3550 T10 3480
auto[1] 410748 1 T9 1026 T10 188 T28 98


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333463528 1 T8 3334 T9 3184 T10 3394
auto[1] 502510 1 T9 1392 T10 274 T28 120


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 320573686 1 T8 3334 T9 1456 T10 830
auto[1] 13392352 1 T9 3120 T10 2838 T30 1364


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 192017396 1 T8 488 T9 2566 T10 1202
auto[1] 141948642 1 T8 2846 T9 2010 T10 2466


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 182188908 1 T8 488 T9 674 T10 392
auto[0] auto[0] auto[0] auto[0] auto[1] 138054430 1 T8 2846 T9 86 T10 266
auto[0] auto[0] auto[0] auto[1] auto[0] 30726 1 T9 68 T10 16 T28 26
auto[0] auto[0] auto[0] auto[1] auto[1] 7690 1 T30 6 T36 40 T1 60
auto[0] auto[0] auto[1] auto[0] auto[0] 9228042 1 T9 616 T10 532 T30 682
auto[0] auto[0] auto[1] auto[0] auto[1] 3768680 1 T9 1686 T10 2126 T30 206
auto[0] auto[0] auto[1] auto[1] auto[0] 55438 1 T9 52 T10 14 T30 162
auto[0] auto[0] auto[1] auto[1] auto[1] 13558 1 T9 2 T36 26 T1 92
auto[0] auto[1] auto[0] auto[0] auto[0] 59152 1 T28 2 T31 16 T4 2596
auto[0] auto[1] auto[0] auto[0] auto[1] 2052 1 T10 16 T36 14 T23 48
auto[0] auto[1] auto[0] auto[1] auto[0] 11564 1 T28 40 T1 220 T119 84
auto[0] auto[1] auto[0] auto[1] auto[1] 3478 1 T36 62 T13 100 T147 50
auto[0] auto[1] auto[1] auto[0] auto[0] 11826 1 T10 14 T30 6 T1 120
auto[0] auto[1] auto[1] auto[0] auto[1] 3108 1 T10 18 T36 4 T1 18
auto[0] auto[1] auto[1] auto[1] auto[0] 19548 1 T30 108 T1 360 T14 94
auto[0] auto[1] auto[1] auto[1] auto[1] 5328 1 T36 56 T1 54 T17 40
auto[1] auto[0] auto[0] auto[0] auto[0] 45850 1 T9 10 T10 8 T28 12
auto[1] auto[0] auto[0] auto[0] auto[1] 4690 1 T9 32 T1 4 T119 42
auto[1] auto[0] auto[0] auto[1] auto[0] 34446 1 T9 74 T10 62 T28 52
auto[1] auto[0] auto[0] auto[1] auto[1] 8722 1 T1 88 T14 58 T149 70
auto[1] auto[0] auto[1] auto[0] auto[0] 34216 1 T9 98 T10 18 T30 10
auto[1] auto[0] auto[1] auto[0] auto[1] 7708 1 T10 8 T30 8 T36 10
auto[1] auto[0] auto[1] auto[1] auto[0] 58600 1 T9 152 T10 38 T30 42
auto[1] auto[0] auto[1] auto[1] auto[1] 13586 1 T36 60 T1 234 T13 82
auto[1] auto[1] auto[0] auto[0] auto[0] 53928 1 T9 126 T10 26 T28 10
auto[1] auto[1] auto[0] auto[0] auto[1] 7032 1 T28 8 T30 2 T36 22
auto[1] auto[1] auto[0] auto[1] auto[0] 49220 1 T9 386 T10 44 T30 48
auto[1] auto[1] auto[0] auto[1] auto[1] 11798 1 T28 38 T30 56 T36 76
auto[1] auto[1] auto[1] auto[0] auto[0] 47558 1 T9 92 T10 38 T30 12
auto[1] auto[1] auto[1] auto[0] auto[1] 13636 1 T9 70 T10 32 T1 54
auto[1] auto[1] auto[1] auto[1] auto[0] 88374 1 T9 218 T30 128 T31 54
auto[1] auto[1] auto[1] auto[1] auto[1] 23146 1 T9 134 T1 276 T27 58

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