Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331115906 1 T6 2978 T1 375726 T7 3868
auto[1] 431766 1 T28 612 T29 138 T3 892


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331156288 1 T6 2978 T1 375726 T7 3732
auto[1] 391384 1 T7 136 T5 8328 T28 530


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331014960 1 T6 2978 T1 375726 T7 3580
auto[1] 532712 1 T7 288 T5 8328 T28 658


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 316374232 1 T6 2978 T1 375726 T7 3002
auto[1] 15173440 1 T7 866 T29 2434 T3 2876


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 176826844 1 T6 2978 T1 375702 T7 1020
auto[1] 154720828 1 T1 24 T7 2848 T18 2788


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 167865024 1 T6 2978 T1 375702 T7 324
auto[0] auto[0] auto[0] auto[0] auto[1] 148179892 1 T1 24 T7 2580 T18 2788
auto[0] auto[0] auto[0] auto[1] auto[0] 30352 1 T28 88 T3 122 T10 272
auto[0] auto[0] auto[0] auto[1] auto[1] 7340 1 T28 36 T10 6 T12 6
auto[0] auto[0] auto[1] auto[0] auto[0] 8360960 1 T7 438 T29 1858 T3 1860
auto[0] auto[0] auto[1] auto[0] auto[1] 6423320 1 T7 238 T29 130 T3 246
auto[0] auto[0] auto[1] auto[1] auto[0] 54746 1 T29 46 T3 34 T10 536
auto[0] auto[0] auto[1] auto[1] auto[1] 13276 1 T3 26 T10 68 T12 48
auto[0] auto[1] auto[0] auto[0] auto[0] 20982 1 T28 20 T3 14 T10 92
auto[0] auto[1] auto[0] auto[0] auto[1] 1112 1 T10 18 T88 2 T94 2
auto[0] auto[1] auto[0] auto[1] auto[0] 13684 1 T28 70 T3 54 T10 190
auto[0] auto[1] auto[0] auto[1] auto[1] 2768 1 T10 68 T88 46 T94 86
auto[0] auto[1] auto[1] auto[0] auto[0] 11052 1 T10 280 T66 2 T11 40
auto[0] auto[1] auto[1] auto[0] auto[1] 2984 1 T29 38 T3 8 T10 4
auto[0] auto[1] auto[1] auto[1] auto[0] 21216 1 T10 130 T66 64 T11 68
auto[0] auto[1] auto[1] auto[1] auto[1] 6252 1 T3 50 T10 68 T66 54
auto[1] auto[0] auto[0] auto[0] auto[0] 59972 1 T7 98 T28 44 T10 396
auto[1] auto[0] auto[0] auto[0] auto[1] 4730 1 T28 66 T29 66 T10 36
auto[1] auto[0] auto[0] auto[1] auto[0] 33592 1 T10 494 T66 46 T11 196
auto[1] auto[0] auto[0] auto[1] auto[1] 8542 1 T28 108 T155 40 T94 74
auto[1] auto[0] auto[1] auto[0] auto[0] 34432 1 T7 54 T29 192 T3 56
auto[1] auto[0] auto[1] auto[0] auto[1] 7706 1 T10 120 T66 8 T12 12
auto[1] auto[0] auto[1] auto[1] auto[0] 58678 1 T29 92 T3 66 T10 552
auto[1] auto[0] auto[1] auto[1] auto[1] 13726 1 T10 64 T12 48 T107 50
auto[1] auto[1] auto[0] auto[0] auto[0] 77652 1 T5 8328 T28 76 T29 112
auto[1] auto[1] auto[0] auto[0] auto[1] 6702 1 T28 54 T10 2 T12 38
auto[1] auto[1] auto[0] auto[1] auto[0] 50110 1 T28 310 T3 120 T10 274
auto[1] auto[1] auto[0] auto[1] auto[1] 11778 1 T10 58 T12 126 T13 138
auto[1] auto[1] auto[1] auto[0] auto[0] 48364 1 T7 106 T29 78 T3 84
auto[1] auto[1] auto[1] auto[0] auto[1] 11022 1 T7 30 T3 26 T10 26
auto[1] auto[1] auto[1] auto[1] auto[0] 86028 1 T3 264 T10 824 T66 138
auto[1] auto[1] auto[1] auto[1] auto[1] 19678 1 T3 156 T10 120 T107 72

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