Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 297750208 1 T7 3012 T8 2696 T9 1922
auto[1] 418018 1 T7 50 T9 418 T20 622


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 297757816 1 T7 2918 T8 2696 T9 1962
auto[1] 410410 1 T7 144 T9 378 T20 250


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 297650062 1 T7 2912 T8 2696 T9 1890
auto[1] 518164 1 T7 150 T9 450 T20 686


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 279042284 1 T7 2260 T8 2696 T9 1760
auto[1] 19125942 1 T7 802 T9 580 T20 3868


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 179909200 1 T7 734 T8 42 T9 2144
auto[1] 118259026 1 T7 2328 T8 2654 T9 196


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 164145536 1 T7 190 T8 42 T9 1382
auto[0] auto[0] auto[0] auto[0] auto[1] 114541624 1 T7 2030 T8 2654 T9 68
auto[0] auto[0] auto[0] auto[1] auto[0] 31486 1 T9 2 T22 24 T109 40
auto[0] auto[0] auto[0] auto[1] auto[1] 8278 1 T9 12 T100 60 T110 108
auto[0] auto[0] auto[1] auto[0] auto[0] 15158884 1 T7 408 T9 264 T20 2882
auto[0] auto[0] auto[1] auto[0] auto[1] 3606044 1 T7 258 T20 224 T109 96
auto[0] auto[0] auto[1] auto[1] auto[0] 51066 1 T9 46 T20 50 T109 178
auto[0] auto[0] auto[1] auto[1] auto[1] 12078 1 T20 76 T109 10 T100 40
auto[0] auto[1] auto[0] auto[0] auto[0] 39638 1 T4 2974 T3 50 T29 16
auto[0] auto[1] auto[0] auto[0] auto[1] 1442 1 T9 12 T82 36 T14 20
auto[0] auto[1] auto[0] auto[1] auto[0] 11544 1 T3 116 T16 138 T17 144
auto[0] auto[1] auto[0] auto[1] auto[1] 1556 1 T9 104 T14 62 T17 62
auto[0] auto[1] auto[1] auto[0] auto[0] 11408 1 T7 26 T109 52 T82 54
auto[0] auto[1] auto[1] auto[0] auto[1] 2196 1 T3 54 T29 14 T91 8
auto[0] auto[1] auto[1] auto[1] auto[0] 22116 1 T109 76 T82 70 T3 122
auto[0] auto[1] auto[1] auto[1] auto[1] 5166 1 T3 68 T29 64 T17 292
auto[1] auto[0] auto[0] auto[0] auto[0] 54016 1 T9 44 T20 10 T22 20
auto[1] auto[0] auto[0] auto[0] auto[1] 3794 1 T7 8 T20 26 T100 16
auto[1] auto[0] auto[0] auto[1] auto[0] 32918 1 T82 126 T110 68 T3 480
auto[1] auto[0] auto[0] auto[1] auto[1] 7716 1 T3 76 T14 78 T16 154
auto[1] auto[0] auto[1] auto[0] auto[0] 28488 1 T9 68 T20 92 T22 16
auto[1] auto[0] auto[1] auto[0] auto[1] 7122 1 T7 24 T20 2 T109 4
auto[1] auto[0] auto[1] auto[1] auto[0] 55192 1 T9 76 T20 248 T22 52
auto[1] auto[0] auto[1] auto[1] auto[1] 13574 1 T20 58 T109 80 T3 66
auto[1] auto[1] auto[0] auto[0] auto[0] 91876 1 T7 24 T9 60 T20 14
auto[1] auto[1] auto[0] auto[0] auto[1] 5994 1 T7 8 T22 8 T110 10
auto[1] auto[1] auto[0] auto[1] auto[0] 51126 1 T9 76 T22 146 T109 236
auto[1] auto[1] auto[0] auto[1] auto[1] 13740 1 T110 44 T3 266 T77 64
auto[1] auto[1] auto[1] auto[0] auto[0] 42052 1 T7 36 T9 24 T20 38
auto[1] auto[1] auto[1] auto[0] auto[1] 10094 1 T20 8 T100 20 T82 156
auto[1] auto[1] auto[1] auto[1] auto[0] 81854 1 T7 50 T9 102 T20 190
auto[1] auto[1] auto[1] auto[1] auto[1] 18608 1 T100 106 T82 70 T110 46

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