Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 292723890 1 T6 3472 T7 2248 T4 1698
auto[1] 398046 1 T7 40 T26 370 T1 1260


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 292725706 1 T6 3472 T7 2214 T4 1432
auto[1] 396230 1 T7 74 T4 266 T26 262


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 292647046 1 T6 3472 T7 2126 T4 1698
auto[1] 474890 1 T7 162 T26 394 T5 3114


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 276982944 1 T6 3472 T7 1474 T4 1698
auto[1] 16138992 1 T7 814 T26 1158 T1 5016


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 156140598 1 T6 3472 T7 794 T4 1698
auto[1] 136981338 1 T7 1494 T25 274 T26 544


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 141904844 1 T6 3472 T7 152 T4 1432
auto[0] auto[0] auto[0] auto[0] auto[1] 134758102 1 T7 1290 T25 274 T26 330
auto[0] auto[0] auto[0] auto[1] auto[0] 28768 1 T26 10 T1 96 T2 242
auto[0] auto[0] auto[0] auto[1] auto[1] 7564 1 T26 26 T2 100 T12 74
auto[0] auto[0] auto[1] auto[0] auto[0] 13675732 1 T7 512 T26 1136 T1 3730
auto[0] auto[0] auto[1] auto[0] auto[1] 2108130 1 T7 172 T1 232 T2 580
auto[0] auto[0] auto[1] auto[1] auto[0] 52204 1 T1 60 T2 664 T11 204
auto[0] auto[0] auto[1] auto[1] auto[1] 13856 1 T1 14 T2 196 T11 78
auto[0] auto[1] auto[0] auto[0] auto[0] 44306 1 T4 266 T2 42 T31 2608
auto[0] auto[1] auto[0] auto[0] auto[1] 1828 1 T13 8 T14 2 T142 54
auto[0] auto[1] auto[0] auto[1] auto[0] 11896 1 T2 96 T12 280 T111 166
auto[0] auto[1] auto[0] auto[1] auto[1] 2998 1 T14 44 T142 68 T146 68
auto[0] auto[1] auto[1] auto[0] auto[0] 10140 1 T1 32 T2 188 T22 34
auto[0] auto[1] auto[1] auto[0] auto[1] 3058 1 T84 20 T173 12 T67 24
auto[0] auto[1] auto[1] auto[1] auto[0] 19494 1 T1 110 T2 194 T11 76
auto[0] auto[1] auto[1] auto[1] auto[1] 4126 1 T84 76 T173 54 T67 58
auto[1] auto[0] auto[0] auto[0] auto[0] 38190 1 T7 8 T26 18 T5 3114
auto[1] auto[0] auto[0] auto[0] auto[1] 3344 1 T1 6 T12 32 T144 10
auto[1] auto[0] auto[0] auto[1] auto[0] 30248 1 T26 114 T1 42 T2 84
auto[1] auto[0] auto[0] auto[1] auto[1] 7868 1 T1 36 T12 160 T144 68
auto[1] auto[0] auto[1] auto[0] auto[0] 29384 1 T7 32 T1 30 T2 130
auto[1] auto[0] auto[1] auto[0] auto[1] 6304 1 T7 8 T1 12 T2 22
auto[1] auto[0] auto[1] auto[1] auto[0] 49086 1 T7 40 T1 176 T2 348
auto[1] auto[0] auto[1] auto[1] auto[1] 12082 1 T1 106 T2 70 T11 72
auto[1] auto[1] auto[0] auto[0] auto[0] 76254 1 T7 8 T26 4 T1 28
auto[1] auto[1] auto[0] auto[0] auto[1] 6584 1 T7 16 T26 16 T2 104
auto[1] auto[1] auto[0] auto[1] auto[0] 47562 1 T26 48 T1 196 T2 156
auto[1] auto[1] auto[0] auto[1] auto[1] 12588 1 T26 172 T2 234 T12 78
auto[1] auto[1] auto[1] auto[0] auto[0] 44788 1 T7 42 T26 22 T1 88
auto[1] auto[1] auto[1] auto[0] auto[1] 12902 1 T7 8 T1 2 T2 194
auto[1] auto[1] auto[1] auto[1] auto[0] 77702 1 T1 376 T2 500 T11 388
auto[1] auto[1] auto[1] auto[1] auto[1] 20004 1 T1 48 T2 524 T11 48

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