Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322360362 1 T6 3188 T1 444628 T7 1662
auto[1] 446458 1 T6 598 T1 4258 T17 782


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322371628 1 T6 3358 T1 444739 T7 1662
auto[1] 435192 1 T6 428 T1 3142 T17 534


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322316082 1 T6 3190 T1 444636 T7 1608
auto[1] 490738 1 T6 596 T1 4172 T7 54


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 304832298 1 T6 3786 T1 443708 T7 54
auto[1] 17974522 1 T1 13450 T7 1608 T17 1598


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 181080214 1 T6 3470 T1 148489 T7 1638
auto[1] 141726606 1 T6 316 T1 296564 T7 24


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 165086394 1 T6 2854 T1 147157 T7 30
auto[0] auto[0] auto[0] auto[0] auto[1] 139414090 1 T6 186 T1 296413 T7 24
auto[0] auto[0] auto[0] auto[1] auto[0] 30892 1 T6 78 T1 240 T17 34
auto[0] auto[0] auto[0] auto[1] auto[1] 8420 1 T6 24 T1 28 T17 10
auto[0] auto[0] auto[1] auto[0] auto[0] 15383384 1 T1 8374 T7 1554 T17 704
auto[0] auto[0] auto[1] auto[0] auto[1] 2194124 1 T1 568 T17 266 T19 1838
auto[0] auto[0] auto[1] auto[1] auto[0] 58006 1 T1 858 T17 18 T19 74
auto[0] auto[0] auto[1] auto[1] auto[1] 13588 1 T1 168 T17 88 T19 30
auto[0] auto[1] auto[0] auto[0] auto[0] 68336 1 T1 4 T17 12 T113 38
auto[0] auto[1] auto[0] auto[0] auto[1] 1638 1 T6 10 T113 8 T2 24
auto[0] auto[1] auto[0] auto[1] auto[0] 13444 1 T1 66 T17 38 T113 214
auto[0] auto[1] auto[0] auto[1] auto[1] 2690 1 T6 38 T113 66 T3 66
auto[0] auto[1] auto[1] auto[0] auto[0] 10704 1 T1 64 T17 36 T19 70
auto[0] auto[1] auto[1] auto[0] auto[1] 3026 1 T1 42 T2 24 T3 38
auto[0] auto[1] auto[1] auto[1] auto[0] 21762 1 T1 140 T17 58 T19 60
auto[0] auto[1] auto[1] auto[1] auto[1] 5584 1 T1 98 T3 64 T147 62
auto[1] auto[0] auto[0] auto[0] auto[0] 28458 1 T6 32 T1 114 T17 8
auto[1] auto[0] auto[0] auto[0] auto[1] 3784 1 T1 22 T17 2 T113 52
auto[1] auto[0] auto[0] auto[1] auto[0] 31720 1 T6 184 T1 338 T19 112
auto[1] auto[0] auto[0] auto[1] auto[1] 6806 1 T1 46 T17 48 T113 82
auto[1] auto[0] auto[1] auto[0] auto[0] 30566 1 T1 350 T7 54 T17 28
auto[1] auto[0] auto[1] auto[0] auto[1] 6828 1 T1 28 T17 10 T19 36
auto[1] auto[0] auto[1] auto[1] auto[0] 59830 1 T1 476 T17 98 T19 78
auto[1] auto[0] auto[1] auto[1] auto[1] 14738 1 T1 70 T17 60 T2 62
auto[1] auto[1] auto[0] auto[0] auto[0] 64250 1 T6 104 T1 136 T17 26
auto[1] auto[1] auto[0] auto[0] auto[1] 6520 1 T6 2 T1 50 T23 34
auto[1] auto[1] auto[0] auto[1] auto[0] 52588 1 T6 218 T1 256 T17 132
auto[1] auto[1] auto[0] auto[1] auto[1] 12268 1 T6 56 T1 72 T2 74
auto[1] auto[1] auto[1] auto[0] auto[0] 48058 1 T1 718 T17 24 T19 54
auto[1] auto[1] auto[1] auto[0] auto[1] 10202 1 T1 94 T17 10 T19 68
auto[1] auto[1] auto[1] auto[1] auto[0] 91822 1 T1 1180 T17 136 T19 150
auto[1] auto[1] auto[1] auto[1] auto[1] 22300 1 T1 222 T17 62 T19 58

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