Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301436800

1

T5

3784

T6

3352

T1

46804

auto[1]

434186

1

T6

590

T15

378

T3

580

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301441038

1

T5

3784

T6

3620

T1

46804

auto[1]

429948

1

T6

322

T15

258

T17

48

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301357562

1

T5

3784

T6

3396

T1

46804

auto[1]

513424

1

T6

546

T15

258

T17

48

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

287672396

1

T5

3784

T6

432

T1

46804

auto[1]

14198590

1

T6

3510

T15

788

T3

2836

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170650312

1

T5

3764

T6

3700

T1

46804

auto[1]

131220674

1

T5

20

T6

242

T14

30

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

159659142

1

T5

3764

T6

256

T1

46804

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

127672884

1

T5

20

T6

16

T14

30

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

29816

1

T6

22

T15

10

T7

192

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8326

1

T3

94

T7

50

T61

52

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

10382596

1

T6

2778

T15

488

T3

2060

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3425158

1

T6

168

T3

156

T7

1472

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54900

1

T6

52

T15

34

T3

132

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13978

1

T3

22

T7

66

T36

46

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49618

1

T7

70

T18

8

T19

4196

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1752

1

T7

16

T36

28

T11

14

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12416

1

T7

176

T9

56

T11

148

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3792

1

T7

120

T11

60

T29

64

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

12322

1

T6

18

T15

18

T3

100

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2408

1

T36

18

T21

28

T10

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23902

1

T6

86

T15

148

T7

166

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4552

1

T36

72

T10

62

T11

92

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

36794

1

T6

16

T15

2

T3

18

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4570

1

T15

56

T7

4

T61

30

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33332

1

T6

122

T15

52

T3

76

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9100

1

T7

68

T61

124

T149

40

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31754

1

T6

44

T15

2

T3

34

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7734

1

T3

16

T7

16

T18

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56848

1

T6

146

T15

54

T3

50

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14106

1

T3

80

T11

246

T12

56

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

83054

1

T15

10

T17

48

T3

22

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7114

1

T7

20

T18

8

T58

38

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48324

1

T15

38

T7

364

T94

46

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12362

1

T7

96

T61

62

T95

58

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

47672

1

T6

42

T15

2

T3

46

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12228

1

T6

14

T3

14

T7

68

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

87822

1

T6

118

T15

42

T3

126

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20610

1

T6

44

T7

316

T9

76