Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

339444236

1

T7

2384

T8

1588

T5

33374

auto[1]

427846

1

T7

72

T30

786

T17

58

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

339403904

1

T7

2418

T8

1588

T5

33374

auto[1]

468178

1

T7

38

T30

540

T17

46

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

339341866

1

T7

2244

T8

1588

T5

33374

auto[1]

530216

1

T7

212

T30

658

T17

46

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322143238

1

T7

290

T8

1588

T5

33374

auto[1]

17728844

1

T7

2166

T30

2444

T38

352

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205361530

1

T7

544

T8

2

T5

33374

auto[1]

134510552

1

T7

1912

T8

1586

T26

4684

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

188418834

1

T7

118

T8

2

T5

33374

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133317186

1

T7

134

T8

1586

T26

4684

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30820

1

T30

6

T17

14

T38

104

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8344

1

T30

102

T2

62

T10

42

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

16272774

1

T7

248

T30

466

T38

132

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1077668

1

T7

1734

T30

1322

T38

64

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53784

1

T7

10

T30

98

T38

20

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13258

1

T2

50

T10

134

T80

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

90386

1

T30

48

T38

2

T2

28

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1406

1

T30

12

T2

16

T80

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

13210

1

T38

52

T10

212

T119

42

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2928

1

T30

68

T80

84

T15

108

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

12036

1

T30

48

T2

116

T10

276

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2548

1

T30

16

T118

18

T2

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21650

1

T2

154

T10

280

T80

60

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5034

1

T30

70

T80

134

T11

106

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

61760

1

T30

30

T38

42

T118

32

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2880

1

T38

8

T2

6

T10

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32034

1

T30

94

T38

212

T2

296

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7500

1

T2

88

T10

70

T120

66

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30658

1

T7

68

T30

30

T38

10

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7616

1

T7

44

T30

16

T2

70

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

55472

1

T7

62

T30

210

T38

58

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13316

1

T2

70

T10

124

T11

232

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

84632

1

T7

38

T30

4

T17

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6168

1

T30

30

T2

58

T10

82

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52106

1

T30

76

T17

44

T38

116

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13044

1

T2

258

T10

216

T80

56

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46540

1

T30

50

T117

6

T118

186

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11144

1

T30

56

T38

6

T2

40

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

84834

1

T30

62

T117

80

T2

790

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20512

1

T38

62

T2

210

T76

50