Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

346942676

1

T7

2898

T8

4564

T9

1852

auto[1]

433500

1

T7

274

T9

126

T25

170

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

346984552

1

T7

2958

T8

4564

T9

1870

auto[1]

391624

1

T7

214

T9

108

T25

178

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

346841020

1

T7

2818

T8

4564

T9

1696

auto[1]

535156

1

T7

354

T9

282

T25

212

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

326341914

1

T7

2958

T8

4564

T9

274

auto[1]

21034262

1

T7

214

T9

1704

T25

376

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

199638098

1

T7

3016

T8

1202

T9

486

auto[1]

147738078

1

T7

156

T8

3362

T9

1492

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

182564170

1

T7

2552

T8

1202

T9

98

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

143441450

1

T7

104

T8

3362

T9

90

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30272

1

T7

12

T25

6

T26

178

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8146

1

T26

6

T1

24

T2

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

16469514

1

T7

150

T9

186

T25

254

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4171032

1

T9

1308

T27

2182

T52

80

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56188

1

T9

14

T25

12

T27

194

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13674

1

T27

52

T40

40

T1

124

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

31038

1

T26

38

T40

2

T19

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1634

1

T3

28

T85

48

T86

24

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12304

1

T26

92

T40

62

T19

42

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3464

1

T3

50

T85

130

T170

76

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11044

1

T27

16

T1

74

T2

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2846

1

T22

8

T3

8

T35

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19476

1

T27

98

T1

152

T2

92

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4768

1

T22

50

T35

60

T15

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

74038

1

T7

46

T9

46

T26

16

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4278

1

T7

6

T26

18

T1

40

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33762

1

T7

42

T26

96

T27

44

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7616

1

T7

46

T26

112

T24

38

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33368

1

T9

22

T25

34

T27

70

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7252

1

T9

54

T27

36

T1

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

55572

1

T9

52

T27

154

T52

66

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14220

1

T1

64

T2

64

T3

132

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

60804

1

T7

26

T25

12

T26

30

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7450

1

T9

40

T27

28

T1

22

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46934

1

T7

124

T25

90

T26

120

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14554

1

T27

68

T1

66

T19

58

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50040

1

T7

14

T9

8

T25

14

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12718

1

T27

44

T1

6

T3

52

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

89574

1

T7

50

T9

60

T25

62

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

22976

1

T27

50

T1

70

T3

210