Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306976452

1

T5

2074

T6

3208

T7

3562

auto[1]

406056

1

T6

510

T7

706

T24

166

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306988994

1

T5

2074

T6

3364

T7

3762

auto[1]

393514

1

T6

354

T7

506

T24

136

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306934356

1

T5

2074

T6

3184

T7

3370

auto[1]

448152

1

T6

534

T7

898

T24

172

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

287827334

1

T5

2074

T6

492

T7

744

auto[1]

19555174

1

T6

3226

T7

3524

T24

1758

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176878162

1

T5

2052

T6

1782

T7

1662

auto[1]

130504346

1

T5

22

T6

1936

T7

2606

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

161426170

1

T5

2052

T6

346

T7

388

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

126102090

1

T5

22

T6

90

T7

118

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

29100

1

T7

20

T24

24

T1

204

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7558

1

T2

226

T3

42

T155

26

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

14897534

1

T6

834

T7

538

T24

1654

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4291154

1

T6

1764

T7

2194

T1

218

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51880

1

T6

120

T7

26

T24

16

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12568

1

T7

14

T1

150

T2

240

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60778

1

T6

30

T1

16

T2

174

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1630

1

T7

28

T2

48

T72

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12714

1

T1

42

T2

406

T22

46

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2992

1

T2

138

T84

54

T185

76

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10866

1

T7

44

T1

20

T2

414

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2950

1

T2

20

T3

8

T113

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19376

1

T1

72

T2

848

T3

132

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4996

1

T2

150

T3

66

T113

56

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

30874

1

T1

32

T2

322

T72

46

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3584

1

T2

152

T72

18

T3

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

30514

1

T1

64

T2

584

T3

336

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6860

1

T2

104

T3

50

T186

56

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27696

1

T6

30

T7

36

T24

36

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6094

1

T6

24

T7

8

T1

18

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52740

1

T6

98

T7

322

T1

104

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12578

1

T6

58

T7

98

T1

114

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50638

1

T6

26

T7

34

T24

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6104

1

T2

258

T72

8

T3

36

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

45020

1

T7

156

T24

78

T1

62

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10708

1

T2

262

T155

172

T73

54

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

47144

1

T6

64

T7

28

T24

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11146

1

T7

146

T2

334

T3

72

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

85118

1

T6

234

T7

70

T24

48

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21334

1

T2

702

T3

352

T114

60