Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335554866

1

T6

2490

T7

3354

T8

1388

auto[1]

423242

1

T6

408

T8

86

T24

414

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335589200

1

T6

2602

T7

3290

T8

1372

auto[1]

388908

1

T6

296

T7

64

T8

102

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335504748

1

T6

2664

T7

3180

T8

1372

auto[1]

473360

1

T6

234

T7

174

T8

102

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316651160

1

T6

2898

T7

424

T8

1474

auto[1]

19326948

1

T7

2930

T24

3186

T20

3116

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

199859696

1

T6

2594

T7

1130

T8

1474

auto[1]

136118412

1

T6

304

T7

2224

T24

28

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

181693138

1

T6

2244

T7

350

T8

1348

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

134634546

1

T6

200

T24

28

T26

38

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30306

1

T6

90

T8

24

T24

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7618

1

T6

60

T20

4

T2

210

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

17584074

1

T7

620

T24

2812

T20

2780

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1370722

1

T7

2202

T20

228

T2

1830

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55806

1

T24

146

T2

512

T66

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12056

1

T2

20

T70

36

T3

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60066

1

T6

14

T4

5212

T17

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1556

1

T2

28

T69

26

T3

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12838

1

T6

56

T17

64

T70

114

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2788

1

T2

94

T60

56

T63

46

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11038

1

T7

8

T24

10

T20

20

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2302

1

T2

102

T158

2

T13

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20480

1

T24

88

T2

122

T67

116

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5414

1

T158

58

T138

80

T159

64

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49974

1

T6

8

T7

74

T17

102

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3802

1

T2

240

T3

12

T79

64

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33878

1

T17

160

T2

170

T66

98

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7642

1

T2

134

T3

94

T13

76

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29102

1

T7

30

T20

24

T2

558

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7170

1

T7

14

T20

10

T2

72

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

55892

1

T2

342

T67

148

T108

78

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13474

1

T70

84

T3

44

T99

166

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

46324

1

T6

22

T8

40

T24

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6318

1

T6

2

T20

10

T2

146

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47728

1

T6

160

T8

62

T24

54

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12638

1

T6

42

T20

52

T2

208

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

44508

1

T7

48

T24

10

T20

36

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10226

1

T7

8

T20

18

T2

96

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

84544

1

T24

120

T2

592

T66

64

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20140

1

T2

82

T67

68

T70

48