Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310341340

1

T8

3346

T6

7798

T9

3760

auto[1]

390028

1

T9

848

T25

630

T26

898

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310353538

1

T8

3346

T6

7798

T9

4040

auto[1]

377830

1

T9

568

T25

450

T4

4812

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310293374

1

T8

3346

T6

7798

T9

3830

auto[1]

437994

1

T9

778

T25

664

T4

4812

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284660186

1

T8

3346

T6

7798

T9

492

auto[1]

26071182

1

T9

4116

T25

2722

T26

4270

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177621686

1

T8

2976

T6

7798

T9

2268

auto[1]

133109682

1

T8

370

T9

2340

T25

760

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

153793036

1

T8

2976

T6

7798

T9

186

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

130574312

1

T8

370

T9

118

T25

292

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

27500

1

T25

18

T2

158

T19

66

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6284

1

T25

24

T2

58

T3

134

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

23298160

1

T9

1216

T25

2080

T26

2986

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2424674

1

T9

2036

T25

248

T26

102

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

48774

1

T9

106

T25

8

T26

232

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13192

1

T25

28

T26

122

T2

154

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51122

1

T5

8412

T2

50

T19

34

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1338

1

T26

46

T3

46

T106

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11824

1

T2

120

T19

106

T3

78

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2934

1

T14

162

T15

66

T47

62

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10794

1

T9

28

T26

6

T2

38

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3510

1

T9

10

T2

20

T3

202

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20308

1

T9

94

T26

58

T2

76

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5612

1

T9

36

T2

162

T3

272

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

30474

1

T26

44

T2

36

T19

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3604

1

T9

20

T25

2

T2

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29406

1

T2

170

T19

56

T3

358

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6688

1

T9

36

T25

48

T2

62

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25762

1

T9

44

T25

22

T26

36

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6174

1

T25

8

T19

4

T3

160

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52906

1

T9

278

T25

134

T26

212

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12592

1

T19

58

T3

130

T14

108

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

60156

1

T9

22

T25

34

T4

4812

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5770

1

T25

10

T2

10

T19

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

44042

1

T9

110

T25

168

T2

276

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11696

1

T25

44

T2

48

T19

36

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

41504

1

T9

58

T25

20

T26

242

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10950

1

T9

22

T25

16

T2

22

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

75918

1

T9

126

T25

118

T26

274

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20352

1

T9

62

T25

40

T2

100