Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 305814384 1 T1 618434 T7 2926 T8 2168
auto[1] 441120 1 T1 6174 T7 846 T18 150


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 305833084 1 T1 618663 T7 3364 T8 2168
auto[1] 422420 1 T1 3882 T7 408 T19 216


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 305738366 1 T1 618488 T7 3104 T8 2168
auto[1] 517138 1 T1 5632 T7 668 T18 222


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 285498344 1 T1 582655 T7 2484 T8 2168
auto[1] 20757160 1 T1 363962 T7 1288 T18 2660


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165817042 1 T1 328191 T7 3140 T8 2168
auto[1] 140438462 1 T1 290861 T7 632 T18 16


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 147389784 1 T1 326482 T7 1936 T8 2168
auto[0] auto[0] auto[0] auto[0] auto[1] 137760644 1 T1 255917 T7 90 T18 16
auto[0] auto[0] auto[0] auto[1] auto[0] 32236 1 T1 448 T7 214 T21 44
auto[0] auto[0] auto[0] auto[1] auto[1] 8724 1 T1 34 T82 8 T86 30
auto[0] auto[0] auto[1] auto[0] auto[0] 17823980 1 T1 10894 T7 384 T18 2438
auto[0] auto[0] auto[1] auto[0] auto[1] 2549228 1 T1 348152 T7 256 T82 246
auto[0] auto[0] auto[1] auto[1] auto[0] 52716 1 T1 528 T7 92 T82 58
auto[0] auto[0] auto[1] auto[1] auto[1] 14312 1 T1 82 T7 28 T82 94
auto[0] auto[1] auto[0] auto[0] auto[0] 47724 1 T1 62 T21 20 T84 80
auto[0] auto[1] auto[0] auto[0] auto[1] 1826 1 T107 20 T12 54 T152 42
auto[0] auto[1] auto[0] auto[1] auto[0] 13936 1 T1 210 T21 54 T84 192
auto[0] auto[1] auto[0] auto[1] auto[1] 3750 1 T107 78 T12 138 T58 110
auto[0] auto[1] auto[1] auto[0] auto[0] 10452 1 T1 58 T7 22 T19 62
auto[0] auto[1] auto[1] auto[0] auto[1] 2694 1 T1 10 T2 44 T107 10
auto[0] auto[1] auto[1] auto[1] auto[0] 20774 1 T1 298 T7 82 T2 378
auto[0] auto[1] auto[1] auto[1] auto[1] 5586 1 T1 116 T2 74 T107 70
auto[1] auto[0] auto[0] auto[0] auto[0] 45192 1 T1 186 T7 72 T19 126
auto[1] auto[0] auto[0] auto[0] auto[1] 3708 1 T1 8 T19 30 T2 84
auto[1] auto[0] auto[0] auto[1] auto[0] 33002 1 T1 512 T82 64 T84 70
auto[1] auto[0] auto[0] auto[1] auto[1] 8008 1 T1 140 T176 62 T58 72
auto[1] auto[0] auto[1] auto[0] auto[0] 29026 1 T1 396 T7 2 T18 72
auto[1] auto[0] auto[1] auto[0] auto[1] 8774 1 T1 54 T7 52 T84 18
auto[1] auto[0] auto[1] auto[1] auto[0] 59318 1 T1 1030 T7 70 T18 150
auto[1] auto[0] auto[1] auto[1] auto[1] 14432 1 T1 178 T7 168 T84 76
auto[1] auto[1] auto[0] auto[0] auto[0] 77372 1 T1 122 T7 14 T19 18
auto[1] auto[1] auto[0] auto[0] auto[1] 6356 1 T1 10 T7 38 T19 32
auto[1] auto[1] auto[0] auto[1] auto[0] 51296 1 T1 786 T7 120 T21 126
auto[1] auto[1] auto[0] auto[1] auto[1] 14786 1 T1 44 T82 46 T86 156
auto[1] auto[1] auto[1] auto[0] auto[0] 45122 1 T1 228 T7 60 T19 104
auto[1] auto[1] auto[1] auto[0] auto[1] 12502 1 T1 170 T82 32 T2 398
auto[1] auto[1] auto[1] auto[1] auto[0] 85112 1 T1 1328 T7 72 T64 44
auto[1] auto[1] auto[1] auto[1] auto[1] 23132 1 T1 440 T82 74 T2 258

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