Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301854586

1

T5

3846

T6

4684

T7

4328

auto[1]

439342

1

T5

1150

T24

524

T26

74

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301834454

1

T5

4222

T6

4684

T7

4328

auto[1]

459474

1

T5

774

T24

562

T26

78

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301758374

1

T5

3808

T6

4684

T7

4328

auto[1]

535554

1

T5

1188

T24

468

T26

184

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

283925560

1

T5

800

T6

4684

T7

4328

auto[1]

18368368

1

T5

4196

T24

3310

T26

2874

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181202980

1

T5

2114

T6

3508

T7

4328

auto[1]

121090948

1

T5

2882

T6

1176

T24

268

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

162778318

1

T5

210

T6

3508

T7

4328

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

120762312

1

T5

196

T6

1176

T24

140

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

36042

1

T5

40

T1

90

T19

184

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7546

1

T5

20

T17

2

T62

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

17767790

1

T5

818

T24

2460

T26

2710

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

208646

1

T5

2258

T24

82

T1

66

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56186

1

T5

66

T24

100

T26

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13420

1

T5

34

T17

22

T19

44

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

70424

1

T20

52

T22

22

T108

60

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1640

1

T5

54

T10

32

T42

14

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12644

1

T108

80

T109

36

T10

88

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2546

1

T5

70

T10

60

T64

66

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11688

1

T24

74

T1

12

T22

20

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2890

1

T5

42

T23

34

T10

16

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21600

1

T24

126

T1

102

T62

94

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4682

1

T11

52

T180

62

T27

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49394

1

T26

32

T1

2

T17

16

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4356

1

T1

12

T17

4

T22

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34030

1

T1

62

T17

48

T62

62

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9162

1

T1

38

T17

42

T62

40

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32664

1

T5

82

T24

30

T26

74

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8202

1

T5

86

T17

2

T23

44

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52102

1

T5

350

T24

76

T1

276

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14284

1

T5

62

T17

56

T93

46

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

85528

1

T5

44

T1

78

T19

92

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7078

1

T1

8

T17

38

T20

30

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52680

1

T5

166

T1

358

T19

332

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11860

1

T1

52

T17

142

T108

96

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

51716

1

T5

52

T24

94

T26

16

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11940

1

T5

4

T24

46

T1

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

90174

1

T5

286

T24

222

T26

62

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20384

1

T5

56

T19

70

T22

46