Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 297387484 1 T1 106707 T6 3178 T7 3274
auto[1] 420864 1 T1 13608 T6 1002 T7 916


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 297405172 1 T1 106744 T6 3174 T7 3346
auto[1] 403176 1 T1 9942 T6 1006 T7 844


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 297298898 1 T1 106704 T6 3264 T7 3184
auto[1] 509450 1 T1 13878 T6 916 T7 1006


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 270514194 1 T1 703431 T6 576 T7 426
auto[1] 27294154 1 T1 365005 T6 3604 T7 3764


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 163460976 1 T1 633753 T6 3376 T7 3900
auto[1] 134347372 1 T1 434682 T6 804 T7 290


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 143427698 1 T1 373909 T6 322 T7 214
auto[0] auto[0] auto[0] auto[0] auto[1] 126751556 1 T1 328933 T6 16 T18 34
auto[0] auto[0] auto[0] auto[1] auto[0] 29746 1 T1 1026 T6 100 T7 4
auto[0] auto[0] auto[0] auto[1] auto[1] 7666 1 T1 210 T2 44 T3 118
auto[0] auto[0] auto[1] auto[0] auto[0] 19438882 1 T1 258360 T6 2074 T7 2592
auto[0] auto[0] auto[1] auto[0] auto[1] 7478288 1 T1 105277 T6 362 T7 202
auto[0] auto[0] auto[1] auto[1] auto[0] 55028 1 T1 1840 T6 66 T7 88
auto[0] auto[0] auto[1] auto[1] auto[1] 13212 1 T1 812 T6 68 T2 184
auto[0] auto[1] auto[0] auto[0] auto[0] 44254 1 T1 42 T6 50 T2 44
auto[0] auto[1] auto[0] auto[0] auto[1] 1382 1 T1 36 T2 44 T135 44
auto[0] auto[1] auto[0] auto[1] auto[0] 11198 1 T1 208 T6 88 T2 86
auto[0] auto[1] auto[0] auto[1] auto[1] 2194 1 T2 66 T39 94 T42 66
auto[0] auto[1] auto[1] auto[0] auto[0] 10466 1 T1 382 T6 66 T7 16
auto[0] auto[1] auto[1] auto[0] auto[1] 2478 1 T1 212 T2 22 T3 18
auto[0] auto[1] auto[1] auto[1] auto[0] 19986 1 T1 634 T6 52 T7 68
auto[0] auto[1] auto[1] auto[1] auto[1] 4864 1 T1 278 T2 136 T3 46
auto[1] auto[0] auto[0] auto[0] auto[0] 50742 1 T1 774 T7 6 T2 64
auto[1] auto[0] auto[0] auto[0] auto[1] 3936 1 T1 104 T2 72 T3 14
auto[1] auto[0] auto[0] auto[1] auto[0] 31282 1 T1 878 T7 78 T2 150
auto[1] auto[0] auto[0] auto[1] auto[1] 8888 1 T1 210 T2 94 T3 210
auto[1] auto[0] auto[1] auto[0] auto[0] 31042 1 T1 1188 T7 26 T2 200
auto[1] auto[0] auto[1] auto[0] auto[1] 8484 1 T1 168 T6 34 T2 254
auto[1] auto[0] auto[1] auto[1] auto[0] 55954 1 T1 1796 T7 136 T2 348
auto[1] auto[0] auto[1] auto[1] auto[1] 12768 1 T1 610 T6 132 T2 352
auto[1] auto[1] auto[0] auto[0] auto[0] 76118 1 T1 652 T7 44 T4 3864
auto[1] auto[1] auto[0] auto[0] auto[1] 6456 1 T1 122 T2 40 T3 42
auto[1] auto[1] auto[0] auto[1] auto[0] 48840 1 T1 1324 T7 80 T2 248
auto[1] auto[1] auto[0] auto[1] auto[1] 12238 1 T1 298 T2 74 T3 194
auto[1] auto[1] auto[1] auto[0] auto[0] 44092 1 T1 1484 T6 226 T7 146
auto[1] auto[1] auto[1] auto[0] auto[1] 11610 1 T1 786 T6 28 T7 28
auto[1] auto[1] auto[1] auto[1] auto[0] 85648 1 T1 2610 T6 332 T7 402
auto[1] auto[1] auto[1] auto[1] auto[1] 21352 1 T1 874 T6 164 T7 60

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%