Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301389758

1

T6

2388

T7

2874

T8

2582

auto[1]

459184

1

T28

88

T29

140

T31

302

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301383896

1

T6

2388

T7

2636

T8

2582

auto[1]

465046

1

T7

238

T27

106

T28

60

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301318382

1

T6

2388

T7

2568

T8

2582

auto[1]

530560

1

T7

306

T27

234

T28

60

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

283877870

1

T6

2388

T7

1746

T8

2582

auto[1]

17971072

1

T7

1128

T27

438

T28

1732

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172117090

1

T6

194

T7

926

T8

2582

auto[1]

129731852

1

T6

2194

T7

1948

T26

524

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

154885388

1

T6

194

T7

250

T8

2582

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

128617234

1

T6

2194

T7

1424

T26

524

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

35524

1

T29

20

T21

52

T23

198

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8808

1

T21

82

T23

68

T12

188

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

16568110

1

T7

420

T27

312

T28

1642

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

984856

1

T7

372

T30

280

T31

86

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62332

1

T28

30

T31

112

T23

134

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13920

1

T22

24

T23

124

T82

28

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

80282

1

T29

22

T48

2

T81

30

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1482

1

T15

20

T16

2

T17

150

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12848

1

T48

46

T12

264

T67

80

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3206

1

T15

58

T16

54

T17

164

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

12940

1

T7

46

T30

140

T81

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3298

1

T7

56

T30

42

T82

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23100

1

T12

242

T15

100

T16

56

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5054

1

T82

50

T12

90

T17

510

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38908

1

T7

38

T27

38

T29

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4186

1

T12

186

T68

20

T17

164

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33572

1

T29

38

T21

62

T23

104

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8080

1

T12

288

T68

42

T17

194

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

36528

1

T7

94

T27

90

T31

30

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9334

1

T7

38

T30

28

T22

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

61336

1

T31

120

T21

56

T23

60

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15780

1

T22

66

T23

78

T12

204

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

75982

1

T7

34

T27

70

T29

20

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6836

1

T12

344

T67

82

T15

42

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52318

1

T29

82

T21

68

T23

140

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13216

1

T12

422

T67

106

T15

46

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50598

1

T7

44

T27

36

T28

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13796

1

T7

58

T30

16

T31

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

87324

1

T28

58

T23

300

T48

144

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

22766

1

T31

70

T23

88

T48

40