Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1010
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T794 /workspace/coverage/default/46.clkmgr_stress_all.3046477577 Jul 04 05:31:56 PM PDT 24 Jul 04 05:32:24 PM PDT 24 5275929367 ps
T795 /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.1175771206 Jul 04 05:29:56 PM PDT 24 Jul 04 05:29:57 PM PDT 24 16439323 ps
T796 /workspace/coverage/default/39.clkmgr_div_intersig_mubi.2207553440 Jul 04 05:31:45 PM PDT 24 Jul 04 05:31:48 PM PDT 24 25461588 ps
T797 /workspace/coverage/default/4.clkmgr_peri.875239233 Jul 04 05:29:31 PM PDT 24 Jul 04 05:29:32 PM PDT 24 27401169 ps
T798 /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3326225796 Jul 04 05:29:59 PM PDT 24 Jul 04 05:30:01 PM PDT 24 28969075 ps
T799 /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2269569454 Jul 04 05:29:54 PM PDT 24 Jul 04 05:29:55 PM PDT 24 68671278 ps
T800 /workspace/coverage/default/38.clkmgr_frequency_timeout.3194168140 Jul 04 05:31:42 PM PDT 24 Jul 04 05:31:52 PM PDT 24 1952894162 ps
T801 /workspace/coverage/default/46.clkmgr_frequency.3317911483 Jul 04 05:31:58 PM PDT 24 Jul 04 05:32:16 PM PDT 24 2238785841 ps
T802 /workspace/coverage/default/49.clkmgr_frequency.1599521145 Jul 04 05:31:58 PM PDT 24 Jul 04 05:32:12 PM PDT 24 1761514880 ps
T803 /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1869697124 Jul 04 05:29:32 PM PDT 24 Jul 04 05:29:34 PM PDT 24 89457550 ps
T804 /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2867131900 Jul 04 05:31:48 PM PDT 24 Jul 04 05:31:50 PM PDT 24 79754476 ps
T805 /workspace/coverage/default/23.clkmgr_regwen.4239049063 Jul 04 05:30:21 PM PDT 24 Jul 04 05:30:24 PM PDT 24 313873782 ps
T806 /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.812895846 Jul 04 05:30:54 PM PDT 24 Jul 04 05:30:57 PM PDT 24 28215888 ps
T807 /workspace/coverage/default/29.clkmgr_alert_test.1055641317 Jul 04 05:30:56 PM PDT 24 Jul 04 05:30:58 PM PDT 24 16810414 ps
T808 /workspace/coverage/default/30.clkmgr_clk_status.1718490043 Jul 04 05:30:55 PM PDT 24 Jul 04 05:30:57 PM PDT 24 14882746 ps
T809 /workspace/coverage/default/22.clkmgr_frequency.3677032185 Jul 04 05:30:26 PM PDT 24 Jul 04 05:30:31 PM PDT 24 1106153442 ps
T810 /workspace/coverage/default/35.clkmgr_peri.1349869248 Jul 04 05:31:38 PM PDT 24 Jul 04 05:31:39 PM PDT 24 18679226 ps
T811 /workspace/coverage/default/12.clkmgr_div_intersig_mubi.699806236 Jul 04 05:29:58 PM PDT 24 Jul 04 05:29:59 PM PDT 24 27762878 ps
T812 /workspace/coverage/default/11.clkmgr_alert_test.972163282 Jul 04 05:29:52 PM PDT 24 Jul 04 05:29:53 PM PDT 24 155490929 ps
T813 /workspace/coverage/default/42.clkmgr_frequency.686182621 Jul 04 05:31:44 PM PDT 24 Jul 04 05:31:49 PM PDT 24 456419828 ps
T814 /workspace/coverage/default/49.clkmgr_stress_all.2169607245 Jul 04 05:31:58 PM PDT 24 Jul 04 05:33:26 PM PDT 24 11604323187 ps
T815 /workspace/coverage/default/11.clkmgr_peri.94523897 Jul 04 05:29:59 PM PDT 24 Jul 04 05:30:01 PM PDT 24 36140865 ps
T816 /workspace/coverage/default/23.clkmgr_frequency_timeout.1792611674 Jul 04 05:30:18 PM PDT 24 Jul 04 05:30:23 PM PDT 24 1122915667 ps
T817 /workspace/coverage/default/42.clkmgr_regwen.1969092453 Jul 04 05:31:47 PM PDT 24 Jul 04 05:31:52 PM PDT 24 407341880 ps
T818 /workspace/coverage/default/19.clkmgr_regwen.257629897 Jul 04 05:30:17 PM PDT 24 Jul 04 05:30:27 PM PDT 24 978500280 ps
T819 /workspace/coverage/default/0.clkmgr_clk_status.487693203 Jul 04 05:29:32 PM PDT 24 Jul 04 05:29:33 PM PDT 24 24929528 ps
T820 /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.1271673138 Jul 04 05:30:33 PM PDT 24 Jul 04 05:33:07 PM PDT 24 8370179324 ps
T821 /workspace/coverage/default/8.clkmgr_div_intersig_mubi.1779339923 Jul 04 05:29:44 PM PDT 24 Jul 04 05:29:46 PM PDT 24 74710728 ps
T822 /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2411367310 Jul 04 05:29:59 PM PDT 24 Jul 04 05:30:00 PM PDT 24 19155291 ps
T823 /workspace/coverage/default/2.clkmgr_smoke.1355632922 Jul 04 05:29:31 PM PDT 24 Jul 04 05:29:32 PM PDT 24 19129555 ps
T824 /workspace/coverage/default/30.clkmgr_extclk.2042994572 Jul 04 05:30:56 PM PDT 24 Jul 04 05:30:58 PM PDT 24 94854431 ps
T825 /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.2483963518 Jul 04 05:31:37 PM PDT 24 Jul 04 05:31:38 PM PDT 24 130967024 ps
T826 /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.3026491983 Jul 04 05:30:31 PM PDT 24 Jul 04 05:39:32 PM PDT 24 53545008526 ps
T827 /workspace/coverage/default/3.clkmgr_extclk.3049648258 Jul 04 05:29:31 PM PDT 24 Jul 04 05:29:33 PM PDT 24 57647283 ps
T828 /workspace/coverage/default/39.clkmgr_stress_all.3415663148 Jul 04 05:31:46 PM PDT 24 Jul 04 05:32:03 PM PDT 24 3348457181 ps
T829 /workspace/coverage/default/42.clkmgr_alert_test.2136412455 Jul 04 05:31:45 PM PDT 24 Jul 04 05:31:48 PM PDT 24 16164056 ps
T830 /workspace/coverage/default/28.clkmgr_peri.597000197 Jul 04 05:30:27 PM PDT 24 Jul 04 05:30:28 PM PDT 24 15454880 ps
T831 /workspace/coverage/default/34.clkmgr_alert_test.3661402493 Jul 04 05:31:44 PM PDT 24 Jul 04 05:31:47 PM PDT 24 19717623 ps
T832 /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.2517001553 Jul 04 05:31:39 PM PDT 24 Jul 04 05:31:40 PM PDT 24 14740266 ps
T833 /workspace/coverage/default/35.clkmgr_frequency.341412398 Jul 04 05:31:40 PM PDT 24 Jul 04 05:31:49 PM PDT 24 1041365019 ps
T834 /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3797155411 Jul 04 05:30:28 PM PDT 24 Jul 04 05:30:29 PM PDT 24 16147439 ps
T835 /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.4155257995 Jul 04 05:30:36 PM PDT 24 Jul 04 05:30:37 PM PDT 24 17295170 ps
T836 /workspace/coverage/default/27.clkmgr_peri.1118687713 Jul 04 05:30:32 PM PDT 24 Jul 04 05:30:33 PM PDT 24 13473263 ps
T837 /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.4068410054 Jul 04 05:30:34 PM PDT 24 Jul 04 05:30:35 PM PDT 24 74550475 ps
T838 /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.1628083167 Jul 04 05:29:26 PM PDT 24 Jul 04 05:29:28 PM PDT 24 45906366 ps
T839 /workspace/coverage/default/40.clkmgr_smoke.3926932080 Jul 04 05:31:44 PM PDT 24 Jul 04 05:31:47 PM PDT 24 46790455 ps
T840 /workspace/coverage/default/25.clkmgr_clk_status.3132809089 Jul 04 05:30:21 PM PDT 24 Jul 04 05:30:22 PM PDT 24 41376493 ps
T841 /workspace/coverage/default/37.clkmgr_extclk.1500792776 Jul 04 05:31:41 PM PDT 24 Jul 04 05:31:44 PM PDT 24 77106361 ps
T842 /workspace/coverage/default/20.clkmgr_div_intersig_mubi.1177328254 Jul 04 05:30:23 PM PDT 24 Jul 04 05:30:24 PM PDT 24 78706598 ps
T843 /workspace/coverage/default/4.clkmgr_regwen.231991514 Jul 04 05:29:30 PM PDT 24 Jul 04 05:29:34 PM PDT 24 762945111 ps
T844 /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1710220295 Jul 04 05:29:55 PM PDT 24 Jul 04 05:29:57 PM PDT 24 171686980 ps
T845 /workspace/coverage/default/35.clkmgr_regwen.2569138038 Jul 04 05:31:42 PM PDT 24 Jul 04 05:31:46 PM PDT 24 798149574 ps
T846 /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.152381084 Jul 04 05:29:47 PM PDT 24 Jul 04 05:29:48 PM PDT 24 38159403 ps
T847 /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1260705057 Jul 04 05:30:31 PM PDT 24 Jul 04 05:30:32 PM PDT 24 23823969 ps
T848 /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1612181523 Jul 04 05:29:45 PM PDT 24 Jul 04 05:29:47 PM PDT 24 22705409 ps
T92 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2636297054 Jul 04 05:28:24 PM PDT 24 Jul 04 05:28:27 PM PDT 24 145738167 ps
T72 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.78580739 Jul 04 05:28:38 PM PDT 24 Jul 04 05:28:39 PM PDT 24 45406322 ps
T849 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2100347880 Jul 04 05:29:01 PM PDT 24 Jul 04 05:29:02 PM PDT 24 33307866 ps
T97 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3623793482 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:30 PM PDT 24 66706784 ps
T850 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2438343034 Jul 04 05:28:56 PM PDT 24 Jul 04 05:28:57 PM PDT 24 75168230 ps
T93 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3338521606 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:27 PM PDT 24 96468343 ps
T50 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.96650456 Jul 04 05:28:28 PM PDT 24 Jul 04 05:28:29 PM PDT 24 77469333 ps
T73 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2132868723 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:31 PM PDT 24 34466501 ps
T74 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.2444494850 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:04 PM PDT 24 55849491 ps
T851 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3173403416 Jul 04 05:28:28 PM PDT 24 Jul 04 05:28:29 PM PDT 24 13519766 ps
T51 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3356007055 Jul 04 05:28:16 PM PDT 24 Jul 04 05:28:18 PM PDT 24 181458837 ps
T852 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.286988434 Jul 04 05:28:24 PM PDT 24 Jul 04 05:28:31 PM PDT 24 393794860 ps
T853 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2865573494 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:39 PM PDT 24 147030307 ps
T854 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1102974462 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:49 PM PDT 24 65305801 ps
T855 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2255012261 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:44 PM PDT 24 33401027 ps
T856 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.557888002 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:26 PM PDT 24 356628501 ps
T52 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.4226425024 Jul 04 05:28:42 PM PDT 24 Jul 04 05:28:45 PM PDT 24 305269132 ps
T857 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2704899147 Jul 04 05:28:55 PM PDT 24 Jul 04 05:28:56 PM PDT 24 24190283 ps
T75 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1663021721 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:26 PM PDT 24 38325405 ps
T858 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2106237786 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:03 PM PDT 24 18393246 ps
T859 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2524175701 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:39 PM PDT 24 21199198 ps
T860 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3014350491 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:29 PM PDT 24 666689003 ps
T94 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.4170751794 Jul 04 05:28:23 PM PDT 24 Jul 04 05:28:26 PM PDT 24 141629728 ps
T861 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.757738199 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:44 PM PDT 24 35973164 ps
T57 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2196782262 Jul 04 05:28:31 PM PDT 24 Jul 04 05:28:33 PM PDT 24 55611655 ps
T862 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.553411016 Jul 04 05:28:40 PM PDT 24 Jul 04 05:28:44 PM PDT 24 535110177 ps
T76 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1811328748 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:39 PM PDT 24 133603433 ps
T863 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.68558909 Jul 04 05:28:57 PM PDT 24 Jul 04 05:28:58 PM PDT 24 36131913 ps
T864 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.530487490 Jul 04 05:28:31 PM PDT 24 Jul 04 05:28:34 PM PDT 24 112104919 ps
T865 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1810167530 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:00 PM PDT 24 26880604 ps
T53 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3070735442 Jul 04 05:28:31 PM PDT 24 Jul 04 05:28:34 PM PDT 24 94238963 ps
T866 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2927761674 Jul 04 05:28:51 PM PDT 24 Jul 04 05:28:52 PM PDT 24 21964816 ps
T77 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.509112864 Jul 04 05:28:39 PM PDT 24 Jul 04 05:28:40 PM PDT 24 24817196 ps
T78 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2144433676 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:38 PM PDT 24 91998169 ps
T867 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3821498744 Jul 04 05:28:26 PM PDT 24 Jul 04 05:28:29 PM PDT 24 44153788 ps
T868 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3250461670 Jul 04 05:28:55 PM PDT 24 Jul 04 05:28:56 PM PDT 24 27887578 ps
T869 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2302423461 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:00 PM PDT 24 110953827 ps
T79 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4216720584 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:31 PM PDT 24 22379019 ps
T870 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3839621146 Jul 04 05:28:45 PM PDT 24 Jul 04 05:28:46 PM PDT 24 13944478 ps
T55 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.698170568 Jul 04 05:28:23 PM PDT 24 Jul 04 05:28:25 PM PDT 24 80584995 ps
T871 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1025643408 Jul 04 05:28:57 PM PDT 24 Jul 04 05:28:58 PM PDT 24 13820550 ps
T54 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1329266317 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:44 PM PDT 24 49158225 ps
T872 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1872110239 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:26 PM PDT 24 15627858 ps
T873 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3303142333 Jul 04 05:28:16 PM PDT 24 Jul 04 05:28:20 PM PDT 24 401936174 ps
T874 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1555153258 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:38 PM PDT 24 16205822 ps
T875 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2606275704 Jul 04 05:28:52 PM PDT 24 Jul 04 05:28:53 PM PDT 24 27699702 ps
T876 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2180160826 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:38 PM PDT 24 28671804 ps
T877 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.15071781 Jul 04 05:28:23 PM PDT 24 Jul 04 05:28:24 PM PDT 24 25790021 ps
T119 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2710930673 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:46 PM PDT 24 124703801 ps
T56 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1562480700 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:25 PM PDT 24 135247627 ps
T878 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2259170665 Jul 04 05:28:44 PM PDT 24 Jul 04 05:28:46 PM PDT 24 17508166 ps
T879 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.4261698792 Jul 04 05:28:24 PM PDT 24 Jul 04 05:28:26 PM PDT 24 84364148 ps
T880 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2458541466 Jul 04 05:28:42 PM PDT 24 Jul 04 05:28:43 PM PDT 24 47482545 ps
T881 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1347225739 Jul 04 05:28:48 PM PDT 24 Jul 04 05:28:52 PM PDT 24 267130670 ps
T882 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2250344642 Jul 04 05:28:44 PM PDT 24 Jul 04 05:28:46 PM PDT 24 212388883 ps
T101 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3345764102 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:32 PM PDT 24 132422008 ps
T58 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3401919135 Jul 04 05:28:39 PM PDT 24 Jul 04 05:28:41 PM PDT 24 108855955 ps
T883 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.325226751 Jul 04 05:28:16 PM PDT 24 Jul 04 05:28:17 PM PDT 24 29915296 ps
T884 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.831888505 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:31 PM PDT 24 13843533 ps
T885 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.15852592 Jul 04 05:28:32 PM PDT 24 Jul 04 05:28:33 PM PDT 24 34854879 ps
T886 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.645496224 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:48 PM PDT 24 136249376 ps
T887 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.103330243 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:46 PM PDT 24 124582902 ps
T143 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1723965292 Jul 04 05:28:48 PM PDT 24 Jul 04 05:28:50 PM PDT 24 111834406 ps
T112 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2721056781 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:39 PM PDT 24 447067903 ps
T888 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3453988165 Jul 04 05:28:45 PM PDT 24 Jul 04 05:28:47 PM PDT 24 29544648 ps
T889 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1748705863 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:30 PM PDT 24 72081571 ps
T890 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.362195615 Jul 04 05:28:15 PM PDT 24 Jul 04 05:28:16 PM PDT 24 26335476 ps
T891 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1461761326 Jul 04 05:28:24 PM PDT 24 Jul 04 05:28:25 PM PDT 24 79905958 ps
T892 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3486499221 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:03 PM PDT 24 37832093 ps
T893 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.4286610864 Jul 04 05:28:31 PM PDT 24 Jul 04 05:28:32 PM PDT 24 19356735 ps
T894 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3277461187 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:38 PM PDT 24 35885808 ps
T895 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3294451290 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:03 PM PDT 24 25177886 ps
T896 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2138565801 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:30 PM PDT 24 26463223 ps
T897 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.612183818 Jul 04 05:28:53 PM PDT 24 Jul 04 05:28:55 PM PDT 24 111913617 ps
T898 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3211317731 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:40 PM PDT 24 491781477 ps
T98 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1152226086 Jul 04 05:28:45 PM PDT 24 Jul 04 05:28:48 PM PDT 24 396036664 ps
T899 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1549611691 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:44 PM PDT 24 65868721 ps
T900 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2708535128 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:39 PM PDT 24 60496195 ps
T901 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3163343093 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:39 PM PDT 24 19555588 ps
T902 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.605718396 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:30 PM PDT 24 98854219 ps
T903 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3197570772 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:24 PM PDT 24 60791314 ps
T113 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2122937080 Jul 04 05:28:45 PM PDT 24 Jul 04 05:28:47 PM PDT 24 233031347 ps
T904 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.29498924 Jul 04 05:28:16 PM PDT 24 Jul 04 05:28:20 PM PDT 24 241132037 ps
T905 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1915369726 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:27 PM PDT 24 80630401 ps
T906 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3601252861 Jul 04 05:28:38 PM PDT 24 Jul 04 05:28:39 PM PDT 24 16971708 ps
T907 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2908808686 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:48 PM PDT 24 38896083 ps
T908 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.316830150 Jul 04 05:28:51 PM PDT 24 Jul 04 05:28:52 PM PDT 24 36990835 ps
T909 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.861002947 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:48 PM PDT 24 110661886 ps
T910 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1955374131 Jul 04 05:28:35 PM PDT 24 Jul 04 05:28:36 PM PDT 24 42186187 ps
T121 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3442501878 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:24 PM PDT 24 132752816 ps
T911 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.4235116987 Jul 04 05:28:52 PM PDT 24 Jul 04 05:28:53 PM PDT 24 71480806 ps
T912 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3753467684 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:38 PM PDT 24 51297409 ps
T913 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3692176448 Jul 04 05:28:24 PM PDT 24 Jul 04 05:28:25 PM PDT 24 36748403 ps
T118 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1290757244 Jul 04 05:28:38 PM PDT 24 Jul 04 05:28:40 PM PDT 24 86751875 ps
T914 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1930065434 Jul 04 05:28:17 PM PDT 24 Jul 04 05:28:18 PM PDT 24 181386743 ps
T915 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3797338847 Jul 04 05:28:32 PM PDT 24 Jul 04 05:28:34 PM PDT 24 134786188 ps
T114 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2956600739 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:39 PM PDT 24 247992482 ps
T916 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.150450070 Jul 04 05:28:51 PM PDT 24 Jul 04 05:28:52 PM PDT 24 17610992 ps
T115 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1871185929 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:48 PM PDT 24 519518670 ps
T917 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2440661536 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:00 PM PDT 24 30242483 ps
T918 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3544789618 Jul 04 05:28:23 PM PDT 24 Jul 04 05:28:30 PM PDT 24 267963071 ps
T919 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.894154250 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:47 PM PDT 24 21891754 ps
T920 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1184584251 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:31 PM PDT 24 90189449 ps
T122 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.2178516122 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:49 PM PDT 24 166006535 ps
T921 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.227848757 Jul 04 05:28:53 PM PDT 24 Jul 04 05:28:54 PM PDT 24 25558902 ps
T125 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.143282082 Jul 04 05:28:28 PM PDT 24 Jul 04 05:28:30 PM PDT 24 95397769 ps
T922 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3810314018 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:23 PM PDT 24 21619105 ps
T923 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2340753810 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:37 PM PDT 24 37925390 ps
T924 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.934429677 Jul 04 05:28:51 PM PDT 24 Jul 04 05:28:51 PM PDT 24 15048231 ps
T925 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3691278770 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:00 PM PDT 24 12705695 ps
T926 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1094056343 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:32 PM PDT 24 47014845 ps
T927 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1493888056 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:30 PM PDT 24 11733157 ps
T928 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3219288039 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:45 PM PDT 24 44528560 ps
T120 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3368312061 Jul 04 05:28:27 PM PDT 24 Jul 04 05:28:29 PM PDT 24 209153845 ps
T929 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2790107703 Jul 04 05:28:28 PM PDT 24 Jul 04 05:28:30 PM PDT 24 161054684 ps
T116 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2469805598 Jul 04 05:28:51 PM PDT 24 Jul 04 05:28:53 PM PDT 24 137525319 ps
T930 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1261045928 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:49 PM PDT 24 132861477 ps
T931 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.311782901 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:24 PM PDT 24 136339869 ps
T932 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3393386147 Jul 04 05:28:40 PM PDT 24 Jul 04 05:28:41 PM PDT 24 77769651 ps
T933 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2822444607 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:26 PM PDT 24 17895446 ps
T99 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2788486899 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:39 PM PDT 24 329053525 ps
T934 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3751366722 Jul 04 05:28:56 PM PDT 24 Jul 04 05:28:56 PM PDT 24 32577054 ps
T100 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1982017769 Jul 04 05:28:47 PM PDT 24 Jul 04 05:28:49 PM PDT 24 198647782 ps
T935 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.917437027 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:23 PM PDT 24 23662292 ps
T123 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.349419877 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:48 PM PDT 24 260400077 ps
T936 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.395158835 Jul 04 05:28:27 PM PDT 24 Jul 04 05:28:30 PM PDT 24 132628923 ps
T937 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.682828546 Jul 04 05:28:28 PM PDT 24 Jul 04 05:28:31 PM PDT 24 155229724 ps
T117 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.4099890006 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:25 PM PDT 24 175541295 ps
T938 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1445276470 Jul 04 05:28:42 PM PDT 24 Jul 04 05:28:44 PM PDT 24 215603620 ps
T939 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1610299712 Jul 04 05:28:53 PM PDT 24 Jul 04 05:28:54 PM PDT 24 19866772 ps
T940 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3672427740 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:48 PM PDT 24 109629478 ps
T941 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1373637945 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:33 PM PDT 24 137065725 ps
T942 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4045511044 Jul 04 05:28:53 PM PDT 24 Jul 04 05:28:54 PM PDT 24 20474788 ps
T943 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3870867036 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:33 PM PDT 24 511672818 ps
T944 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2582186067 Jul 04 05:28:50 PM PDT 24 Jul 04 05:28:51 PM PDT 24 21814503 ps
T945 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.2420025 Jul 04 05:28:48 PM PDT 24 Jul 04 05:28:49 PM PDT 24 19278607 ps
T946 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2210278236 Jul 04 05:28:31 PM PDT 24 Jul 04 05:28:32 PM PDT 24 21038827 ps
T947 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2146916833 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:41 PM PDT 24 255741875 ps
T948 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2220565652 Jul 04 05:28:50 PM PDT 24 Jul 04 05:28:52 PM PDT 24 194301697 ps
T949 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.434683976 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:26 PM PDT 24 42129809 ps
T102 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1286492351 Jul 04 05:28:15 PM PDT 24 Jul 04 05:28:17 PM PDT 24 57239934 ps
T950 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3153869317 Jul 04 05:28:45 PM PDT 24 Jul 04 05:28:46 PM PDT 24 11882789 ps
T951 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.801342480 Jul 04 05:28:51 PM PDT 24 Jul 04 05:28:52 PM PDT 24 11361661 ps
T952 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3007458789 Jul 04 05:28:53 PM PDT 24 Jul 04 05:28:54 PM PDT 24 17847831 ps
T953 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2507741649 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:48 PM PDT 24 54601899 ps
T954 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1900085118 Jul 04 05:29:00 PM PDT 24 Jul 04 05:29:01 PM PDT 24 35934290 ps
T955 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3397193710 Jul 04 05:28:44 PM PDT 24 Jul 04 05:28:48 PM PDT 24 146848536 ps
T956 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1350867886 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:00 PM PDT 24 13775814 ps
T957 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1330315317 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:32 PM PDT 24 139233112 ps
T958 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.213928588 Jul 04 05:28:37 PM PDT 24 Jul 04 05:28:39 PM PDT 24 205461809 ps
T959 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2085730829 Jul 04 05:28:42 PM PDT 24 Jul 04 05:28:43 PM PDT 24 12670590 ps
T960 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1737647482 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:45 PM PDT 24 6608759233 ps
T961 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.874602152 Jul 04 05:28:35 PM PDT 24 Jul 04 05:28:36 PM PDT 24 75635609 ps
T103 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.510208557 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:48 PM PDT 24 184809072 ps
T962 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.506070288 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:03 PM PDT 24 21181912 ps
T963 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1807449856 Jul 04 05:28:19 PM PDT 24 Jul 04 05:28:23 PM PDT 24 452788246 ps
T124 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3773173758 Jul 04 05:28:46 PM PDT 24 Jul 04 05:28:49 PM PDT 24 544715602 ps
T964 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1720956858 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:45 PM PDT 24 58140110 ps
T965 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.736975895 Jul 04 05:28:39 PM PDT 24 Jul 04 05:28:41 PM PDT 24 69530527 ps
T966 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.4268488925 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:23 PM PDT 24 38821738 ps
T967 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2400878069 Jul 04 05:28:45 PM PDT 24 Jul 04 05:28:47 PM PDT 24 220869233 ps
T968 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2477640564 Jul 04 05:28:15 PM PDT 24 Jul 04 05:28:17 PM PDT 24 133775896 ps
T969 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3060866517 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:32 PM PDT 24 103759920 ps
T970 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.689224985 Jul 04 05:29:03 PM PDT 24 Jul 04 05:29:04 PM PDT 24 48757729 ps
T971 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.105134247 Jul 04 05:28:41 PM PDT 24 Jul 04 05:28:43 PM PDT 24 253510120 ps
T972 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.970495421 Jul 04 05:28:15 PM PDT 24 Jul 04 05:28:16 PM PDT 24 60096313 ps
T973 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.119594065 Jul 04 05:28:32 PM PDT 24 Jul 04 05:28:34 PM PDT 24 76468354 ps
T974 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2588368071 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:04 PM PDT 24 255532447 ps
T975 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1368706896 Jul 04 05:28:43 PM PDT 24 Jul 04 05:28:44 PM PDT 24 21549555 ps
T976 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1504189267 Jul 04 05:28:52 PM PDT 24 Jul 04 05:28:53 PM PDT 24 19565558 ps
T977 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3064687711 Jul 04 05:28:16 PM PDT 24 Jul 04 05:28:18 PM PDT 24 33232032 ps
T978 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.4043741581 Jul 04 05:28:30 PM PDT 24 Jul 04 05:28:32 PM PDT 24 180717470 ps
T979 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2432893553 Jul 04 05:28:31 PM PDT 24 Jul 04 05:28:33 PM PDT 24 33481367 ps
T980 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3206435931 Jul 04 05:28:42 PM PDT 24 Jul 04 05:28:44 PM PDT 24 47459613 ps
T981 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1760975504 Jul 04 05:28:44 PM PDT 24 Jul 04 05:28:45 PM PDT 24 13060570 ps
T982 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2686683637 Jul 04 05:28:16 PM PDT 24 Jul 04 05:28:17 PM PDT 24 22230877 ps
T983 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.580875583 Jul 04 05:28:22 PM PDT 24 Jul 04 05:28:24 PM PDT 24 26187431 ps
T984 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3602668101 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:27 PM PDT 24 202612242 ps
T985 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.835742338 Jul 04 05:28:52 PM PDT 24 Jul 04 05:28:54 PM PDT 24 179866342 ps
T986 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3418772766 Jul 04 05:28:16 PM PDT 24 Jul 04 05:28:18 PM PDT 24 109614831 ps
T987 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.707216057 Jul 04 05:28:25 PM PDT 24 Jul 04 05:28:27 PM PDT 24 61332770 ps
T988 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3703373979 Jul 04 05:28:36 PM PDT 24 Jul 04 05:28:37 PM PDT 24 90315599 ps
T989 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.2173614404 Jul 04 05:28:28 PM PDT 24 Jul 04 05:28:30 PM PDT 24 81113019 ps
T990 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.2543499653 Jul 04 05:28:24 PM PDT 24 Jul 04 05:28:26 PM PDT 24 86067021 ps
T991 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3648573783 Jul 04 05:28:15 PM PDT 24 Jul 04 05:28:16 PM PDT 24 19949180 ps
T992 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.398102129 Jul 04 05:28:45 PM PDT 24 Jul 04 05:28:47 PM PDT 24 361917386 ps
T993 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3380881103 Jul 04 05:28:29 PM PDT 24 Jul 04 05:28:30 PM PDT 24 29866149 ps
T994 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1982315194 Jul 04 05:28:51 PM PDT 24 Jul 04 05:28:54 PM PDT 24 138139998 ps
T995 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3751411860 Jul 04 05:28:38 PM PDT 24 Jul 04 05:28:42 PM PDT 24 592546038 ps
T996 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3077478883 Jul 04 05:28:42 PM PDT 24 Jul 04 05:28:43 PM PDT 24 16657947 ps
T997 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1613759027 Jul 04 05:28:41 PM PDT 24 Jul 04 05:28:43 PM PDT 24 62878371 ps
T144 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1748911834 Jul 04 05:28:42 PM PDT 24 Jul 04 05:28:45 PM PDT 24 142708776 ps
T998 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.738305719 Jul 04 05:28:14 PM PDT 24 Jul 04 05:28:16 PM PDT 24 89175123 ps
T999 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2039216885 Jul 04 05:28:23 PM PDT 24 Jul 04 05:28:24 PM PDT 24 26278636 ps
T1000 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2665581203 Jul 04 05:28:58 PM PDT 24 Jul 04 05:28:59 PM PDT 24 24459066 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%