Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338299666

1

T5

1812

T6

2700

T7

2588

auto[1]

409554

1

T6

410

T21

116

T31

848

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338323216

1

T5

1804

T6

2840

T7

2588

auto[1]

386004

1

T5

8

T6

270

T4

842

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338250880

1

T5

1762

T6

2846

T7

2588

auto[1]

458340

1

T5

50

T6

264

T21

114

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

317080896

1

T5

1732

T6

2924

T7

2588

auto[1]

21628324

1

T5

80

T6

186

T21

90

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

196903876

1

T5

1812

T6

3110

T7

2588

auto[1]

141805344

1

T1

24

T4

20

T16

16

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

181643262

1

T5

1708

T6

2598

T7

2588

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

135117416

1

T1

24

T4

20

T16

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30516

1

T6

56

T21

14

T31

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7180

1

T3

26

T108

10

T81

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

14705290

1

T5

54

T6

48

T21

82

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6574858

1

T31

82

T3

68

T62

102

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50270

1

T6

44

T31

92

T70

56

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12026

1

T31

30

T3

4

T81

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55622

1

T6

22

T4

842

T21

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1410

1

T12

36

T25

30

T55

80

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11428

1

T6

78

T31

56

T12

358

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2884

1

T12

114

T25

42

T55

72

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10228

1

T62

92

T81

84

T12

100

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2912

1

T108

24

T12

38

T13

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20302

1

T12

708

T82

74

T13

52

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5276

1

T108

50

T12

62

T13

46

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

35366

1

T5

16

T31

22

T70

20

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4236

1

T3

16

T62

76

T108

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

35368

1

T31

84

T70

64

T81

98

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7938

1

T3

80

T108

96

T12

162

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

26066

1

T5

26

T6

4

T21

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6240

1

T62

60

T108

38

T81

28

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

53216

1

T6

90

T31

64

T70

66

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13968

1

T108

42

T81

48

T12

584

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

59946

1

T5

8

T6

28

T21

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6508

1

T67

42

T81

2

T12

140

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48768

1

T6

142

T21

102

T3

74

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13048

1

T81

58

T12

342

T82

52

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39826

1

T31

78

T70

36

T62

144

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10480

1

T31

14

T3

26

T108

34

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

78402

1

T31

434

T70

122

T62

76

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18964

1

T31

72

T3

60

T108

100