Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1010
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T800 /workspace/coverage/default/8.clkmgr_frequency_timeout.882296659 Jul 05 04:38:15 PM PDT 24 Jul 05 04:38:24 PM PDT 24 856578127 ps
T801 /workspace/coverage/default/19.clkmgr_peri.3005929563 Jul 05 04:38:44 PM PDT 24 Jul 05 04:38:49 PM PDT 24 23531625 ps
T802 /workspace/coverage/default/6.clkmgr_frequency.3914163423 Jul 05 04:39:29 PM PDT 24 Jul 05 04:39:35 PM PDT 24 907670293 ps
T803 /workspace/coverage/default/21.clkmgr_alert_test.3843326060 Jul 05 04:38:45 PM PDT 24 Jul 05 04:38:51 PM PDT 24 63254614 ps
T804 /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.3518398178 Jul 05 04:39:04 PM PDT 24 Jul 05 04:39:10 PM PDT 24 185058129 ps
T805 /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.4230153554 Jul 05 04:38:35 PM PDT 24 Jul 05 04:38:40 PM PDT 24 23813515 ps
T806 /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.975946634 Jul 05 04:39:31 PM PDT 24 Jul 05 05:03:36 PM PDT 24 209644553158 ps
T807 /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.2653674286 Jul 05 04:39:46 PM PDT 24 Jul 05 04:51:49 PM PDT 24 38148928407 ps
T808 /workspace/coverage/default/6.clkmgr_clk_status.4159647366 Jul 05 04:38:08 PM PDT 24 Jul 05 04:38:13 PM PDT 24 14886314 ps
T809 /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.132805016 Jul 05 04:39:05 PM PDT 24 Jul 05 04:39:10 PM PDT 24 55722668 ps
T810 /workspace/coverage/default/42.clkmgr_div_intersig_mubi.2521263264 Jul 05 04:39:44 PM PDT 24 Jul 05 04:39:47 PM PDT 24 29547286 ps
T811 /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.61627007 Jul 05 04:39:01 PM PDT 24 Jul 05 04:39:05 PM PDT 24 14800965 ps
T812 /workspace/coverage/default/22.clkmgr_frequency_timeout.2908874245 Jul 05 04:38:49 PM PDT 24 Jul 05 04:38:58 PM PDT 24 1353748376 ps
T813 /workspace/coverage/default/49.clkmgr_extclk.3547948984 Jul 05 04:40:06 PM PDT 24 Jul 05 04:40:07 PM PDT 24 107994021 ps
T814 /workspace/coverage/default/31.clkmgr_alert_test.1443079258 Jul 05 04:39:32 PM PDT 24 Jul 05 04:39:39 PM PDT 24 77666020 ps
T815 /workspace/coverage/default/3.clkmgr_trans.278220945 Jul 05 04:38:14 PM PDT 24 Jul 05 04:38:17 PM PDT 24 20019918 ps
T816 /workspace/coverage/default/47.clkmgr_frequency_timeout.4093454735 Jul 05 04:39:49 PM PDT 24 Jul 05 04:39:58 PM PDT 24 2294772026 ps
T817 /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.352595135 Jul 05 04:39:20 PM PDT 24 Jul 05 04:39:22 PM PDT 24 48206028 ps
T818 /workspace/coverage/default/43.clkmgr_div_intersig_mubi.4128851229 Jul 05 04:39:38 PM PDT 24 Jul 05 04:39:40 PM PDT 24 18027764 ps
T819 /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.824173360 Jul 05 04:38:10 PM PDT 24 Jul 05 04:38:15 PM PDT 24 23578937 ps
T820 /workspace/coverage/default/23.clkmgr_regwen.8733216 Jul 05 04:38:57 PM PDT 24 Jul 05 04:39:06 PM PDT 24 1272217179 ps
T157 /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.576289963 Jul 05 04:39:35 PM PDT 24 Jul 05 04:43:45 PM PDT 24 16839456075 ps
T821 /workspace/coverage/default/32.clkmgr_clk_status.2929349050 Jul 05 04:39:21 PM PDT 24 Jul 05 04:39:22 PM PDT 24 42284918 ps
T822 /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2395125497 Jul 05 04:39:18 PM PDT 24 Jul 05 04:39:20 PM PDT 24 102858325 ps
T823 /workspace/coverage/default/7.clkmgr_stress_all.2212331072 Jul 05 04:38:31 PM PDT 24 Jul 05 04:40:02 PM PDT 24 12032899384 ps
T824 /workspace/coverage/default/16.clkmgr_clk_status.3868529226 Jul 05 04:38:54 PM PDT 24 Jul 05 04:38:56 PM PDT 24 26907122 ps
T825 /workspace/coverage/default/35.clkmgr_peri.3323542187 Jul 05 04:39:32 PM PDT 24 Jul 05 04:39:36 PM PDT 24 163416036 ps
T826 /workspace/coverage/default/29.clkmgr_frequency_timeout.4116140878 Jul 05 04:39:21 PM PDT 24 Jul 05 04:39:33 PM PDT 24 741563648 ps
T827 /workspace/coverage/default/31.clkmgr_peri.1912873374 Jul 05 04:39:19 PM PDT 24 Jul 05 04:39:21 PM PDT 24 14663117 ps
T828 /workspace/coverage/default/1.clkmgr_alert_test.398740897 Jul 05 04:38:12 PM PDT 24 Jul 05 04:38:17 PM PDT 24 28212633 ps
T829 /workspace/coverage/default/11.clkmgr_stress_all.1008076292 Jul 05 04:39:02 PM PDT 24 Jul 05 04:39:29 PM PDT 24 4737097894 ps
T830 /workspace/coverage/default/31.clkmgr_div_intersig_mubi.3138045262 Jul 05 04:39:22 PM PDT 24 Jul 05 04:39:24 PM PDT 24 24508661 ps
T831 /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2332561257 Jul 05 04:39:51 PM PDT 24 Jul 05 04:39:54 PM PDT 24 56478239 ps
T832 /workspace/coverage/default/17.clkmgr_frequency.245064700 Jul 05 04:38:40 PM PDT 24 Jul 05 04:38:46 PM PDT 24 337135868 ps
T833 /workspace/coverage/default/1.clkmgr_smoke.756313394 Jul 05 04:38:09 PM PDT 24 Jul 05 04:38:15 PM PDT 24 82495877 ps
T834 /workspace/coverage/default/8.clkmgr_clk_status.3291854649 Jul 05 04:38:16 PM PDT 24 Jul 05 04:38:19 PM PDT 24 16657454 ps
T835 /workspace/coverage/default/24.clkmgr_trans.3004807810 Jul 05 04:39:06 PM PDT 24 Jul 05 04:39:11 PM PDT 24 28524518 ps
T836 /workspace/coverage/default/26.clkmgr_regwen.209187674 Jul 05 04:39:05 PM PDT 24 Jul 05 04:39:13 PM PDT 24 534115209 ps
T837 /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.200781382 Jul 05 04:39:05 PM PDT 24 Jul 05 05:18:22 PM PDT 24 694928656825 ps
T838 /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2240341048 Jul 05 04:38:39 PM PDT 24 Jul 05 04:38:44 PM PDT 24 14587516 ps
T839 /workspace/coverage/default/34.clkmgr_stress_all.6800163 Jul 05 04:39:52 PM PDT 24 Jul 05 04:40:13 PM PDT 24 2951087346 ps
T840 /workspace/coverage/default/28.clkmgr_peri.1989103074 Jul 05 04:39:08 PM PDT 24 Jul 05 04:39:12 PM PDT 24 13894071 ps
T841 /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.90242128 Jul 05 04:38:07 PM PDT 24 Jul 05 04:38:12 PM PDT 24 21748493 ps
T842 /workspace/coverage/default/0.clkmgr_frequency_timeout.2595354849 Jul 05 04:38:05 PM PDT 24 Jul 05 04:38:10 PM PDT 24 278082822 ps
T843 /workspace/coverage/default/14.clkmgr_peri.736504090 Jul 05 04:38:37 PM PDT 24 Jul 05 04:38:42 PM PDT 24 21281236 ps
T844 /workspace/coverage/default/0.clkmgr_trans.777304043 Jul 05 04:37:58 PM PDT 24 Jul 05 04:38:02 PM PDT 24 40104899 ps
T845 /workspace/coverage/default/40.clkmgr_regwen.1013575159 Jul 05 04:39:31 PM PDT 24 Jul 05 04:39:38 PM PDT 24 782172570 ps
T846 /workspace/coverage/default/0.clkmgr_smoke.226937443 Jul 05 04:38:06 PM PDT 24 Jul 05 04:38:11 PM PDT 24 69351040 ps
T847 /workspace/coverage/default/26.clkmgr_smoke.2174601283 Jul 05 04:39:02 PM PDT 24 Jul 05 04:39:07 PM PDT 24 17689731 ps
T848 /workspace/coverage/default/17.clkmgr_extclk.3084247248 Jul 05 04:38:50 PM PDT 24 Jul 05 04:38:54 PM PDT 24 54188956 ps
T849 /workspace/coverage/default/41.clkmgr_stress_all.2770055361 Jul 05 04:39:41 PM PDT 24 Jul 05 04:39:42 PM PDT 24 19614374 ps
T850 /workspace/coverage/default/26.clkmgr_frequency.3940536262 Jul 05 04:39:03 PM PDT 24 Jul 05 04:39:16 PM PDT 24 1992066751 ps
T851 /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1009092600 Jul 05 04:38:36 PM PDT 24 Jul 05 04:38:41 PM PDT 24 24042873 ps
T852 /workspace/coverage/default/28.clkmgr_clk_status.3107241137 Jul 05 04:39:18 PM PDT 24 Jul 05 04:39:20 PM PDT 24 15379883 ps
T853 /workspace/coverage/default/45.clkmgr_peri.1883542212 Jul 05 04:39:45 PM PDT 24 Jul 05 04:39:49 PM PDT 24 37326272 ps
T101 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4226836583 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:04 PM PDT 24 35154446 ps
T47 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.988526626 Jul 05 04:28:35 PM PDT 24 Jul 05 04:28:49 PM PDT 24 113191405 ps
T102 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3026258594 Jul 05 04:27:32 PM PDT 24 Jul 05 04:27:35 PM PDT 24 322682047 ps
T95 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2048041474 Jul 05 04:27:34 PM PDT 24 Jul 05 04:27:39 PM PDT 24 221234554 ps
T48 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1605118644 Jul 05 04:27:19 PM PDT 24 Jul 05 04:27:23 PM PDT 24 390686878 ps
T854 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3051628816 Jul 05 04:27:19 PM PDT 24 Jul 05 04:27:20 PM PDT 24 15705016 ps
T855 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3829995416 Jul 05 04:27:17 PM PDT 24 Jul 05 04:27:19 PM PDT 24 20183260 ps
T75 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.4271394307 Jul 05 04:27:12 PM PDT 24 Jul 05 04:27:14 PM PDT 24 246179936 ps
T96 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2109606261 Jul 05 04:28:34 PM PDT 24 Jul 05 04:28:47 PM PDT 24 128543630 ps
T856 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.345055744 Jul 05 04:27:14 PM PDT 24 Jul 05 04:27:15 PM PDT 24 30381618 ps
T857 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3754725258 Jul 05 04:27:41 PM PDT 24 Jul 05 04:27:47 PM PDT 24 78601166 ps
T49 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3746367050 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:39 PM PDT 24 725913476 ps
T858 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3567940712 Jul 05 04:27:55 PM PDT 24 Jul 05 04:28:00 PM PDT 24 43572710 ps
T97 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1290465179 Jul 05 04:27:17 PM PDT 24 Jul 05 04:27:20 PM PDT 24 118945710 ps
T859 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1388063748 Jul 05 04:27:34 PM PDT 24 Jul 05 04:27:37 PM PDT 24 25044186 ps
T860 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1171090185 Jul 05 04:27:28 PM PDT 24 Jul 05 04:27:35 PM PDT 24 14120334 ps
T50 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.618367179 Jul 05 04:27:12 PM PDT 24 Jul 05 04:27:14 PM PDT 24 77044325 ps
T51 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3341869838 Jul 05 04:27:28 PM PDT 24 Jul 05 04:27:31 PM PDT 24 62828085 ps
T76 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1618145066 Jul 05 04:27:38 PM PDT 24 Jul 05 04:27:42 PM PDT 24 163778238 ps
T53 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3977441852 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:37 PM PDT 24 98573059 ps
T52 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1169044033 Jul 05 04:27:17 PM PDT 24 Jul 05 04:27:19 PM PDT 24 207089088 ps
T77 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1078326043 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:41 PM PDT 24 195779768 ps
T861 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2545699773 Jul 05 04:28:08 PM PDT 24 Jul 05 04:28:19 PM PDT 24 40374027 ps
T862 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.4000996552 Jul 05 04:28:02 PM PDT 24 Jul 05 04:28:10 PM PDT 24 24958891 ps
T78 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3435956741 Jul 05 04:27:24 PM PDT 24 Jul 05 04:27:26 PM PDT 24 67268096 ps
T79 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1571698901 Jul 05 04:27:19 PM PDT 24 Jul 05 04:27:21 PM PDT 24 203309876 ps
T863 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.4258916939 Jul 05 04:27:30 PM PDT 24 Jul 05 04:27:33 PM PDT 24 43571190 ps
T864 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1997867556 Jul 05 04:28:03 PM PDT 24 Jul 05 04:28:12 PM PDT 24 161101323 ps
T54 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3401924011 Jul 05 04:27:34 PM PDT 24 Jul 05 04:27:37 PM PDT 24 104438466 ps
T865 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3664663292 Jul 05 04:27:38 PM PDT 24 Jul 05 04:27:42 PM PDT 24 24362921 ps
T866 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2957622558 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:39 PM PDT 24 15617726 ps
T166 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.258988350 Jul 05 04:27:16 PM PDT 24 Jul 05 04:27:19 PM PDT 24 190061114 ps
T867 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.1081691253 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:04 PM PDT 24 12462894 ps
T868 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1395008406 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:19 PM PDT 24 136119747 ps
T869 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3279631377 Jul 05 04:27:46 PM PDT 24 Jul 05 04:27:52 PM PDT 24 102522223 ps
T870 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.370579145 Jul 05 04:27:54 PM PDT 24 Jul 05 04:27:59 PM PDT 24 12497602 ps
T871 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2642627573 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:41 PM PDT 24 32932138 ps
T115 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1310320460 Jul 05 04:27:51 PM PDT 24 Jul 05 04:27:57 PM PDT 24 158708353 ps
T872 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.954361335 Jul 05 04:27:49 PM PDT 24 Jul 05 04:27:55 PM PDT 24 26719249 ps
T873 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.2427814904 Jul 05 04:27:25 PM PDT 24 Jul 05 04:27:28 PM PDT 24 100698411 ps
T874 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.362843878 Jul 05 04:27:38 PM PDT 24 Jul 05 04:27:42 PM PDT 24 62078137 ps
T167 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2847241156 Jul 05 04:27:39 PM PDT 24 Jul 05 04:27:43 PM PDT 24 54953007 ps
T875 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2037331229 Jul 05 04:27:06 PM PDT 24 Jul 05 04:27:10 PM PDT 24 346820380 ps
T80 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1603456805 Jul 05 04:27:38 PM PDT 24 Jul 05 04:27:42 PM PDT 24 50045362 ps
T116 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1735666437 Jul 05 04:27:12 PM PDT 24 Jul 05 04:27:15 PM PDT 24 208928196 ps
T876 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1921852193 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:35 PM PDT 24 28118394 ps
T877 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1600823223 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:40 PM PDT 24 62321345 ps
T878 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1415952158 Jul 05 04:28:40 PM PDT 24 Jul 05 04:28:52 PM PDT 24 11799285 ps
T104 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1929194485 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:39 PM PDT 24 86902865 ps
T879 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3095125005 Jul 05 04:27:48 PM PDT 24 Jul 05 04:27:54 PM PDT 24 11558407 ps
T880 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.4006399804 Jul 05 04:27:16 PM PDT 24 Jul 05 04:27:20 PM PDT 24 165577758 ps
T881 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1853988961 Jul 05 04:27:21 PM PDT 24 Jul 05 04:27:22 PM PDT 24 26380479 ps
T125 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3997758140 Jul 05 04:28:31 PM PDT 24 Jul 05 04:28:45 PM PDT 24 109362082 ps
T882 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2105341534 Jul 05 04:27:15 PM PDT 24 Jul 05 04:27:17 PM PDT 24 186575479 ps
T883 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1291371669 Jul 05 04:27:45 PM PDT 24 Jul 05 04:27:50 PM PDT 24 19095545 ps
T884 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1094565832 Jul 05 04:27:48 PM PDT 24 Jul 05 04:27:53 PM PDT 24 33833484 ps
T117 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1354371100 Jul 05 04:27:14 PM PDT 24 Jul 05 04:27:16 PM PDT 24 57449577 ps
T885 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3392742907 Jul 05 04:27:07 PM PDT 24 Jul 05 04:27:09 PM PDT 24 94929237 ps
T886 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2173140914 Jul 05 04:27:50 PM PDT 24 Jul 05 04:27:56 PM PDT 24 19404290 ps
T887 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2238484656 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:36 PM PDT 24 110248331 ps
T888 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3027222554 Jul 05 04:28:39 PM PDT 24 Jul 05 04:28:51 PM PDT 24 14687205 ps
T889 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.2850542107 Jul 05 04:27:28 PM PDT 24 Jul 05 04:27:31 PM PDT 24 53636009 ps
T890 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.3085615657 Jul 05 04:27:44 PM PDT 24 Jul 05 04:27:51 PM PDT 24 107475928 ps
T891 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3701672777 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:38 PM PDT 24 30914193 ps
T892 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3887806789 Jul 05 04:27:29 PM PDT 24 Jul 05 04:27:32 PM PDT 24 34011901 ps
T893 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3280981889 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:09 PM PDT 24 28432630 ps
T128 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.872493556 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:05 PM PDT 24 100429150 ps
T118 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.194579177 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:49 PM PDT 24 286736350 ps
T126 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2191999956 Jul 05 04:27:13 PM PDT 24 Jul 05 04:27:16 PM PDT 24 160287697 ps
T894 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.325114682 Jul 05 04:27:13 PM PDT 24 Jul 05 04:27:15 PM PDT 24 73227332 ps
T895 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3571183219 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:46 PM PDT 24 52979518 ps
T896 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3318381751 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:06 PM PDT 24 491051030 ps
T897 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.193911887 Jul 05 04:27:14 PM PDT 24 Jul 05 04:27:17 PM PDT 24 43208255 ps
T119 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2866351006 Jul 05 04:27:26 PM PDT 24 Jul 05 04:27:30 PM PDT 24 104397919 ps
T898 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3096564619 Jul 05 04:27:11 PM PDT 24 Jul 05 04:27:13 PM PDT 24 35099570 ps
T899 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2373512957 Jul 05 04:28:33 PM PDT 24 Jul 05 04:28:46 PM PDT 24 32046699 ps
T900 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3524685002 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:39 PM PDT 24 235821568 ps
T901 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.189896863 Jul 05 04:27:30 PM PDT 24 Jul 05 04:27:35 PM PDT 24 126864476 ps
T902 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1978568035 Jul 05 04:27:12 PM PDT 24 Jul 05 04:27:17 PM PDT 24 263965870 ps
T903 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3822505208 Jul 05 04:27:13 PM PDT 24 Jul 05 04:27:15 PM PDT 24 69335500 ps
T904 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.3517869833 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:16 PM PDT 24 12589181 ps
T905 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3676795690 Jul 05 04:28:00 PM PDT 24 Jul 05 04:28:06 PM PDT 24 57850374 ps
T906 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2553050201 Jul 05 04:27:16 PM PDT 24 Jul 05 04:27:17 PM PDT 24 12443026 ps
T121 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2056215509 Jul 05 04:27:22 PM PDT 24 Jul 05 04:27:30 PM PDT 24 92936966 ps
T907 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1821683236 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:38 PM PDT 24 19336388 ps
T908 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3323865907 Jul 05 04:27:20 PM PDT 24 Jul 05 04:27:22 PM PDT 24 170714301 ps
T909 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2393606142 Jul 05 04:27:12 PM PDT 24 Jul 05 04:27:14 PM PDT 24 58015898 ps
T910 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.4263610607 Jul 05 04:27:38 PM PDT 24 Jul 05 04:27:42 PM PDT 24 35943898 ps
T98 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.974585752 Jul 05 04:28:03 PM PDT 24 Jul 05 04:28:12 PM PDT 24 116003523 ps
T911 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.4129664445 Jul 05 04:27:29 PM PDT 24 Jul 05 04:27:32 PM PDT 24 149711695 ps
T99 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3963822209 Jul 05 04:28:47 PM PDT 24 Jul 05 04:28:59 PM PDT 24 230626452 ps
T912 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.559837211 Jul 05 04:27:28 PM PDT 24 Jul 05 04:27:31 PM PDT 24 265910089 ps
T913 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.737718213 Jul 05 04:27:10 PM PDT 24 Jul 05 04:27:13 PM PDT 24 69029332 ps
T914 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1330807059 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:35 PM PDT 24 34905792 ps
T915 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.528575079 Jul 05 04:27:28 PM PDT 24 Jul 05 04:27:30 PM PDT 24 35983088 ps
T916 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2539412783 Jul 05 04:27:38 PM PDT 24 Jul 05 04:27:42 PM PDT 24 13704251 ps
T917 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.441884764 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:37 PM PDT 24 361765586 ps
T918 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.4241002174 Jul 05 04:27:45 PM PDT 24 Jul 05 04:27:50 PM PDT 24 14857758 ps
T919 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3816702746 Jul 05 04:27:11 PM PDT 24 Jul 05 04:27:12 PM PDT 24 16985781 ps
T106 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1104135021 Jul 05 04:27:32 PM PDT 24 Jul 05 04:27:35 PM PDT 24 77125567 ps
T920 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.290136729 Jul 05 04:27:25 PM PDT 24 Jul 05 04:27:27 PM PDT 24 14352739 ps
T921 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1175045238 Jul 05 04:27:18 PM PDT 24 Jul 05 04:27:19 PM PDT 24 63968596 ps
T922 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3248885571 Jul 05 04:27:23 PM PDT 24 Jul 05 04:27:24 PM PDT 24 19217711 ps
T122 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2076021610 Jul 05 04:27:24 PM PDT 24 Jul 05 04:27:26 PM PDT 24 191203066 ps
T134 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.417852073 Jul 05 04:27:07 PM PDT 24 Jul 05 04:27:09 PM PDT 24 54235987 ps
T923 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.909264923 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:57 PM PDT 24 24079413 ps
T924 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2108802029 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:41 PM PDT 24 85942522 ps
T925 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3064136925 Jul 05 04:27:14 PM PDT 24 Jul 05 04:27:16 PM PDT 24 71247955 ps
T123 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1311702742 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:41 PM PDT 24 284902906 ps
T926 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4242101714 Jul 05 04:27:30 PM PDT 24 Jul 05 04:27:33 PM PDT 24 28503109 ps
T927 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.74771566 Jul 05 04:27:31 PM PDT 24 Jul 05 04:27:35 PM PDT 24 510575229 ps
T928 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2876182712 Jul 05 04:27:17 PM PDT 24 Jul 05 04:27:28 PM PDT 24 1744330228 ps
T929 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.757719868 Jul 05 04:27:14 PM PDT 24 Jul 05 04:27:22 PM PDT 24 520461420 ps
T930 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.945904886 Jul 05 04:27:19 PM PDT 24 Jul 05 04:27:27 PM PDT 24 39529045 ps
T127 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2620847343 Jul 05 04:27:31 PM PDT 24 Jul 05 04:27:36 PM PDT 24 186699773 ps
T931 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.984125859 Jul 05 04:27:19 PM PDT 24 Jul 05 04:27:21 PM PDT 24 115209530 ps
T932 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2826686192 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:13 PM PDT 24 20495135 ps
T933 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3554030996 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:45 PM PDT 24 33052550 ps
T934 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1851584650 Jul 05 04:27:56 PM PDT 24 Jul 05 04:28:02 PM PDT 24 101182013 ps
T935 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2879019220 Jul 05 04:27:21 PM PDT 24 Jul 05 04:27:28 PM PDT 24 269557926 ps
T936 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3542132905 Jul 05 04:27:49 PM PDT 24 Jul 05 04:27:55 PM PDT 24 38059090 ps
T937 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.680437810 Jul 05 04:27:26 PM PDT 24 Jul 05 04:27:30 PM PDT 24 189006763 ps
T130 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.90790810 Jul 05 04:27:23 PM PDT 24 Jul 05 04:27:26 PM PDT 24 417958751 ps
T938 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.172505353 Jul 05 04:27:22 PM PDT 24 Jul 05 04:27:24 PM PDT 24 108769704 ps
T939 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.395042172 Jul 05 04:27:24 PM PDT 24 Jul 05 04:27:25 PM PDT 24 18875733 ps
T940 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1312643473 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:41 PM PDT 24 42837393 ps
T941 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.827041803 Jul 05 04:27:45 PM PDT 24 Jul 05 04:27:51 PM PDT 24 93729714 ps
T942 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2292654508 Jul 05 04:27:40 PM PDT 24 Jul 05 04:27:44 PM PDT 24 16187314 ps
T132 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2460057265 Jul 05 04:27:12 PM PDT 24 Jul 05 04:27:15 PM PDT 24 98514459 ps
T943 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.119147816 Jul 05 04:27:31 PM PDT 24 Jul 05 04:27:35 PM PDT 24 111872439 ps
T944 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2294949523 Jul 05 04:27:07 PM PDT 24 Jul 05 04:27:10 PM PDT 24 349209730 ps
T945 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.533476573 Jul 05 04:27:23 PM PDT 24 Jul 05 04:27:24 PM PDT 24 11067990 ps
T103 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2209871895 Jul 05 04:27:31 PM PDT 24 Jul 05 04:27:35 PM PDT 24 51961995 ps
T946 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2660211857 Jul 05 04:27:32 PM PDT 24 Jul 05 04:27:40 PM PDT 24 1039662379 ps
T947 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.751183215 Jul 05 04:27:23 PM PDT 24 Jul 05 04:27:26 PM PDT 24 288194594 ps
T948 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3251189235 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:57 PM PDT 24 81668776 ps
T949 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1086902995 Jul 05 04:27:20 PM PDT 24 Jul 05 04:27:21 PM PDT 24 33658701 ps
T950 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2877605603 Jul 05 04:27:14 PM PDT 24 Jul 05 04:27:17 PM PDT 24 416951579 ps
T951 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.738924973 Jul 05 04:27:30 PM PDT 24 Jul 05 04:27:32 PM PDT 24 16539224 ps
T952 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2067080963 Jul 05 04:28:03 PM PDT 24 Jul 05 04:28:10 PM PDT 24 14851024 ps
T953 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1889835143 Jul 05 04:27:43 PM PDT 24 Jul 05 04:27:48 PM PDT 24 12307236 ps
T954 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.738339086 Jul 05 04:27:39 PM PDT 24 Jul 05 04:27:50 PM PDT 24 93607204 ps
T955 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2447146595 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:47 PM PDT 24 30101760 ps
T956 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.2360919431 Jul 05 04:27:23 PM PDT 24 Jul 05 04:27:25 PM PDT 24 114327600 ps
T957 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.302608488 Jul 05 04:27:25 PM PDT 24 Jul 05 04:27:26 PM PDT 24 89742143 ps
T958 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2034755846 Jul 05 04:27:29 PM PDT 24 Jul 05 04:27:33 PM PDT 24 109274028 ps
T959 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1679411825 Jul 05 04:27:10 PM PDT 24 Jul 05 04:27:12 PM PDT 24 110666994 ps
T960 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.778510307 Jul 05 04:27:39 PM PDT 24 Jul 05 04:27:42 PM PDT 24 30409664 ps
T961 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.932404296 Jul 05 04:27:29 PM PDT 24 Jul 05 04:27:33 PM PDT 24 55664769 ps
T124 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.4142301560 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:39 PM PDT 24 96794275 ps
T129 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1942750860 Jul 05 04:27:22 PM PDT 24 Jul 05 04:27:24 PM PDT 24 81408126 ps
T962 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3703966947 Jul 05 04:27:25 PM PDT 24 Jul 05 04:27:29 PM PDT 24 35315821 ps
T963 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4274717969 Jul 05 04:27:24 PM PDT 24 Jul 05 04:27:26 PM PDT 24 39613759 ps
T964 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2483737449 Jul 05 04:27:44 PM PDT 24 Jul 05 04:27:48 PM PDT 24 54507475 ps
T965 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3854690552 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:36 PM PDT 24 228878578 ps
T966 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2106014367 Jul 05 04:27:25 PM PDT 24 Jul 05 04:27:26 PM PDT 24 31076750 ps
T133 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.4255937003 Jul 05 04:27:08 PM PDT 24 Jul 05 04:27:11 PM PDT 24 285902648 ps
T967 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3871892612 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:15 PM PDT 24 183488837 ps
T968 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2307315844 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:58 PM PDT 24 154254179 ps
T969 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1141779389 Jul 05 04:27:28 PM PDT 24 Jul 05 04:27:30 PM PDT 24 11332348 ps
T970 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2197441200 Jul 05 04:27:45 PM PDT 24 Jul 05 04:27:50 PM PDT 24 14950742 ps
T971 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1783651712 Jul 05 04:27:27 PM PDT 24 Jul 05 04:27:29 PM PDT 24 11889847 ps
T972 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1758019222 Jul 05 04:28:33 PM PDT 24 Jul 05 04:28:47 PM PDT 24 216017352 ps
T973 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3471179236 Jul 05 04:27:04 PM PDT 24 Jul 05 04:27:06 PM PDT 24 28187675 ps
T974 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.4107571200 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:58 PM PDT 24 21244590 ps
T975 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.4212116723 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:58 PM PDT 24 34203615 ps
T976 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.25976877 Jul 05 04:27:30 PM PDT 24 Jul 05 04:27:33 PM PDT 24 32519050 ps
T977 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1974343352 Jul 05 04:27:25 PM PDT 24 Jul 05 04:27:27 PM PDT 24 74000406 ps
T978 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1573100392 Jul 05 04:28:07 PM PDT 24 Jul 05 04:28:18 PM PDT 24 12764493 ps
T979 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3266287135 Jul 05 04:27:18 PM PDT 24 Jul 05 04:27:19 PM PDT 24 15740672 ps
T105 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1266578632 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:58 PM PDT 24 111884920 ps
T980 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.330457829 Jul 05 04:28:27 PM PDT 24 Jul 05 04:28:42 PM PDT 24 23324358 ps
T981 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2517657937 Jul 05 04:28:00 PM PDT 24 Jul 05 04:28:06 PM PDT 24 21509496 ps
T982 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.373051354 Jul 05 04:27:17 PM PDT 24 Jul 05 04:27:19 PM PDT 24 159746702 ps
T983 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3698020422 Jul 05 04:27:14 PM PDT 24 Jul 05 04:27:16 PM PDT 24 69467249 ps
T120 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2069237753 Jul 05 04:27:16 PM PDT 24 Jul 05 04:27:19 PM PDT 24 100374207 ps
T984 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1623495980 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:48 PM PDT 24 164187584 ps
T985 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2486285928 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:39 PM PDT 24 101933120 ps
T986 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.4115009040 Jul 05 04:27:17 PM PDT 24 Jul 05 04:27:19 PM PDT 24 62051546 ps
T987 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2790097624 Jul 05 04:27:48 PM PDT 24 Jul 05 04:27:53 PM PDT 24 53233673 ps
T988 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1032346866 Jul 05 04:27:43 PM PDT 24 Jul 05 04:27:48 PM PDT 24 26959304 ps
T989 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3956455885 Jul 05 04:27:21 PM PDT 24 Jul 05 04:27:23 PM PDT 24 136942012 ps
T990 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2526987240 Jul 05 04:27:32 PM PDT 24 Jul 05 04:27:34 PM PDT 24 38110877 ps
T991 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4079849836 Jul 05 04:27:12 PM PDT 24 Jul 05 04:27:13 PM PDT 24 18912189 ps
T131 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3332118320 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:39 PM PDT 24 333756653 ps
T992 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1611487067 Jul 05 04:27:48 PM PDT 24 Jul 05 04:27:55 PM PDT 24 169336317 ps
T993 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.227733522 Jul 05 04:27:29 PM PDT 24 Jul 05 04:27:37 PM PDT 24 35393561 ps
T994 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1060550421 Jul 05 04:27:40 PM PDT 24 Jul 05 04:27:43 PM PDT 24 33498859 ps
T995 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.4193229443 Jul 05 04:28:28 PM PDT 24 Jul 05 04:28:43 PM PDT 24 175079400 ps
T996 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2360233194 Jul 05 04:27:27 PM PDT 24 Jul 05 04:27:30 PM PDT 24 35829083 ps
T997 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3237158467 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:38 PM PDT 24 21137385 ps
T998 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3163512274 Jul 05 04:27:11 PM PDT 24 Jul 05 04:27:13 PM PDT 24 70934536 ps
T999 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3740084125 Jul 05 04:27:25 PM PDT 24 Jul 05 04:27:27 PM PDT 24 43649552 ps
T1000 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1973675015 Jul 05 04:27:28 PM PDT 24 Jul 05 04:27:37 PM PDT 24 230578088 ps
T1001 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1436987073 Jul 05 04:27:15 PM PDT 24 Jul 05 04:27:17 PM PDT 24 204425527 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%