Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323145394

1

T5

74880

T6

1940

T7

2724

auto[1]

429338

1

T5

244

T7

562

T25

90

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323125842

1

T5

74798

T6

1940

T7

2840

auto[1]

448890

1

T5

326

T7

446

T25

138

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323072276

1

T5

74870

T6

1940

T7

2856

auto[1]

502456

1

T5

254

T7

430

T25

422

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304515446

1

T5

74048

T6

1940

T7

344

auto[1]

19059286

1

T5

1076

T7

2942

T25

3902

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171945038

1

T5

70296

T6

1940

T7

3134

auto[1]

151629694

1

T5

4828

T7

152

T25

3012

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

155400428

1

T5

69930

T6

1940

T7

226

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

148746036

1

T5

3878

T25

72

T18

476

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

32124

1

T5

14

T7

16

T22

96

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8192

1

T25

90

T2

44

T3

90

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

15909394

1

T5

98

T7

2282

T25

874

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2764706

1

T5

878

T7

74

T25

2724

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55724

1

T7

132

T22

162

T46

46

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12592

1

T7

8

T2

102

T3

356

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

87068

1

T21

8

T2

12

T29

38

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1564

1

T22

66

T2

2

T3

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11314

1

T2

220

T32

56

T155

52

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2944

1

T2

50

T3

86

T32

46

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

12274

1

T7

38

T25

26

T46

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2756

1

T5

26

T32

2

T156

16

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19806

1

T7

80

T46

60

T2

346

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5354

1

T5

46

T32

50

T101

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38338

1

T25

86

T21

34

T2

52

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4132

1

T2

12

T156

8

T131

34

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32464

1

T2

258

T3

562

T39

92

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7488

1

T2

112

T157

46

T158

64

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32956

1

T7

20

T25

140

T2

294

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8224

1

T25

84

T2

18

T3

566

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

58370

1

T7

82

T2

420

T3

2186

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14674

1

T2

58

T3

426

T32

38

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

73156

1

T5

42

T7

40

T25

58

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6054

1

T2

8

T3

20

T39

28

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52046

1

T5

184

T7

62

T22

56

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12098

1

T3

56

T108

72

T157

50

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

45854

1

T5

28

T7

38

T25

12

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12454

1

T7

6

T25

42

T2

92

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

83722

1

T7

118

T22

330

T46

80

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20426

1

T7

64

T2

348

T3

852