Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 353280536 1 T4 5058 T1 104261 T5 3188
auto[1] 428196 1 T1 382 T5 370 T18 344


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 353343142 1 T4 3696 T1 104284 T5 3418
auto[1] 365590 1 T4 1362 T1 156 T5 140


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 353205822 1 T4 5058 T1 104273 T5 3298
auto[1] 502910 1 T1 266 T5 260 T18 400


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331259200 1 T4 5058 T1 104234 T5 1166
auto[1] 22449532 1 T1 660 T5 2392 T18 706


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 183509224 1 T4 5038 T1 104029 T5 3464
auto[1] 170199508 1 T4 20 T1 2708 T5 94


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 168542164 1 T4 3676 T1 103950 T5 600
auto[0] auto[0] auto[0] auto[0] auto[1] 162393774 1 T4 20 T1 2708 T5 68
auto[0] auto[0] auto[0] auto[1] auto[0] 30198 1 T1 68 T5 140 T18 6
auto[0] auto[0] auto[0] auto[1] auto[1] 7586 1 T18 16 T2 116 T3 104
auto[0] auto[0] auto[1] auto[0] auto[0] 14388150 1 T1 380 T5 2326 T18 458
auto[0] auto[0] auto[1] auto[0] auto[1] 7685558 1 T2 6470 T3 260 T9 816
auto[0] auto[0] auto[1] auto[1] auto[0] 54554 1 T1 72 T5 66 T18 34
auto[0] auto[0] auto[1] auto[1] auto[1] 13424 1 T2 314 T3 80 T9 130
auto[0] auto[1] auto[0] auto[0] auto[0] 36462 1 T4 1362 T5 8 T2 84
auto[0] auto[1] auto[0] auto[0] auto[1] 1462 1 T2 26 T3 76 T24 12
auto[0] auto[1] auto[0] auto[1] auto[0] 12776 1 T5 90 T2 48 T3 96
auto[0] auto[1] auto[0] auto[1] auto[1] 2798 1 T2 130 T3 216 T24 58
auto[0] auto[1] auto[1] auto[0] auto[0] 10232 1 T2 122 T3 164 T9 140
auto[0] auto[1] auto[1] auto[0] auto[1] 3046 1 T2 190 T3 90 T9 40
auto[0] auto[1] auto[1] auto[1] auto[0] 18010 1 T2 194 T3 290 T9 204
auto[0] auto[1] auto[1] auto[1] auto[1] 5628 1 T2 76 T3 232 T9 138
auto[1] auto[0] auto[0] auto[0] auto[0] 70784 1 T5 118 T18 34 T2 52
auto[1] auto[0] auto[0] auto[0] auto[1] 4066 1 T5 26 T18 18 T2 8
auto[1] auto[0] auto[0] auto[1] auto[0] 34466 1 T5 74 T18 80 T2 262
auto[1] auto[0] auto[0] auto[1] auto[1] 9598 1 T18 54 T2 120 T3 102
auto[1] auto[0] auto[1] auto[0] auto[0] 30086 1 T1 10 T18 18 T2 498
auto[1] auto[0] auto[1] auto[0] auto[1] 7204 1 T2 142 T3 110 T9 56
auto[1] auto[0] auto[1] auto[1] auto[0] 57166 1 T1 100 T18 80 T2 488
auto[1] auto[0] auto[1] auto[1] auto[1] 14364 1 T2 246 T9 152 T10 268
auto[1] auto[1] auto[0] auto[0] auto[0] 47258 1 T1 10 T5 42 T2 456
auto[1] auto[1] auto[0] auto[0] auto[1] 6306 1 T2 52 T3 16 T9 162
auto[1] auto[1] auto[0] auto[1] auto[0] 47754 1 T1 48 T2 624 T9 282
auto[1] auto[1] auto[0] auto[1] auto[1] 11748 1 T2 78 T3 78 T9 120
auto[1] auto[1] auto[1] auto[0] auto[0] 42712 1 T1 4 T18 42 T2 866
auto[1] auto[1] auto[1] auto[0] auto[1] 11272 1 T2 104 T9 86 T10 96
auto[1] auto[1] auto[1] auto[1] auto[0] 86452 1 T1 94 T18 74 T2 1152
auto[1] auto[1] auto[1] auto[1] auto[1] 21674 1 T2 286 T9 202 T10 222

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