Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308760836

1

T6

3128

T7

1960

T8

1868

auto[1]

417956

1

T6

288

T8

94

T1

82

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308807944

1

T6

3302

T7

1960

T8

1802

auto[1]

370848

1

T6

114

T8

160

T1

74

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308704268

1

T6

3134

T7

1960

T8

1700

auto[1]

474524

1

T6

282

T8

262

T1

74

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

293620990

1

T6

684

T7

1960

T8

1246

auto[1]

15557802

1

T6

2732

T8

716

T1

1764

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167487912

1

T6

786

T7

1938

T8

1826

auto[1]

141690880

1

T6

2630

T7

22

T8

136

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

157562608

1

T6

372

T7

1938

T8

1200

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

135748228

1

T6

88

T7

22

T1

1038

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

31350

1

T6

16

T22

40

T3

32

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8218

1

T22

22

T3

44

T77

50

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

9365538

1

T6

128

T8

370

T19

104

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5830870

1

T6

2466

T8

98

T1

1664

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51484

1

T8

32

T19

6

T23

26

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11852

1

T6

10

T1

26

T19

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44152

1

T22

12

T3

98

T12

28

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1420

1

T3

28

T12

28

T118

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10310

1

T22

62

T14

116

T118

62

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2072

1

T3

72

T118

114

T83

78

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10826

1

T22

8

T3

12

T77

40

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1796

1

T6

2

T3

84

T77

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19300

1

T22

54

T3

144

T12

82

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4244

1

T6

52

T3

66

T77

76

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43198

1

T6

34

T22

14

T3

20

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3626

1

T3

26

T79

20

T14

22

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34354

1

T6

114

T22

48

T3

92

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7450

1

T3

74

T79

64

T14

62

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

28096

1

T6

24

T8

40

T23

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7710

1

T19

2

T23

32

T12

16

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

58886

1

T6

50

T8

62

T23

50

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14476

1

T19

60

T23

64

T12

66

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

55978

1

T6

2

T8

46

T19

24

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6176

1

T6

12

T22

8

T77

12

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48480

1

T6

46

T19

40

T3

72

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13370

1

T22

68

T77

128

T14

186

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

41182

1

T8

76

T19

2

T22

36

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9432

1

T8

38

T1

18

T3

70

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

82170

1

T19

60

T3

422

T77

250

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19940

1

T1

56

T3

74

T14

476