SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
io_div2_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div2_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
shadow_update_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19210 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 796 | 1 | T1 | 4 | T2 | 2 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16405 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 3601 | 1 | T3 | 46 | T12 | 26 | T14 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19210 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 796 | 1 | T1 | 2 | T2 | 1 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16450 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 3556 | 1 | T3 | 40 | T12 | 30 | T14 | 47 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19189 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 817 | 1 | T1 | 2 | T2 | 2 | T3 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16404 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 3602 | 1 | T3 | 46 | T12 | 26 | T14 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19263 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 743 | 1 | T1 | 2 | T2 | 1 | T3 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19124 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 882 | 1 | T3 | 9 | T12 | 8 | T14 | 15 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19838 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 168 | 1 | T61 | 4 | T62 | 2 | T63 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19205 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 801 | 1 | T1 | 2 | T2 | 1 | T25 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19090 | 1 | T6 | 1 | T7 | 1 | T8 | 1 | ||||
auto[1] | 916 | 1 | T3 | 13 | T12 | 6 | T14 | 10 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |