Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313489040

1

T5

35868

T6

3922

T7

3254

auto[1]

394900

1

T6

614

T7

94

T22

790

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313453626

1

T5

35868

T6

4034

T7

2926

auto[1]

430314

1

T6

502

T7

422

T22

554

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313431672

1

T5

35868

T6

3870

T7

2892

auto[1]

452268

1

T6

666

T7

456

T22

646

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294435584

1

T5

35868

T6

914

T7

668

auto[1]

19448356

1

T6

3622

T7

2680

T22

2302

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177746226

1

T5

35822

T6

4122

T7

3238

auto[1]

136137714

1

T5

46

T6

414

T7

110

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

163187782

1

T5

35822

T6

472

T7

562

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

130900856

1

T5

46

T6

176

T21

114

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

26660

1

T6

52

T22

70

T24

96

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7492

1

T6

30

T24

24

T3

242

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

13976758

1

T6

3030

T7

2136

T22

414

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5126556

1

T6

90

T7

52

T22

1502

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46786

1

T6

12

T7

32

T22

70

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11268

1

T22

22

T3

418

T86

82

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

92218

1

T7

20

T22

16

T24

32

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1186

1

T22

8

T24

58

T3

72

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11704

1

T22

42

T24

84

T3

150

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2560

1

T22

58

T162

64

T70

116

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10384

1

T6

8

T7

90

T22

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2790

1

T3

78

T12

14

T13

78

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20962

1

T3

206

T12

204

T13

340

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5710

1

T13

52

T27

52

T29

78

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

30118

1

T6

8

T7

56

T22

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3494

1

T6

2

T3

50

T86

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29922

1

T22

114

T24

204

T3

314

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7542

1

T6

50

T3

212

T108

58

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

26870

1

T6

16

T7

26

T22

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5614

1

T3

134

T86

2

T12

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

53106

1

T6

96

T7

62

T22

80

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12802

1

T3

206

T86

46

T12

56

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

68084

1

T6

26

T7

30

T22

56

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6110

1

T6

10

T24

2

T3

242

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46536

1

T6

40

T22

166

T24

54

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13320

1

T6

48

T24

94

T3

296

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40458

1

T6

76

T7

224

T22

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9762

1

T6

8

T7

58

T22

24

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

77878

1

T6

286

T24

64

T3

1472

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20652

1

T22

168

T3

1146

T86

36