Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 329568250 1 T5 2792 T6 3924 T7 4638
auto[1] 393626 1 T5 480 T6 66 T23 366


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 329599760 1 T5 2868 T6 3590 T7 4638
auto[1] 362116 1 T5 404 T6 400 T4 6064


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 329480356 1 T5 2790 T6 3504 T7 4638
auto[1] 481520 1 T5 482 T6 486 T4 6064


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 304174488 1 T5 482 T6 2694 T7 4638
auto[1] 25787388 1 T5 2790 T6 1296 T23 620


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 205657000 1 T5 3098 T6 3580 T7 1112
auto[1] 124304876 1 T5 174 T6 410 T7 3526


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 181923202 1 T5 340 T6 2320 T7 1112
auto[0] auto[0] auto[0] auto[0] auto[1] 121941296 1 T6 178 T7 3526 T4 30
auto[0] auto[0] auto[0] auto[1] auto[0] 27046 1 T5 30 T23 14 T24 18
auto[0] auto[0] auto[0] auto[1] auto[1] 6796 1 T2 186 T3 68 T9 136
auto[0] auto[0] auto[1] auto[0] auto[0] 23188870 1 T5 2162 T6 804 T23 318
auto[0] auto[0] auto[1] auto[0] auto[1] 2255360 1 T5 62 T6 116 T23 74
auto[0] auto[0] auto[1] auto[1] auto[0] 47184 1 T5 76 T23 22 T24 48
auto[0] auto[0] auto[1] auto[1] auto[1] 11740 1 T5 36 T1 28 T2 182
auto[0] auto[1] auto[0] auto[0] auto[0] 29004 1 T2 88 T3 150 T9 168
auto[0] auto[1] auto[0] auto[0] auto[1] 1150 1 T6 28 T1 24 T2 22
auto[0] auto[1] auto[0] auto[1] auto[0] 10984 1 T2 88 T3 136 T9 228
auto[0] auto[1] auto[0] auto[1] auto[1] 2342 1 T1 60 T2 70 T3 78
auto[0] auto[1] auto[1] auto[0] auto[0] 9518 1 T5 26 T6 58 T24 16
auto[0] auto[1] auto[1] auto[0] auto[1] 2196 1 T23 10 T2 42 T3 238
auto[0] auto[1] auto[1] auto[1] auto[0] 17354 1 T5 58 T2 484 T3 80
auto[0] auto[1] auto[1] auto[1] auto[1] 6314 1 T2 114 T3 74 T9 280
auto[1] auto[0] auto[0] auto[0] auto[0] 56468 1 T5 42 T23 2 T1 18
auto[1] auto[0] auto[0] auto[0] auto[1] 3290 1 T1 16 T3 50 T9 56
auto[1] auto[0] auto[0] auto[1] auto[0] 30662 1 T23 62 T1 146 T2 196
auto[1] auto[0] auto[0] auto[1] auto[1] 7094 1 T1 64 T3 254 T9 248
auto[1] auto[0] auto[1] auto[0] auto[0] 27350 1 T5 54 T6 74 T1 54
auto[1] auto[0] auto[1] auto[0] auto[1] 6166 1 T6 32 T24 16 T1 6
auto[1] auto[0] auto[1] auto[1] auto[0] 53964 1 T5 66 T6 66 T1 298
auto[1] auto[0] auto[1] auto[1] auto[1] 13272 1 T24 50 T1 44 T2 268
auto[1] auto[1] auto[0] auto[0] auto[0] 69268 1 T5 14 T6 112 T4 6064
auto[1] auto[1] auto[0] auto[0] auto[1] 5860 1 T6 56 T2 94 T3 170
auto[1] auto[1] auto[0] auto[1] auto[0] 47678 1 T5 56 T23 136 T24 66
auto[1] auto[1] auto[0] auto[1] auto[1] 12348 1 T2 276 T3 90 T9 246
auto[1] auto[1] auto[1] auto[0] auto[0] 39848 1 T5 72 T6 146 T23 64
auto[1] auto[1] auto[1] auto[0] auto[1] 9404 1 T5 20 T1 10 T2 54
auto[1] auto[1] auto[1] auto[1] auto[0] 78600 1 T5 102 T23 132 T1 328
auto[1] auto[1] auto[1] auto[1] auto[1] 20248 1 T5 56 T1 64 T2 278

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