Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 326984026 1 T4 5276 T5 3160 T6 2808
auto[1] 391542 1 T5 534 T6 296 T1 2232


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 326984468 1 T4 5276 T5 3394 T6 2866
auto[1] 391100 1 T5 300 T6 238 T1 1452


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 326925626 1 T4 5276 T5 3160 T6 2862
auto[1] 449942 1 T5 534 T6 242 T1 2060


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 313352014 1 T4 5276 T5 402 T6 392
auto[1] 14023554 1 T5 3292 T6 2712 T1 526228


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 194389158 1 T4 1748 T5 3372 T6 1008
auto[1] 132986410 1 T4 3528 T5 322 T6 2096


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 182783242 1 T4 1748 T5 262 T6 256
auto[0] auto[0] auto[0] auto[0] auto[1] 130241580 1 T4 3528 T6 20 T1 235788
auto[0] auto[0] auto[0] auto[1] auto[0] 29934 1 T5 30 T6 48 T1 144
auto[0] auto[0] auto[0] auto[1] auto[1] 6940 1 T98 10 T12 32 T130 22
auto[0] auto[0] auto[1] auto[0] auto[0] 11042598 1 T5 2498 T6 418 T1 524170
auto[0] auto[0] auto[1] auto[0] auto[1] 2637380 1 T5 208 T6 1986 T1 88
auto[0] auto[0] auto[1] auto[1] auto[0] 48280 1 T5 80 T6 32 T1 388
auto[0] auto[0] auto[1] auto[1] auto[1] 11364 1 T5 82 T1 24 T2 30
auto[0] auto[1] auto[0] auto[0] auto[0] 69662 1 T6 2 T1 2 T2 30
auto[0] auto[1] auto[0] auto[0] auto[1] 1558 1 T11 6 T12 50 T124 8
auto[0] auto[1] auto[0] auto[1] auto[0] 11222 1 T6 52 T1 66 T2 154
auto[0] auto[1] auto[0] auto[1] auto[1] 3274 1 T11 48 T12 128 T124 94
auto[0] auto[1] auto[1] auto[0] auto[0] 10756 1 T6 2 T2 58 T16 26
auto[0] auto[1] auto[1] auto[0] auto[1] 3556 1 T12 12 T130 50 T151 8
auto[0] auto[1] auto[1] auto[1] auto[0] 19828 1 T6 46 T2 234 T16 60
auto[0] auto[1] auto[1] auto[1] auto[1] 4452 1 T12 56 T15 82 T152 60
auto[1] auto[0] auto[0] auto[0] auto[0] 41216 1 T5 30 T6 14 T1 34
auto[1] auto[0] auto[0] auto[0] auto[1] 4134 1 T16 8 T65 100 T130 18
auto[1] auto[0] auto[0] auto[1] auto[0] 31242 1 T2 64 T22 224 T98 90
auto[1] auto[0] auto[0] auto[1] auto[1] 7680 1 T130 54 T153 48 T154 102
auto[1] auto[0] auto[1] auto[0] auto[0] 28892 1 T5 26 T6 10 T1 106
auto[1] auto[0] auto[1] auto[0] auto[1] 6640 1 T5 32 T6 20 T1 24
auto[1] auto[0] auto[1] auto[1] auto[0] 51968 1 T5 146 T6 62 T1 446
auto[1] auto[0] auto[1] auto[1] auto[1] 11378 1 T1 66 T2 120 T22 62
auto[1] auto[1] auto[0] auto[0] auto[0] 56806 1 T5 14 T1 78 T2 2
auto[1] auto[1] auto[0] auto[0] auto[1] 5340 1 T23 34 T65 46 T98 2
auto[1] auto[1] auto[0] auto[1] auto[0] 46266 1 T5 66 T1 390 T2 72
auto[1] auto[1] auto[0] auto[1] auto[1] 11918 1 T98 42 T12 98 T131 200
auto[1] auto[1] auto[1] auto[0] auto[0] 40580 1 T5 90 T6 10 T1 208
auto[1] auto[1] auto[1] auto[0] auto[1] 10086 1 T6 70 T2 122 T22 70
auto[1] auto[1] auto[1] auto[1] auto[0] 76666 1 T5 130 T6 56 T1 708
auto[1] auto[1] auto[1] auto[1] auto[1] 19130 1 T2 126 T22 252 T97 66

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%