Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.80	100.00	100.00	98.81	97.02	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.4219968252			Jul 12 06:35:46 PM PDT 24	Jul 12 06:35:48 PM PDT 24	16286691 ps
T1002	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.690971263			Jul 12 06:35:56 PM PDT 24	Jul 12 06:35:58 PM PDT 24	12815277 ps
T1003	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3983416113			Jul 12 06:35:53 PM PDT 24	Jul 12 06:35:55 PM PDT 24	104084241 ps
T1004	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2083026032			Jul 12 06:35:45 PM PDT 24	Jul 12 06:35:48 PM PDT 24	114169707 ps
T1005	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3710350888			Jul 12 06:35:57 PM PDT 24	Jul 12 06:35:59 PM PDT 24	223562536 ps
T1006	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.4129425952			Jul 12 06:35:40 PM PDT 24	Jul 12 06:35:43 PM PDT 24	15047579 ps
T1007	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2312001136			Jul 12 06:36:04 PM PDT 24	Jul 12 06:36:07 PM PDT 24	13081738 ps
T1008	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1805844469			Jul 12 06:36:04 PM PDT 24	Jul 12 06:36:06 PM PDT 24	10747720 ps
T1009	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4153045429			Jul 12 06:36:01 PM PDT 24	Jul 12 06:36:02 PM PDT 24	13081189 ps
T1010	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2382045946			Jul 12 06:36:00 PM PDT 24	Jul 12 06:36:02 PM PDT 24	72367234 ps

Test location	/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.1823483753
Short name	T1
Test name
Test status
Simulation time	80886184638 ps
CPU time	523.27 seconds
Started	Jul 12 05:50:36 PM PDT 24
Finished	Jul 12 05:59:21 PM PDT 24
Peak memory	209164 kb
Host	smart-9dbf0237-a175-441e-a6e5-3c3fb10e0d77
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1823483753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1823483753
Directory	/workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.clkmgr_regwen.4158447080
Short name	T96
Test name
Test status
Simulation time	881750438 ps
CPU time	5.28 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:51:23 PM PDT 24
Peak memory	200616 kb
Host	smart-9f06dd57-47b5-44b4-9925-d347f7f3af07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158447080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.4158447080
Directory	/workspace/43.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1684007684
Short name	T50
Test name
Test status
Simulation time	364887630 ps
CPU time	2.78 seconds
Started	Jul 12 06:35:57 PM PDT 24
Finished	Jul 12 06:36:01 PM PDT 24
Peak memory	200848 kb
Host	smart-202b0ef3-69cf-417e-ae66-065a482f6aac
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684007684 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.clkmgr_shadow_reg_errors.1684007684
Directory	/workspace/18.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all.4128147318
Short name	T2
Test name
Test status
Simulation time	6019127481 ps
CPU time	20.81 seconds
Started	Jul 12 05:49:51 PM PDT 24
Finished	Jul 12 05:50:12 PM PDT 24
Peak memory	200828 kb
Host	smart-8e281552-5c45-4128-b90a-102aa94b9797
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128147318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.4128147318
Directory	/workspace/6.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/1.clkmgr_sec_cm.2165639516
Short name	T38
Test name
Test status
Simulation time	148227835 ps
CPU time	1.97 seconds
Started	Jul 12 05:49:36 PM PDT 24
Finished	Jul 12 05:49:39 PM PDT 24
Peak memory	220208 kb
Host	smart-192a6e0d-d06a-46d5-b755-c566bcb3dc3f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165639516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg r_sec_cm.2165639516
Directory	/workspace/1.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_status.1475893158
Short name	T21
Test name
Test status
Simulation time	17137958 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	199708 kb
Host	smart-57d0135d-0e34-45f0-9b16-2dcf423a68e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475893158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1475893158
Directory	/workspace/16.clkmgr_clk_status/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2100000487
Short name	T113
Test name
Test status
Simulation time	103679605 ps
CPU time	1.3 seconds
Started	Jul 12 06:35:54 PM PDT 24
Finished	Jul 12 06:35:56 PM PDT 24
Peak memory	200752 kb
Host	smart-bb5ecb39-869d-4832-bfcc-3e5fcb07e81f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100000487 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.clkmgr_shadow_reg_errors.2100000487
Directory	/workspace/17.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/0.clkmgr_idle_intersig_mubi.2266142314
Short name	T41
Test name
Test status
Simulation time	92931191 ps
CPU time	1.23 seconds
Started	Jul 12 05:49:28 PM PDT 24
Finished	Jul 12 05:49:33 PM PDT 24
Peak memory	200508 kb
Host	smart-3b0918a7-adaa-41d2-a63c-47145028c0f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266142314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.2266142314
Directory	/workspace/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.2222443230
Short name	T12
Test name
Test status
Simulation time	180225488393 ps
CPU time	1216.54 seconds
Started	Jul 12 05:50:32 PM PDT 24
Finished	Jul 12 06:10:52 PM PDT 24
Peak memory	209176 kb
Host	smart-7f8a29f6-1398-4d71-9ff2-1ef7ad6d2adf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2222443230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.2222443230
Directory	/workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2160863899
Short name	T89
Test name
Test status
Simulation time	942022322 ps
CPU time	4.73 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:51 PM PDT 24
Peak memory	200552 kb
Host	smart-2451e983-17ee-4750-86d6-0bf4e7b049c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160863899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.2160863899
Directory	/workspace/10.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.4267946209
Short name	T141
Test name
Test status
Simulation time	424933253543 ps
CPU time	1649.02 seconds
Started	Jul 12 05:50:12 PM PDT 24
Finished	Jul 12 06:17:42 PM PDT 24
Peak memory	213144 kb
Host	smart-851ad01c-db32-4857-a38b-8f038465da65
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4267946209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.4267946209
Directory	/workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2525417206
Short name	T71
Test name
Test status
Simulation time	50632991 ps
CPU time	1.29 seconds
Started	Jul 12 06:35:46 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200576 kb
Host	smart-7584275f-c27b-4246-97ce-5155036d69a0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525417206 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.clkmgr_same_csr_outstanding.2525417206
Directory	/workspace/10.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/default/16.clkmgr_alert_test.1783975980
Short name	T171
Test name
Test status
Simulation time	15002391 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200600 kb
Host	smart-6c0571ca-267e-4872-88b5-3e73dc4127e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783975980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk mgr_alert_test.1783975980
Directory	/workspace/16.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all.844818504
Short name	T68
Test name
Test status
Simulation time	4304973994 ps
CPU time	30.15 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:43 PM PDT 24
Peak memory	200860 kb
Host	smart-5bdd03d2-01be-4f51-8c89-d9bcaa178321
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844818504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.844818504
Directory	/workspace/38.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1116097377
Short name	T112
Test name
Test status
Simulation time	376809008 ps
CPU time	2.51 seconds
Started	Jul 12 06:35:39 PM PDT 24
Finished	Jul 12 06:35:43 PM PDT 24
Peak memory	200896 kb
Host	smart-9760ec4a-2b90-442a-a260-b530cbef9a58
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116097377 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.clkmgr_shadow_reg_errors.1116097377
Directory	/workspace/9.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/24.clkmgr_regwen.1754557659
Short name	T8
Test name
Test status
Simulation time	1213162963 ps
CPU time	6.37 seconds
Started	Jul 12 05:50:30 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	200652 kb
Host	smart-8c5c794b-4f91-4eee-83ea-8a3afd51e885
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754557659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.1754557659
Directory	/workspace/24.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2048901546
Short name	T85
Test name
Test status
Simulation time	321364550 ps
CPU time	3.02 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	200552 kb
Host	smart-c24391b2-4058-44ac-b84e-199ae2f09e11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048901546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 19.clkmgr_tl_intg_err.2048901546
Directory	/workspace/19.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1961685322
Short name	T109
Test name
Test status
Simulation time	394544490 ps
CPU time	2.63 seconds
Started	Jul 12 06:35:20 PM PDT 24
Finished	Jul 12 06:35:24 PM PDT 24
Peak memory	200848 kb
Host	smart-bb5078bd-84f4-4ed5-a662-2cb188798f28
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961685322 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.clkmgr_shadow_reg_errors.1961685322
Directory	/workspace/0.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3714674750
Short name	T79
Test name
Test status
Simulation time	26396733 ps
CPU time	0.97 seconds
Started	Jul 12 05:49:29 PM PDT 24
Finished	Jul 12 05:49:33 PM PDT 24
Peak memory	200568 kb
Host	smart-b436d505-bb27-46ca-a0f2-38dd557ae427
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714674750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.3714674750
Directory	/workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.770966888
Short name	T120
Test name
Test status
Simulation time	109608203 ps
CPU time	1.43 seconds
Started	Jul 12 06:35:20 PM PDT 24
Finished	Jul 12 06:35:23 PM PDT 24
Peak memory	200784 kb
Host	smart-bd5a92ca-cac1-4f21-838e-a91aa0079492
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770966888 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.clkmgr_shadow_reg_errors.770966888
Directory	/workspace/1.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all.3941171343
Short name	T35
Test name
Test status
Simulation time	10098869541 ps
CPU time	42.83 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:51:00 PM PDT 24
Peak memory	201076 kb
Host	smart-678bf1cf-5008-4349-a286-fd1cd1298205
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941171343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.3941171343
Directory	/workspace/16.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.868931620
Short name	T95
Test name
Test status
Simulation time	100224945 ps
CPU time	1.76 seconds
Started	Jul 12 06:35:50 PM PDT 24
Finished	Jul 12 06:35:53 PM PDT 24
Peak memory	200552 kb
Host	smart-7b804dbc-d469-4328-8e7e-e1c44c7ed5a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868931620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.clkmgr_tl_intg_err.868931620
Directory	/workspace/12.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3979355039
Short name	T892
Test name
Test status
Simulation time	64354230 ps
CPU time	1.22 seconds
Started	Jul 12 06:35:19 PM PDT 24
Finished	Jul 12 06:35:22 PM PDT 24
Peak memory	200460 kb
Host	smart-65f91488-b9ef-448a-a86b-b7a47f0a6393
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979355039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_aliasing.3979355039
Directory	/workspace/0.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.4213582093
Short name	T931
Test name
Test status
Simulation time	1856523153 ps
CPU time	11.6 seconds
Started	Jul 12 06:35:20 PM PDT 24
Finished	Jul 12 06:35:33 PM PDT 24
Peak memory	200536 kb
Host	smart-b7a6a65b-8bf2-4647-b98d-13f27d553c95
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213582093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_bit_bash.4213582093
Directory	/workspace/0.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.616503751
Short name	T1000
Test name
Test status
Simulation time	68339421 ps
CPU time	0.96 seconds
Started	Jul 12 06:35:19 PM PDT 24
Finished	Jul 12 06:35:22 PM PDT 24
Peak memory	200460 kb
Host	smart-46b9e1cd-91a6-4aa3-973f-82497cd6bb49
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616503751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.clkmgr_csr_hw_reset.616503751
Directory	/workspace/0.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1598961098
Short name	T862
Test name
Test status
Simulation time	33873034 ps
CPU time	1.67 seconds
Started	Jul 12 06:35:17 PM PDT 24
Finished	Jul 12 06:35:20 PM PDT 24
Peak memory	200668 kb
Host	smart-e6d0587d-c523-491d-a5cf-1516bcfb13a0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598961098 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.1598961098
Directory	/workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3756461809
Short name	T886
Test name
Test status
Simulation time	22184818 ps
CPU time	0.87 seconds
Started	Jul 12 06:35:18 PM PDT 24
Finished	Jul 12 06:35:20 PM PDT 24
Peak memory	200372 kb
Host	smart-878a117d-e8f2-407b-9056-11598b1c55ab
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756461809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. clkmgr_csr_rw.3756461809
Directory	/workspace/0.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.938535825
Short name	T912
Test name
Test status
Simulation time	34245416 ps
CPU time	0.7 seconds
Started	Jul 12 06:35:17 PM PDT 24
Finished	Jul 12 06:35:18 PM PDT 24
Peak memory	198956 kb
Host	smart-0caf267f-868d-4868-8175-cefb5162551a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938535825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm gr_intr_test.938535825
Directory	/workspace/0.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.232811678
Short name	T938
Test name
Test status
Simulation time	37700008 ps
CPU time	1.15 seconds
Started	Jul 12 06:35:18 PM PDT 24
Finished	Jul 12 06:35:21 PM PDT 24
Peak memory	200444 kb
Host	smart-85154713-5033-41d2-812d-3b9efc67a02b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232811678 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.clkmgr_same_csr_outstanding.232811678
Directory	/workspace/0.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4024103983
Short name	T111
Test name
Test status
Simulation time	576849290 ps
CPU time	3.8 seconds
Started	Jul 12 06:35:19 PM PDT 24
Finished	Jul 12 06:35:25 PM PDT 24
Peak memory	217256 kb
Host	smart-3213158d-eda1-4b49-bc60-5e29e77dd98d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024103983 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.4024103983
Directory	/workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3932978375
Short name	T911
Test name
Test status
Simulation time	41549128 ps
CPU time	1.37 seconds
Started	Jul 12 06:35:18 PM PDT 24
Finished	Jul 12 06:35:21 PM PDT 24
Peak memory	200576 kb
Host	smart-4a2d38a6-d7a7-4db3-b481-08607dd1d018
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932978375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_tl_errors.3932978375
Directory	/workspace/0.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3085632971
Short name	T925
Test name
Test status
Simulation time	201896326 ps
CPU time	2.47 seconds
Started	Jul 12 06:35:17 PM PDT 24
Finished	Jul 12 06:35:21 PM PDT 24
Peak memory	200608 kb
Host	smart-fc06027e-6845-4a58-87ac-3e1a67726069
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085632971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 0.clkmgr_tl_intg_err.3085632971
Directory	/workspace/0.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2289846192
Short name	T910
Test name
Test status
Simulation time	57076576 ps
CPU time	1.71 seconds
Started	Jul 12 06:35:21 PM PDT 24
Finished	Jul 12 06:35:24 PM PDT 24
Peak memory	200596 kb
Host	smart-eebe80cf-7d1d-46d0-8774-75334d568f5d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289846192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_aliasing.2289846192
Directory	/workspace/1.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2533093085
Short name	T913
Test name
Test status
Simulation time	902108946 ps
CPU time	5.84 seconds
Started	Jul 12 06:35:21 PM PDT 24
Finished	Jul 12 06:35:28 PM PDT 24
Peak memory	200516 kb
Host	smart-016b47b1-3025-4e9f-8eec-7406c7ffe73c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533093085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_bit_bash.2533093085
Directory	/workspace/1.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2361626049
Short name	T870
Test name
Test status
Simulation time	25047756 ps
CPU time	0.87 seconds
Started	Jul 12 06:35:21 PM PDT 24
Finished	Jul 12 06:35:23 PM PDT 24
Peak memory	200436 kb
Host	smart-a89c72c5-b7cd-45a4-a889-c45deac85b20
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361626049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_hw_reset.2361626049
Directory	/workspace/1.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.656034155
Short name	T989
Test name
Test status
Simulation time	42801751 ps
CPU time	1.01 seconds
Started	Jul 12 06:35:20 PM PDT 24
Finished	Jul 12 06:35:22 PM PDT 24
Peak memory	200556 kb
Host	smart-5b6c7984-4a3c-444a-9b20-a27e074ebe4a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656034155 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.656034155
Directory	/workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3258007780
Short name	T971
Test name
Test status
Simulation time	69098788 ps
CPU time	0.94 seconds
Started	Jul 12 06:35:24 PM PDT 24
Finished	Jul 12 06:35:26 PM PDT 24
Peak memory	200412 kb
Host	smart-221cc538-80d2-4bc9-a5e6-d65c8abfa9e7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258007780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. clkmgr_csr_rw.3258007780
Directory	/workspace/1.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1051257789
Short name	T964
Test name
Test status
Simulation time	17169682 ps
CPU time	0.71 seconds
Started	Jul 12 06:35:29 PM PDT 24
Finished	Jul 12 06:35:31 PM PDT 24
Peak memory	198976 kb
Host	smart-5b9099ab-3198-4fb7-937a-3524fe5a92fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051257789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_intr_test.1051257789
Directory	/workspace/1.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.895691798
Short name	T876
Test name
Test status
Simulation time	89865335 ps
CPU time	1.24 seconds
Started	Jul 12 06:35:22 PM PDT 24
Finished	Jul 12 06:35:24 PM PDT 24
Peak memory	200708 kb
Host	smart-dfdbdbbd-c1c9-48d4-9aec-262c8af401bf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895691798 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.clkmgr_same_csr_outstanding.895691798
Directory	/workspace/1.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3091185755
Short name	T58
Test name
Test status
Simulation time	714815405 ps
CPU time	4.5 seconds
Started	Jul 12 06:35:18 PM PDT 24
Finished	Jul 12 06:35:23 PM PDT 24
Peak memory	209120 kb
Host	smart-f71cc21a-ad5d-44f9-8c30-48ddb0609873
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091185755 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.3091185755
Directory	/workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1324064785
Short name	T955
Test name
Test status
Simulation time	232090012 ps
CPU time	2.13 seconds
Started	Jul 12 06:35:18 PM PDT 24
Finished	Jul 12 06:35:22 PM PDT 24
Peak memory	200592 kb
Host	smart-1e8c8bb4-a2cd-4426-8ec0-fe98b13bc214
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324064785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_tl_errors.1324064785
Directory	/workspace/1.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1975692747
Short name	T84
Test name
Test status
Simulation time	218150371 ps
CPU time	2.61 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	200592 kb
Host	smart-3d9e7712-f37b-4ebb-9e0f-e8b6daa479b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975692747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 1.clkmgr_tl_intg_err.1975692747
Directory	/workspace/1.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2553141075
Short name	T974
Test name
Test status
Simulation time	23767623 ps
CPU time	0.93 seconds
Started	Jul 12 06:35:47 PM PDT 24
Finished	Jul 12 06:35:49 PM PDT 24
Peak memory	200504 kb
Host	smart-f68f3ffb-7d97-4a16-b156-2364ac5a841c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553141075 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2553141075
Directory	/workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.4219968252
Short name	T1001
Test name
Test status
Simulation time	16286691 ps
CPU time	0.8 seconds
Started	Jul 12 06:35:46 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200436 kb
Host	smart-0a4bb017-0162-4f7d-919f-07c338719971
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219968252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .clkmgr_csr_rw.4219968252
Directory	/workspace/10.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1018027315
Short name	T896
Test name
Test status
Simulation time	32913610 ps
CPU time	0.69 seconds
Started	Jul 12 06:35:47 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	198988 kb
Host	smart-ea9621e8-03f0-4e0b-ae5b-a0bd730c2467
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018027315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_intr_test.1018027315
Directory	/workspace/10.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2308079232
Short name	T954
Test name
Test status
Simulation time	111464263 ps
CPU time	1.29 seconds
Started	Jul 12 06:35:37 PM PDT 24
Finished	Jul 12 06:35:39 PM PDT 24
Peak memory	200768 kb
Host	smart-04c598c2-b62b-4017-9cbb-bb20e1e05489
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308079232 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.clkmgr_shadow_reg_errors.2308079232
Directory	/workspace/10.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.106079551
Short name	T979
Test name
Test status
Simulation time	248678927 ps
CPU time	2.31 seconds
Started	Jul 12 06:35:39 PM PDT 24
Finished	Jul 12 06:35:43 PM PDT 24
Peak memory	209080 kb
Host	smart-b3aa8635-f4c5-4b75-b02c-a62707651b75
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106079551 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.106079551
Directory	/workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.3264518540
Short name	T867
Test name
Test status
Simulation time	30613272 ps
CPU time	1.69 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:41 PM PDT 24
Peak memory	200496 kb
Host	smart-7b9e8f34-810a-43a5-83da-158abcc5f1cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264518540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_tl_errors.3264518540
Directory	/workspace/10.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.4038210210
Short name	T994
Test name
Test status
Simulation time	43318156 ps
CPU time	1.23 seconds
Started	Jul 12 06:35:46 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200532 kb
Host	smart-d30b7d9c-89c5-4543-ae08-eaa9184e3538
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038210210 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.4038210210
Directory	/workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.124491502
Short name	T857
Test name
Test status
Simulation time	54511102 ps
CPU time	0.93 seconds
Started	Jul 12 06:35:48 PM PDT 24
Finished	Jul 12 06:35:50 PM PDT 24
Peak memory	200368 kb
Host	smart-12ef12cc-69d6-4dda-beec-f79495d5ffc1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124491502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. clkmgr_csr_rw.124491502
Directory	/workspace/11.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1986186162
Short name	T880
Test name
Test status
Simulation time	11729415 ps
CPU time	0.66 seconds
Started	Jul 12 06:35:47 PM PDT 24
Finished	Jul 12 06:35:49 PM PDT 24
Peak memory	199020 kb
Host	smart-10b06042-967b-45c7-b70f-6ae7c9871756
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986186162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_intr_test.1986186162
Directory	/workspace/11.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2058142525
Short name	T996
Test name
Test status
Simulation time	38824044 ps
CPU time	1.31 seconds
Started	Jul 12 06:35:46 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200444 kb
Host	smart-80cc5a16-b27f-4836-a78b-ca91909268cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058142525 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.clkmgr_same_csr_outstanding.2058142525
Directory	/workspace/11.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2462842793
Short name	T110
Test name
Test status
Simulation time	93603502 ps
CPU time	1.79 seconds
Started	Jul 12 06:35:50 PM PDT 24
Finished	Jul 12 06:35:53 PM PDT 24
Peak memory	217264 kb
Host	smart-c2297198-9520-4d02-b8e9-c1c4cfa0d139
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462842793 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.clkmgr_shadow_reg_errors.2462842793
Directory	/workspace/11.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.707087549
Short name	T926
Test name
Test status
Simulation time	439967996 ps
CPU time	3.34 seconds
Started	Jul 12 06:42:08 PM PDT 24
Finished	Jul 12 06:42:12 PM PDT 24
Peak memory	209124 kb
Host	smart-e776a8de-dffe-41dc-999c-96fbdd0f30d5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707087549 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.707087549
Directory	/workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.144550949
Short name	T889
Test name
Test status
Simulation time	79775229 ps
CPU time	2.49 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200564 kb
Host	smart-47298d06-566c-4867-8aed-b530d4ac36c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144550949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk mgr_tl_errors.144550949
Directory	/workspace/11.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2468985098
Short name	T94
Test name
Test status
Simulation time	231186171 ps
CPU time	2.07 seconds
Started	Jul 12 06:35:48 PM PDT 24
Finished	Jul 12 06:35:51 PM PDT 24
Peak memory	200556 kb
Host	smart-145de72c-574a-4543-808c-f816e83e012f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468985098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 11.clkmgr_tl_intg_err.2468985098
Directory	/workspace/11.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3997147093
Short name	T941
Test name
Test status
Simulation time	32510666 ps
CPU time	1.72 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:47 PM PDT 24
Peak memory	208776 kb
Host	smart-4876b8de-07c0-49ad-ae88-3fbb4dc7b86f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997147093 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3997147093
Directory	/workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3153263714
Short name	T942
Test name
Test status
Simulation time	11986217 ps
CPU time	0.76 seconds
Started	Jul 12 06:35:46 PM PDT 24
Finished	Jul 12 06:35:47 PM PDT 24
Peak memory	200388 kb
Host	smart-71538a30-4b8c-45cb-9456-e6c9486206f9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153263714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .clkmgr_csr_rw.3153263714
Directory	/workspace/12.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1555311434
Short name	T947
Test name
Test status
Simulation time	56930420 ps
CPU time	0.77 seconds
Started	Jul 12 06:35:48 PM PDT 24
Finished	Jul 12 06:35:50 PM PDT 24
Peak memory	198984 kb
Host	smart-8b4c052c-5015-4ca8-95b6-b55506957009
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555311434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.1555311434
Directory	/workspace/12.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.748903622
Short name	T74
Test name
Test status
Simulation time	110278075 ps
CPU time	1.44 seconds
Started	Jul 12 06:35:50 PM PDT 24
Finished	Jul 12 06:35:53 PM PDT 24
Peak memory	200584 kb
Host	smart-05669944-29c4-4e4c-b58c-3fe4f7c1331c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748903622 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 12.clkmgr_same_csr_outstanding.748903622
Directory	/workspace/12.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2058109739
Short name	T995
Test name
Test status
Simulation time	121645974 ps
CPU time	2.01 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200872 kb
Host	smart-8f30261c-cbe5-42b9-9eea-69f4c190124b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058109739 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 12.clkmgr_shadow_reg_errors.2058109739
Directory	/workspace/12.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1838919611
Short name	T56
Test name
Test status
Simulation time	78690981 ps
CPU time	1.69 seconds
Started	Jul 12 06:35:48 PM PDT 24
Finished	Jul 12 06:35:50 PM PDT 24
Peak memory	217256 kb
Host	smart-35949785-f314-4004-8ebc-d56ba5f663ef
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838919611 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1838919611
Directory	/workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3601827740
Short name	T959
Test name
Test status
Simulation time	1823005420 ps
CPU time	7.07 seconds
Started	Jul 12 06:35:48 PM PDT 24
Finished	Jul 12 06:35:56 PM PDT 24
Peak memory	200532 kb
Host	smart-a1d62178-dc86-4b88-b60f-19665b3333e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601827740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_tl_errors.3601827740
Directory	/workspace/12.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.4201199812
Short name	T879
Test name
Test status
Simulation time	108648234 ps
CPU time	1.6 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200604 kb
Host	smart-84a264ed-9826-41c2-8374-c3f9e4db4b44
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201199812 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.4201199812
Directory	/workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2178511826
Short name	T878
Test name
Test status
Simulation time	24643262 ps
CPU time	0.8 seconds
Started	Jul 12 06:35:49 PM PDT 24
Finished	Jul 12 06:35:51 PM PDT 24
Peak memory	200464 kb
Host	smart-b8a8eeda-c139-4d0a-8919-445244736fac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178511826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .clkmgr_csr_rw.2178511826
Directory	/workspace/13.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.435672348
Short name	T923
Test name
Test status
Simulation time	19895108 ps
CPU time	0.7 seconds
Started	Jul 12 06:35:50 PM PDT 24
Finished	Jul 12 06:35:52 PM PDT 24
Peak memory	199168 kb
Host	smart-cd581e3e-82d6-4bb0-9dbb-275d50a4eec3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435672348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk mgr_intr_test.435672348
Directory	/workspace/13.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1352132687
Short name	T70
Test name
Test status
Simulation time	108280617 ps
CPU time	1.26 seconds
Started	Jul 12 06:35:48 PM PDT 24
Finished	Jul 12 06:35:50 PM PDT 24
Peak memory	200500 kb
Host	smart-44203b87-a47d-48cf-a7b3-80b03914e639
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352132687 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.clkmgr_same_csr_outstanding.1352132687
Directory	/workspace/13.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1862982930
Short name	T51
Test name
Test status
Simulation time	152635840 ps
CPU time	1.44 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200804 kb
Host	smart-aa5a80fe-f950-4e9d-940c-9c10a6eb8725
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862982930 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.1862982930
Directory	/workspace/13.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.443217858
Short name	T57
Test name
Test status
Simulation time	151513403 ps
CPU time	2.74 seconds
Started	Jul 12 06:35:49 PM PDT 24
Finished	Jul 12 06:35:53 PM PDT 24
Peak memory	217260 kb
Host	smart-0c54ee44-42e1-41fb-9cf4-71230c28e473
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443217858 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.443217858
Directory	/workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3346075460
Short name	T851
Test name
Test status
Simulation time	159200205 ps
CPU time	1.64 seconds
Started	Jul 12 06:35:47 PM PDT 24
Finished	Jul 12 06:35:50 PM PDT 24
Peak memory	200424 kb
Host	smart-2283f517-7918-43be-b0e9-57a58434f666
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346075460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_tl_errors.3346075460
Directory	/workspace/13.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.731848282
Short name	T92
Test name
Test status
Simulation time	71052053 ps
CPU time	1.85 seconds
Started	Jul 12 06:35:47 PM PDT 24
Finished	Jul 12 06:35:49 PM PDT 24
Peak memory	200536 kb
Host	smart-94b0adf4-f071-4b22-8298-f0e8e502f2eb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731848282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.clkmgr_tl_intg_err.731848282
Directory	/workspace/13.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3710350888
Short name	T1005
Test name
Test status
Simulation time	223562536 ps
CPU time	1.57 seconds
Started	Jul 12 06:35:57 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	200428 kb
Host	smart-4eaad936-cb87-4a7e-9eae-295675ddfcac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710350888 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.3710350888
Directory	/workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2246746708
Short name	T924
Test name
Test status
Simulation time	37614402 ps
CPU time	0.81 seconds
Started	Jul 12 06:35:48 PM PDT 24
Finished	Jul 12 06:35:50 PM PDT 24
Peak memory	200396 kb
Host	smart-ebae236a-e88d-4e09-b4e2-06bda5757f8a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246746708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .clkmgr_csr_rw.2246746708
Directory	/workspace/14.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.250440066
Short name	T884
Test name
Test status
Simulation time	36004345 ps
CPU time	0.73 seconds
Started	Jul 12 06:35:47 PM PDT 24
Finished	Jul 12 06:35:49 PM PDT 24
Peak memory	198924 kb
Host	smart-beeb344b-481d-4931-a3a8-bb234c66bf0d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250440066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk mgr_intr_test.250440066
Directory	/workspace/14.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.647694566
Short name	T898
Test name
Test status
Simulation time	54261373 ps
CPU time	0.99 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:54 PM PDT 24
Peak memory	200352 kb
Host	smart-5a4d7386-9136-41f5-b0ef-f465f350faee
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647694566 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 14.clkmgr_same_csr_outstanding.647694566
Directory	/workspace/14.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.4187446910
Short name	T49
Test name
Test status
Simulation time	84103395 ps
CPU time	1.34 seconds
Started	Jul 12 06:35:49 PM PDT 24
Finished	Jul 12 06:35:51 PM PDT 24
Peak memory	200752 kb
Host	smart-3ba29415-d184-4e53-9e0d-dc998aa5ef72
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187446910 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.clkmgr_shadow_reg_errors.4187446910
Directory	/workspace/14.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.2516744793
Short name	T55
Test name
Test status
Simulation time	131218555 ps
CPU time	1.81 seconds
Started	Jul 12 06:35:49 PM PDT 24
Finished	Jul 12 06:35:52 PM PDT 24
Peak memory	209212 kb
Host	smart-dec8294f-3d53-4037-acc5-94175265b6ce
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516744793 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.2516744793
Directory	/workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2083026032
Short name	T1004
Test name
Test status
Simulation time	114169707 ps
CPU time	3.17 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200564 kb
Host	smart-167fea86-f48f-43c4-814a-0c9fa8958694
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083026032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.2083026032
Directory	/workspace/14.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3761647605
Short name	T91
Test name
Test status
Simulation time	82721183 ps
CPU time	1.59 seconds
Started	Jul 12 06:35:47 PM PDT 24
Finished	Jul 12 06:35:50 PM PDT 24
Peak memory	200600 kb
Host	smart-f95d9dc4-825b-4d14-8978-677d5186d50a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761647605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.clkmgr_tl_intg_err.3761647605
Directory	/workspace/14.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2382045946
Short name	T1010
Test name
Test status
Simulation time	72367234 ps
CPU time	1.41 seconds
Started	Jul 12 06:36:00 PM PDT 24
Finished	Jul 12 06:36:02 PM PDT 24
Peak memory	200532 kb
Host	smart-2c1c3c8c-f6ff-4e2c-a32b-a6f0e5453d40
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382045946 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.2382045946
Directory	/workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2586972982
Short name	T865
Test name
Test status
Simulation time	82502119 ps
CPU time	0.93 seconds
Started	Jul 12 06:35:58 PM PDT 24
Finished	Jul 12 06:36:00 PM PDT 24
Peak memory	200364 kb
Host	smart-90c86988-6b2b-417d-9986-e7e2ddcaa919
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586972982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .clkmgr_csr_rw.2586972982
Directory	/workspace/15.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.690971263
Short name	T1002
Test name
Test status
Simulation time	12815277 ps
CPU time	0.67 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:58 PM PDT 24
Peak memory	198964 kb
Host	smart-e020a1c6-50fc-406f-8159-093aea260e3f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690971263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk mgr_intr_test.690971263
Directory	/workspace/15.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1821549906
Short name	T962
Test name
Test status
Simulation time	44797700 ps
CPU time	1.26 seconds
Started	Jul 12 06:36:00 PM PDT 24
Finished	Jul 12 06:36:01 PM PDT 24
Peak memory	200452 kb
Host	smart-45ba3a26-0b45-4e81-a2bb-57594905bfe3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821549906 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.clkmgr_same_csr_outstanding.1821549906
Directory	/workspace/15.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3983416113
Short name	T1003
Test name
Test status
Simulation time	104084241 ps
CPU time	1.51 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:55 PM PDT 24
Peak memory	200764 kb
Host	smart-5fd917c1-3ec5-4eec-a3d1-3187b8573170
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983416113 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.3983416113
Directory	/workspace/15.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1055183657
Short name	T937
Test name
Test status
Simulation time	882185755 ps
CPU time	4.86 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:09 PM PDT 24
Peak memory	201176 kb
Host	smart-8c0193ea-5582-4fed-b54e-fdf0d2985150
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055183657 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.1055183657
Directory	/workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2969962440
Short name	T945
Test name
Test status
Simulation time	58023352 ps
CPU time	1.85 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:55 PM PDT 24
Peak memory	200600 kb
Host	smart-373940ac-1b7c-4bc7-beaa-53cd86feea82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969962440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_tl_errors.2969962440
Directory	/workspace/15.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3391043761
Short name	T907
Test name
Test status
Simulation time	99939783 ps
CPU time	2.51 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	200528 kb
Host	smart-c8fabc65-9ca9-49b9-878a-47d718e21969
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391043761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.clkmgr_tl_intg_err.3391043761
Directory	/workspace/15.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2436851883
Short name	T978
Test name
Test status
Simulation time	69338399 ps
CPU time	1.09 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:58 PM PDT 24
Peak memory	200520 kb
Host	smart-dc5e5a5b-8b00-4958-9f57-2781a808b421
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436851883 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.2436851883
Directory	/workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3388821708
Short name	T872
Test name
Test status
Simulation time	15680314 ps
CPU time	0.8 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	200380 kb
Host	smart-a15436c5-f469-4b05-a2a6-bcd9506f325c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388821708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .clkmgr_csr_rw.3388821708
Directory	/workspace/16.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2741106759
Short name	T902
Test name
Test status
Simulation time	12437030 ps
CPU time	0.65 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:55 PM PDT 24
Peak memory	198944 kb
Host	smart-b434a842-fa47-4bb8-b84f-bed04b9cc620
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741106759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_intr_test.2741106759
Directory	/workspace/16.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2341613727
Short name	T934
Test name
Test status
Simulation time	39890461 ps
CPU time	0.96 seconds
Started	Jul 12 06:35:57 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	200484 kb
Host	smart-7a1149cb-9f65-49d7-9c5e-cfea709ff9e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341613727 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.clkmgr_same_csr_outstanding.2341613727
Directory	/workspace/16.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3411011728
Short name	T993
Test name
Test status
Simulation time	321992939 ps
CPU time	2.44 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	200836 kb
Host	smart-7223a07b-bd97-45c8-be4f-7e63813fb6af
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411011728 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.clkmgr_shadow_reg_errors.3411011728
Directory	/workspace/16.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.171135428
Short name	T957
Test name
Test status
Simulation time	161170664 ps
CPU time	2.85 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:56 PM PDT 24
Peak memory	201216 kb
Host	smart-c23fbd95-f41d-4f7b-b95c-9090eeb9d991
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171135428 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.171135428
Directory	/workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.801956935
Short name	T958
Test name
Test status
Simulation time	242077724 ps
CPU time	3.69 seconds
Started	Jul 12 06:35:57 PM PDT 24
Finished	Jul 12 06:36:01 PM PDT 24
Peak memory	200572 kb
Host	smart-e701601d-4b60-4b3a-bce8-0d5fa69af1ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801956935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk mgr_tl_errors.801956935
Directory	/workspace/16.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2067053873
Short name	T150
Test name
Test status
Simulation time	212375524 ps
CPU time	2.86 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	200600 kb
Host	smart-5be4a034-549b-4e37-85c1-a76f0d21df92
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067053873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.clkmgr_tl_intg_err.2067053873
Directory	/workspace/16.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.2726390735
Short name	T900
Test name
Test status
Simulation time	27556786 ps
CPU time	1.04 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:55 PM PDT 24
Peak memory	200464 kb
Host	smart-a03bffe2-5372-42f2-a7e5-0ab3f6edf68f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726390735 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.2726390735
Directory	/workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1616233236
Short name	T909
Test name
Test status
Simulation time	20893618 ps
CPU time	0.86 seconds
Started	Jul 12 06:35:54 PM PDT 24
Finished	Jul 12 06:35:56 PM PDT 24
Peak memory	200460 kb
Host	smart-051fceb5-19fa-4f66-895a-d260e37669ec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616233236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .clkmgr_csr_rw.1616233236
Directory	/workspace/17.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1829907032
Short name	T888
Test name
Test status
Simulation time	17585084 ps
CPU time	0.73 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:05 PM PDT 24
Peak memory	198972 kb
Host	smart-ea768e19-ba7e-45e5-a898-b72e50c28aff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829907032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_intr_test.1829907032
Directory	/workspace/17.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1278185881
Short name	T75
Test name
Test status
Simulation time	35519053 ps
CPU time	1.04 seconds
Started	Jul 12 06:35:54 PM PDT 24
Finished	Jul 12 06:35:56 PM PDT 24
Peak memory	200436 kb
Host	smart-b0be5005-c783-4c8b-a0b8-da315f5642d8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278185881 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.clkmgr_same_csr_outstanding.1278185881
Directory	/workspace/17.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3297464372
Short name	T53
Test name
Test status
Simulation time	156650318 ps
CPU time	1.84 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:56 PM PDT 24
Peak memory	217252 kb
Host	smart-87882e94-c846-4fa8-8460-18f19983add9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297464372 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.3297464372
Directory	/workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2267205322
Short name	T855
Test name
Test status
Simulation time	52785164 ps
CPU time	1.66 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	200580 kb
Host	smart-2bb80bb9-a6c0-4f55-92aa-266a82ed83b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267205322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_tl_errors.2267205322
Directory	/workspace/17.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1543809340
Short name	T952
Test name
Test status
Simulation time	185610406 ps
CPU time	2.79 seconds
Started	Jul 12 06:35:57 PM PDT 24
Finished	Jul 12 06:36:01 PM PDT 24
Peak memory	200536 kb
Host	smart-5e25a9a3-d499-4a6a-b6a8-c4da9e05cd67
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543809340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 17.clkmgr_tl_intg_err.1543809340
Directory	/workspace/17.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2687223970
Short name	T970
Test name
Test status
Simulation time	115039196 ps
CPU time	1.91 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	208820 kb
Host	smart-21a986b5-2ec4-49e9-af77-51c9aec5fe38
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687223970 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.2687223970
Directory	/workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1798098148
Short name	T984
Test name
Test status
Simulation time	14620177 ps
CPU time	0.77 seconds
Started	Jul 12 06:35:58 PM PDT 24
Finished	Jul 12 06:36:00 PM PDT 24
Peak memory	200428 kb
Host	smart-a4ce7b3c-95c1-460b-a9f5-bd393d801944
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798098148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .clkmgr_csr_rw.1798098148
Directory	/workspace/18.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.482567235
Short name	T997
Test name
Test status
Simulation time	14985867 ps
CPU time	0.7 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:55 PM PDT 24
Peak memory	199104 kb
Host	smart-f3b74925-52d1-47a3-b30f-e7685eacac4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482567235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk mgr_intr_test.482567235
Directory	/workspace/18.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3197241367
Short name	T946
Test name
Test status
Simulation time	142319358 ps
CPU time	1.48 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	200436 kb
Host	smart-6a520d63-93a2-491c-9086-25149bd8681f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197241367 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.clkmgr_same_csr_outstanding.3197241367
Directory	/workspace/18.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1185938031
Short name	T122
Test name
Test status
Simulation time	231891744 ps
CPU time	2.94 seconds
Started	Jul 12 06:35:53 PM PDT 24
Finished	Jul 12 06:35:57 PM PDT 24
Peak memory	209088 kb
Host	smart-aa6f2ca0-7450-4c8d-a199-9428608dec58
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185938031 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1185938031
Directory	/workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2407635655
Short name	T883
Test name
Test status
Simulation time	74081088 ps
CPU time	1.81 seconds
Started	Jul 12 06:35:56 PM PDT 24
Finished	Jul 12 06:35:59 PM PDT 24
Peak memory	200548 kb
Host	smart-cfdf4b47-e285-4d7c-9575-a24f65b0c36a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407635655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_tl_errors.2407635655
Directory	/workspace/18.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3012944338
Short name	T988
Test name
Test status
Simulation time	127083824 ps
CPU time	2.69 seconds
Started	Jul 12 06:36:01 PM PDT 24
Finished	Jul 12 06:36:04 PM PDT 24
Peak memory	200608 kb
Host	smart-0741bdc8-1902-4d68-b3ae-8088878fbb9f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012944338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.clkmgr_tl_intg_err.3012944338
Directory	/workspace/18.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.712403199
Short name	T976
Test name
Test status
Simulation time	22713354 ps
CPU time	1.11 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:03 PM PDT 24
Peak memory	200532 kb
Host	smart-2d25e580-79cb-4875-aa98-c134ad70056b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712403199 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.712403199
Directory	/workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1415209522
Short name	T72
Test name
Test status
Simulation time	14904968 ps
CPU time	0.73 seconds
Started	Jul 12 06:36:01 PM PDT 24
Finished	Jul 12 06:36:03 PM PDT 24
Peak memory	200392 kb
Host	smart-dcfaf21b-d9f1-4c74-8e28-1ed94e028537
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415209522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .clkmgr_csr_rw.1415209522
Directory	/workspace/19.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2312001136
Short name	T1007
Test name
Test status
Simulation time	13081738 ps
CPU time	0.69 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	198956 kb
Host	smart-c997bd0c-590a-4637-99c7-9094202bf4c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312001136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_intr_test.2312001136
Directory	/workspace/19.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1085614991
Short name	T927
Test name
Test status
Simulation time	37233763 ps
CPU time	1.09 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:04 PM PDT 24
Peak memory	200456 kb
Host	smart-4dfbfa9f-df69-4b7d-b789-b08f1f4f1fa4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085614991 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.clkmgr_same_csr_outstanding.1085614991
Directory	/workspace/19.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.607778318
Short name	T114
Test name
Test status
Simulation time	194813487 ps
CPU time	2.48 seconds
Started	Jul 12 06:35:54 PM PDT 24
Finished	Jul 12 06:35:57 PM PDT 24
Peak memory	217080 kb
Host	smart-9fdfacd4-e5f9-427e-8da5-dda5f17834dd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607778318 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 19.clkmgr_shadow_reg_errors.607778318
Directory	/workspace/19.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.363003476
Short name	T980
Test name
Test status
Simulation time	164939893 ps
CPU time	3.12 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:08 PM PDT 24
Peak memory	201028 kb
Host	smart-7b35fd10-2698-416c-8ce3-a54566e376eb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363003476 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.363003476
Directory	/workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.766419015
Short name	T850
Test name
Test status
Simulation time	90618697 ps
CPU time	1.88 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:05 PM PDT 24
Peak memory	200584 kb
Host	smart-c5e5e6ba-e6dc-44be-8627-85e4d6ac439d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766419015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk mgr_tl_errors.766419015
Directory	/workspace/19.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.169863853
Short name	T986
Test name
Test status
Simulation time	809581412 ps
CPU time	3.6 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:36 PM PDT 24
Peak memory	200464 kb
Host	smart-1211e192-6307-43d5-8e59-f6849504c831
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169863853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.clkmgr_csr_aliasing.169863853
Directory	/workspace/2.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1409623162
Short name	T966
Test name
Test status
Simulation time	678326295 ps
CPU time	6.95 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:39 PM PDT 24
Peak memory	200556 kb
Host	smart-1a5ad44a-cb4e-4801-86dd-05d1c33f351e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409623162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_bit_bash.1409623162
Directory	/workspace/2.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2492529038
Short name	T917
Test name
Test status
Simulation time	26682111 ps
CPU time	0.81 seconds
Started	Jul 12 06:35:23 PM PDT 24
Finished	Jul 12 06:35:25 PM PDT 24
Peak memory	200300 kb
Host	smart-3fbec2e3-f1cb-41ea-9235-ecc5bf95305a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492529038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_hw_reset.2492529038
Directory	/workspace/2.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1377665592
Short name	T939
Test name
Test status
Simulation time	158737711 ps
CPU time	1.61 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	200544 kb
Host	smart-bde347b8-83c3-4392-86d1-690e6fb0ae4a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377665592 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1377665592
Directory	/workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2349951728
Short name	T903
Test name
Test status
Simulation time	49966120 ps
CPU time	0.84 seconds
Started	Jul 12 06:35:22 PM PDT 24
Finished	Jul 12 06:35:24 PM PDT 24
Peak memory	200432 kb
Host	smart-e1df9d08-18f3-4549-9146-b4dbd598005c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349951728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. clkmgr_csr_rw.2349951728
Directory	/workspace/2.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3523509758
Short name	T919
Test name
Test status
Simulation time	14213929 ps
CPU time	0.69 seconds
Started	Jul 12 06:35:22 PM PDT 24
Finished	Jul 12 06:35:24 PM PDT 24
Peak memory	198980 kb
Host	smart-ce2a7f88-66b0-499e-868e-bbd9f0224d94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523509758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_intr_test.3523509758
Directory	/workspace/2.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.362856644
Short name	T983
Test name
Test status
Simulation time	24140010 ps
CPU time	0.99 seconds
Started	Jul 12 06:35:22 PM PDT 24
Finished	Jul 12 06:35:24 PM PDT 24
Peak memory	200384 kb
Host	smart-c38454fc-1a85-4da7-85f0-e9d80caef411
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362856644 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.clkmgr_same_csr_outstanding.362856644
Directory	/workspace/2.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.208666906
Short name	T54
Test name
Test status
Simulation time	473900880 ps
CPU time	2.19 seconds
Started	Jul 12 06:35:20 PM PDT 24
Finished	Jul 12 06:35:23 PM PDT 24
Peak memory	200760 kb
Host	smart-5362e422-dee9-40d8-9318-84464a18d7dd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208666906 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.clkmgr_shadow_reg_errors.208666906
Directory	/workspace/2.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2000428413
Short name	T123
Test name
Test status
Simulation time	92678119 ps
CPU time	1.73 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	200992 kb
Host	smart-0f4643f4-b1bc-4493-89e8-afb882b0bf8c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000428413 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.2000428413
Directory	/workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.1687493936
Short name	T894
Test name
Test status
Simulation time	535439288 ps
CPU time	4.53 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:36 PM PDT 24
Peak memory	200644 kb
Host	smart-e61496de-c049-49ca-8bee-3c1ad4f97876
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687493936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_tl_errors.1687493936
Directory	/workspace/2.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.14152878
Short name	T874
Test name
Test status
Simulation time	132213395 ps
CPU time	1.7 seconds
Started	Jul 12 06:35:27 PM PDT 24
Finished	Jul 12 06:35:29 PM PDT 24
Peak memory	200576 kb
Host	smart-b1b50555-bd57-474b-8a19-a6bbc0f211ef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14152878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.clkmgr_tl_intg_err.14152878
Directory	/workspace/2.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1805844469
Short name	T1008
Test name
Test status
Simulation time	10747720 ps
CPU time	0.65 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	198956 kb
Host	smart-a7fe8aa4-c236-49df-89ff-46eebc389e31
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805844469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl kmgr_intr_test.1805844469
Directory	/workspace/20.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1140243543
Short name	T906
Test name
Test status
Simulation time	14719548 ps
CPU time	0.7 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:04 PM PDT 24
Peak memory	199052 kb
Host	smart-67c245fe-dff3-4d46-b4ed-c04d3bdbed07
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140243543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl kmgr_intr_test.1140243543
Directory	/workspace/21.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3636849940
Short name	T918
Test name
Test status
Simulation time	15068592 ps
CPU time	0.68 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:04 PM PDT 24
Peak memory	199020 kb
Host	smart-14fef0c8-3d1c-46d4-bb33-6603fbadea0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636849940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl kmgr_intr_test.3636849940
Directory	/workspace/22.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.588567857
Short name	T854
Test name
Test status
Simulation time	11425443 ps
CPU time	0.71 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	198956 kb
Host	smart-41c2388f-77c5-4067-810a-96afb711ed39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588567857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clk mgr_intr_test.588567857
Directory	/workspace/23.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2430860799
Short name	T852
Test name
Test status
Simulation time	38264416 ps
CPU time	0.73 seconds
Started	Jul 12 06:36:01 PM PDT 24
Finished	Jul 12 06:36:02 PM PDT 24
Peak memory	199056 kb
Host	smart-b496d4bf-2caf-4565-aded-79d507827c39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430860799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl kmgr_intr_test.2430860799
Directory	/workspace/24.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2798267627
Short name	T860
Test name
Test status
Simulation time	35646198 ps
CPU time	0.75 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	198972 kb
Host	smart-2836df25-40d1-4c7c-92e9-b2205beb4d03
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798267627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl kmgr_intr_test.2798267627
Directory	/workspace/25.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3110138239
Short name	T981
Test name
Test status
Simulation time	19707560 ps
CPU time	0.68 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	198992 kb
Host	smart-691dd0f2-04f4-4eb3-b04e-364afdc42f8f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110138239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl kmgr_intr_test.3110138239
Directory	/workspace/26.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.102871604
Short name	T936
Test name
Test status
Simulation time	40683592 ps
CPU time	0.71 seconds
Started	Jul 12 06:36:05 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	198968 kb
Host	smart-4ed53e79-c484-4343-a6a4-fe890f16710c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102871604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clk mgr_intr_test.102871604
Directory	/workspace/27.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2963104505
Short name	T948
Test name
Test status
Simulation time	22679618 ps
CPU time	0.73 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:05 PM PDT 24
Peak memory	199040 kb
Host	smart-ddb03706-b182-4351-b49b-a57441fc6466
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963104505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl kmgr_intr_test.2963104505
Directory	/workspace/28.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.4089285910
Short name	T904
Test name
Test status
Simulation time	11758431 ps
CPU time	0.65 seconds
Started	Jul 12 06:36:06 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	198920 kb
Host	smart-997d91e7-4eae-4fc7-bd19-a5dbffb8cf84
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089285910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl kmgr_intr_test.4089285910
Directory	/workspace/29.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.298149078
Short name	T873
Test name
Test status
Simulation time	21978939 ps
CPU time	1.08 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:33 PM PDT 24
Peak memory	200320 kb
Host	smart-201029c1-1645-40c7-b5ee-8cb1e4485850
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298149078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.clkmgr_csr_aliasing.298149078
Directory	/workspace/3.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1239170221
Short name	T960
Test name
Test status
Simulation time	138488037 ps
CPU time	3.74 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	200532 kb
Host	smart-ef1a2c6e-ab5f-4fb8-9333-d27f06111478
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239170221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_bit_bash.1239170221
Directory	/workspace/3.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2674435533
Short name	T975
Test name
Test status
Simulation time	18537627 ps
CPU time	0.8 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	200368 kb
Host	smart-c55ea860-eefc-49c0-af24-c61fe008313c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674435533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.2674435533
Directory	/workspace/3.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.440586297
Short name	T882
Test name
Test status
Simulation time	55078024 ps
CPU time	1.06 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:33 PM PDT 24
Peak memory	200520 kb
Host	smart-237a0a98-d626-48e4-b61d-9d2c1b458c9e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440586297 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.440586297
Directory	/workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.784468283
Short name	T949
Test name
Test status
Simulation time	166604714 ps
CPU time	1.2 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	200444 kb
Host	smart-01390663-9c63-4372-9adb-f0d370d83345
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784468283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.c lkmgr_csr_rw.784468283
Directory	/workspace/3.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3078366597
Short name	T990
Test name
Test status
Simulation time	83786353 ps
CPU time	0.84 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:33 PM PDT 24
Peak memory	199280 kb
Host	smart-df06900d-df3c-4ef3-850c-0fc22a2ad118
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078366597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_intr_test.3078366597
Directory	/workspace/3.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.164471087
Short name	T991
Test name
Test status
Simulation time	37375285 ps
CPU time	1.23 seconds
Started	Jul 12 06:35:34 PM PDT 24
Finished	Jul 12 06:35:37 PM PDT 24
Peak memory	200544 kb
Host	smart-c4157b14-a92b-431e-8b0b-2b51a92a1157
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164471087 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.clkmgr_same_csr_outstanding.164471087
Directory	/workspace/3.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1237986743
Short name	T119
Test name
Test status
Simulation time	124326606 ps
CPU time	2.11 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	209060 kb
Host	smart-0c7b30e4-c69c-4cc7-b03d-83d4db7d3ea8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237986743 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.clkmgr_shadow_reg_errors.1237986743
Directory	/workspace/3.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3159675415
Short name	T969
Test name
Test status
Simulation time	160643245 ps
CPU time	3.03 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:36 PM PDT 24
Peak memory	209060 kb
Host	smart-b45d2515-77a1-4671-a99d-357576a89dbe
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159675415 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.3159675415
Directory	/workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2243561513
Short name	T901
Test name
Test status
Simulation time	197645769 ps
CPU time	2.91 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:37 PM PDT 24
Peak memory	200544 kb
Host	smart-afd0566c-5409-49ef-a2b9-da7e4ab5c9f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243561513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_tl_errors.2243561513
Directory	/workspace/3.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2893654364
Short name	T973
Test name
Test status
Simulation time	141177527 ps
CPU time	1.76 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	200524 kb
Host	smart-aca30624-ff38-494e-8b14-6363c08b6e27
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893654364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 3.clkmgr_tl_intg_err.2893654364
Directory	/workspace/3.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.977147883
Short name	T916
Test name
Test status
Simulation time	33115100 ps
CPU time	0.72 seconds
Started	Jul 12 06:36:05 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	198960 kb
Host	smart-18af536c-8065-4053-9e8c-fbc31bea663c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977147883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clk mgr_intr_test.977147883
Directory	/workspace/30.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1310740454
Short name	T897
Test name
Test status
Simulation time	29664272 ps
CPU time	0.71 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	199216 kb
Host	smart-13da0ad1-5571-4bee-9584-087ddfd63043
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310740454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl kmgr_intr_test.1310740454
Directory	/workspace/31.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3114307417
Short name	T875
Test name
Test status
Simulation time	25284580 ps
CPU time	0.69 seconds
Started	Jul 12 06:36:00 PM PDT 24
Finished	Jul 12 06:36:01 PM PDT 24
Peak memory	198988 kb
Host	smart-eca4fa8f-e429-42b8-bb72-8a6b3e9f19ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114307417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl kmgr_intr_test.3114307417
Directory	/workspace/32.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1921878843
Short name	T914
Test name
Test status
Simulation time	13301763 ps
CPU time	0.7 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:04 PM PDT 24
Peak memory	198868 kb
Host	smart-1030b067-9a97-4e4f-a8ab-5e2452a6ffbf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921878843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl kmgr_intr_test.1921878843
Directory	/workspace/33.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.257747436
Short name	T881
Test name
Test status
Simulation time	11784949 ps
CPU time	0.67 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:04 PM PDT 24
Peak memory	198968 kb
Host	smart-55e1ebff-de24-4433-9c4f-67a3c50fc3bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257747436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk mgr_intr_test.257747436
Directory	/workspace/34.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2999105187
Short name	T940
Test name
Test status
Simulation time	40880328 ps
CPU time	0.69 seconds
Started	Jul 12 06:36:01 PM PDT 24
Finished	Jul 12 06:36:02 PM PDT 24
Peak memory	199008 kb
Host	smart-570645a8-02e8-43ad-9521-073f67c02e8c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999105187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl kmgr_intr_test.2999105187
Directory	/workspace/35.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4153045429
Short name	T1009
Test name
Test status
Simulation time	13081189 ps
CPU time	0.71 seconds
Started	Jul 12 06:36:01 PM PDT 24
Finished	Jul 12 06:36:02 PM PDT 24
Peak memory	198968 kb
Host	smart-479ae714-c2cb-4df5-874f-3576b9156617
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153045429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl kmgr_intr_test.4153045429
Directory	/workspace/36.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.382165150
Short name	T863
Test name
Test status
Simulation time	13096621 ps
CPU time	0.76 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:03 PM PDT 24
Peak memory	198976 kb
Host	smart-bfa3a4e9-1564-4ef3-bf36-bb967268fd6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382165150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk mgr_intr_test.382165150
Directory	/workspace/37.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2047137908
Short name	T893
Test name
Test status
Simulation time	11654386 ps
CPU time	0.69 seconds
Started	Jul 12 06:36:05 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	198964 kb
Host	smart-3591f963-9fb5-4c66-bcbd-5bc878c1e344
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047137908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl kmgr_intr_test.2047137908
Directory	/workspace/38.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3441962768
Short name	T930
Test name
Test status
Simulation time	13419556 ps
CPU time	0.7 seconds
Started	Jul 12 06:36:02 PM PDT 24
Finished	Jul 12 06:36:04 PM PDT 24
Peak memory	198972 kb
Host	smart-d6c9c732-2862-4aa5-a554-a25b39b0203a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441962768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl kmgr_intr_test.3441962768
Directory	/workspace/39.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1880785677
Short name	T871
Test name
Test status
Simulation time	80449440 ps
CPU time	1.4 seconds
Started	Jul 12 06:35:35 PM PDT 24
Finished	Jul 12 06:35:37 PM PDT 24
Peak memory	200460 kb
Host	smart-0d1f24ad-cf58-40a3-ac6e-733078f8121e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880785677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_aliasing.1880785677
Directory	/workspace/4.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3057780515
Short name	T853
Test name
Test status
Simulation time	947956123 ps
CPU time	6.11 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:41 PM PDT 24
Peak memory	200608 kb
Host	smart-423f3402-ffc7-4daa-b420-444c95a66d6b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057780515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_bit_bash.3057780515
Directory	/workspace/4.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.96379924
Short name	T961
Test name
Test status
Simulation time	66090808 ps
CPU time	0.94 seconds
Started	Jul 12 06:35:29 PM PDT 24
Finished	Jul 12 06:35:31 PM PDT 24
Peak memory	200472 kb
Host	smart-ef541ea0-c9e8-44a6-996d-78290432c8f2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96379924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.clkmgr_csr_hw_reset.96379924
Directory	/workspace/4.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3080165355
Short name	T905
Test name
Test status
Simulation time	60722196 ps
CPU time	1.27 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	200548 kb
Host	smart-897aa48f-73b2-4563-96b5-8bae8a860f01
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080165355 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.3080165355
Directory	/workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3552774188
Short name	T858
Test name
Test status
Simulation time	71215864 ps
CPU time	1.03 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:33 PM PDT 24
Peak memory	200564 kb
Host	smart-521cc46c-dc95-488c-95e7-57ad625a58e8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552774188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.3552774188
Directory	/workspace/4.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3567981860
Short name	T868
Test name
Test status
Simulation time	12063079 ps
CPU time	0.66 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	198992 kb
Host	smart-47dfd806-1967-4901-9a1e-ad906ff2bf4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567981860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.3567981860
Directory	/workspace/4.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.88161960
Short name	T864
Test name
Test status
Simulation time	105141040 ps
CPU time	1.44 seconds
Started	Jul 12 06:35:33 PM PDT 24
Finished	Jul 12 06:35:36 PM PDT 24
Peak memory	200520 kb
Host	smart-64ce2dec-905e-413e-8f32-ef57c433b5a5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88161960 -assert nopostproc +UVM_TESTNAME=clkmgr_ba se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.clkmgr_same_csr_outstanding.88161960
Directory	/workspace/4.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1804914242
Short name	T115
Test name
Test status
Simulation time	221498957 ps
CPU time	1.99 seconds
Started	Jul 12 06:35:30 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	209040 kb
Host	smart-1f4440c5-7357-489a-b662-f5258bc35406
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804914242 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.clkmgr_shadow_reg_errors.1804914242
Directory	/workspace/4.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2992133350
Short name	T52
Test name
Test status
Simulation time	134395207 ps
CPU time	1.83 seconds
Started	Jul 12 06:35:29 PM PDT 24
Finished	Jul 12 06:35:32 PM PDT 24
Peak memory	209068 kb
Host	smart-74d6cc05-adcc-425f-a07f-57e244f163ed
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992133350 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2992133350
Directory	/workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2809155883
Short name	T866
Test name
Test status
Simulation time	158173383 ps
CPU time	3.74 seconds
Started	Jul 12 06:35:33 PM PDT 24
Finished	Jul 12 06:35:39 PM PDT 24
Peak memory	200476 kb
Host	smart-f221a474-6fb8-4b1f-88ca-0787c353a6d0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809155883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.2809155883
Directory	/workspace/4.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1530948233
Short name	T935
Test name
Test status
Simulation time	81441821 ps
CPU time	1.79 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:36 PM PDT 24
Peak memory	200564 kb
Host	smart-fb45d255-2cc6-4348-9e38-845e27e94bb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530948233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.1530948233
Directory	/workspace/4.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3511475564
Short name	T933
Test name
Test status
Simulation time	14095965 ps
CPU time	0.69 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:05 PM PDT 24
Peak memory	198972 kb
Host	smart-9770b424-376f-4ff8-86d1-b16b67c1869e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511475564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl kmgr_intr_test.3511475564
Directory	/workspace/40.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.964140009
Short name	T885
Test name
Test status
Simulation time	16860768 ps
CPU time	0.67 seconds
Started	Jul 12 06:36:37 PM PDT 24
Finished	Jul 12 06:36:40 PM PDT 24
Peak memory	198968 kb
Host	smart-b49470c3-62ae-4525-bb89-f5ec8e6d8dbf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964140009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk mgr_intr_test.964140009
Directory	/workspace/41.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2149297897
Short name	T953
Test name
Test status
Simulation time	23599340 ps
CPU time	0.68 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:05 PM PDT 24
Peak memory	198920 kb
Host	smart-4ac9cc18-a77f-4d33-881f-eab62c4482f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149297897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl kmgr_intr_test.2149297897
Directory	/workspace/42.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2457918307
Short name	T856
Test name
Test status
Simulation time	12612671 ps
CPU time	0.7 seconds
Started	Jul 12 06:36:04 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	199216 kb
Host	smart-11267316-8614-4888-ad2a-fc685989c1f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457918307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl kmgr_intr_test.2457918307
Directory	/workspace/43.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1151410935
Short name	T982
Test name
Test status
Simulation time	37699224 ps
CPU time	0.73 seconds
Started	Jul 12 06:36:05 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	199028 kb
Host	smart-ae2f90d6-9aea-4f36-945b-38b46f5e453c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151410935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl kmgr_intr_test.1151410935
Directory	/workspace/44.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1865960681
Short name	T992
Test name
Test status
Simulation time	12295204 ps
CPU time	0.66 seconds
Started	Jul 12 06:36:05 PM PDT 24
Finished	Jul 12 06:36:07 PM PDT 24
Peak memory	198940 kb
Host	smart-933d2caf-d260-4fbc-82b2-7796585a3a87
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865960681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl kmgr_intr_test.1865960681
Directory	/workspace/45.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3439660673
Short name	T891
Test name
Test status
Simulation time	31162465 ps
CPU time	0.75 seconds
Started	Jul 12 06:36:01 PM PDT 24
Finished	Jul 12 06:36:02 PM PDT 24
Peak memory	198988 kb
Host	smart-d697cd5e-4df9-447b-ac59-bb651171bedf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439660673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl kmgr_intr_test.3439660673
Directory	/workspace/46.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1883239628
Short name	T951
Test name
Test status
Simulation time	12965382 ps
CPU time	0.71 seconds
Started	Jul 12 06:36:03 PM PDT 24
Finished	Jul 12 06:36:06 PM PDT 24
Peak memory	198952 kb
Host	smart-88ef5b90-efca-4c18-9e9a-2655227dd82c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883239628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.1883239628
Directory	/workspace/47.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3690482721
Short name	T968
Test name
Test status
Simulation time	28521771 ps
CPU time	0.74 seconds
Started	Jul 12 06:35:59 PM PDT 24
Finished	Jul 12 06:36:01 PM PDT 24
Peak memory	199052 kb
Host	smart-26933397-543d-4156-98ee-bbf50b606c3c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690482721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl kmgr_intr_test.3690482721
Directory	/workspace/48.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.861198830
Short name	T915
Test name
Test status
Simulation time	13313321 ps
CPU time	0.73 seconds
Started	Jul 12 06:36:08 PM PDT 24
Finished	Jul 12 06:36:09 PM PDT 24
Peak memory	198976 kb
Host	smart-39c6917b-2f50-4e81-8d71-5b1e0e064168
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861198830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clk mgr_intr_test.861198830
Directory	/workspace/49.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1357122633
Short name	T963
Test name
Test status
Simulation time	41915444 ps
CPU time	1.23 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	200560 kb
Host	smart-9daba756-5dfd-4afd-af50-92486c8a6b62
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357122633 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1357122633
Directory	/workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2264606163
Short name	T908
Test name
Test status
Simulation time	22239872 ps
CPU time	0.84 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	200412 kb
Host	smart-6d5c7cab-1420-47ac-b3c1-7eccbe10ee74
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264606163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.2264606163
Directory	/workspace/5.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3978697797
Short name	T869
Test name
Test status
Simulation time	11899998 ps
CPU time	0.67 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	199032 kb
Host	smart-b404ba22-bee2-4405-a9e8-7f888df38822
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978697797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_intr_test.3978697797
Directory	/workspace/5.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2202556985
Short name	T69
Test name
Test status
Simulation time	32828925 ps
CPU time	1.01 seconds
Started	Jul 12 06:35:32 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	200388 kb
Host	smart-f4db4dee-bd61-4b1a-9fab-2b7d8e3c4dd6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202556985 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.clkmgr_same_csr_outstanding.2202556985
Directory	/workspace/5.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2120875818
Short name	T928
Test name
Test status
Simulation time	183187101 ps
CPU time	1.57 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	200708 kb
Host	smart-3e6dfa29-d45d-4894-84d2-dd4a9cbb3b33
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120875818 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.clkmgr_shadow_reg_errors.2120875818
Directory	/workspace/5.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3341882414
Short name	T118
Test name
Test status
Simulation time	156982049 ps
CPU time	2.07 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:35 PM PDT 24
Peak memory	209040 kb
Host	smart-0b2e996a-7160-4c5e-93dd-ee828cd4c77b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341882414 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3341882414
Directory	/workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2778096419
Short name	T920
Test name
Test status
Simulation time	22821898 ps
CPU time	1.34 seconds
Started	Jul 12 06:35:31 PM PDT 24
Finished	Jul 12 06:35:34 PM PDT 24
Peak memory	200480 kb
Host	smart-9b9c51d4-36c0-49e4-9e3a-2488eff88bf5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778096419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_tl_errors.2778096419
Directory	/workspace/5.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.219849511
Short name	T86
Test name
Test status
Simulation time	55558043 ps
CPU time	1.52 seconds
Started	Jul 12 06:35:29 PM PDT 24
Finished	Jul 12 06:35:31 PM PDT 24
Peak memory	200596 kb
Host	smart-cd3a8d1c-5885-49bd-95e9-ee2e626c77c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219849511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.clkmgr_tl_intg_err.219849511
Directory	/workspace/5.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.847587753
Short name	T877
Test name
Test status
Simulation time	24975314 ps
CPU time	1.19 seconds
Started	Jul 12 06:35:42 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	200536 kb
Host	smart-82c6d05a-ecd5-4aff-8ed3-0ddd85d4d00f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847587753 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.847587753
Directory	/workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3873854050
Short name	T921
Test name
Test status
Simulation time	16369657 ps
CPU time	0.82 seconds
Started	Jul 12 06:35:37 PM PDT 24
Finished	Jul 12 06:35:39 PM PDT 24
Peak memory	200436 kb
Host	smart-946df4ab-0f79-487f-95ba-595ec2ecd57b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873854050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. clkmgr_csr_rw.3873854050
Directory	/workspace/6.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.869170279
Short name	T987
Test name
Test status
Simulation time	13906430 ps
CPU time	0.69 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:40 PM PDT 24
Peak memory	199020 kb
Host	smart-16ab0f7a-862e-476e-93b4-adfe54525185
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869170279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm gr_intr_test.869170279
Directory	/workspace/6.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2859766014
Short name	T890
Test name
Test status
Simulation time	28991580 ps
CPU time	1.01 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:40 PM PDT 24
Peak memory	200436 kb
Host	smart-f2ba6ad3-d2f1-4761-ad64-134b57f98ec6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859766014 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.clkmgr_same_csr_outstanding.2859766014
Directory	/workspace/6.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2710268233
Short name	T117
Test name
Test status
Simulation time	443966784 ps
CPU time	2.37 seconds
Started	Jul 12 06:35:39 PM PDT 24
Finished	Jul 12 06:35:43 PM PDT 24
Peak memory	217188 kb
Host	smart-0edf70ac-6873-4d51-9786-7de0a2502883
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710268233 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.clkmgr_shadow_reg_errors.2710268233
Directory	/workspace/6.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2212142579
Short name	T121
Test name
Test status
Simulation time	510472053 ps
CPU time	3.53 seconds
Started	Jul 12 06:35:39 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	201192 kb
Host	smart-c17675e6-0b43-4c46-97e0-03d24378bfd8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212142579 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.2212142579
Directory	/workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2918430504
Short name	T943
Test name
Test status
Simulation time	98347567 ps
CPU time	2.81 seconds
Started	Jul 12 06:35:37 PM PDT 24
Finished	Jul 12 06:35:41 PM PDT 24
Peak memory	200568 kb
Host	smart-9a0d229e-0ffa-45e6-9306-166e61c824ec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918430504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_tl_errors.2918430504
Directory	/workspace/6.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1191393758
Short name	T93
Test name
Test status
Simulation time	828038325 ps
CPU time	3.44 seconds
Started	Jul 12 06:35:40 PM PDT 24
Finished	Jul 12 06:35:45 PM PDT 24
Peak memory	200524 kb
Host	smart-392cada9-c2bf-44e1-83c1-861ad4e7d460
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191393758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.1191393758
Directory	/workspace/6.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2951951611
Short name	T950
Test name
Test status
Simulation time	267492197 ps
CPU time	1.88 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:42 PM PDT 24
Peak memory	200504 kb
Host	smart-0b29e6ec-bd56-465d-8e3c-73d20cb02977
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951951611 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.2951951611
Directory	/workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2127252989
Short name	T999
Test name
Test status
Simulation time	73405723 ps
CPU time	0.95 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:41 PM PDT 24
Peak memory	200404 kb
Host	smart-4ee0bd46-0fac-40c2-94d5-92f108c73dcb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127252989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. clkmgr_csr_rw.2127252989
Directory	/workspace/7.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1881536412
Short name	T861
Test name
Test status
Simulation time	36870307 ps
CPU time	0.76 seconds
Started	Jul 12 06:35:37 PM PDT 24
Finished	Jul 12 06:35:39 PM PDT 24
Peak memory	198980 kb
Host	smart-c515aada-c40e-46b4-b70b-db5d7ae4e7be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881536412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_intr_test.1881536412
Directory	/workspace/7.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1346760471
Short name	T73
Test name
Test status
Simulation time	141602590 ps
CPU time	1.48 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:41 PM PDT 24
Peak memory	200452 kb
Host	smart-01fa369b-9f1c-4991-9639-70ec9b40dd9a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346760471 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.clkmgr_same_csr_outstanding.1346760471
Directory	/workspace/7.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2089739563
Short name	T985
Test name
Test status
Simulation time	131120825 ps
CPU time	1.33 seconds
Started	Jul 12 06:35:37 PM PDT 24
Finished	Jul 12 06:35:38 PM PDT 24
Peak memory	200768 kb
Host	smart-c31235e2-5ad4-4bed-9b62-3873801e25da
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089739563 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.clkmgr_shadow_reg_errors.2089739563
Directory	/workspace/7.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1212352475
Short name	T998
Test name
Test status
Simulation time	577444471 ps
CPU time	4.07 seconds
Started	Jul 12 06:35:41 PM PDT 24
Finished	Jul 12 06:35:46 PM PDT 24
Peak memory	201156 kb
Host	smart-88d80a47-b454-4a74-a4a6-e2be76b7f27d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212352475 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.1212352475
Directory	/workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1291490096
Short name	T956
Test name
Test status
Simulation time	192548439 ps
CPU time	2.4 seconds
Started	Jul 12 06:35:40 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	200488 kb
Host	smart-44d597c1-4e08-479f-b440-a8a9f19a27cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291490096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_tl_errors.1291490096
Directory	/workspace/7.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2028872433
Short name	T895
Test name
Test status
Simulation time	243831236 ps
CPU time	2.18 seconds
Started	Jul 12 06:35:40 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	200588 kb
Host	smart-addaecdc-f58e-4190-8336-6a6ef1723fd2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028872433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.2028872433
Directory	/workspace/7.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.419223801
Short name	T944
Test name
Test status
Simulation time	79517710 ps
CPU time	1.55 seconds
Started	Jul 12 06:35:41 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	200656 kb
Host	smart-c5c581fc-5d66-4ef1-ab6b-5ed750fe9da1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419223801 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.419223801
Directory	/workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3912551283
Short name	T965
Test name
Test status
Simulation time	16630746 ps
CPU time	0.81 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:40 PM PDT 24
Peak memory	200432 kb
Host	smart-cae6f145-5e22-456a-ad22-81d79be34af5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912551283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. clkmgr_csr_rw.3912551283
Directory	/workspace/8.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3476303046
Short name	T859
Test name
Test status
Simulation time	13135188 ps
CPU time	0.67 seconds
Started	Jul 12 06:35:38 PM PDT 24
Finished	Jul 12 06:35:41 PM PDT 24
Peak memory	198936 kb
Host	smart-c8e18d5c-e1e4-4038-bdfc-e78bf04f2225
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476303046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_intr_test.3476303046
Directory	/workspace/8.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3683895421
Short name	T922
Test name
Test status
Simulation time	30188455 ps
CPU time	1 seconds
Started	Jul 12 06:35:39 PM PDT 24
Finished	Jul 12 06:35:42 PM PDT 24
Peak memory	200468 kb
Host	smart-24f36b7e-811d-4fe5-8283-7cc5cc6c2edb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683895421 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.clkmgr_same_csr_outstanding.3683895421
Directory	/workspace/8.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1097976870
Short name	T932
Test name
Test status
Simulation time	103251754 ps
CPU time	1.48 seconds
Started	Jul 12 06:35:45 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	208952 kb
Host	smart-06e72222-8a27-4bc2-acd4-c216581a6c30
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097976870 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.clkmgr_shadow_reg_errors.1097976870
Directory	/workspace/8.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2935642929
Short name	T48
Test name
Test status
Simulation time	89202402 ps
CPU time	1.93 seconds
Started	Jul 12 06:35:39 PM PDT 24
Finished	Jul 12 06:35:43 PM PDT 24
Peak memory	209076 kb
Host	smart-80fc0555-9298-4cc0-9511-6397db84e11b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935642929 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2935642929
Directory	/workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.696462179
Short name	T977
Test name
Test status
Simulation time	36087167 ps
CPU time	2.32 seconds
Started	Jul 12 06:35:40 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	200528 kb
Host	smart-56ac3d67-56a6-4251-848f-ff8d26dde41a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696462179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm gr_tl_errors.696462179
Directory	/workspace/8.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2468478489
Short name	T899
Test name
Test status
Simulation time	53795440 ps
CPU time	1.62 seconds
Started	Jul 12 06:35:39 PM PDT 24
Finished	Jul 12 06:35:43 PM PDT 24
Peak memory	200616 kb
Host	smart-c01f6e21-f141-45dc-9c7b-77c39ead82f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468478489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 8.clkmgr_tl_intg_err.2468478489
Directory	/workspace/8.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2087067877
Short name	T972
Test name
Test status
Simulation time	229642105 ps
CPU time	1.56 seconds
Started	Jul 12 06:35:42 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	200512 kb
Host	smart-79612949-df7f-4add-86d2-17aefe016649
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087067877 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.2087067877
Directory	/workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.4129425952
Short name	T1006
Test name
Test status
Simulation time	15047579 ps
CPU time	0.84 seconds
Started	Jul 12 06:35:40 PM PDT 24
Finished	Jul 12 06:35:43 PM PDT 24
Peak memory	200432 kb
Host	smart-09fd41b4-3891-4420-b43e-23ae4e64fc30
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129425952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. clkmgr_csr_rw.4129425952
Directory	/workspace/9.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2281864950
Short name	T929
Test name
Test status
Simulation time	12819403 ps
CPU time	0.68 seconds
Started	Jul 12 06:35:43 PM PDT 24
Finished	Jul 12 06:35:45 PM PDT 24
Peak memory	199024 kb
Host	smart-e6e3d1bf-53c1-4f01-b31b-4fb713322c61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281864950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_intr_test.2281864950
Directory	/workspace/9.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3460626042
Short name	T967
Test name
Test status
Simulation time	115184140 ps
CPU time	1.5 seconds
Started	Jul 12 06:35:46 PM PDT 24
Finished	Jul 12 06:35:48 PM PDT 24
Peak memory	200560 kb
Host	smart-65fa15fe-458a-4be1-8b37-935ac8f2332a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460626042 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.clkmgr_same_csr_outstanding.3460626042
Directory	/workspace/9.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2165622907
Short name	T116
Test name
Test status
Simulation time	151662896 ps
CPU time	1.87 seconds
Started	Jul 12 06:35:37 PM PDT 24
Finished	Jul 12 06:35:40 PM PDT 24
Peak memory	217208 kb
Host	smart-f20567e2-0daa-49c8-98da-8009dd4a7e12
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165622907 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.2165622907
Directory	/workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2734933503
Short name	T887
Test name
Test status
Simulation time	227370513 ps
CPU time	2.46 seconds
Started	Jul 12 06:35:40 PM PDT 24
Finished	Jul 12 06:35:44 PM PDT 24
Peak memory	200556 kb
Host	smart-250ea9f8-c577-484c-a910-ee1d5b53cab9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734933503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_tl_errors.2734933503
Directory	/workspace/9.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2844417905
Short name	T90
Test name
Test status
Simulation time	76446904 ps
CPU time	1.57 seconds
Started	Jul 12 06:35:42 PM PDT 24
Finished	Jul 12 06:35:45 PM PDT 24
Peak memory	200596 kb
Host	smart-201db18a-4baa-4a74-a3ba-cbd2efd13f98
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844417905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 9.clkmgr_tl_intg_err.2844417905
Directory	/workspace/9.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_alert_test.2399018997
Short name	T731
Test name
Test status
Simulation time	18526967 ps
CPU time	0.83 seconds
Started	Jul 12 05:49:37 PM PDT 24
Finished	Jul 12 05:49:39 PM PDT 24
Peak memory	200700 kb
Host	smart-3ae63ba0-8a8a-4451-b0d9-a4322a52f55f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399018997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm gr_alert_test.2399018997
Directory	/workspace/0.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_status.544059969
Short name	T369
Test name
Test status
Simulation time	15539071 ps
CPU time	0.7 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	199708 kb
Host	smart-59b27650-0f99-4384-b17f-76147c61693d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544059969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.544059969
Directory	/workspace/0.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_div_intersig_mubi.1914448753
Short name	T690
Test name
Test status
Simulation time	49075060 ps
CPU time	0.91 seconds
Started	Jul 12 05:49:29 PM PDT 24
Finished	Jul 12 05:49:33 PM PDT 24
Peak memory	200572 kb
Host	smart-38b44770-0620-4f25-ad85-e1316e89ef28
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914448753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.1914448753
Directory	/workspace/0.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_extclk.2952739101
Short name	T345
Test name
Test status
Simulation time	13929431 ps
CPU time	0.76 seconds
Started	Jul 12 05:49:26 PM PDT 24
Finished	Jul 12 05:49:30 PM PDT 24
Peak memory	200540 kb
Host	smart-5254139a-695b-49c8-844c-61d2221b0e82
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952739101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2952739101
Directory	/workspace/0.clkmgr_extclk/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency.2424368934
Short name	T668
Test name
Test status
Simulation time	917629047 ps
CPU time	6.49 seconds
Started	Jul 12 05:49:28 PM PDT 24
Finished	Jul 12 05:49:38 PM PDT 24
Peak memory	200648 kb
Host	smart-b47313c9-9b58-4619-b8ea-521084a9b968
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424368934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2424368934
Directory	/workspace/0.clkmgr_frequency/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency_timeout.2667692631
Short name	T406
Test name
Test status
Simulation time	2422941201 ps
CPU time	9.35 seconds
Started	Jul 12 05:49:27 PM PDT 24
Finished	Jul 12 05:49:40 PM PDT 24
Peak memory	201136 kb
Host	smart-a059eab7-9a54-4189-9cb5-c39ad70f3e99
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667692631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti meout.2667692631
Directory	/workspace/0.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2952194737
Short name	T627
Test name
Test status
Simulation time	69128058 ps
CPU time	0.98 seconds
Started	Jul 12 05:49:36 PM PDT 24
Finished	Jul 12 05:49:39 PM PDT 24
Peak memory	200608 kb
Host	smart-f0ebc642-489c-4c46-bdcf-16e6797d8921
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952194737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_clk_byp_req_intersig_mubi.2952194737
Directory	/workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1860695711
Short name	T775
Test name
Test status
Simulation time	17368957 ps
CPU time	0.79 seconds
Started	Jul 12 05:49:34 PM PDT 24
Finished	Jul 12 05:49:36 PM PDT 24
Peak memory	200564 kb
Host	smart-618abedc-70ae-490c-a157-016c6320f1a4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860695711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_ctrl_intersig_mubi.1860695711
Directory	/workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_peri.3995901894
Short name	T260
Test name
Test status
Simulation time	15545830 ps
CPU time	0.71 seconds
Started	Jul 12 05:49:33 PM PDT 24
Finished	Jul 12 05:49:35 PM PDT 24
Peak memory	200456 kb
Host	smart-aee85752-494e-4ec6-a255-29f23e7d15ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995901894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3995901894
Directory	/workspace/0.clkmgr_peri/latest

Test location	/workspace/coverage/default/0.clkmgr_regwen.2284706710
Short name	T756
Test name
Test status
Simulation time	242897469 ps
CPU time	1.54 seconds
Started	Jul 12 05:49:28 PM PDT 24
Finished	Jul 12 05:49:32 PM PDT 24
Peak memory	200528 kb
Host	smart-5e1036f6-5b05-421f-8c6e-96cd28673bcc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284706710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.2284706710
Directory	/workspace/0.clkmgr_regwen/latest

Test location	/workspace/coverage/default/0.clkmgr_sec_cm.3590450709
Short name	T47
Test name
Test status
Simulation time	1040103644 ps
CPU time	4.78 seconds
Started	Jul 12 05:49:40 PM PDT 24
Finished	Jul 12 05:49:48 PM PDT 24
Peak memory	217436 kb
Host	smart-7a56e60b-cb86-4e97-810d-380a8fd6b64b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590450709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_sec_cm.3590450709
Directory	/workspace/0.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/0.clkmgr_smoke.3808302565
Short name	T45
Test name
Test status
Simulation time	34498297 ps
CPU time	0.9 seconds
Started	Jul 12 05:49:36 PM PDT 24
Finished	Jul 12 05:49:39 PM PDT 24
Peak memory	200468 kb
Host	smart-4191aca9-5b27-4256-bfc4-1f54e885607b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808302565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3808302565
Directory	/workspace/0.clkmgr_smoke/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all.1408837984
Short name	T492
Test name
Test status
Simulation time	3546268624 ps
CPU time	27.44 seconds
Started	Jul 12 05:49:52 PM PDT 24
Finished	Jul 12 05:50:20 PM PDT 24
Peak memory	200848 kb
Host	smart-756723a3-d099-49a6-98d3-50dc09fa01ee
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408837984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.1408837984
Directory	/workspace/0.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.3083951200
Short name	T15
Test name
Test status
Simulation time	334593950206 ps
CPU time	1293.51 seconds
Started	Jul 12 05:49:32 PM PDT 24
Finished	Jul 12 06:11:08 PM PDT 24
Peak memory	212308 kb
Host	smart-475addb4-a2f2-4345-bed1-016ac8d08b1c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3083951200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.3083951200
Directory	/workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_trans.1601182081
Short name	T237
Test name
Test status
Simulation time	102322393 ps
CPU time	1.15 seconds
Started	Jul 12 05:49:30 PM PDT 24
Finished	Jul 12 05:49:34 PM PDT 24
Peak memory	200512 kb
Host	smart-63929e4c-7f8c-449a-bdaf-e3477592dab8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601182081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.1601182081
Directory	/workspace/0.clkmgr_trans/latest

Test location	/workspace/coverage/default/1.clkmgr_alert_test.2939510685
Short name	T343
Test name
Test status
Simulation time	32973702 ps
CPU time	0.78 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:41 PM PDT 24
Peak memory	200608 kb
Host	smart-c1d8811f-896a-4a91-8bd3-dd698dd4121a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939510685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm gr_alert_test.2939510685
Directory	/workspace/1.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.549404072
Short name	T699
Test name
Test status
Simulation time	81117269 ps
CPU time	1.08 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:49:44 PM PDT 24
Peak memory	200572 kb
Host	smart-fbc9a3e1-05e6-4d21-96b0-ea75b7040ac5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549404072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.549404072
Directory	/workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_status.912503264
Short name	T236
Test name
Test status
Simulation time	49724884 ps
CPU time	0.78 seconds
Started	Jul 12 05:49:34 PM PDT 24
Finished	Jul 12 05:49:36 PM PDT 24
Peak memory	199764 kb
Host	smart-b25b0538-f920-4567-9694-30866ac38d27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912503264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.912503264
Directory	/workspace/1.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/1.clkmgr_div_intersig_mubi.3939968541
Short name	T228
Test name
Test status
Simulation time	40957368 ps
CPU time	1.01 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200532 kb
Host	smart-835eb7b3-3307-4231-8a25-68610120dd7e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939968541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.3939968541
Directory	/workspace/1.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_extclk.371495286
Short name	T454
Test name
Test status
Simulation time	74705938 ps
CPU time	0.98 seconds
Started	Jul 12 05:49:44 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200576 kb
Host	smart-6f23a686-18a5-4d3b-a97f-ff2b4ef9d8fd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371495286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.371495286
Directory	/workspace/1.clkmgr_extclk/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency.488635576
Short name	T102
Test name
Test status
Simulation time	1773943745 ps
CPU time	8.11 seconds
Started	Jul 12 05:49:35 PM PDT 24
Finished	Jul 12 05:49:45 PM PDT 24
Peak memory	200648 kb
Host	smart-1d46442c-c528-4868-bc3a-0bc26aae113c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488635576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.488635576
Directory	/workspace/1.clkmgr_frequency/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency_timeout.2274668589
Short name	T461
Test name
Test status
Simulation time	1285672354 ps
CPU time	5.46 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:47 PM PDT 24
Peak memory	200700 kb
Host	smart-343d28ed-a33c-41e1-bb32-e02c86441424
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274668589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.2274668589
Directory	/workspace/1.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/1.clkmgr_idle_intersig_mubi.1948416887
Short name	T766
Test name
Test status
Simulation time	45128589 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:35 PM PDT 24
Finished	Jul 12 05:49:37 PM PDT 24
Peak memory	200800 kb
Host	smart-3e8d6789-20e5-4268-9963-219450e1e351
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948416887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.1948416887
Directory	/workspace/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2726271199
Short name	T23
Test name
Test status
Simulation time	172151149 ps
CPU time	1.32 seconds
Started	Jul 12 05:49:42 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200548 kb
Host	smart-be7ff895-9971-4c51-8c18-2a83dd193172
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726271199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_clk_byp_req_intersig_mubi.2726271199
Directory	/workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1483501177
Short name	T762
Test name
Test status
Simulation time	44173923 ps
CPU time	0.84 seconds
Started	Jul 12 05:49:40 PM PDT 24
Finished	Jul 12 05:49:43 PM PDT 24
Peak memory	200580 kb
Host	smart-c3f2cca4-e09c-48ae-9380-d34f9af14946
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483501177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.1483501177
Directory	/workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_peri.399992554
Short name	T403
Test name
Test status
Simulation time	62072715 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:41 PM PDT 24
Peak memory	200460 kb
Host	smart-64fc5443-de9a-43ee-b954-5fd232a14f71
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399992554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.399992554
Directory	/workspace/1.clkmgr_peri/latest

Test location	/workspace/coverage/default/1.clkmgr_regwen.1798207557
Short name	T785
Test name
Test status
Simulation time	1334294565 ps
CPU time	4.67 seconds
Started	Jul 12 05:49:35 PM PDT 24
Finished	Jul 12 05:49:42 PM PDT 24
Peak memory	200660 kb
Host	smart-ea7e12a1-02c8-48ba-af40-008b1e2cf45e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798207557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1798207557
Directory	/workspace/1.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_smoke.1646488682
Short name	T826
Test name
Test status
Simulation time	76439470 ps
CPU time	0.94 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:41 PM PDT 24
Peak memory	200500 kb
Host	smart-7134f284-b120-4dd0-be60-93d0eedafdf2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646488682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1646488682
Directory	/workspace/1.clkmgr_smoke/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all.3957149041
Short name	T124
Test name
Test status
Simulation time	164582550 ps
CPU time	1.43 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:41 PM PDT 24
Peak memory	200608 kb
Host	smart-0982596e-7740-430d-856f-c9a4f744cc67
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957149041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.3957149041
Directory	/workspace/1.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.2613074133
Short name	T157
Test name
Test status
Simulation time	44523819683 ps
CPU time	818.43 seconds
Started	Jul 12 05:49:40 PM PDT 24
Finished	Jul 12 06:03:21 PM PDT 24
Peak memory	217352 kb
Host	smart-19d8effe-9fdb-4eb6-a616-d8ec55577372
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2613074133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.2613074133
Directory	/workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.clkmgr_trans.1013058429
Short name	T278
Test name
Test status
Simulation time	124668994 ps
CPU time	1.27 seconds
Started	Jul 12 05:49:42 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200552 kb
Host	smart-0ac81b6e-26e9-42d1-9b14-488bf7eadfd4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013058429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1013058429
Directory	/workspace/1.clkmgr_trans/latest

Test location	/workspace/coverage/default/10.clkmgr_alert_test.2571821963
Short name	T485
Test name
Test status
Simulation time	29792031 ps
CPU time	0.83 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:08 PM PDT 24
Peak memory	200688 kb
Host	smart-d45f6d2f-8e4a-4baa-bbca-915ed211a8c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571821963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk mgr_alert_test.2571821963
Directory	/workspace/10.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2559173683
Short name	T82
Test name
Test status
Simulation time	54265636 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:06 PM PDT 24
Finished	Jul 12 05:50:08 PM PDT 24
Peak memory	200588 kb
Host	smart-c9391832-dae2-4578-a154-5d22b5422a82
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559173683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.2559173683
Directory	/workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_status.2526286721
Short name	T387
Test name
Test status
Simulation time	17480943 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:00 PM PDT 24
Finished	Jul 12 05:50:02 PM PDT 24
Peak memory	199756 kb
Host	smart-478514e6-624b-41c7-a6d6-90f4c1661f8f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526286721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2526286721
Directory	/workspace/10.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/10.clkmgr_div_intersig_mubi.285462940
Short name	T208
Test name
Test status
Simulation time	17759595 ps
CPU time	0.83 seconds
Started	Jul 12 05:50:03 PM PDT 24
Finished	Jul 12 05:50:05 PM PDT 24
Peak memory	200608 kb
Host	smart-67c850ee-b500-4943-8e0e-eecab610f262
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285462940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.clkmgr_div_intersig_mubi.285462940
Directory	/workspace/10.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_extclk.3293958443
Short name	T742
Test name
Test status
Simulation time	47612089 ps
CPU time	0.84 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:57 PM PDT 24
Peak memory	200576 kb
Host	smart-7a23fac9-bfb9-4e5d-b090-4f5ef7341dfe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293958443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3293958443
Directory	/workspace/10.clkmgr_extclk/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency.653211549
Short name	T527
Test name
Test status
Simulation time	1769960652 ps
CPU time	10.29 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200752 kb
Host	smart-4ea2bbc5-b3f0-4932-b263-86c58c0b0dee
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653211549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.653211549
Directory	/workspace/10.clkmgr_frequency/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency_timeout.2049243888
Short name	T622
Test name
Test status
Simulation time	376374143 ps
CPU time	3.26 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:26 PM PDT 24
Peak memory	200624 kb
Host	smart-8192defe-443f-4d50-b86c-99ebce383405
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049243888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t imeout.2049243888
Directory	/workspace/10.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/10.clkmgr_idle_intersig_mubi.114112051
Short name	T100
Test name
Test status
Simulation time	33236950 ps
CPU time	0.97 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200500 kb
Host	smart-1f1e7c89-e925-42df-9556-473d6d0171b2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114112051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.clkmgr_idle_intersig_mubi.114112051
Directory	/workspace/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.224109326
Short name	T502
Test name
Test status
Simulation time	62152662 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:03 PM PDT 24
Finished	Jul 12 05:50:05 PM PDT 24
Peak memory	200560 kb
Host	smart-7ca62095-acfa-4f8c-b499-c95116f7f2ed
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224109326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.clkmgr_lc_clk_byp_req_intersig_mubi.224109326
Directory	/workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1719464884
Short name	T214
Test name
Test status
Simulation time	34880020 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:11 PM PDT 24
Peak memory	200500 kb
Host	smart-fbf5efa3-5bba-40f6-82d9-a412cd1b3bf8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719464884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.1719464884
Directory	/workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_peri.494390618
Short name	T765
Test name
Test status
Simulation time	14363826 ps
CPU time	0.74 seconds
Started	Jul 12 05:50:06 PM PDT 24
Finished	Jul 12 05:50:08 PM PDT 24
Peak memory	200544 kb
Host	smart-20bf6226-d7d4-401a-8d99-c7c3d553b4e0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494390618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.494390618
Directory	/workspace/10.clkmgr_peri/latest

Test location	/workspace/coverage/default/10.clkmgr_regwen.2722297038
Short name	T444
Test name
Test status
Simulation time	1258708248 ps
CPU time	5.41 seconds
Started	Jul 12 05:50:04 PM PDT 24
Finished	Jul 12 05:50:10 PM PDT 24
Peak memory	200640 kb
Host	smart-74beb38e-8ae5-417e-b217-640688d21da8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722297038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2722297038
Directory	/workspace/10.clkmgr_regwen/latest

Test location	/workspace/coverage/default/10.clkmgr_smoke.1972659296
Short name	T493
Test name
Test status
Simulation time	30139385 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:49:56 PM PDT 24
Peak memory	200504 kb
Host	smart-2894fcab-da1c-46a1-9d47-d1b36efe9b1e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972659296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1972659296
Directory	/workspace/10.clkmgr_smoke/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all.1457123549
Short name	T128
Test name
Test status
Simulation time	5819061960 ps
CPU time	40.9 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:50:37 PM PDT 24
Peak memory	200856 kb
Host	smart-3b58f0f0-b869-424c-abff-b7311472058c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457123549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.1457123549
Directory	/workspace/10.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.2920336608
Short name	T578
Test name
Test status
Simulation time	31225632008 ps
CPU time	544.52 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:59:00 PM PDT 24
Peak memory	217324 kb
Host	smart-61830203-e573-4a0e-a03e-15e21224e95c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2920336608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.2920336608
Directory	/workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.clkmgr_trans.1241954625
Short name	T652
Test name
Test status
Simulation time	68279554 ps
CPU time	1.19 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:12 PM PDT 24
Peak memory	200508 kb
Host	smart-839022ee-b4a8-4ef7-96d2-097d781c9146
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241954625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.1241954625
Directory	/workspace/10.clkmgr_trans/latest

Test location	/workspace/coverage/default/11.clkmgr_alert_test.2007963320
Short name	T723
Test name
Test status
Simulation time	96302803 ps
CPU time	0.96 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:23 PM PDT 24
Peak memory	200700 kb
Host	smart-ddce063e-57d6-42a2-b688-2a5b73aac6d3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007963320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk mgr_alert_test.2007963320
Directory	/workspace/11.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2406842198
Short name	T452
Test name
Test status
Simulation time	42452746 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:09 PM PDT 24
Peak memory	200600 kb
Host	smart-8a1fa9d6-2dce-46cc-92f6-ee9fa1ea52e4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406842198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.2406842198
Directory	/workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_status.2875448744
Short name	T748
Test name
Test status
Simulation time	18254403 ps
CPU time	0.74 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:57 PM PDT 24
Peak memory	199764 kb
Host	smart-0f8befcb-660c-4076-b14a-e0c2359a3228
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875448744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.2875448744
Directory	/workspace/11.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/11.clkmgr_div_intersig_mubi.673063970
Short name	T337
Test name
Test status
Simulation time	136432871 ps
CPU time	1.11 seconds
Started	Jul 12 05:50:16 PM PDT 24
Finished	Jul 12 05:50:19 PM PDT 24
Peak memory	200544 kb
Host	smart-1ed3d2f2-57bc-4c13-abc6-bfeed481af90
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673063970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.clkmgr_div_intersig_mubi.673063970
Directory	/workspace/11.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_extclk.3445729265
Short name	T246
Test name
Test status
Simulation time	15256820 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:18 PM PDT 24
Finished	Jul 12 05:50:19 PM PDT 24
Peak memory	200564 kb
Host	smart-34fbf961-d2f5-43ef-bc62-569fc894198c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445729265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.3445729265
Directory	/workspace/11.clkmgr_extclk/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency.2306599468
Short name	T10
Test name
Test status
Simulation time	1162553396 ps
CPU time	9.27 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200624 kb
Host	smart-2b15f9f3-730a-48d8-83bf-1ddeda0c852f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306599468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.2306599468
Directory	/workspace/11.clkmgr_frequency/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency_timeout.1667065294
Short name	T303
Test name
Test status
Simulation time	2309317765 ps
CPU time	9.94 seconds
Started	Jul 12 05:49:57 PM PDT 24
Finished	Jul 12 05:50:09 PM PDT 24
Peak memory	200888 kb
Host	smart-43bad6ca-8082-4f21-9f12-c50797fd3c5a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667065294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t imeout.1667065294
Directory	/workspace/11.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2805137999
Short name	T760
Test name
Test status
Simulation time	56070975 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:04 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200600 kb
Host	smart-db066df7-9cc8-4894-9af6-a2de26741726
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805137999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.2805137999
Directory	/workspace/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.3589126981
Short name	T711
Test name
Test status
Simulation time	237513761 ps
CPU time	1.59 seconds
Started	Jul 12 05:50:12 PM PDT 24
Finished	Jul 12 05:50:15 PM PDT 24
Peak memory	200588 kb
Host	smart-65b70ba7-271e-42fc-b540-12d95e1fd6e7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589126981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_clk_byp_req_intersig_mubi.3589126981
Directory	/workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2434255751
Short name	T349
Test name
Test status
Simulation time	22535271 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:11 PM PDT 24
Peak memory	200556 kb
Host	smart-0ad4d0cf-77ce-4f18-91bb-e6ab1921e2dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434255751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_ctrl_intersig_mubi.2434255751
Directory	/workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_peri.1654466306
Short name	T417
Test name
Test status
Simulation time	22035401 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:11 PM PDT 24
Peak memory	200368 kb
Host	smart-d5564f6e-7587-42ee-a485-5d3e60d7924a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654466306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1654466306
Directory	/workspace/11.clkmgr_peri/latest

Test location	/workspace/coverage/default/11.clkmgr_regwen.1755930348
Short name	T658
Test name
Test status
Simulation time	764089120 ps
CPU time	4.93 seconds
Started	Jul 12 05:50:12 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200640 kb
Host	smart-f2a373cf-f89f-435f-a6cb-20920347e3f2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755930348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1755930348
Directory	/workspace/11.clkmgr_regwen/latest

Test location	/workspace/coverage/default/11.clkmgr_smoke.438840266
Short name	T541
Test name
Test status
Simulation time	35399095 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:03 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200484 kb
Host	smart-e01e743b-29a4-4482-b556-b6005dcdd4de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438840266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.438840266
Directory	/workspace/11.clkmgr_smoke/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all.24890368
Short name	T367
Test name
Test status
Simulation time	3672272731 ps
CPU time	19.77 seconds
Started	Jul 12 05:50:16 PM PDT 24
Finished	Jul 12 05:50:37 PM PDT 24
Peak memory	200812 kb
Host	smart-227c7e0b-d0b7-416c-9286-44f5c8af9942
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24890368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.clkmgr_stress_all.24890368
Directory	/workspace/11.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3697337335
Short name	T642
Test name
Test status
Simulation time	23715490439 ps
CPU time	348.14 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:56:05 PM PDT 24
Peak memory	216224 kb
Host	smart-0e30d051-fb4d-464d-8558-e231b6c3485e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3697337335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3697337335
Directory	/workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_trans.1158165138
Short name	T290
Test name
Test status
Simulation time	72338592 ps
CPU time	0.98 seconds
Started	Jul 12 05:49:56 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200560 kb
Host	smart-2de4db73-070c-4d6f-a8d1-ef9418f79571
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158165138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1158165138
Directory	/workspace/11.clkmgr_trans/latest

Test location	/workspace/coverage/default/12.clkmgr_alert_test.585513516
Short name	T827
Test name
Test status
Simulation time	22293777 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:05 PM PDT 24
Finished	Jul 12 05:50:07 PM PDT 24
Peak memory	200920 kb
Host	smart-967fe6b0-f692-432e-b3d7-0a410aaf932b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585513516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkm gr_alert_test.585513516
Directory	/workspace/12.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3605886633
Short name	T200
Test name
Test status
Simulation time	18279292 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:04 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200616 kb
Host	smart-cacd479c-a0e9-45f4-a27e-bd4cf3c924a1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605886633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.3605886633
Directory	/workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_status.1895712869
Short name	T834
Test name
Test status
Simulation time	37831119 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:03 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	199764 kb
Host	smart-03232d67-abfc-4d1c-b2f1-8e58c7a100a4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895712869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1895712869
Directory	/workspace/12.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/12.clkmgr_div_intersig_mubi.1581455994
Short name	T230
Test name
Test status
Simulation time	71832051 ps
CPU time	0.99 seconds
Started	Jul 12 05:50:18 PM PDT 24
Finished	Jul 12 05:50:20 PM PDT 24
Peak memory	200564 kb
Host	smart-1ae16e4e-ecf2-44a5-be12-edaaa7fe4196
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581455994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.1581455994
Directory	/workspace/12.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_extclk.535735592
Short name	T772
Test name
Test status
Simulation time	94966594 ps
CPU time	1.13 seconds
Started	Jul 12 05:50:02 PM PDT 24
Finished	Jul 12 05:50:05 PM PDT 24
Peak memory	200564 kb
Host	smart-ef77ca57-a84a-4049-88ae-bfe4179ddf9c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535735592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.535735592
Directory	/workspace/12.clkmgr_extclk/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency.628343576
Short name	T782
Test name
Test status
Simulation time	2250608221 ps
CPU time	12.92 seconds
Started	Jul 12 05:50:08 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200784 kb
Host	smart-b4ed178c-d69a-4a6c-b35f-b8efb0a172a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628343576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.628343576
Directory	/workspace/12.clkmgr_frequency/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency_timeout.28970428
Short name	T653
Test name
Test status
Simulation time	1738579451 ps
CPU time	6.58 seconds
Started	Jul 12 05:50:08 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200684 kb
Host	smart-291039e7-b781-41eb-bae3-e9586575818c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28970428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_tim eout.28970428
Directory	/workspace/12.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/12.clkmgr_idle_intersig_mubi.1305039226
Short name	T238
Test name
Test status
Simulation time	62221319 ps
CPU time	1.08 seconds
Started	Jul 12 05:50:03 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200556 kb
Host	smart-b483cf58-358f-43b6-81da-6d06b94a15ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305039226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.1305039226
Directory	/workspace/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.761097976
Short name	T503
Test name
Test status
Simulation time	48438097 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:05 PM PDT 24
Finished	Jul 12 05:50:07 PM PDT 24
Peak memory	200568 kb
Host	smart-59f3a0e3-6697-450d-afa2-953d83d45d11
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761097976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.clkmgr_lc_clk_byp_req_intersig_mubi.761097976
Directory	/workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1910796611
Short name	T465
Test name
Test status
Simulation time	17425539 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:02 PM PDT 24
Finished	Jul 12 05:50:05 PM PDT 24
Peak memory	200556 kb
Host	smart-85f90784-2c02-4df7-9eac-364f85512084
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910796611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.1910796611
Directory	/workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_peri.3789095270
Short name	T474
Test name
Test status
Simulation time	38024424 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:03 PM PDT 24
Finished	Jul 12 05:50:05 PM PDT 24
Peak memory	200780 kb
Host	smart-b347d3fd-1224-4cf2-9d29-b2eebb016080
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789095270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3789095270
Directory	/workspace/12.clkmgr_peri/latest

Test location	/workspace/coverage/default/12.clkmgr_regwen.3206233224
Short name	T720
Test name
Test status
Simulation time	104533923 ps
CPU time	1.04 seconds
Started	Jul 12 05:50:10 PM PDT 24
Finished	Jul 12 05:50:13 PM PDT 24
Peak memory	200516 kb
Host	smart-2fb58727-ce5e-4e23-8d8d-917515e81e68
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206233224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3206233224
Directory	/workspace/12.clkmgr_regwen/latest

Test location	/workspace/coverage/default/12.clkmgr_smoke.1105322030
Short name	T17
Test name
Test status
Simulation time	87328069 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:12 PM PDT 24
Peak memory	200508 kb
Host	smart-d970c1f0-966d-4509-9097-0bdc6df84916
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105322030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1105322030
Directory	/workspace/12.clkmgr_smoke/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all.3249289893
Short name	T835
Test name
Test status
Simulation time	4910116338 ps
CPU time	21.66 seconds
Started	Jul 12 05:50:04 PM PDT 24
Finished	Jul 12 05:50:27 PM PDT 24
Peak memory	200840 kb
Host	smart-7827cf37-006e-4de5-9684-6280a557dd1d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249289893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.3249289893
Directory	/workspace/12.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/12.clkmgr_trans.2940840905
Short name	T761
Test name
Test status
Simulation time	26681689 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:01 PM PDT 24
Finished	Jul 12 05:50:03 PM PDT 24
Peak memory	200560 kb
Host	smart-008d5fdb-65e0-4d65-ab2e-61a0ca4d4745
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940840905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2940840905
Directory	/workspace/12.clkmgr_trans/latest

Test location	/workspace/coverage/default/13.clkmgr_alert_test.3233006577
Short name	T383
Test name
Test status
Simulation time	15185733 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:08 PM PDT 24
Peak memory	200700 kb
Host	smart-a32ccac7-935f-4689-9fe7-8deffb61d358
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233006577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk mgr_alert_test.3233006577
Directory	/workspace/13.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.929533452
Short name	T725
Test name
Test status
Simulation time	170328838 ps
CPU time	1.26 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:11 PM PDT 24
Peak memory	200552 kb
Host	smart-16e221da-0fe6-41ce-87e2-24dd729ecff8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929533452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.929533452
Directory	/workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_status.3828407943
Short name	T145
Test name
Test status
Simulation time	16142819 ps
CPU time	0.72 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:50:17 PM PDT 24
Peak memory	199740 kb
Host	smart-b317bc68-2e85-470b-957d-28c6fedfc5ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828407943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3828407943
Directory	/workspace/13.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/13.clkmgr_div_intersig_mubi.2135584921
Short name	T594
Test name
Test status
Simulation time	61853495 ps
CPU time	0.98 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200584 kb
Host	smart-c33c690a-a861-4545-9245-91b6980d5777
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135584921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.2135584921
Directory	/workspace/13.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_extclk.2572764472
Short name	T356
Test name
Test status
Simulation time	17901674 ps
CPU time	0.71 seconds
Started	Jul 12 05:50:12 PM PDT 24
Finished	Jul 12 05:50:14 PM PDT 24
Peak memory	200560 kb
Host	smart-32966d6b-3813-4242-ba71-68f0f350c2cd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572764472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2572764472
Directory	/workspace/13.clkmgr_extclk/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency.1192681327
Short name	T26
Test name
Test status
Simulation time	2115533318 ps
CPU time	16.16 seconds
Started	Jul 12 05:50:11 PM PDT 24
Finished	Jul 12 05:50:28 PM PDT 24
Peak memory	200736 kb
Host	smart-ad80905a-7fd6-4858-9c67-c2818412a558
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192681327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1192681327
Directory	/workspace/13.clkmgr_frequency/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency_timeout.576840712
Short name	T575
Test name
Test status
Simulation time	2179757082 ps
CPU time	11.63 seconds
Started	Jul 12 05:50:00 PM PDT 24
Finished	Jul 12 05:50:13 PM PDT 24
Peak memory	200828 kb
Host	smart-a4f2638a-af8f-464e-be9e-5a83986c2760
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576840712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_ti meout.576840712
Directory	/workspace/13.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.4246474084
Short name	T218
Test name
Test status
Simulation time	43153882 ps
CPU time	0.91 seconds
Started	Jul 12 05:50:10 PM PDT 24
Finished	Jul 12 05:50:12 PM PDT 24
Peak memory	200564 kb
Host	smart-7e3d36d5-6ebe-4739-bd07-ea02b44239d0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246474084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.4246474084
Directory	/workspace/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2051112877
Short name	T735
Test name
Test status
Simulation time	55073031 ps
CPU time	0.95 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:12 PM PDT 24
Peak memory	200552 kb
Host	smart-ab41bf01-1ede-4c0d-8d7b-dced149b6ac5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051112877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2051112877
Directory	/workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2129769671
Short name	T177
Test name
Test status
Simulation time	41799670 ps
CPU time	0.99 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:12 PM PDT 24
Peak memory	200588 kb
Host	smart-1cab5ea1-169b-44b3-81ec-7d255297e5f5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129769671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_ctrl_intersig_mubi.2129769671
Directory	/workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_peri.3325503977
Short name	T844
Test name
Test status
Simulation time	28611900 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:05 PM PDT 24
Finished	Jul 12 05:50:07 PM PDT 24
Peak memory	200424 kb
Host	smart-ca2c0dd3-cd80-4aad-b0f1-d73f16409d20
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325503977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.3325503977
Directory	/workspace/13.clkmgr_peri/latest

Test location	/workspace/coverage/default/13.clkmgr_regwen.1422134818
Short name	T221
Test name
Test status
Simulation time	718400413 ps
CPU time	3.87 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:14 PM PDT 24
Peak memory	200608 kb
Host	smart-d35879dd-3adc-4c58-8392-5aa85b81e68a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422134818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1422134818
Directory	/workspace/13.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_smoke.3001362072
Short name	T778
Test name
Test status
Simulation time	17702619 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:08 PM PDT 24
Peak memory	200500 kb
Host	smart-aca614e8-542d-4334-a029-c76ae0764267
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001362072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3001362072
Directory	/workspace/13.clkmgr_smoke/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all.1244663441
Short name	T521
Test name
Test status
Simulation time	3457051526 ps
CPU time	21.19 seconds
Started	Jul 12 05:50:11 PM PDT 24
Finished	Jul 12 05:50:36 PM PDT 24
Peak memory	200836 kb
Host	smart-9c40807e-054a-4976-9348-3f3d434b1111
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244663441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.1244663441
Directory	/workspace/13.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.601758110
Short name	T675
Test name
Test status
Simulation time	18352263176 ps
CPU time	159.8 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:52:50 PM PDT 24
Peak memory	215024 kb
Host	smart-19e4a8e9-cf59-4c2f-8005-faa81633416c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=601758110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.601758110
Directory	/workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.clkmgr_trans.1505630484
Short name	T302
Test name
Test status
Simulation time	47207173 ps
CPU time	0.94 seconds
Started	Jul 12 05:50:01 PM PDT 24
Finished	Jul 12 05:50:03 PM PDT 24
Peak memory	200564 kb
Host	smart-6f46a1de-436c-4d4a-99aa-eead712d37f3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505630484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.1505630484
Directory	/workspace/13.clkmgr_trans/latest

Test location	/workspace/coverage/default/14.clkmgr_alert_test.1475985232
Short name	T677
Test name
Test status
Simulation time	102037832 ps
CPU time	0.98 seconds
Started	Jul 12 05:50:08 PM PDT 24
Finished	Jul 12 05:50:10 PM PDT 24
Peak memory	200684 kb
Host	smart-0a5cab15-e90d-4c5f-b999-f3e08529b8fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475985232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk mgr_alert_test.1475985232
Directory	/workspace/14.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2550089615
Short name	T424
Test name
Test status
Simulation time	16158745 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:09 PM PDT 24
Peak memory	200584 kb
Host	smart-08f62099-ae91-407d-8590-33c487a18053
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550089615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.2550089615
Directory	/workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_status.3282064720
Short name	T726
Test name
Test status
Simulation time	24456661 ps
CPU time	0.72 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:10 PM PDT 24
Peak memory	199752 kb
Host	smart-e8964470-9324-4a09-9080-15e14c7970b1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282064720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.3282064720
Directory	/workspace/14.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/14.clkmgr_div_intersig_mubi.3672523069
Short name	T325
Test name
Test status
Simulation time	38569467 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:28 PM PDT 24
Peak memory	200516 kb
Host	smart-958b7700-ee78-470b-ba9a-1db35ccdf22e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672523069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.3672523069
Directory	/workspace/14.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_extclk.3903194482
Short name	T297
Test name
Test status
Simulation time	41980740 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:12 PM PDT 24
Finished	Jul 12 05:50:14 PM PDT 24
Peak memory	200556 kb
Host	smart-031fcdbd-ba3e-4034-9c29-35bb0d09460f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903194482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3903194482
Directory	/workspace/14.clkmgr_extclk/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency.1751808833
Short name	T350
Test name
Test status
Simulation time	1610346037 ps
CPU time	7.51 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200624 kb
Host	smart-fdec112d-5bf6-482e-b399-57246f75816d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751808833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1751808833
Directory	/workspace/14.clkmgr_frequency/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency_timeout.488730020
Short name	T476
Test name
Test status
Simulation time	533247608 ps
CPU time	2.59 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200692 kb
Host	smart-490be827-9556-476e-ae50-4da96c427e31
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488730020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti meout.488730020
Directory	/workspace/14.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3594836901
Short name	T513
Test name
Test status
Simulation time	102987918 ps
CPU time	1.18 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200560 kb
Host	smart-87d78a15-8fc1-4f45-a0c4-b2a454896e8f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594836901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.3594836901
Directory	/workspace/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1707743465
Short name	T697
Test name
Test status
Simulation time	19463748 ps
CPU time	0.84 seconds
Started	Jul 12 05:50:06 PM PDT 24
Finished	Jul 12 05:50:08 PM PDT 24
Peak memory	200544 kb
Host	smart-8fc6d293-83f6-4fd1-848b-61d845a4efca
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707743465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_clk_byp_req_intersig_mubi.1707743465
Directory	/workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.697784751
Short name	T773
Test name
Test status
Simulation time	28145101 ps
CPU time	0.89 seconds
Started	Jul 12 05:50:08 PM PDT 24
Finished	Jul 12 05:50:10 PM PDT 24
Peak memory	200584 kb
Host	smart-af27c206-f003-447b-b806-11afe0c89700
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697784751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.clkmgr_lc_ctrl_intersig_mubi.697784751
Directory	/workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_peri.3840532108
Short name	T640
Test name
Test status
Simulation time	18878062 ps
CPU time	0.83 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:09 PM PDT 24
Peak memory	200672 kb
Host	smart-8f108953-6745-4fea-a288-63ba7bd99050
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840532108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3840532108
Directory	/workspace/14.clkmgr_peri/latest

Test location	/workspace/coverage/default/14.clkmgr_regwen.11782060
Short name	T614
Test name
Test status
Simulation time	684378261 ps
CPU time	4.13 seconds
Started	Jul 12 05:50:08 PM PDT 24
Finished	Jul 12 05:50:13 PM PDT 24
Peak memory	200672 kb
Host	smart-56d340f8-3ea8-4729-a5ab-13deb2e1baa7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11782060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.11782060
Directory	/workspace/14.clkmgr_regwen/latest

Test location	/workspace/coverage/default/14.clkmgr_smoke.254586760
Short name	T569
Test name
Test status
Simulation time	26192676 ps
CPU time	0.9 seconds
Started	Jul 12 05:50:08 PM PDT 24
Finished	Jul 12 05:50:10 PM PDT 24
Peak memory	200496 kb
Host	smart-bf33c3b6-5526-4c6f-95fe-a3f260d3b69d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254586760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.254586760
Directory	/workspace/14.clkmgr_smoke/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all.1233127303
Short name	T842
Test name
Test status
Simulation time	4608780703 ps
CPU time	35.11 seconds
Started	Jul 12 05:50:16 PM PDT 24
Finished	Jul 12 05:50:53 PM PDT 24
Peak memory	200908 kb
Host	smart-34aff1e0-94b0-413c-88e9-91a0eab7e052
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233127303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.1233127303
Directory	/workspace/14.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.964929160
Short name	T139
Test name
Test status
Simulation time	51919073301 ps
CPU time	252.7 seconds
Started	Jul 12 05:50:10 PM PDT 24
Finished	Jul 12 05:54:24 PM PDT 24
Peak memory	217324 kb
Host	smart-f659ce90-8f61-4fe0-acc9-50742b433b3a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=964929160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.964929160
Directory	/workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.clkmgr_trans.859113680
Short name	T167
Test name
Test status
Simulation time	27138563 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:15 PM PDT 24
Peak memory	200564 kb
Host	smart-be57ce29-eb31-4d36-a746-897bf7045569
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859113680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.859113680
Directory	/workspace/14.clkmgr_trans/latest

Test location	/workspace/coverage/default/15.clkmgr_alert_test.2249486254
Short name	T248
Test name
Test status
Simulation time	59108345 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:23 PM PDT 24
Peak memory	200668 kb
Host	smart-3ed99564-ec3f-4f87-8aad-87c0534f079c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249486254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk mgr_alert_test.2249486254
Directory	/workspace/15.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2151293187
Short name	T480
Test name
Test status
Simulation time	16002086 ps
CPU time	0.74 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:28 PM PDT 24
Peak memory	200592 kb
Host	smart-425f6632-3c14-4b43-a766-faeb9c781689
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151293187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.2151293187
Directory	/workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_status.1592883840
Short name	T498
Test name
Test status
Simulation time	22650671 ps
CPU time	0.71 seconds
Started	Jul 12 05:50:09 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	199744 kb
Host	smart-8642e700-5540-4277-b489-673ae8f2baf8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592883840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1592883840
Directory	/workspace/15.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/15.clkmgr_div_intersig_mubi.916185004
Short name	T706
Test name
Test status
Simulation time	68359433 ps
CPU time	0.98 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:50:17 PM PDT 24
Peak memory	200564 kb
Host	smart-1b3209d5-8999-4739-a7f1-6ee80af7d278
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916185004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_div_intersig_mubi.916185004
Directory	/workspace/15.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_extclk.65289048
Short name	T263
Test name
Test status
Simulation time	17491489 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:11 PM PDT 24
Finished	Jul 12 05:50:13 PM PDT 24
Peak memory	200548 kb
Host	smart-a67c221b-e033-45ce-a8b7-0c445d2b41cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65289048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.65289048
Directory	/workspace/15.clkmgr_extclk/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency.3770331583
Short name	T517
Test name
Test status
Simulation time	2368872427 ps
CPU time	13.19 seconds
Started	Jul 12 05:50:08 PM PDT 24
Finished	Jul 12 05:50:28 PM PDT 24
Peak memory	200732 kb
Host	smart-3a68ceb4-bc01-420a-a737-d7e8c4dd2633
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770331583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.3770331583
Directory	/workspace/15.clkmgr_frequency/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency_timeout.2599080712
Short name	T300
Test name
Test status
Simulation time	1719826808 ps
CPU time	7.42 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200656 kb
Host	smart-d0bd4b28-d18a-4a45-a7a7-1f05a84eec21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599080712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.2599080712
Directory	/workspace/15.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/15.clkmgr_idle_intersig_mubi.3558859723
Short name	T553
Test name
Test status
Simulation time	49399395 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:23 PM PDT 24
Peak memory	200576 kb
Host	smart-7be69098-9e09-45a4-8e46-2a4d63b32b66
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558859723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.3558859723
Directory	/workspace/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3279191540
Short name	T831
Test name
Test status
Simulation time	16072177 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:23 PM PDT 24
Peak memory	200600 kb
Host	smart-77445338-a2d0-425b-bd6d-4aabe566f0a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279191540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3279191540
Directory	/workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3075570794
Short name	T721
Test name
Test status
Simulation time	79583621 ps
CPU time	1.02 seconds
Started	Jul 12 05:50:28 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200544 kb
Host	smart-fec0e27f-e7ac-4ad7-924e-ddca95440dc8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075570794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.3075570794
Directory	/workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_peri.1175801444
Short name	T316
Test name
Test status
Simulation time	68095787 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:15 PM PDT 24
Peak memory	200544 kb
Host	smart-f2e05aab-af2c-4a42-828d-52752c2ef964
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175801444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.1175801444
Directory	/workspace/15.clkmgr_peri/latest

Test location	/workspace/coverage/default/15.clkmgr_regwen.3675670661
Short name	T477
Test name
Test status
Simulation time	1256912633 ps
CPU time	4.42 seconds
Started	Jul 12 05:50:12 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200684 kb
Host	smart-2050ed60-ead5-4780-bd31-ab35771c392e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675670661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3675670661
Directory	/workspace/15.clkmgr_regwen/latest

Test location	/workspace/coverage/default/15.clkmgr_smoke.1878314802
Short name	T710
Test name
Test status
Simulation time	23366179 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:10 PM PDT 24
Finished	Jul 12 05:50:12 PM PDT 24
Peak memory	200508 kb
Host	smart-272756e8-f0b7-415e-a463-ab50f9214330
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878314802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1878314802
Directory	/workspace/15.clkmgr_smoke/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all.1701268267
Short name	T473
Test name
Test status
Simulation time	6516499115 ps
CPU time	47.19 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200848 kb
Host	smart-939d6cf3-ab46-4fd9-bec0-fe1a1802e416
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701268267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.1701268267
Directory	/workspace/15.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.3021816395
Short name	T437
Test name
Test status
Simulation time	48042792808 ps
CPU time	746.62 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 06:02:55 PM PDT 24
Peak memory	209156 kb
Host	smart-928df130-05c7-4f40-b080-7ce414caaa47
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3021816395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3021816395
Directory	/workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.clkmgr_trans.4119609746
Short name	T414
Test name
Test status
Simulation time	44973816 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:11 PM PDT 24
Finished	Jul 12 05:50:14 PM PDT 24
Peak memory	200572 kb
Host	smart-345ac146-66dd-4911-bd50-6a5485922904
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119609746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.4119609746
Directory	/workspace/15.clkmgr_trans/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.2182343280
Short name	T490
Test name
Test status
Simulation time	51712166 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:30 PM PDT 24
Peak memory	200588 kb
Host	smart-70414c11-9aa2-4163-a515-ae2560ac91fb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182343280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.2182343280
Directory	/workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_div_intersig_mubi.2402817421
Short name	T646
Test name
Test status
Simulation time	80987702 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:30 PM PDT 24
Peak memory	200584 kb
Host	smart-8a3b3c93-96cb-4fe4-9394-11fc922d5c54
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402817421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.2402817421
Directory	/workspace/16.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_extclk.1507441519
Short name	T338
Test name
Test status
Simulation time	40534429 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:27 PM PDT 24
Peak memory	200552 kb
Host	smart-73061afc-7c46-4d17-9d29-ff3fc4d90ea3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507441519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.1507441519
Directory	/workspace/16.clkmgr_extclk/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency.2740707280
Short name	T585
Test name
Test status
Simulation time	2480538820 ps
CPU time	19.04 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:43 PM PDT 24
Peak memory	200852 kb
Host	smart-d2f20a08-87e1-491c-a698-cd801a05c226
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740707280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.2740707280
Directory	/workspace/16.clkmgr_frequency/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency_timeout.2130889551
Short name	T413
Test name
Test status
Simulation time	378679687 ps
CPU time	2.63 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:31 PM PDT 24
Peak memory	200688 kb
Host	smart-8fe4df2d-8e3d-4e1e-ba84-ad66af53c1da
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130889551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t imeout.2130889551
Directory	/workspace/16.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.1524553287
Short name	T770
Test name
Test status
Simulation time	20583467 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:17 PM PDT 24
Finished	Jul 12 05:50:19 PM PDT 24
Peak memory	200520 kb
Host	smart-51bbed62-189d-488a-8359-825118d5260a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524553287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.1524553287
Directory	/workspace/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.383706515
Short name	T686
Test name
Test status
Simulation time	20556227 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:38 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	200584 kb
Host	smart-89c407b0-f9ea-4bc3-98ea-371d34b13b21
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383706515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.clkmgr_lc_clk_byp_req_intersig_mubi.383706515
Directory	/workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3827645009
Short name	T667
Test name
Test status
Simulation time	22222161 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200556 kb
Host	smart-e15c58b2-df61-4ccc-9447-80319fdd0957
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827645009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_ctrl_intersig_mubi.3827645009
Directory	/workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_peri.2338929270
Short name	T310
Test name
Test status
Simulation time	39293206 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	200524 kb
Host	smart-d165014f-7e09-4d14-9ae9-023c333a6c4a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338929270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2338929270
Directory	/workspace/16.clkmgr_peri/latest

Test location	/workspace/coverage/default/16.clkmgr_regwen.3643430951
Short name	T792
Test name
Test status
Simulation time	887157578 ps
CPU time	4 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:31 PM PDT 24
Peak memory	200676 kb
Host	smart-20c51ba1-7a0c-42b1-8321-de22b2c77902
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643430951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3643430951
Directory	/workspace/16.clkmgr_regwen/latest

Test location	/workspace/coverage/default/16.clkmgr_smoke.3389458163
Short name	T215
Test name
Test status
Simulation time	76657146 ps
CPU time	0.96 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200524 kb
Host	smart-7c4c961b-6874-4e4a-80c7-42c12e72d3cd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389458163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3389458163
Directory	/workspace/16.clkmgr_smoke/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2406428140
Short name	T738
Test name
Test status
Simulation time	37644706039 ps
CPU time	421.46 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:57:25 PM PDT 24
Peak memory	209156 kb
Host	smart-f2f67cf9-759e-4115-aada-8bca54b1b995
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2406428140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2406428140
Directory	/workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.clkmgr_trans.2871059173
Short name	T44
Test name
Test status
Simulation time	29529554 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:36 PM PDT 24
Finished	Jul 12 05:50:39 PM PDT 24
Peak memory	200532 kb
Host	smart-a8e644da-85d4-4815-aec7-209439963e9d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871059173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.2871059173
Directory	/workspace/16.clkmgr_trans/latest

Test location	/workspace/coverage/default/17.clkmgr_alert_test.3785525823
Short name	T630
Test name
Test status
Simulation time	30246533 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:23 PM PDT 24
Peak memory	200708 kb
Host	smart-47c56cc9-29e9-4377-b678-5b6fca73df0a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785525823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.3785525823
Directory	/workspace/17.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.4155465557
Short name	T564
Test name
Test status
Simulation time	22012559 ps
CPU time	0.89 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200592 kb
Host	smart-8eb47242-4d94-40cd-87d3-376e71d8885a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155465557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.4155465557
Directory	/workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_status.611540786
Short name	T146
Test name
Test status
Simulation time	24994505 ps
CPU time	0.73 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200452 kb
Host	smart-f719f2cd-264d-4f50-97a2-5679e4eeb745
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611540786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.611540786
Directory	/workspace/17.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/17.clkmgr_div_intersig_mubi.2893478966
Short name	T357
Test name
Test status
Simulation time	59367790 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:24 PM PDT 24
Peak memory	200504 kb
Host	smart-cfaa5dd9-79f4-4695-a453-04f0cabdd4d0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893478966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.2893478966
Directory	/workspace/17.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_extclk.2064113487
Short name	T524
Test name
Test status
Simulation time	61832873 ps
CPU time	0.98 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:50:17 PM PDT 24
Peak memory	200564 kb
Host	smart-1cf8ec80-df18-4537-89a3-4974f5b5fac9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064113487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2064113487
Directory	/workspace/17.clkmgr_extclk/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency.726045253
Short name	T415
Test name
Test status
Simulation time	1420389936 ps
CPU time	6.5 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	200644 kb
Host	smart-63f6214f-d375-4648-ad88-bc20c00732dc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726045253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.726045253
Directory	/workspace/17.clkmgr_frequency/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency_timeout.3352255515
Short name	T843
Test name
Test status
Simulation time	640521165 ps
CPU time	3.02 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:26 PM PDT 24
Peak memory	200688 kb
Host	smart-61cc538f-4e13-4bbb-a25c-7119de77fc1c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352255515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t imeout.3352255515
Directory	/workspace/17.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/17.clkmgr_idle_intersig_mubi.1695095728
Short name	T304
Test name
Test status
Simulation time	83786864 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200544 kb
Host	smart-c2444e84-1145-4855-bc87-ad3d3faa3166
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695095728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.1695095728
Directory	/workspace/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.347631613
Short name	T235
Test name
Test status
Simulation time	75673364 ps
CPU time	1.03 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200568 kb
Host	smart-e5499b03-73cf-4298-86ab-188865de253d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347631613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.clkmgr_lc_clk_byp_req_intersig_mubi.347631613
Directory	/workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2160553276
Short name	T455
Test name
Test status
Simulation time	22730795 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200600 kb
Host	smart-75f812a7-b398-4e4f-b199-96e933b8fbd3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160553276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_ctrl_intersig_mubi.2160553276
Directory	/workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_peri.2654366973
Short name	T346
Test name
Test status
Simulation time	43301346 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:24 PM PDT 24
Peak memory	200528 kb
Host	smart-86833c4d-bb48-47d5-aae8-e306f2e33f1a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654366973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2654366973
Directory	/workspace/17.clkmgr_peri/latest

Test location	/workspace/coverage/default/17.clkmgr_regwen.85427887
Short name	T789
Test name
Test status
Simulation time	1279975512 ps
CPU time	5.9 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:20 PM PDT 24
Peak memory	200664 kb
Host	smart-0d1ce46f-9ca2-4ff7-8ddc-de606a5dc28f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85427887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.85427887
Directory	/workspace/17.clkmgr_regwen/latest

Test location	/workspace/coverage/default/17.clkmgr_smoke.1513336793
Short name	T348
Test name
Test status
Simulation time	24063702 ps
CPU time	0.84 seconds
Started	Jul 12 05:50:32 PM PDT 24
Finished	Jul 12 05:50:36 PM PDT 24
Peak memory	200484 kb
Host	smart-53090137-39d9-4247-b4c7-c81b5dab5be3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513336793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1513336793
Directory	/workspace/17.clkmgr_smoke/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all.3485890182
Short name	T617
Test name
Test status
Simulation time	7440352983 ps
CPU time	31.23 seconds
Started	Jul 12 05:50:17 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	201032 kb
Host	smart-7f634168-b49a-4e8e-b463-34b8afb2b4f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485890182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.3485890182
Directory	/workspace/17.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/17.clkmgr_trans.1648121238
Short name	T283
Test name
Test status
Simulation time	32057215 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200588 kb
Host	smart-1523dd4e-6fdb-46df-873e-989f45161d29
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648121238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.1648121238
Directory	/workspace/17.clkmgr_trans/latest

Test location	/workspace/coverage/default/18.clkmgr_alert_test.190710881
Short name	T233
Test name
Test status
Simulation time	44318070 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:25 PM PDT 24
Peak memory	200696 kb
Host	smart-92d47a4c-fa40-4bd0-b6e4-6b62df4f2fcd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190710881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkm gr_alert_test.190710881
Directory	/workspace/18.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1788082843
Short name	T83
Test name
Test status
Simulation time	19651465 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200616 kb
Host	smart-ad409618-38a3-4a27-b760-b8517c2a0ce2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788082843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.1788082843
Directory	/workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_status.4146798759
Short name	T703
Test name
Test status
Simulation time	43804666 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:29 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	199712 kb
Host	smart-322197e5-f589-44b5-b220-2626514e6659
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146798759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.4146798759
Directory	/workspace/18.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/18.clkmgr_div_intersig_mubi.251448241
Short name	T408
Test name
Test status
Simulation time	18652040 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200572 kb
Host	smart-dcde0c41-60b3-48c1-ab05-86ac8b3be77f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251448241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.clkmgr_div_intersig_mubi.251448241
Directory	/workspace/18.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_extclk.2680776938
Short name	T160
Test name
Test status
Simulation time	16606748 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200548 kb
Host	smart-47ab1f44-7a8f-48f0-bfa7-04b4f77dacc5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680776938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2680776938
Directory	/workspace/18.clkmgr_extclk/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency.2154522460
Short name	T101
Test name
Test status
Simulation time	1642931993 ps
CPU time	13.32 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200612 kb
Host	smart-e41da430-50fa-49e0-825f-8d251dea75c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154522460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.2154522460
Directory	/workspace/18.clkmgr_frequency/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency_timeout.2324604253
Short name	T29
Test name
Test status
Simulation time	1348802576 ps
CPU time	5.65 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:20 PM PDT 24
Peak memory	200708 kb
Host	smart-39dee31d-41c0-4521-b371-d995e6c62c4d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324604253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.2324604253
Directory	/workspace/18.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2346564518
Short name	T189
Test name
Test status
Simulation time	23177222 ps
CPU time	0.83 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200488 kb
Host	smart-3ca89273-55bf-474f-8b71-7a63eb97a7c1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346564518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.2346564518
Directory	/workspace/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3321082675
Short name	T577
Test name
Test status
Simulation time	215455236 ps
CPU time	1.37 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200512 kb
Host	smart-0cbabed5-7336-4522-a599-aad2777449e7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321082675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3321082675
Directory	/workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.102524757
Short name	T234
Test name
Test status
Simulation time	97779581 ps
CPU time	0.99 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:24 PM PDT 24
Peak memory	200584 kb
Host	smart-e565ae80-3749-4ba3-8bb2-fcf6d72f9719
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102524757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.clkmgr_lc_ctrl_intersig_mubi.102524757
Directory	/workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_peri.324215160
Short name	T163
Test name
Test status
Simulation time	48474789 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:20 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200464 kb
Host	smart-8e1f2cf0-f533-47b0-9c02-07414a48b6d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324215160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.324215160
Directory	/workspace/18.clkmgr_peri/latest

Test location	/workspace/coverage/default/18.clkmgr_regwen.3324115481
Short name	T507
Test name
Test status
Simulation time	1304671117 ps
CPU time	4.73 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200612 kb
Host	smart-386b2798-a5db-4a9b-bff7-a9c70ea3aed8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324115481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3324115481
Directory	/workspace/18.clkmgr_regwen/latest

Test location	/workspace/coverage/default/18.clkmgr_smoke.4269537997
Short name	T323
Test name
Test status
Simulation time	23594193 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:13 PM PDT 24
Finished	Jul 12 05:50:15 PM PDT 24
Peak memory	200508 kb
Host	smart-7f16880f-cd68-46ed-a1f1-e5e65bbc6051
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269537997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.4269537997
Directory	/workspace/18.clkmgr_smoke/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all.3589713427
Short name	T106
Test name
Test status
Simulation time	11095846017 ps
CPU time	47.27 seconds
Started	Jul 12 05:50:14 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200828 kb
Host	smart-33fe5f63-3488-4cf3-8695-ae56441ff0cf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589713427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.3589713427
Directory	/workspace/18.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3794528357
Short name	T816
Test name
Test status
Simulation time	84704044530 ps
CPU time	519.49 seconds
Started	Jul 12 05:50:17 PM PDT 24
Finished	Jul 12 05:58:58 PM PDT 24
Peak memory	217320 kb
Host	smart-5b6b1fad-8f01-49ff-be52-76a5cbf5be70
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3794528357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3794528357
Directory	/workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.clkmgr_trans.2064196537
Short name	T168
Test name
Test status
Simulation time	34508064 ps
CPU time	0.97 seconds
Started	Jul 12 05:50:44 PM PDT 24
Finished	Jul 12 05:50:46 PM PDT 24
Peak memory	200528 kb
Host	smart-940bcb63-7035-405f-a012-2b1f26c06e93
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064196537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.2064196537
Directory	/workspace/18.clkmgr_trans/latest

Test location	/workspace/coverage/default/19.clkmgr_alert_test.3667505032
Short name	T213
Test name
Test status
Simulation time	28397205 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:40 PM PDT 24
Finished	Jul 12 05:50:41 PM PDT 24
Peak memory	200656 kb
Host	smart-d8b842c0-ed06-421f-baaf-cd1aa6a1dd7c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667505032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk mgr_alert_test.3667505032
Directory	/workspace/19.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3216446566
Short name	T6
Test name
Test status
Simulation time	83416635 ps
CPU time	1.08 seconds
Started	Jul 12 05:50:32 PM PDT 24
Finished	Jul 12 05:50:37 PM PDT 24
Peak memory	200556 kb
Host	smart-2f2d0c02-900b-4e01-87a9-b71c668b0425
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216446566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.3216446566
Directory	/workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_status.4191691445
Short name	T19
Test name
Test status
Simulation time	52841026 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	199752 kb
Host	smart-af2240e6-c8ee-4c32-b45d-5a496074b191
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191691445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.4191691445
Directory	/workspace/19.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/19.clkmgr_div_intersig_mubi.2609501335
Short name	T595
Test name
Test status
Simulation time	36634104 ps
CPU time	0.91 seconds
Started	Jul 12 05:50:31 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200560 kb
Host	smart-3bd7e143-3b60-4393-8037-d4aa3765d30e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609501335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.2609501335
Directory	/workspace/19.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_extclk.1467562311
Short name	T837
Test name
Test status
Simulation time	17370093 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:17 PM PDT 24
Finished	Jul 12 05:50:19 PM PDT 24
Peak memory	200680 kb
Host	smart-4b271b69-e686-43a3-9c96-f55e49b95fe1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467562311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1467562311
Directory	/workspace/19.clkmgr_extclk/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency.426137651
Short name	T552
Test name
Test status
Simulation time	1654309014 ps
CPU time	7.5 seconds
Started	Jul 12 05:50:28 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	200592 kb
Host	smart-dab8ee01-648a-489e-8537-8f47fe10a050
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426137651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.426137651
Directory	/workspace/19.clkmgr_frequency/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency_timeout.1354980303
Short name	T184
Test name
Test status
Simulation time	1115079697 ps
CPU time	3.96 seconds
Started	Jul 12 05:50:18 PM PDT 24
Finished	Jul 12 05:50:24 PM PDT 24
Peak memory	200676 kb
Host	smart-63162cd7-f5b8-4642-8a1d-87341cb50cc2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354980303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t imeout.1354980303
Directory	/workspace/19.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/19.clkmgr_idle_intersig_mubi.3529393267
Short name	T196
Test name
Test status
Simulation time	60472521 ps
CPU time	0.91 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200532 kb
Host	smart-f2b6713f-3fec-48b3-a272-bc45282a201b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529393267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.3529393267
Directory	/workspace/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.546710032
Short name	T396
Test name
Test status
Simulation time	50759077 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:22 PM PDT 24
Finished	Jul 12 05:50:26 PM PDT 24
Peak memory	200564 kb
Host	smart-236be79e-24f6-4066-9f74-3491518fcd00
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546710032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.clkmgr_lc_clk_byp_req_intersig_mubi.546710032
Directory	/workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1341936706
Short name	T814
Test name
Test status
Simulation time	79120303 ps
CPU time	1.01 seconds
Started	Jul 12 05:50:30 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200524 kb
Host	smart-49295203-a84a-4e67-b601-d9cceb2d3838
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341936706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_ctrl_intersig_mubi.1341936706
Directory	/workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_peri.887705190
Short name	T708
Test name
Test status
Simulation time	20280252 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200536 kb
Host	smart-c7017c02-dda3-4481-b98e-eb74e6530786
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887705190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.887705190
Directory	/workspace/19.clkmgr_peri/latest

Test location	/workspace/coverage/default/19.clkmgr_regwen.1999067190
Short name	T846
Test name
Test status
Simulation time	1892755829 ps
CPU time	5.75 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:33 PM PDT 24
Peak memory	200668 kb
Host	smart-998714b5-5963-4ef6-b8c5-100efbb2aff1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999067190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1999067190
Directory	/workspace/19.clkmgr_regwen/latest

Test location	/workspace/coverage/default/19.clkmgr_smoke.1907087214
Short name	T656
Test name
Test status
Simulation time	22471230 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:32 PM PDT 24
Finished	Jul 12 05:50:36 PM PDT 24
Peak memory	200484 kb
Host	smart-a5cfb30a-156f-4c23-92ca-650060f30a71
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907087214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.1907087214
Directory	/workspace/19.clkmgr_smoke/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all.2244006932
Short name	T670
Test name
Test status
Simulation time	1088455017 ps
CPU time	5.49 seconds
Started	Jul 12 05:50:22 PM PDT 24
Finished	Jul 12 05:50:30 PM PDT 24
Peak memory	200740 kb
Host	smart-50b92714-11e5-4a32-b9d5-168f7d150915
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244006932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.2244006932
Directory	/workspace/19.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.2602210360
Short name	T34
Test name
Test status
Simulation time	39022425040 ps
CPU time	378 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:56:46 PM PDT 24
Peak memory	209168 kb
Host	smart-a0095f7d-acaa-4e78-a8d6-451d42952614
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2602210360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.2602210360
Directory	/workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.clkmgr_trans.1323848409
Short name	T619
Test name
Test status
Simulation time	272439786 ps
CPU time	1.56 seconds
Started	Jul 12 05:50:18 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	200488 kb
Host	smart-da33d0cf-c820-4fa3-9d4c-5e54037ab67c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323848409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1323848409
Directory	/workspace/19.clkmgr_trans/latest

Test location	/workspace/coverage/default/2.clkmgr_alert_test.2568254729
Short name	T836
Test name
Test status
Simulation time	40223290 ps
CPU time	0.84 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:49:44 PM PDT 24
Peak memory	200712 kb
Host	smart-78a237a6-59d4-4e70-a822-1338bb557c90
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568254729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm gr_alert_test.2568254729
Directory	/workspace/2.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1521027779
Short name	T753
Test name
Test status
Simulation time	37326189 ps
CPU time	0.89 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:49:45 PM PDT 24
Peak memory	200572 kb
Host	smart-098b366e-437c-40c6-8aea-c73ed7b4e3d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521027779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.1521027779
Directory	/workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_status.1373203857
Short name	T20
Test name
Test status
Simulation time	16505617 ps
CPU time	0.79 seconds
Started	Jul 12 05:49:35 PM PDT 24
Finished	Jul 12 05:49:36 PM PDT 24
Peak memory	199980 kb
Host	smart-d97c6f7c-86e3-41af-8267-43a58c7453c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373203857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1373203857
Directory	/workspace/2.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/2.clkmgr_div_intersig_mubi.3013012326
Short name	T251
Test name
Test status
Simulation time	27114580 ps
CPU time	0.79 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:40 PM PDT 24
Peak memory	200568 kb
Host	smart-87b28313-a101-4310-8b86-2f6f086ccaea
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013012326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.3013012326
Directory	/workspace/2.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_extclk.4264310302
Short name	T779
Test name
Test status
Simulation time	14745475 ps
CPU time	0.77 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:42 PM PDT 24
Peak memory	200552 kb
Host	smart-4d97b5f9-0b82-4351-9700-25ec859f092a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264310302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.4264310302
Directory	/workspace/2.clkmgr_extclk/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency.1419262245
Short name	T790
Test name
Test status
Simulation time	1878324329 ps
CPU time	14.54 seconds
Started	Jul 12 05:49:35 PM PDT 24
Finished	Jul 12 05:49:51 PM PDT 24
Peak memory	200732 kb
Host	smart-1599c780-736e-4ae1-9711-44fc17e44666
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419262245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1419262245
Directory	/workspace/2.clkmgr_frequency/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency_timeout.2910883109
Short name	T347
Test name
Test status
Simulation time	2419571614 ps
CPU time	17.77 seconds
Started	Jul 12 05:49:42 PM PDT 24
Finished	Jul 12 05:50:02 PM PDT 24
Peak memory	200812 kb
Host	smart-39ddbecc-435b-4f12-b55f-ae947a8c8765
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910883109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti meout.2910883109
Directory	/workspace/2.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/2.clkmgr_idle_intersig_mubi.4203727709
Short name	T495
Test name
Test status
Simulation time	27058896 ps
CPU time	1.06 seconds
Started	Jul 12 05:49:35 PM PDT 24
Finished	Jul 12 05:49:37 PM PDT 24
Peak memory	200576 kb
Host	smart-65b3b2b7-b9ea-4f1b-a587-1f9763769cc1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203727709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.4203727709
Directory	/workspace/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1743505775
Short name	T549
Test name
Test status
Simulation time	21158063 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:42 PM PDT 24
Peak memory	200580 kb
Host	smart-8e5a07e5-ec79-4f86-9003-59bddde7f185
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743505775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.1743505775
Directory	/workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.4005665770
Short name	T131
Test name
Test status
Simulation time	17658497 ps
CPU time	0.75 seconds
Started	Jul 12 05:49:37 PM PDT 24
Finished	Jul 12 05:49:39 PM PDT 24
Peak memory	200552 kb
Host	smart-19e4faca-0dae-45a7-8527-23d11271cd91
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005665770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.4005665770
Directory	/workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_peri.2386132225
Short name	T633
Test name
Test status
Simulation time	16929066 ps
CPU time	0.71 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:49:44 PM PDT 24
Peak memory	200448 kb
Host	smart-a57345f6-f40c-44ec-9a14-1847a77615a4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386132225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2386132225
Directory	/workspace/2.clkmgr_peri/latest

Test location	/workspace/coverage/default/2.clkmgr_regwen.1597706003
Short name	T597
Test name
Test status
Simulation time	1578052811 ps
CPU time	4.97 seconds
Started	Jul 12 05:49:36 PM PDT 24
Finished	Jul 12 05:49:42 PM PDT 24
Peak memory	200632 kb
Host	smart-d9f9bc2d-f4d9-4fb5-ab71-6904b490a79e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597706003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1597706003
Directory	/workspace/2.clkmgr_regwen/latest

Test location	/workspace/coverage/default/2.clkmgr_sec_cm.669290589
Short name	T46
Test name
Test status
Simulation time	1904905301 ps
CPU time	7.44 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:47 PM PDT 24
Peak memory	217400 kb
Host	smart-49ef1ac6-fe07-498e-8a43-ea146289aa43
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669290589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr _sec_cm.669290589
Directory	/workspace/2.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/2.clkmgr_smoke.2217461156
Short name	T743
Test name
Test status
Simulation time	44330202 ps
CPU time	0.86 seconds
Started	Jul 12 05:49:36 PM PDT 24
Finished	Jul 12 05:49:39 PM PDT 24
Peak memory	200492 kb
Host	smart-c575c58d-36de-4ae6-ae5a-1d6526a72148
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217461156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2217461156
Directory	/workspace/2.clkmgr_smoke/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all.3858758997
Short name	T127
Test name
Test status
Simulation time	7963042413 ps
CPU time	33.48 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:50:16 PM PDT 24
Peak memory	200856 kb
Host	smart-8ec13120-966c-4ee9-a729-fba73f1365ab
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858758997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.3858758997
Directory	/workspace/2.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.2580353019
Short name	T744
Test name
Test status
Simulation time	199132067516 ps
CPU time	1297.75 seconds
Started	Jul 12 05:49:33 PM PDT 24
Finished	Jul 12 06:11:12 PM PDT 24
Peak memory	217348 kb
Host	smart-584cb6d0-fae1-425a-ad49-34bcdebc899f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2580353019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2580353019
Directory	/workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_trans.2243192053
Short name	T588
Test name
Test status
Simulation time	27036874 ps
CPU time	0.79 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:42 PM PDT 24
Peak memory	200564 kb
Host	smart-7c35cb1b-9b0e-4873-9c9f-719a41e12bc4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243192053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2243192053
Directory	/workspace/2.clkmgr_trans/latest

Test location	/workspace/coverage/default/20.clkmgr_alert_test.3135772144
Short name	T458
Test name
Test status
Simulation time	17932445 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:30 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200656 kb
Host	smart-0f62cbeb-b5f3-40e1-83f8-d54002c96a23
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135772144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk mgr_alert_test.3135772144
Directory	/workspace/20.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3880226987
Short name	T804
Test name
Test status
Simulation time	21721568 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:30 PM PDT 24
Peak memory	200584 kb
Host	smart-e1ae6567-cca0-46f7-a98e-d53403def58e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880226987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3880226987
Directory	/workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_status.1120747897
Short name	T678
Test name
Test status
Simulation time	17033450 ps
CPU time	0.75 seconds
Started	Jul 12 05:53:24 PM PDT 24
Finished	Jul 12 05:53:26 PM PDT 24
Peak memory	199744 kb
Host	smart-39f63548-9652-48d3-bdbe-4e14e6011679
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120747897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1120747897
Directory	/workspace/20.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/20.clkmgr_div_intersig_mubi.2480343760
Short name	T42
Test name
Test status
Simulation time	22888948 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:27 PM PDT 24
Peak memory	200432 kb
Host	smart-defde130-4aa5-4284-aa32-2bf039de49b3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480343760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.2480343760
Directory	/workspace/20.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_extclk.3325195285
Short name	T714
Test name
Test status
Simulation time	14682286 ps
CPU time	0.74 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:24 PM PDT 24
Peak memory	200560 kb
Host	smart-71c9ff8d-7a2d-4363-8a44-a9e02019b1a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325195285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3325195285
Directory	/workspace/20.clkmgr_extclk/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency.2364841506
Short name	T654
Test name
Test status
Simulation time	797316278 ps
CPU time	6.19 seconds
Started	Jul 12 05:50:28 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200620 kb
Host	smart-d5b202e5-6050-428a-8251-6ca3a552c033
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364841506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2364841506
Directory	/workspace/20.clkmgr_frequency/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency_timeout.732501279
Short name	T314
Test name
Test status
Simulation time	2063875060 ps
CPU time	10.64 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:39 PM PDT 24
Peak memory	200784 kb
Host	smart-b6452fba-6637-4481-9a9a-2454cb110bf4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732501279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_ti meout.732501279
Directory	/workspace/20.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1125584465
Short name	T222
Test name
Test status
Simulation time	66234499 ps
CPU time	1.14 seconds
Started	Jul 12 05:50:32 PM PDT 24
Finished	Jul 12 05:50:36 PM PDT 24
Peak memory	200684 kb
Host	smart-4c571722-f12a-4dc8-9825-ab8f92310a0b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125584465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.1125584465
Directory	/workspace/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1897686656
Short name	T244
Test name
Test status
Simulation time	65818275 ps
CPU time	0.95 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:27 PM PDT 24
Peak memory	200588 kb
Host	smart-fcab745e-a1b2-4b04-8970-bb69902fc8e1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897686656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_clk_byp_req_intersig_mubi.1897686656
Directory	/workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2466395235
Short name	T393
Test name
Test status
Simulation time	17374613 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:30 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200692 kb
Host	smart-c2b85359-0688-49ad-b038-c55ee494aec0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466395235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_ctrl_intersig_mubi.2466395235
Directory	/workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_peri.2169306010
Short name	T611
Test name
Test status
Simulation time	23416458 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200452 kb
Host	smart-f61dccf0-680a-418b-a9d0-5340a2370366
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169306010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.2169306010
Directory	/workspace/20.clkmgr_peri/latest

Test location	/workspace/coverage/default/20.clkmgr_regwen.1929365275
Short name	T669
Test name
Test status
Simulation time	114018834 ps
CPU time	1.3 seconds
Started	Jul 12 05:50:28 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200504 kb
Host	smart-ea50f390-9151-490b-a080-a06d0c8bde99
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929365275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1929365275
Directory	/workspace/20.clkmgr_regwen/latest

Test location	/workspace/coverage/default/20.clkmgr_smoke.3191553769
Short name	T757
Test name
Test status
Simulation time	27529677 ps
CPU time	0.9 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:24 PM PDT 24
Peak memory	200520 kb
Host	smart-7fb21f72-80ec-4167-aa66-0380b4da0e9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191553769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3191553769
Directory	/workspace/20.clkmgr_smoke/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all.3247430223
Short name	T33
Test name
Test status
Simulation time	9526425420 ps
CPU time	50.63 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200836 kb
Host	smart-d801ba1f-d774-41b3-a6c3-b5052cdf5f63
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247430223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3247430223
Directory	/workspace/20.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.1042011908
Short name	T370
Test name
Test status
Simulation time	45546098682 ps
CPU time	701.14 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 06:02:09 PM PDT 24
Peak memory	209204 kb
Host	smart-8ac4a9ae-8111-4f09-9d5b-915deaf9efc7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1042011908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.1042011908
Directory	/workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.clkmgr_trans.1808258733
Short name	T825
Test name
Test status
Simulation time	31049102 ps
CPU time	0.94 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:31 PM PDT 24
Peak memory	200528 kb
Host	smart-719e4d8a-74a2-4946-8de7-5669efe9dd32
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808258733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1808258733
Directory	/workspace/20.clkmgr_trans/latest

Test location	/workspace/coverage/default/21.clkmgr_alert_test.3838120148
Short name	T460
Test name
Test status
Simulation time	54676747 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200656 kb
Host	smart-8e126b8f-f97f-422a-9998-c2914a07ec36
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838120148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.3838120148
Directory	/workspace/21.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2656892719
Short name	T719
Test name
Test status
Simulation time	40274915 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200588 kb
Host	smart-eb306249-e148-44c1-9410-ed84c3872707
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656892719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.2656892719
Directory	/workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_status.1215149689
Short name	T555
Test name
Test status
Simulation time	19468461 ps
CPU time	0.73 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	199752 kb
Host	smart-26b4e6eb-fcf6-4cb3-ad37-9d21cb73a2ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215149689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1215149689
Directory	/workspace/21.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/21.clkmgr_div_intersig_mubi.565674152
Short name	T365
Test name
Test status
Simulation time	23789264 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:31 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200528 kb
Host	smart-bc88603b-5569-4b51-8ca5-74c3374c7241
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565674152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.clkmgr_div_intersig_mubi.565674152
Directory	/workspace/21.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_extclk.2950117030
Short name	T676
Test name
Test status
Simulation time	91090051 ps
CPU time	1.15 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200552 kb
Host	smart-399b1cb8-2517-4568-a5a5-09cd8a253210
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950117030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2950117030
Directory	/workspace/21.clkmgr_extclk/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency.2722532554
Short name	T515
Test name
Test status
Simulation time	1579216906 ps
CPU time	7.77 seconds
Started	Jul 12 05:50:27 PM PDT 24
Finished	Jul 12 05:50:39 PM PDT 24
Peak memory	200584 kb
Host	smart-8d9ea8a7-6f5f-4dd2-9d6a-27017734a86b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722532554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2722532554
Directory	/workspace/21.clkmgr_frequency/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency_timeout.2381812350
Short name	T377
Test name
Test status
Simulation time	1733749157 ps
CPU time	6.13 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:36 PM PDT 24
Peak memory	200936 kb
Host	smart-1b43914f-093e-4d40-b277-2fabff0c5b6f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381812350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t imeout.2381812350
Directory	/workspace/21.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3617849061
Short name	T570
Test name
Test status
Simulation time	96005039 ps
CPU time	1.12 seconds
Started	Jul 12 05:50:23 PM PDT 24
Finished	Jul 12 05:50:28 PM PDT 24
Peak memory	200576 kb
Host	smart-e45f3a65-f373-406a-b9d4-f8ed5317f050
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617849061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3617849061
Directory	/workspace/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1433745123
Short name	T510
Test name
Test status
Simulation time	13511834 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:50:24 PM PDT 24
Peak memory	200576 kb
Host	smart-9e18e8bd-8eea-4c66-8649-ca115123b379
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433745123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_clk_byp_req_intersig_mubi.1433745123
Directory	/workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1395146500
Short name	T788
Test name
Test status
Simulation time	40535896 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:22 PM PDT 24
Peak memory	200484 kb
Host	smart-56e1ebf6-c428-4d91-aa2d-894784013be1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395146500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_ctrl_intersig_mubi.1395146500
Directory	/workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_peri.3926197391
Short name	T823
Test name
Test status
Simulation time	20384222 ps
CPU time	0.74 seconds
Started	Jul 12 05:50:22 PM PDT 24
Finished	Jul 12 05:50:26 PM PDT 24
Peak memory	200504 kb
Host	smart-96d8a4b1-1797-4ad2-9b28-03661997989a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926197391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3926197391
Directory	/workspace/21.clkmgr_peri/latest

Test location	/workspace/coverage/default/21.clkmgr_regwen.1285762424
Short name	T67
Test name
Test status
Simulation time	1132557406 ps
CPU time	5.53 seconds
Started	Jul 12 05:50:35 PM PDT 24
Finished	Jul 12 05:50:43 PM PDT 24
Peak memory	200652 kb
Host	smart-935b3151-9fb2-4f04-b9cb-390380d830f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285762424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1285762424
Directory	/workspace/21.clkmgr_regwen/latest

Test location	/workspace/coverage/default/21.clkmgr_smoke.1353652403
Short name	T423
Test name
Test status
Simulation time	28591976 ps
CPU time	0.83 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200508 kb
Host	smart-fb57bf99-829e-4663-be1e-3280401848c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353652403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1353652403
Directory	/workspace/21.clkmgr_smoke/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all.3423040378
Short name	T530
Test name
Test status
Simulation time	5700077907 ps
CPU time	41.11 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200856 kb
Host	smart-6c0d8575-6720-49fd-959d-5f2487303c03
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423040378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.3423040378
Directory	/workspace/21.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.389659517
Short name	T158
Test name
Test status
Simulation time	89466570311 ps
CPU time	539.02 seconds
Started	Jul 12 05:50:21 PM PDT 24
Finished	Jul 12 05:59:22 PM PDT 24
Peak memory	211336 kb
Host	smart-f429ed4e-d7a4-40a2-bc0f-78c0a520fb4d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=389659517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.389659517
Directory	/workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.clkmgr_trans.2055571765
Short name	T291
Test name
Test status
Simulation time	65565036 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:26 PM PDT 24
Finished	Jul 12 05:50:31 PM PDT 24
Peak memory	200564 kb
Host	smart-2ffe843a-ebb6-4603-a637-6f29e64e266d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055571765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2055571765
Directory	/workspace/21.clkmgr_trans/latest

Test location	/workspace/coverage/default/22.clkmgr_alert_test.459206846
Short name	T583
Test name
Test status
Simulation time	17840358 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:37 PM PDT 24
Finished	Jul 12 05:50:39 PM PDT 24
Peak memory	200688 kb
Host	smart-eee3ee38-ef76-4a09-a7d2-dae28fed7cc7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459206846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkm gr_alert_test.459206846
Directory	/workspace/22.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.2832415256
Short name	T679
Test name
Test status
Simulation time	21709916 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:28 PM PDT 24
Peak memory	200604 kb
Host	smart-e3984f90-dfee-4b19-b96f-f89f52ed9aca
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832415256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.2832415256
Directory	/workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_status.3619213716
Short name	T559
Test name
Test status
Simulation time	12400868 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:28 PM PDT 24
Finished	Jul 12 05:50:33 PM PDT 24
Peak memory	199748 kb
Host	smart-d8daf703-3771-45d3-ae06-acc6f441bc8a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619213716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3619213716
Directory	/workspace/22.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/22.clkmgr_div_intersig_mubi.3187414802
Short name	T537
Test name
Test status
Simulation time	39360811 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:32 PM PDT 24
Peak memory	200588 kb
Host	smart-432f8e28-323f-4108-b5ea-c9dee6d5ad69
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187414802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.3187414802
Directory	/workspace/22.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_extclk.70828540
Short name	T342
Test name
Test status
Simulation time	55557749 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200508 kb
Host	smart-144a924b-b828-4a79-88af-7feb588f4307
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70828540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.70828540
Directory	/workspace/22.clkmgr_extclk/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency.3393342489
Short name	T486
Test name
Test status
Simulation time	2000594235 ps
CPU time	15.09 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200772 kb
Host	smart-c04ece49-cf01-4a23-9a81-b26f89d4482e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393342489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3393342489
Directory	/workspace/22.clkmgr_frequency/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency_timeout.3811454836
Short name	T456
Test name
Test status
Simulation time	1352630611 ps
CPU time	6.93 seconds
Started	Jul 12 05:50:27 PM PDT 24
Finished	Jul 12 05:50:39 PM PDT 24
Peak memory	200908 kb
Host	smart-3361eb6a-35c7-4e35-bf77-5a1934446ed1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811454836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t imeout.3811454836
Directory	/workspace/22.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1656580550
Short name	T449
Test name
Test status
Simulation time	57078089 ps
CPU time	0.91 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200572 kb
Host	smart-f9474bea-d0ba-4b3f-bf31-303e6ecda182
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656580550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.1656580550
Directory	/workspace/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.1879180722
Short name	T182
Test name
Test status
Simulation time	38726615 ps
CPU time	0.84 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:29 PM PDT 24
Peak memory	200496 kb
Host	smart-9d9863ba-9416-4636-a360-42860bcb67be
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879180722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_clk_byp_req_intersig_mubi.1879180722
Directory	/workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.4018879744
Short name	T750
Test name
Test status
Simulation time	25064600 ps
CPU time	0.91 seconds
Started	Jul 12 05:50:31 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200564 kb
Host	smart-99c2a3ea-08b8-4bd1-b939-0d1d611fc091
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018879744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_ctrl_intersig_mubi.4018879744
Directory	/workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_peri.258172272
Short name	T494
Test name
Test status
Simulation time	26873797 ps
CPU time	0.74 seconds
Started	Jul 12 05:50:26 PM PDT 24
Finished	Jul 12 05:50:31 PM PDT 24
Peak memory	200572 kb
Host	smart-536ee1d5-ee9e-4bbf-b21b-e4542c0784f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258172272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.258172272
Directory	/workspace/22.clkmgr_peri/latest

Test location	/workspace/coverage/default/22.clkmgr_regwen.1029305751
Short name	T87
Test name
Test status
Simulation time	396242901 ps
CPU time	2.23 seconds
Started	Jul 12 05:50:52 PM PDT 24
Finished	Jul 12 05:50:56 PM PDT 24
Peak memory	200564 kb
Host	smart-2fa02f07-4a75-4313-bd52-5b95e2a4b3b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029305751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.1029305751
Directory	/workspace/22.clkmgr_regwen/latest

Test location	/workspace/coverage/default/22.clkmgr_smoke.3357693352
Short name	T352
Test name
Test status
Simulation time	17388820 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:26 PM PDT 24
Finished	Jul 12 05:50:31 PM PDT 24
Peak memory	200504 kb
Host	smart-75d0f06e-d2e3-44ea-b41f-76e0f97b5e4c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357693352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.3357693352
Directory	/workspace/22.clkmgr_smoke/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all.2318083654
Short name	T651
Test name
Test status
Simulation time	1528748666 ps
CPU time	12 seconds
Started	Jul 12 05:50:36 PM PDT 24
Finished	Jul 12 05:50:50 PM PDT 24
Peak memory	200816 kb
Host	smart-5c15dd14-f1f9-41af-9306-2dc0404dd253
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318083654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2318083654
Directory	/workspace/22.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.3765639127
Short name	T59
Test name
Test status
Simulation time	202051452976 ps
CPU time	1230.84 seconds
Started	Jul 12 05:50:29 PM PDT 24
Finished	Jul 12 06:11:04 PM PDT 24
Peak memory	209196 kb
Host	smart-67bd2370-5f4c-41a2-babb-bae6a1944e45
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3765639127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.3765639127
Directory	/workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.clkmgr_trans.4183390804
Short name	T548
Test name
Test status
Simulation time	47787982 ps
CPU time	1.03 seconds
Started	Jul 12 05:50:28 PM PDT 24
Finished	Jul 12 05:50:33 PM PDT 24
Peak memory	200744 kb
Host	smart-721b35f3-4e4b-4351-b307-347a39f25e83
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183390804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.4183390804
Directory	/workspace/22.clkmgr_trans/latest

Test location	/workspace/coverage/default/23.clkmgr_alert_test.3490172628
Short name	T277
Test name
Test status
Simulation time	17077002 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:45 PM PDT 24
Finished	Jul 12 05:50:46 PM PDT 24
Peak memory	200548 kb
Host	smart-76dff297-ff2e-400c-8800-eee2c485e0c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490172628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk mgr_alert_test.3490172628
Directory	/workspace/23.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3676868934
Short name	T76
Test name
Test status
Simulation time	24029912 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:30 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200576 kb
Host	smart-9419c5c4-6a29-426e-bcb1-13cbe29fed43
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676868934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.3676868934
Directory	/workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_status.3239594688
Short name	T265
Test name
Test status
Simulation time	16768830 ps
CPU time	0.74 seconds
Started	Jul 12 05:50:26 PM PDT 24
Finished	Jul 12 05:50:31 PM PDT 24
Peak memory	200448 kb
Host	smart-7da565bf-20a2-4e4c-a857-3054fce9c799
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239594688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3239594688
Directory	/workspace/23.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/23.clkmgr_div_intersig_mubi.3092046750
Short name	T579
Test name
Test status
Simulation time	16612498 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:39 PM PDT 24
Finished	Jul 12 05:50:41 PM PDT 24
Peak memory	200572 kb
Host	smart-85452e2f-680e-45d0-8bc0-234fe0866464
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092046750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.3092046750
Directory	/workspace/23.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_extclk.931730171
Short name	T500
Test name
Test status
Simulation time	40023237 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:30 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200560 kb
Host	smart-68852575-701f-4128-9e28-87341fa96dcf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931730171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.931730171
Directory	/workspace/23.clkmgr_extclk/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency.1178531404
Short name	T807
Test name
Test status
Simulation time	2040747251 ps
CPU time	7.74 seconds
Started	Jul 12 05:50:35 PM PDT 24
Finished	Jul 12 05:50:45 PM PDT 24
Peak memory	200708 kb
Host	smart-c128203b-ed72-4494-ae2d-1ffa2f4b218d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178531404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1178531404
Directory	/workspace/23.clkmgr_frequency/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency_timeout.3527205083
Short name	T250
Test name
Test status
Simulation time	142730068 ps
CPU time	1.54 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200684 kb
Host	smart-cf5d76f2-1cca-49d9-8a16-c1cde0159b3f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527205083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t imeout.3527205083
Directory	/workspace/23.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/23.clkmgr_idle_intersig_mubi.470417552
Short name	T674
Test name
Test status
Simulation time	18530897 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200556 kb
Host	smart-1dab34bb-d993-4a0a-b470-c254d1597fdd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470417552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.clkmgr_idle_intersig_mubi.470417552
Directory	/workspace/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.4229686673
Short name	T176
Test name
Test status
Simulation time	20056221 ps
CPU time	0.84 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200568 kb
Host	smart-3ef2bb7b-f22e-4066-9bb1-06802b385d87
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229686673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.4229686673
Directory	/workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3146226684
Short name	T320
Test name
Test status
Simulation time	17637196 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:27 PM PDT 24
Finished	Jul 12 05:50:32 PM PDT 24
Peak memory	200568 kb
Host	smart-f54c9af1-e5ab-4fd6-b26d-4408f652ff77
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146226684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_ctrl_intersig_mubi.3146226684
Directory	/workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_peri.2501075989
Short name	T810
Test name
Test status
Simulation time	24185279 ps
CPU time	0.72 seconds
Started	Jul 12 05:50:31 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200544 kb
Host	smart-91318642-c88c-4d89-99ef-756d916f0723
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501075989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.2501075989
Directory	/workspace/23.clkmgr_peri/latest

Test location	/workspace/coverage/default/23.clkmgr_regwen.3698015808
Short name	T732
Test name
Test status
Simulation time	422235016 ps
CPU time	3.02 seconds
Started	Jul 12 05:50:25 PM PDT 24
Finished	Jul 12 05:50:33 PM PDT 24
Peak memory	200544 kb
Host	smart-fcdf3e07-520b-4db4-9724-cdc8e9b44212
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698015808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3698015808
Directory	/workspace/23.clkmgr_regwen/latest

Test location	/workspace/coverage/default/23.clkmgr_smoke.972326194
Short name	T571
Test name
Test status
Simulation time	22400405 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200524 kb
Host	smart-b80fffa5-02cc-48ab-b51a-3501ff737a3a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972326194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.972326194
Directory	/workspace/23.clkmgr_smoke/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all.415975031
Short name	T809
Test name
Test status
Simulation time	11249448534 ps
CPU time	45.6 seconds
Started	Jul 12 05:50:36 PM PDT 24
Finished	Jul 12 05:51:23 PM PDT 24
Peak memory	200972 kb
Host	smart-8ecdf796-2328-40f3-bf50-bf4898ddfa9b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415975031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.415975031
Directory	/workspace/23.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.2705008920
Short name	T730
Test name
Test status
Simulation time	135407622223 ps
CPU time	917.09 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 06:05:54 PM PDT 24
Peak memory	209132 kb
Host	smart-057506b6-5700-4e18-a5cd-c030e3969910
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2705008920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2705008920
Directory	/workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.clkmgr_trans.2872838939
Short name	T481
Test name
Test status
Simulation time	37917141 ps
CPU time	1.01 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200568 kb
Host	smart-6ddf383e-9c1a-4c9a-967f-bbae53553c58
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872838939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2872838939
Directory	/workspace/23.clkmgr_trans/latest

Test location	/workspace/coverage/default/24.clkmgr_alert_test.1146573947
Short name	T397
Test name
Test status
Simulation time	17483709 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200664 kb
Host	smart-85f43ff4-3e24-4eaa-b105-f30e6ac2cb8d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146573947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk mgr_alert_test.1146573947
Directory	/workspace/24.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1908605533
Short name	T584
Test name
Test status
Simulation time	24558661 ps
CPU time	0.83 seconds
Started	Jul 12 05:50:30 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200608 kb
Host	smart-478ed019-8fed-4a2b-a4b4-dee2248cf143
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908605533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.1908605533
Directory	/workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_status.2041822046
Short name	T147
Test name
Test status
Simulation time	26030992 ps
CPU time	0.72 seconds
Started	Jul 12 05:50:31 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	199780 kb
Host	smart-6d063a40-c02b-4eaf-9a3a-0dec4e86cac0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041822046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2041822046
Directory	/workspace/24.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/24.clkmgr_div_intersig_mubi.805871063
Short name	T698
Test name
Test status
Simulation time	27008873 ps
CPU time	0.83 seconds
Started	Jul 12 05:50:37 PM PDT 24
Finished	Jul 12 05:50:39 PM PDT 24
Peak memory	200536 kb
Host	smart-9961e02b-235b-4c25-ba55-41d77fa84684
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805871063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.clkmgr_div_intersig_mubi.805871063
Directory	/workspace/24.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_extclk.3862778421
Short name	T764
Test name
Test status
Simulation time	82540891 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:39 PM PDT 24
Finished	Jul 12 05:50:41 PM PDT 24
Peak memory	200516 kb
Host	smart-b5a67d37-7126-4c06-887e-4355c3617367
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862778421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3862778421
Directory	/workspace/24.clkmgr_extclk/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency.2862421339
Short name	T331
Test name
Test status
Simulation time	1521417428 ps
CPU time	11.84 seconds
Started	Jul 12 05:50:40 PM PDT 24
Finished	Jul 12 05:50:53 PM PDT 24
Peak memory	200640 kb
Host	smart-2db34a7f-a42d-44ca-8d90-d04cc7e8f618
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862421339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.2862421339
Directory	/workspace/24.clkmgr_frequency/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency_timeout.438236635
Short name	T544
Test name
Test status
Simulation time	862554694 ps
CPU time	4.87 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:41 PM PDT 24
Peak memory	200704 kb
Host	smart-50296ece-6f9d-416b-8d87-70b954a3fd6c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438236635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_ti meout.438236635
Directory	/workspace/24.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2246782534
Short name	T781
Test name
Test status
Simulation time	30901805 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:31 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200520 kb
Host	smart-bbb33902-5e74-431d-a04e-01f43e1bfc06
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246782534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.2246782534
Directory	/workspace/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2410982467
Short name	T811
Test name
Test status
Simulation time	32152543 ps
CPU time	0.89 seconds
Started	Jul 12 05:50:31 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200556 kb
Host	smart-30caeb27-ce07-4c40-ab09-1e7cede6a864
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410982467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2410982467
Directory	/workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.1806247509
Short name	T644
Test name
Test status
Simulation time	19938500 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:29 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200528 kb
Host	smart-16e2c805-eed5-4cd9-8a6e-10dd2e8d5992
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806247509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_ctrl_intersig_mubi.1806247509
Directory	/workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_peri.3102595585
Short name	T229
Test name
Test status
Simulation time	22750754 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:41 PM PDT 24
Finished	Jul 12 05:50:42 PM PDT 24
Peak memory	200448 kb
Host	smart-110c5c8b-badc-462d-97c5-fd945cad35b3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102595585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3102595585
Directory	/workspace/24.clkmgr_peri/latest

Test location	/workspace/coverage/default/24.clkmgr_smoke.1910026615
Short name	T523
Test name
Test status
Simulation time	126976233 ps
CPU time	1.1 seconds
Started	Jul 12 05:50:33 PM PDT 24
Finished	Jul 12 05:50:37 PM PDT 24
Peak memory	200516 kb
Host	smart-061624d7-e104-410a-a0db-acf82b10284c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910026615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.1910026615
Directory	/workspace/24.clkmgr_smoke/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all.1211554043
Short name	T295
Test name
Test status
Simulation time	3823071107 ps
CPU time	20.61 seconds
Started	Jul 12 05:50:35 PM PDT 24
Finished	Jul 12 05:50:58 PM PDT 24
Peak memory	200840 kb
Host	smart-771f67a7-6ee8-4935-b43b-16f589b58a25
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211554043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1211554043
Directory	/workspace/24.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.3950202498
Short name	T488
Test name
Test status
Simulation time	42100963568 ps
CPU time	565.95 seconds
Started	Jul 12 05:50:26 PM PDT 24
Finished	Jul 12 05:59:57 PM PDT 24
Peak memory	217388 kb
Host	smart-a71011fe-096a-4611-9cc9-fb3466a41b2f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3950202498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.3950202498
Directory	/workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.clkmgr_trans.4183308094
Short name	T217
Test name
Test status
Simulation time	43096558 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:35 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200564 kb
Host	smart-bcee84fc-5b64-44c8-9cc7-4fd202807a6b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183308094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.4183308094
Directory	/workspace/24.clkmgr_trans/latest

Test location	/workspace/coverage/default/25.clkmgr_alert_test.3091830221
Short name	T363
Test name
Test status
Simulation time	31161772 ps
CPU time	0.89 seconds
Started	Jul 12 05:50:33 PM PDT 24
Finished	Jul 12 05:50:37 PM PDT 24
Peak memory	200920 kb
Host	smart-7d4fc90a-6de2-4299-8e4a-ed20160d5444
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091830221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk mgr_alert_test.3091830221
Directory	/workspace/25.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.3030933636
Short name	T471
Test name
Test status
Simulation time	123585383 ps
CPU time	1.1 seconds
Started	Jul 12 05:50:39 PM PDT 24
Finished	Jul 12 05:50:41 PM PDT 24
Peak memory	200568 kb
Host	smart-22275911-f666-4074-b4d5-cde8ae448b5e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030933636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.3030933636
Directory	/workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_status.2556183337
Short name	T808
Test name
Test status
Simulation time	50538710 ps
CPU time	0.84 seconds
Started	Jul 12 05:50:37 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	199756 kb
Host	smart-7703da01-2834-4ff9-9c23-ad97803e4fec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556183337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.2556183337
Directory	/workspace/25.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/25.clkmgr_div_intersig_mubi.2788275636
Short name	T629
Test name
Test status
Simulation time	23201716 ps
CPU time	0.9 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	200564 kb
Host	smart-dbc0af29-1e26-427c-a0a2-39df2a712d6b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788275636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.2788275636
Directory	/workspace/25.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_extclk.1872016902
Short name	T453
Test name
Test status
Simulation time	44288601 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:35 PM PDT 24
Finished	Jul 12 05:50:38 PM PDT 24
Peak memory	200568 kb
Host	smart-31f4366e-504b-4f87-adb7-a5e31a552284
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872016902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.1872016902
Directory	/workspace/25.clkmgr_extclk/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency.481091988
Short name	T312
Test name
Test status
Simulation time	1640910584 ps
CPU time	12.22 seconds
Started	Jul 12 05:50:40 PM PDT 24
Finished	Jul 12 05:50:53 PM PDT 24
Peak memory	200644 kb
Host	smart-476b6bd8-aebb-4a91-923e-c58721671055
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481091988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.481091988
Directory	/workspace/25.clkmgr_frequency/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency_timeout.810479960
Short name	T684
Test name
Test status
Simulation time	2186095276 ps
CPU time	11.31 seconds
Started	Jul 12 05:50:24 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	200888 kb
Host	smart-cc631202-e404-45cc-99e3-61ca77902767
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810479960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_ti meout.810479960
Directory	/workspace/25.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/25.clkmgr_idle_intersig_mubi.1817603688
Short name	T526
Test name
Test status
Simulation time	18426608 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:32 PM PDT 24
Finished	Jul 12 05:50:36 PM PDT 24
Peak memory	200684 kb
Host	smart-491edd72-9389-406a-b569-2e51ced51d64
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817603688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1817603688
Directory	/workspace/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.4294233472
Short name	T717
Test name
Test status
Simulation time	22918135 ps
CPU time	0.84 seconds
Started	Jul 12 05:50:40 PM PDT 24
Finished	Jul 12 05:50:41 PM PDT 24
Peak memory	200568 kb
Host	smart-de2d6269-d62a-4f55-a73a-c55ac9b440e0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294233472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_clk_byp_req_intersig_mubi.4294233472
Directory	/workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.1838790231
Short name	T796
Test name
Test status
Simulation time	46471471 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:37 PM PDT 24
Peak memory	200520 kb
Host	smart-5cc93fe0-cf05-4426-9dcb-27e7e58ae80b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838790231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_ctrl_intersig_mubi.1838790231
Directory	/workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_peri.3764276937
Short name	T289
Test name
Test status
Simulation time	14029802 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:50:37 PM PDT 24
Peak memory	200392 kb
Host	smart-d32041a5-84f1-49dc-b71e-56f3370eb88f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764276937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3764276937
Directory	/workspace/25.clkmgr_peri/latest

Test location	/workspace/coverage/default/25.clkmgr_regwen.3739315103
Short name	T626
Test name
Test status
Simulation time	286675647 ps
CPU time	2.12 seconds
Started	Jul 12 05:50:48 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200512 kb
Host	smart-68124c4b-63fe-4afa-9330-e3b46eaa7178
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739315103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3739315103
Directory	/workspace/25.clkmgr_regwen/latest

Test location	/workspace/coverage/default/25.clkmgr_smoke.2016418467
Short name	T505
Test name
Test status
Simulation time	18198952 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:29 PM PDT 24
Finished	Jul 12 05:50:34 PM PDT 24
Peak memory	200528 kb
Host	smart-f82092e4-9256-4a9d-8279-cfcf5f491394
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016418467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2016418467
Directory	/workspace/25.clkmgr_smoke/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all.3656636182
Short name	T394
Test name
Test status
Simulation time	3235521854 ps
CPU time	24.9 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:51:02 PM PDT 24
Peak memory	200812 kb
Host	smart-140a8b55-67d6-423e-b791-068c04b6a102
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656636182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.3656636182
Directory	/workspace/25.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.3295161976
Short name	T13
Test name
Test status
Simulation time	43459766824 ps
CPU time	370.21 seconds
Started	Jul 12 05:50:34 PM PDT 24
Finished	Jul 12 05:56:47 PM PDT 24
Peak memory	209156 kb
Host	smart-f9fed133-8602-4d83-829b-2b6d3ad16800
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3295161976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3295161976
Directory	/workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.clkmgr_trans.1729677911
Short name	T326
Test name
Test status
Simulation time	23169262 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:38 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	200560 kb
Host	smart-6aeeab4e-c716-44d7-905a-7dafbf6af1e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729677911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1729677911
Directory	/workspace/25.clkmgr_trans/latest

Test location	/workspace/coverage/default/26.clkmgr_alert_test.2168952267
Short name	T269
Test name
Test status
Simulation time	42747764 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:38 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	200704 kb
Host	smart-8a2f4b91-3594-4ea9-aade-40a5b1f05d09
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168952267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.2168952267
Directory	/workspace/26.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.4021897568
Short name	T769
Test name
Test status
Simulation time	44031006 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:48 PM PDT 24
Peak memory	200760 kb
Host	smart-92442635-f6b9-4831-a1df-cea3b914c5ba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021897568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.4021897568
Directory	/workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_status.2313143644
Short name	T148
Test name
Test status
Simulation time	15665302 ps
CPU time	0.72 seconds
Started	Jul 12 05:50:43 PM PDT 24
Finished	Jul 12 05:50:45 PM PDT 24
Peak memory	199980 kb
Host	smart-e8bd6276-e9ea-4e34-9ad3-aecdde70ac26
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313143644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2313143644
Directory	/workspace/26.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/26.clkmgr_div_intersig_mubi.2185362878
Short name	T223
Test name
Test status
Simulation time	53609927 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:39 PM PDT 24
Finished	Jul 12 05:50:41 PM PDT 24
Peak memory	200572 kb
Host	smart-1df543cd-a711-4d49-8fea-e0995ccfcf31
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185362878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.2185362878
Directory	/workspace/26.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_extclk.3294183795
Short name	T516
Test name
Test status
Simulation time	15946131 ps
CPU time	0.73 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:48 PM PDT 24
Peak memory	200556 kb
Host	smart-cd6f834e-7def-4076-806c-be4e45b9ed9c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294183795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3294183795
Directory	/workspace/26.clkmgr_extclk/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency.4196201697
Short name	T751
Test name
Test status
Simulation time	802692167 ps
CPU time	6.43 seconds
Started	Jul 12 05:50:36 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200628 kb
Host	smart-01730db3-8904-49be-b86a-37c92d2780b3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196201697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.4196201697
Directory	/workspace/26.clkmgr_frequency/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency_timeout.2233815086
Short name	T390
Test name
Test status
Simulation time	1821164099 ps
CPU time	13.56 seconds
Started	Jul 12 05:50:44 PM PDT 24
Finished	Jul 12 05:50:59 PM PDT 24
Peak memory	200708 kb
Host	smart-5c36ab87-e658-43de-b54c-1c3b682de814
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233815086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t imeout.2233815086
Directory	/workspace/26.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2666945445
Short name	T612
Test name
Test status
Simulation time	167628978 ps
CPU time	1.18 seconds
Started	Jul 12 05:50:37 PM PDT 24
Finished	Jul 12 05:50:40 PM PDT 24
Peak memory	200572 kb
Host	smart-d0df0ac6-5fe1-4189-bb0f-5f0169b94763
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666945445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.2666945445
Directory	/workspace/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.1704803737
Short name	T786
Test name
Test status
Simulation time	21111696 ps
CPU time	0.84 seconds
Started	Jul 12 05:51:06 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200416 kb
Host	smart-ff4c7df9-deed-4710-8884-3cb23d1c34bc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704803737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_clk_byp_req_intersig_mubi.1704803737
Directory	/workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.287701846
Short name	T736
Test name
Test status
Simulation time	44352246 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:56 PM PDT 24
Finished	Jul 12 05:50:58 PM PDT 24
Peak memory	200476 kb
Host	smart-4479e688-2458-4635-b836-b9028be319cc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287701846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.clkmgr_lc_ctrl_intersig_mubi.287701846
Directory	/workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_peri.343565143
Short name	T138
Test name
Test status
Simulation time	27369362 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200408 kb
Host	smart-7033f14a-a69e-4d1f-85a4-680df59adbcf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343565143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.343565143
Directory	/workspace/26.clkmgr_peri/latest

Test location	/workspace/coverage/default/26.clkmgr_regwen.3435043890
Short name	T643
Test name
Test status
Simulation time	701364291 ps
CPU time	3.03 seconds
Started	Jul 12 05:50:58 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200652 kb
Host	smart-2628f776-529d-49bc-8b9b-6327aa03d3d0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435043890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3435043890
Directory	/workspace/26.clkmgr_regwen/latest

Test location	/workspace/coverage/default/26.clkmgr_smoke.442609729
Short name	T466
Test name
Test status
Simulation time	92183004 ps
CPU time	1.02 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:45 PM PDT 24
Peak memory	200504 kb
Host	smart-209c1c13-9967-494c-85dd-e6b78fb0c310
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442609729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.442609729
Directory	/workspace/26.clkmgr_smoke/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all.2293061034
Short name	T202
Test name
Test status
Simulation time	8645517164 ps
CPU time	30.67 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200860 kb
Host	smart-d1ad65f2-09e6-4d18-9da5-00e7371e37e1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293061034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.2293061034
Directory	/workspace/26.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/26.clkmgr_trans.1117565277
Short name	T143
Test name
Test status
Simulation time	59506421 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:50 PM PDT 24
Peak memory	200572 kb
Host	smart-c7c56429-bbf4-4a34-bc82-f88dac1a715b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117565277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1117565277
Directory	/workspace/26.clkmgr_trans/latest

Test location	/workspace/coverage/default/27.clkmgr_alert_test.60041666
Short name	T482
Test name
Test status
Simulation time	17643404 ps
CPU time	0.77 seconds
Started	Jul 12 06:13:32 PM PDT 24
Finished	Jul 12 06:14:55 PM PDT 24
Peak memory	200704 kb
Host	smart-239dc3ce-23bb-41b0-be54-43e6b720cd99
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60041666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmg r_alert_test.60041666
Directory	/workspace/27.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.881260233
Short name	T696
Test name
Test status
Simulation time	12938355 ps
CPU time	0.72 seconds
Started	Jul 12 05:50:41 PM PDT 24
Finished	Jul 12 05:50:43 PM PDT 24
Peak memory	200588 kb
Host	smart-a5a9cf7f-0e79-4d8c-9416-09025befb728
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881260233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.881260233
Directory	/workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_status.2450095906
Short name	T839
Test name
Test status
Simulation time	23658666 ps
CPU time	0.73 seconds
Started	Jul 12 05:50:43 PM PDT 24
Finished	Jul 12 05:50:45 PM PDT 24
Peak memory	199764 kb
Host	smart-3eb8c394-fdb5-4520-bda0-5110725c7479
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450095906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.2450095906
Directory	/workspace/27.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/27.clkmgr_div_intersig_mubi.1618293625
Short name	T545
Test name
Test status
Simulation time	25637900 ps
CPU time	0.91 seconds
Started	Jul 12 05:50:48 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200588 kb
Host	smart-4db981f1-8301-444d-949b-739458620196
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618293625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.1618293625
Directory	/workspace/27.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_extclk.521338288
Short name	T407
Test name
Test status
Simulation time	16581105 ps
CPU time	0.75 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	200552 kb
Host	smart-11257071-3a1f-4198-a0c8-f6cae083d01b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521338288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.521338288
Directory	/workspace/27.clkmgr_extclk/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency.3114422222
Short name	T829
Test name
Test status
Simulation time	1079236371 ps
CPU time	5.08 seconds
Started	Jul 12 05:50:52 PM PDT 24
Finished	Jul 12 05:50:58 PM PDT 24
Peak memory	200584 kb
Host	smart-7aae5350-26dc-48d7-86bf-2064cafe647d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114422222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.3114422222
Directory	/workspace/27.clkmgr_frequency/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency_timeout.2105195602
Short name	T749
Test name
Test status
Simulation time	1983839940 ps
CPU time	8.16 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:52 PM PDT 24
Peak memory	200688 kb
Host	smart-c4af31aa-44a5-48ea-bcf7-3234f5af3d2d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105195602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t imeout.2105195602
Directory	/workspace/27.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/27.clkmgr_idle_intersig_mubi.1981682561
Short name	T620
Test name
Test status
Simulation time	16915812 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:48 PM PDT 24
Peak memory	200556 kb
Host	smart-2841d110-6700-442b-ae4a-ad59ab6a3b0b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981682561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.1981682561
Directory	/workspace/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.242808686
Short name	T191
Test name
Test status
Simulation time	22001615 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200576 kb
Host	smart-21ee1aef-e7e1-467f-a589-a476776c3b00
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242808686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.clkmgr_lc_clk_byp_req_intersig_mubi.242808686
Directory	/workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.958747454
Short name	T225
Test name
Test status
Simulation time	18189738 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:47 PM PDT 24
Peak memory	200576 kb
Host	smart-985a0e17-3365-4acf-94bf-60f1ccdacabb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958747454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.clkmgr_lc_ctrl_intersig_mubi.958747454
Directory	/workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_peri.1073608389
Short name	T280
Test name
Test status
Simulation time	43741381 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:48 PM PDT 24
Peak memory	200448 kb
Host	smart-fda551d8-476a-484b-90e4-47a75a549a2f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073608389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1073608389
Directory	/workspace/27.clkmgr_peri/latest

Test location	/workspace/coverage/default/27.clkmgr_regwen.4030249523
Short name	T692
Test name
Test status
Simulation time	113289402 ps
CPU time	1.05 seconds
Started	Jul 12 05:50:50 PM PDT 24
Finished	Jul 12 05:50:53 PM PDT 24
Peak memory	200516 kb
Host	smart-4b9c1ee6-d917-4fbb-a037-858d76d6f0ee
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030249523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.4030249523
Directory	/workspace/27.clkmgr_regwen/latest

Test location	/workspace/coverage/default/27.clkmgr_smoke.902078376
Short name	T532
Test name
Test status
Simulation time	34862102 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:43 PM PDT 24
Finished	Jul 12 05:50:45 PM PDT 24
Peak memory	200528 kb
Host	smart-9268c842-b561-47fb-99b7-d865b30d97ad
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902078376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.902078376
Directory	/workspace/27.clkmgr_smoke/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all.2866205095
Short name	T712
Test name
Test status
Simulation time	8201015535 ps
CPU time	33.75 seconds
Started	Jul 12 06:16:12 PM PDT 24
Finished	Jul 12 06:17:09 PM PDT 24
Peak memory	200760 kb
Host	smart-5f2341bb-652d-4250-96c9-5247a472562e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866205095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.2866205095
Directory	/workspace/27.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.3055035515
Short name	T137
Test name
Test status
Simulation time	158164605608 ps
CPU time	881.16 seconds
Started	Jul 12 05:51:03 PM PDT 24
Finished	Jul 12 06:05:46 PM PDT 24
Peak memory	213004 kb
Host	smart-966326c2-e700-4ee0-a738-32d116904fc2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3055035515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.3055035515
Directory	/workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.clkmgr_trans.261328672
Short name	T426
Test name
Test status
Simulation time	54460827 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:44 PM PDT 24
Finished	Jul 12 05:50:46 PM PDT 24
Peak memory	200548 kb
Host	smart-ee7c6336-4d0d-4460-acf6-96c4e913c693
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261328672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.261328672
Directory	/workspace/27.clkmgr_trans/latest

Test location	/workspace/coverage/default/28.clkmgr_alert_test.1653579432
Short name	T31
Test name
Test status
Simulation time	18566537 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:50 PM PDT 24
Peak memory	200708 kb
Host	smart-01115406-f97d-49d0-b988-0e84a6bb4441
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653579432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk mgr_alert_test.1653579432
Directory	/workspace/28.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.133553862
Short name	T311
Test name
Test status
Simulation time	15783417 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200536 kb
Host	smart-44e0b471-a825-492e-b2d9-6fdba63799d2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133553862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.133553862
Directory	/workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_status.346759694
Short name	T795
Test name
Test status
Simulation time	19511878 ps
CPU time	0.73 seconds
Started	Jul 12 05:50:54 PM PDT 24
Finished	Jul 12 05:50:56 PM PDT 24
Peak memory	199892 kb
Host	smart-ab687b80-140f-44ec-af20-02d9b5d21153
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346759694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.346759694
Directory	/workspace/28.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/28.clkmgr_div_intersig_mubi.2942827203
Short name	T817
Test name
Test status
Simulation time	68571829 ps
CPU time	1.01 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200528 kb
Host	smart-4558e80b-058a-4aaf-9146-e0c7c3611671
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942827203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.2942827203
Directory	/workspace/28.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_extclk.1637669994
Short name	T727
Test name
Test status
Simulation time	13911557 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	200592 kb
Host	smart-48f2666a-1517-42a9-809b-a429ac7d4856
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637669994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1637669994
Directory	/workspace/28.clkmgr_extclk/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency.685872571
Short name	T589
Test name
Test status
Simulation time	497210794 ps
CPU time	2.18 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200656 kb
Host	smart-5d0089c8-93ba-45bf-9d40-3e452a5a4c00
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685872571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.685872571
Directory	/workspace/28.clkmgr_frequency/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency_timeout.2954570713
Short name	T197
Test name
Test status
Simulation time	2174845992 ps
CPU time	15.34 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200988 kb
Host	smart-040a83a3-0e43-4bb2-be20-95febe5cdb7c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954570713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t imeout.2954570713
Directory	/workspace/28.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/28.clkmgr_idle_intersig_mubi.277904876
Short name	T601
Test name
Test status
Simulation time	24071566 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:54 PM PDT 24
Finished	Jul 12 05:50:56 PM PDT 24
Peak memory	200604 kb
Host	smart-3a7bcecd-7661-4fcf-92dc-68b514f4cceb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277904876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.clkmgr_idle_intersig_mubi.277904876
Directory	/workspace/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.3225760554
Short name	T284
Test name
Test status
Simulation time	56286281 ps
CPU time	1.01 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:52 PM PDT 24
Peak memory	200568 kb
Host	smart-8612e8d9-0be9-404e-9fd8-8b2708ef46ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225760554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_clk_byp_req_intersig_mubi.3225760554
Directory	/workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1956774572
Short name	T499
Test name
Test status
Simulation time	123024912 ps
CPU time	1.05 seconds
Started	Jul 12 05:50:48 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200488 kb
Host	smart-570b39fc-6c21-4dca-b933-8cbd7e6ea2ba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956774572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_ctrl_intersig_mubi.1956774572
Directory	/workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_peri.2756693885
Short name	T432
Test name
Test status
Simulation time	37854538 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:50 PM PDT 24
Finished	Jul 12 05:50:52 PM PDT 24
Peak memory	200468 kb
Host	smart-887fc77d-8544-4349-ba59-563c23e9d01d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756693885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2756693885
Directory	/workspace/28.clkmgr_peri/latest

Test location	/workspace/coverage/default/28.clkmgr_regwen.2163253808
Short name	T483
Test name
Test status
Simulation time	263036419 ps
CPU time	1.6 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	200496 kb
Host	smart-3b2a1de0-4924-4fa2-931d-6fce0a515f7c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163253808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2163253808
Directory	/workspace/28.clkmgr_regwen/latest

Test location	/workspace/coverage/default/28.clkmgr_smoke.3371060272
Short name	T99
Test name
Test status
Simulation time	20495450 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:48 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200508 kb
Host	smart-b994f0eb-fc32-44f2-94f7-1c1c65b7a207
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371060272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3371060272
Directory	/workspace/28.clkmgr_smoke/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all.899388939
Short name	T531
Test name
Test status
Simulation time	3202436476 ps
CPU time	24 seconds
Started	Jul 12 05:50:51 PM PDT 24
Finished	Jul 12 05:51:17 PM PDT 24
Peak memory	200916 kb
Host	smart-94ad11ac-5b70-4e56-8920-45e0dceb8b6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899388939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.899388939
Directory	/workspace/28.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.3284207139
Short name	T61
Test name
Test status
Simulation time	108487807718 ps
CPU time	790.45 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 06:04:01 PM PDT 24
Peak memory	217388 kb
Host	smart-c22f900b-c682-4087-9496-b648d083fda6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3284207139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3284207139
Directory	/workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.clkmgr_trans.2665588267
Short name	T420
Test name
Test status
Simulation time	22614780 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200576 kb
Host	smart-c4d19c2e-b734-41ab-972c-d9bc912aa57f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665588267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2665588267
Directory	/workspace/28.clkmgr_trans/latest

Test location	/workspace/coverage/default/29.clkmgr_alert_test.3482262360
Short name	T315
Test name
Test status
Simulation time	74083513 ps
CPU time	0.99 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	200656 kb
Host	smart-bed97aa3-98c7-432b-80d6-0f1cb1c024f5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482262360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk mgr_alert_test.3482262360
Directory	/workspace/29.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3452632433
Short name	T602
Test name
Test status
Simulation time	43271735 ps
CPU time	0.81 seconds
Started	Jul 12 05:50:43 PM PDT 24
Finished	Jul 12 05:50:45 PM PDT 24
Peak memory	200576 kb
Host	smart-72b5b1cf-3682-40b4-bab6-22cad81c507e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452632433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.3452632433
Directory	/workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_status.3110475822
Short name	T149
Test name
Test status
Simulation time	33566912 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:48 PM PDT 24
Peak memory	199720 kb
Host	smart-e449e318-13e5-42d7-81d4-665e8d51be5a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110475822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.3110475822
Directory	/workspace/29.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/29.clkmgr_div_intersig_mubi.1766923366
Short name	T355
Test name
Test status
Simulation time	38553660 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:51 PM PDT 24
Finished	Jul 12 05:50:54 PM PDT 24
Peak memory	200536 kb
Host	smart-305f0610-c999-46f2-86e0-3fd0755afb4a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766923366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.1766923366
Directory	/workspace/29.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_extclk.2084295610
Short name	T623
Test name
Test status
Simulation time	30304982 ps
CPU time	0.99 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:52 PM PDT 24
Peak memory	200556 kb
Host	smart-2855caae-d17a-417e-82af-b24092302baf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084295610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.2084295610
Directory	/workspace/29.clkmgr_extclk/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency.1826272844
Short name	T353
Test name
Test status
Simulation time	1490844948 ps
CPU time	6.56 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200656 kb
Host	smart-95b67d5b-129c-4245-bbc2-61e2ebe6f94f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826272844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.1826272844
Directory	/workspace/29.clkmgr_frequency/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency_timeout.2353748207
Short name	T645
Test name
Test status
Simulation time	261974460 ps
CPU time	2.03 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	200672 kb
Host	smart-dfeeacd8-d936-45e9-b835-92943c4074f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353748207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t imeout.2353748207
Directory	/workspace/29.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/29.clkmgr_idle_intersig_mubi.2113195077
Short name	T253
Test name
Test status
Simulation time	57558783 ps
CPU time	0.88 seconds
Started	Jul 12 05:50:59 PM PDT 24
Finished	Jul 12 05:51:01 PM PDT 24
Peak memory	200568 kb
Host	smart-76a3a8c5-8a6b-40a3-afb2-752097893d44
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113195077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.2113195077
Directory	/workspace/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1944796627
Short name	T635
Test name
Test status
Simulation time	19475988 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200592 kb
Host	smart-42cb9ecf-a835-4e57-80ad-339f2b2cd100
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944796627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1944796627
Directory	/workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.243002618
Short name	T216
Test name
Test status
Simulation time	48491787 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 05:51:03 PM PDT 24
Peak memory	200672 kb
Host	smart-9c6a2657-6600-42cd-8a96-dc64776dcebe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243002618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.clkmgr_lc_ctrl_intersig_mubi.243002618
Directory	/workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_peri.188696109
Short name	T802
Test name
Test status
Simulation time	24190412 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200472 kb
Host	smart-85e1c6e2-8b30-4b49-82ff-57e116ff1b6e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188696109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.188696109
Directory	/workspace/29.clkmgr_peri/latest

Test location	/workspace/coverage/default/29.clkmgr_regwen.3618150125
Short name	T536
Test name
Test status
Simulation time	1279728633 ps
CPU time	6.7 seconds
Started	Jul 12 05:50:51 PM PDT 24
Finished	Jul 12 05:50:59 PM PDT 24
Peak memory	200656 kb
Host	smart-6dc1aea2-6515-44e7-9c6c-7a33a9dbc816
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618150125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3618150125
Directory	/workspace/29.clkmgr_regwen/latest

Test location	/workspace/coverage/default/29.clkmgr_smoke.1815827635
Short name	T448
Test name
Test status
Simulation time	83066624 ps
CPU time	0.98 seconds
Started	Jul 12 05:50:42 PM PDT 24
Finished	Jul 12 05:50:44 PM PDT 24
Peak memory	200532 kb
Host	smart-c726c5fc-16a7-4898-83a3-fe329ac9202a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815827635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1815827635
Directory	/workspace/29.clkmgr_smoke/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all.1757025578
Short name	T398
Test name
Test status
Simulation time	5435053483 ps
CPU time	42.29 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:51:33 PM PDT 24
Peak memory	200816 kb
Host	smart-20c930b0-9d14-47d3-af25-34be73370891
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757025578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.1757025578
Directory	/workspace/29.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.3319097352
Short name	T755
Test name
Test status
Simulation time	202689558111 ps
CPU time	1124.02 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 06:09:41 PM PDT 24
Peak memory	213920 kb
Host	smart-3425241d-e8b3-4f05-a70d-01d23defb676
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3319097352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.3319097352
Directory	/workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_trans.3235529106
Short name	T512
Test name
Test status
Simulation time	29453582 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:58 PM PDT 24
Finished	Jul 12 05:51:00 PM PDT 24
Peak memory	200512 kb
Host	smart-cbd5a4fd-f753-4c97-8d39-e462cf310fb1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235529106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3235529106
Directory	/workspace/29.clkmgr_trans/latest

Test location	/workspace/coverage/default/3.clkmgr_alert_test.769676175
Short name	T783
Test name
Test status
Simulation time	22376265 ps
CPU time	0.8 seconds
Started	Jul 12 05:49:47 PM PDT 24
Finished	Jul 12 05:49:48 PM PDT 24
Peak memory	200684 kb
Host	smart-a10d585b-cc9b-4c19-b0f2-c2ac205d5a92
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769676175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg r_alert_test.769676175
Directory	/workspace/3.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3320312186
Short name	T220
Test name
Test status
Simulation time	69334664 ps
CPU time	0.96 seconds
Started	Jul 12 05:49:51 PM PDT 24
Finished	Jul 12 05:49:53 PM PDT 24
Peak memory	200584 kb
Host	smart-6b8f9b2f-f0e8-4506-af2d-3dde81d44f35
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320312186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.3320312186
Directory	/workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_status.2757528512
Short name	T689
Test name
Test status
Simulation time	26739512 ps
CPU time	0.73 seconds
Started	Jul 12 05:49:50 PM PDT 24
Finished	Jul 12 05:49:51 PM PDT 24
Peak memory	199764 kb
Host	smart-50982331-9c9a-4622-b435-59e7720e621f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757528512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2757528512
Directory	/workspace/3.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/3.clkmgr_div_intersig_mubi.1680527568
Short name	T556
Test name
Test status
Simulation time	28290004 ps
CPU time	0.93 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:41 PM PDT 24
Peak memory	200552 kb
Host	smart-ed160e14-135f-4393-8474-3e810166dfe3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680527568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.1680527568
Directory	/workspace/3.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_extclk.20275686
Short name	T509
Test name
Test status
Simulation time	57399224 ps
CPU time	0.9 seconds
Started	Jul 12 05:49:36 PM PDT 24
Finished	Jul 12 05:49:44 PM PDT 24
Peak memory	200564 kb
Host	smart-74c09741-fbf3-42e6-9d61-fdd973a47e58
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.20275686
Directory	/workspace/3.clkmgr_extclk/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency.3560544696
Short name	T107
Test name
Test status
Simulation time	2486188972 ps
CPU time	10.45 seconds
Started	Jul 12 05:49:37 PM PDT 24
Finished	Jul 12 05:49:50 PM PDT 24
Peak memory	200816 kb
Host	smart-c0c29d2a-af3b-4adc-b3bc-579e4e728ce6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560544696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.3560544696
Directory	/workspace/3.clkmgr_frequency/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency_timeout.226079908
Short name	T188
Test name
Test status
Simulation time	2082416466 ps
CPU time	8.32 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:48 PM PDT 24
Peak memory	200784 kb
Host	smart-c9246444-c374-44a5-bd24-abac243eb45e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226079908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_tim eout.226079908
Directory	/workspace/3.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/3.clkmgr_idle_intersig_mubi.1131688265
Short name	T361
Test name
Test status
Simulation time	44400336 ps
CPU time	0.82 seconds
Started	Jul 12 05:49:47 PM PDT 24
Finished	Jul 12 05:49:49 PM PDT 24
Peak memory	200564 kb
Host	smart-ecb3867b-ec81-4338-bd25-5d689c4c2558
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131688265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1131688265
Directory	/workspace/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.482975116
Short name	T440
Test name
Test status
Simulation time	43632834 ps
CPU time	0.84 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:42 PM PDT 24
Peak memory	200568 kb
Host	smart-0aac023d-6b25-43af-8c8f-13a1546a7b13
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482975116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.clkmgr_lc_clk_byp_req_intersig_mubi.482975116
Directory	/workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1899442728
Short name	T621
Test name
Test status
Simulation time	67416792 ps
CPU time	0.99 seconds
Started	Jul 12 05:49:52 PM PDT 24
Finished	Jul 12 05:49:54 PM PDT 24
Peak memory	200568 kb
Host	smart-e667ac2e-771e-45a8-9634-515c4009e5c5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899442728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_ctrl_intersig_mubi.1899442728
Directory	/workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_peri.3173075721
Short name	T487
Test name
Test status
Simulation time	15085317 ps
CPU time	0.82 seconds
Started	Jul 12 05:49:42 PM PDT 24
Finished	Jul 12 05:49:45 PM PDT 24
Peak memory	200440 kb
Host	smart-9c374213-b717-4dcf-b5d4-6a5c541184d1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173075721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3173075721
Directory	/workspace/3.clkmgr_peri/latest

Test location	/workspace/coverage/default/3.clkmgr_regwen.914847452
Short name	T580
Test name
Test status
Simulation time	770110216 ps
CPU time	3.42 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:50 PM PDT 24
Peak memory	200688 kb
Host	smart-fbff604e-2444-4284-a7ed-193645750a34
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914847452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.914847452
Directory	/workspace/3.clkmgr_regwen/latest

Test location	/workspace/coverage/default/3.clkmgr_sec_cm.313333223
Short name	T37
Test name
Test status
Simulation time	302245290 ps
CPU time	3.36 seconds
Started	Jul 12 05:49:52 PM PDT 24
Finished	Jul 12 05:49:56 PM PDT 24
Peak memory	217492 kb
Host	smart-96923a29-4788-4fe2-9da4-e11ac1b79ef5
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313333223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr _sec_cm.313333223
Directory	/workspace/3.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.clkmgr_smoke.149318705
Short name	T763
Test name
Test status
Simulation time	46190518 ps
CPU time	1.04 seconds
Started	Jul 12 05:49:37 PM PDT 24
Finished	Jul 12 05:49:39 PM PDT 24
Peak memory	200528 kb
Host	smart-8986b4ba-f084-4ffd-8136-b0f374558031
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149318705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.149318705
Directory	/workspace/3.clkmgr_smoke/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all.2470325152
Short name	T190
Test name
Test status
Simulation time	5234859982 ps
CPU time	18.04 seconds
Started	Jul 12 05:49:47 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200880 kb
Host	smart-437ae402-bf69-49c0-a2ee-6f7a3b221060
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470325152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.2470325152
Directory	/workspace/3.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.478678867
Short name	T787
Test name
Test status
Simulation time	30340767560 ps
CPU time	481.58 seconds
Started	Jul 12 05:49:40 PM PDT 24
Finished	Jul 12 05:57:43 PM PDT 24
Peak memory	209204 kb
Host	smart-b755458d-99d1-4171-bf35-af4c4d2f86c0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=478678867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.478678867
Directory	/workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.clkmgr_trans.2668904762
Short name	T610
Test name
Test status
Simulation time	25799686 ps
CPU time	0.89 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:41 PM PDT 24
Peak memory	200544 kb
Host	smart-6ac38d2f-b47b-438c-a9cb-e048f1e668a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668904762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2668904762
Directory	/workspace/3.clkmgr_trans/latest

Test location	/workspace/coverage/default/30.clkmgr_alert_test.2116121811
Short name	T806
Test name
Test status
Simulation time	17519591 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200672 kb
Host	smart-c04d9d07-1782-4a63-9c99-63e2f2a9a43a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116121811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk mgr_alert_test.2116121811
Directory	/workspace/30.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1550165896
Short name	T741
Test name
Test status
Simulation time	25865057 ps
CPU time	0.94 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200572 kb
Host	smart-45f01006-2b07-4546-aeda-25918c4f2dc0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550165896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1550165896
Directory	/workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_status.2814258777
Short name	T604
Test name
Test status
Simulation time	31636859 ps
CPU time	0.74 seconds
Started	Jul 12 05:50:46 PM PDT 24
Finished	Jul 12 05:50:48 PM PDT 24
Peak memory	200468 kb
Host	smart-26a5384e-06c0-4f20-98b8-79fe4da902bf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814258777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2814258777
Directory	/workspace/30.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/30.clkmgr_div_intersig_mubi.1933996871
Short name	T609
Test name
Test status
Simulation time	55167469 ps
CPU time	0.9 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 05:50:57 PM PDT 24
Peak memory	200560 kb
Host	smart-ab07290d-52fb-4bb7-b04b-60a1ed5001f8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933996871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.1933996871
Directory	/workspace/30.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_extclk.1829920561
Short name	T152
Test name
Test status
Simulation time	39102920 ps
CPU time	0.9 seconds
Started	Jul 12 05:50:51 PM PDT 24
Finished	Jul 12 05:50:53 PM PDT 24
Peak memory	200556 kb
Host	smart-4d07a331-de5e-4fcf-b664-b54daa00fce8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829920561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1829920561
Directory	/workspace/30.clkmgr_extclk/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency.2029733810
Short name	T364
Test name
Test status
Simulation time	2224117952 ps
CPU time	8.53 seconds
Started	Jul 12 05:50:45 PM PDT 24
Finished	Jul 12 05:50:54 PM PDT 24
Peak memory	200784 kb
Host	smart-8463058f-7649-44a2-9b6e-916e29077a26
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029733810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2029733810
Directory	/workspace/30.clkmgr_frequency/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency_timeout.1158646330
Short name	T358
Test name
Test status
Simulation time	1098465935 ps
CPU time	8.17 seconds
Started	Jul 12 05:50:48 PM PDT 24
Finished	Jul 12 05:50:58 PM PDT 24
Peak memory	200648 kb
Host	smart-af826556-c870-42da-aaf4-79e355cd1258
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158646330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t imeout.1158646330
Directory	/workspace/30.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2026128245
Short name	T351
Test name
Test status
Simulation time	39263726 ps
CPU time	1.1 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200532 kb
Host	smart-0821a6d6-6918-451f-a21d-01ea2327aac2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026128245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.2026128245
Directory	/workspace/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.166225266
Short name	T340
Test name
Test status
Simulation time	78559254 ps
CPU time	1.02 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 05:50:57 PM PDT 24
Peak memory	200540 kb
Host	smart-cacde20b-901f-4b35-8c7c-b31d2058ece9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166225266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.clkmgr_lc_clk_byp_req_intersig_mubi.166225266
Directory	/workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1113059962
Short name	T132
Test name
Test status
Simulation time	55420437 ps
CPU time	0.89 seconds
Started	Jul 12 05:50:43 PM PDT 24
Finished	Jul 12 05:50:45 PM PDT 24
Peak memory	200572 kb
Host	smart-db1921ce-54e5-46d2-a46a-82dd9bcb0121
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113059962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_ctrl_intersig_mubi.1113059962
Directory	/workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_peri.266043727
Short name	T231
Test name
Test status
Simulation time	59536503 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:50 PM PDT 24
Finished	Jul 12 05:50:53 PM PDT 24
Peak memory	200400 kb
Host	smart-63f320f4-b974-4ff8-8f90-743260a31b27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266043727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.266043727
Directory	/workspace/30.clkmgr_peri/latest

Test location	/workspace/coverage/default/30.clkmgr_regwen.489618108
Short name	T518
Test name
Test status
Simulation time	542934862 ps
CPU time	3.27 seconds
Started	Jul 12 05:50:51 PM PDT 24
Finished	Jul 12 05:50:56 PM PDT 24
Peak memory	200632 kb
Host	smart-afd2dff7-0be9-4cb3-9044-6dcdf624184f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489618108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.489618108
Directory	/workspace/30.clkmgr_regwen/latest

Test location	/workspace/coverage/default/30.clkmgr_smoke.1723763666
Short name	T639
Test name
Test status
Simulation time	40396721 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:51 PM PDT 24
Finished	Jul 12 05:50:54 PM PDT 24
Peak memory	200464 kb
Host	smart-c894e9c9-6f4c-4b79-92fa-6e8fd030c175
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723763666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.1723763666
Directory	/workspace/30.clkmgr_smoke/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all.283832001
Short name	T634
Test name
Test status
Simulation time	5170537129 ps
CPU time	37.85 seconds
Started	Jul 12 05:50:50 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200876 kb
Host	smart-832dbaba-d5e5-4d5a-a87a-9042bb3977a3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283832001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.283832001
Directory	/workspace/30.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.1818342902
Short name	T607
Test name
Test status
Simulation time	42666539288 ps
CPU time	290.28 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:55:44 PM PDT 24
Peak memory	216780 kb
Host	smart-f3593b4f-5dea-4fb8-8975-d9de8ba7ea2a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1818342902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.1818342902
Directory	/workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.clkmgr_trans.800553359
Short name	T819
Test name
Test status
Simulation time	125349237 ps
CPU time	1.25 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:50 PM PDT 24
Peak memory	200548 kb
Host	smart-4ed5d6a4-9f25-4120-ad6a-bd7f452fdbc1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800553359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.800553359
Directory	/workspace/30.clkmgr_trans/latest

Test location	/workspace/coverage/default/31.clkmgr_alert_test.3417046379
Short name	T798
Test name
Test status
Simulation time	18063287 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:51 PM PDT 24
Finished	Jul 12 05:50:54 PM PDT 24
Peak memory	200652 kb
Host	smart-065c9b7c-b883-49d6-92f7-58e2954238ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417046379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk mgr_alert_test.3417046379
Directory	/workspace/31.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1341006356
Short name	T154
Test name
Test status
Simulation time	51525160 ps
CPU time	1.03 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:50:56 PM PDT 24
Peak memory	200624 kb
Host	smart-396739a4-59c7-4ef7-a7d3-ba9b729cbe0f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341006356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.1341006356
Directory	/workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_status.4074808827
Short name	T830
Test name
Test status
Simulation time	40432900 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:44 PM PDT 24
Finished	Jul 12 05:50:46 PM PDT 24
Peak memory	199724 kb
Host	smart-bea0f58e-6e15-4da6-be77-3bb0585febad
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074808827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.4074808827
Directory	/workspace/31.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/31.clkmgr_div_intersig_mubi.678560264
Short name	T547
Test name
Test status
Simulation time	16821976 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 05:50:57 PM PDT 24
Peak memory	200584 kb
Host	smart-f7f5b1e4-7206-462e-b525-4482059ad3cc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678560264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.clkmgr_div_intersig_mubi.678560264
Directory	/workspace/31.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_extclk.3060539038
Short name	T206
Test name
Test status
Simulation time	20349251 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:52 PM PDT 24
Peak memory	200508 kb
Host	smart-b677a93d-5c9f-4a8a-b3cf-bfa0cf54721f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060539038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3060539038
Directory	/workspace/31.clkmgr_extclk/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency.3318215917
Short name	T335
Test name
Test status
Simulation time	2117016198 ps
CPU time	15.48 seconds
Started	Jul 12 05:50:50 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200704 kb
Host	smart-afc7aab2-2f62-4d2c-8c10-d815f88095aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318215917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3318215917
Directory	/workspace/31.clkmgr_frequency/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency_timeout.2051952830
Short name	T434
Test name
Test status
Simulation time	2297313087 ps
CPU time	16.9 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 05:51:13 PM PDT 24
Peak memory	200860 kb
Host	smart-75c524be-c4d6-4172-94d5-76a349e0ee9c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051952830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t imeout.2051952830
Directory	/workspace/31.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3125899524
Short name	T799
Test name
Test status
Simulation time	22673522 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:52 PM PDT 24
Peak memory	200548 kb
Host	smart-ca278d39-0bc6-4283-a6b4-ffe0147fcfdf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125899524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.3125899524
Directory	/workspace/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3034479940
Short name	T429
Test name
Test status
Simulation time	22223983 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:54 PM PDT 24
Finished	Jul 12 05:50:56 PM PDT 24
Peak memory	200796 kb
Host	smart-a511b35e-36ef-4984-b59b-9fe5fe7b712c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034479940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3034479940
Directory	/workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2544782942
Short name	T687
Test name
Test status
Simulation time	17379572 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:59 PM PDT 24
Finished	Jul 12 05:51:02 PM PDT 24
Peak memory	200788 kb
Host	smart-7a94aa08-4104-453b-9335-0ad0ef3f5aa0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544782942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_ctrl_intersig_mubi.2544782942
Directory	/workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_peri.1839738664
Short name	T701
Test name
Test status
Simulation time	18423409 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:49 PM PDT 24
Peak memory	200420 kb
Host	smart-68eb3512-e565-4181-bb03-17f4b30d567f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839738664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1839738664
Directory	/workspace/31.clkmgr_peri/latest

Test location	/workspace/coverage/default/31.clkmgr_regwen.1765771966
Short name	T24
Test name
Test status
Simulation time	580451161 ps
CPU time	3.85 seconds
Started	Jul 12 05:50:58 PM PDT 24
Finished	Jul 12 05:51:03 PM PDT 24
Peak memory	200652 kb
Host	smart-01bf0bda-066f-4652-8416-73c4a43774df
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765771966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.1765771966
Directory	/workspace/31.clkmgr_regwen/latest

Test location	/workspace/coverage/default/31.clkmgr_smoke.3088244099
Short name	T411
Test name
Test status
Simulation time	41608490 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:50:51 PM PDT 24
Peak memory	200492 kb
Host	smart-06bea1f4-88be-4a78-945b-1a7bfdaa8616
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088244099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3088244099
Directory	/workspace/31.clkmgr_smoke/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all.3772027316
Short name	T14
Test name
Test status
Simulation time	6971962046 ps
CPU time	29.06 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:36 PM PDT 24
Peak memory	200872 kb
Host	smart-7bfdc311-baf1-4925-9ff5-24bedbecb32c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772027316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.3772027316
Directory	/workspace/31.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.3923163130
Short name	T428
Test name
Test status
Simulation time	35735243609 ps
CPU time	411.77 seconds
Started	Jul 12 05:50:52 PM PDT 24
Finished	Jul 12 05:57:45 PM PDT 24
Peak memory	209316 kb
Host	smart-3923d0d4-f857-4aee-b00a-986863ba9785
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3923163130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3923163130
Directory	/workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.clkmgr_trans.1108051255
Short name	T682
Test name
Test status
Simulation time	226688690 ps
CPU time	1.48 seconds
Started	Jul 12 05:50:47 PM PDT 24
Finished	Jul 12 05:50:50 PM PDT 24
Peak memory	200552 kb
Host	smart-655f06c4-eca0-44b0-86d6-61e77a017fea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108051255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1108051255
Directory	/workspace/31.clkmgr_trans/latest

Test location	/workspace/coverage/default/32.clkmgr_alert_test.3731536037
Short name	T433
Test name
Test status
Simulation time	27581212 ps
CPU time	0.78 seconds
Started	Jul 12 05:50:59 PM PDT 24
Finished	Jul 12 05:51:01 PM PDT 24
Peak memory	200688 kb
Host	smart-63a7b300-72e4-4f5c-8c46-43e9165b08e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731536037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk mgr_alert_test.3731536037
Directory	/workspace/32.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.591073029
Short name	T97
Test name
Test status
Simulation time	32656412 ps
CPU time	0.84 seconds
Started	Jul 12 05:50:57 PM PDT 24
Finished	Jul 12 05:51:00 PM PDT 24
Peak memory	200608 kb
Host	smart-b6231838-5d42-4926-8565-56a2b967bec6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591073029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.591073029
Directory	/workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_status.3319187521
Short name	T649
Test name
Test status
Simulation time	17458652 ps
CPU time	0.74 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:03 PM PDT 24
Peak memory	199764 kb
Host	smart-194891ca-6f7e-43a0-90c2-599087fa93e6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319187521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3319187521
Directory	/workspace/32.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/32.clkmgr_div_intersig_mubi.1374041575
Short name	T776
Test name
Test status
Simulation time	34762219 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:56 PM PDT 24
Finished	Jul 12 05:50:59 PM PDT 24
Peak memory	200564 kb
Host	smart-c1e1105b-54bf-4d02-b954-dc7b9fa04f45
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374041575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.1374041575
Directory	/workspace/32.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_extclk.2660193606
Short name	T153
Test name
Test status
Simulation time	83342939 ps
CPU time	1.06 seconds
Started	Jul 12 05:50:56 PM PDT 24
Finished	Jul 12 05:50:59 PM PDT 24
Peak memory	200536 kb
Host	smart-ee2b6778-e2da-401b-b319-1a69a058a0bf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660193606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2660193606
Directory	/workspace/32.clkmgr_extclk/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency.2079762095
Short name	T650
Test name
Test status
Simulation time	2135356926 ps
CPU time	9.81 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:14 PM PDT 24
Peak memory	200720 kb
Host	smart-4624444d-4b06-410b-996a-286a1c6b4a0b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079762095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.2079762095
Directory	/workspace/32.clkmgr_frequency/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency_timeout.1080419921
Short name	T822
Test name
Test status
Simulation time	2060417848 ps
CPU time	13.9 seconds
Started	Jul 12 05:50:50 PM PDT 24
Finished	Jul 12 05:51:05 PM PDT 24
Peak memory	200724 kb
Host	smart-43f72488-d64b-44d4-b328-8ba1bf443f71
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080419921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t imeout.1080419921
Directory	/workspace/32.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/32.clkmgr_idle_intersig_mubi.2751299880
Short name	T285
Test name
Test status
Simulation time	25240163 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:58 PM PDT 24
Finished	Jul 12 05:51:00 PM PDT 24
Peak memory	200556 kb
Host	smart-ea32c1f8-dc48-4ed8-a06a-a089bf35e4ba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751299880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.2751299880
Directory	/workspace/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1044629543
Short name	T271
Test name
Test status
Simulation time	53109208 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:56 PM PDT 24
Finished	Jul 12 05:50:58 PM PDT 24
Peak memory	200572 kb
Host	smart-f6c5ab87-92af-4f8d-8568-e7f5ed00fcf0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044629543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.1044629543
Directory	/workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2390550349
Short name	T587
Test name
Test status
Simulation time	26404949 ps
CPU time	0.92 seconds
Started	Jul 12 05:51:08 PM PDT 24
Finished	Jul 12 05:51:10 PM PDT 24
Peak memory	200572 kb
Host	smart-f13a7a39-9d12-42b0-a770-4586e08ebf51
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390550349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_ctrl_intersig_mubi.2390550349
Directory	/workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_peri.1843898703
Short name	T328
Test name
Test status
Simulation time	14707081 ps
CPU time	0.72 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 05:50:57 PM PDT 24
Peak memory	200580 kb
Host	smart-005c70b1-0518-4cfa-9144-343ea17a0b3b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843898703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1843898703
Directory	/workspace/32.clkmgr_peri/latest

Test location	/workspace/coverage/default/32.clkmgr_regwen.1766633140
Short name	T412
Test name
Test status
Simulation time	1237588795 ps
CPU time	4.65 seconds
Started	Jul 12 05:51:03 PM PDT 24
Finished	Jul 12 05:51:10 PM PDT 24
Peak memory	200652 kb
Host	smart-a0149069-72f0-4765-a807-682f4045066a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766633140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1766633140
Directory	/workspace/32.clkmgr_regwen/latest

Test location	/workspace/coverage/default/32.clkmgr_smoke.650418017
Short name	T179
Test name
Test status
Simulation time	20027649 ps
CPU time	0.85 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200508 kb
Host	smart-4b7978fd-35ff-42eb-92f9-f516f969d94f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650418017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.650418017
Directory	/workspace/32.clkmgr_smoke/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all.3859470856
Short name	T832
Test name
Test status
Simulation time	3509824609 ps
CPU time	14.78 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	201116 kb
Host	smart-7c52ea33-e25c-494c-99b3-c3795a1cad49
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859470856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.3859470856
Directory	/workspace/32.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.433546646
Short name	T135
Test name
Test status
Simulation time	8255805968 ps
CPU time	117.95 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:53:05 PM PDT 24
Peak memory	209180 kb
Host	smart-5a81ec7c-cc37-4698-b608-c498b8de5119
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=433546646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.433546646
Directory	/workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.clkmgr_trans.3080484400
Short name	T173
Test name
Test status
Simulation time	258929934 ps
CPU time	1.66 seconds
Started	Jul 12 05:50:59 PM PDT 24
Finished	Jul 12 05:51:02 PM PDT 24
Peak memory	200504 kb
Host	smart-a8938620-dd87-4203-8b17-d7697dff2484
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080484400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3080484400
Directory	/workspace/32.clkmgr_trans/latest

Test location	/workspace/coverage/default/33.clkmgr_alert_test.776364761
Short name	T801
Test name
Test status
Simulation time	146860504 ps
CPU time	1.14 seconds
Started	Jul 12 05:51:03 PM PDT 24
Finished	Jul 12 05:51:06 PM PDT 24
Peak memory	200684 kb
Host	smart-0eb9b17a-e91a-4460-a33e-63779df815ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776364761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkm gr_alert_test.776364761
Directory	/workspace/33.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.130891358
Short name	T80
Test name
Test status
Simulation time	23199836 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	200560 kb
Host	smart-447cc7e6-6e72-4fc9-8888-6d35dd657084
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130891358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.130891358
Directory	/workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_status.1407154027
Short name	T249
Test name
Test status
Simulation time	54355776 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:58 PM PDT 24
Finished	Jul 12 05:51:01 PM PDT 24
Peak memory	199752 kb
Host	smart-c924da22-5dc2-4925-a6b3-0cfe2a21354c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407154027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1407154027
Directory	/workspace/33.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/33.clkmgr_div_intersig_mubi.2265143014
Short name	T40
Test name
Test status
Simulation time	56564603 ps
CPU time	0.95 seconds
Started	Jul 12 05:51:01 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200568 kb
Host	smart-f39604fc-a9db-45ee-8a9c-9273a7890c3a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265143014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.2265143014
Directory	/workspace/33.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_extclk.2101071062
Short name	T286
Test name
Test status
Simulation time	62260715 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:57 PM PDT 24
Finished	Jul 12 05:51:00 PM PDT 24
Peak memory	200556 kb
Host	smart-d11c07c8-7eaa-4ad8-849e-f714d4492f96
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101071062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2101071062
Directory	/workspace/33.clkmgr_extclk/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency.4195849823
Short name	T561
Test name
Test status
Simulation time	1883889908 ps
CPU time	10.9 seconds
Started	Jul 12 05:50:49 PM PDT 24
Finished	Jul 12 05:51:02 PM PDT 24
Peak memory	200760 kb
Host	smart-3be8c9fe-6f04-4dd0-8bc7-ca04cfd7e916
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195849823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.4195849823
Directory	/workspace/33.clkmgr_frequency/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency_timeout.1763458186
Short name	T447
Test name
Test status
Simulation time	1791933365 ps
CPU time	6.17 seconds
Started	Jul 12 05:50:54 PM PDT 24
Finished	Jul 12 05:51:02 PM PDT 24
Peak memory	200648 kb
Host	smart-55eee647-a7a2-4e5e-aab8-90b256d52cca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763458186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t imeout.1763458186
Directory	/workspace/33.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/33.clkmgr_idle_intersig_mubi.3605188649
Short name	T203
Test name
Test status
Simulation time	36270263 ps
CPU time	1.05 seconds
Started	Jul 12 05:50:52 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200552 kb
Host	smart-78eb8c81-09e0-48ae-a692-b2190de2084b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605188649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.3605188649
Directory	/workspace/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2792080125
Short name	T441
Test name
Test status
Simulation time	22594293 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:06 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200568 kb
Host	smart-80bc6069-dfcc-4216-804f-3eef684691e4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792080125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.2792080125
Directory	/workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.2976626685
Short name	T771
Test name
Test status
Simulation time	38184446 ps
CPU time	0.95 seconds
Started	Jul 12 05:50:59 PM PDT 24
Finished	Jul 12 05:51:02 PM PDT 24
Peak memory	200516 kb
Host	smart-5374b39b-aaa9-4597-aeda-062c385e6a38
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976626685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_ctrl_intersig_mubi.2976626685
Directory	/workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_peri.1879748830
Short name	T287
Test name
Test status
Simulation time	40586771 ps
CPU time	0.82 seconds
Started	Jul 12 05:50:52 PM PDT 24
Finished	Jul 12 05:50:54 PM PDT 24
Peak memory	200464 kb
Host	smart-eb7b5042-3c18-43d6-8ae2-28a1855a6449
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879748830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1879748830
Directory	/workspace/33.clkmgr_peri/latest

Test location	/workspace/coverage/default/33.clkmgr_regwen.674513167
Short name	T7
Test name
Test status
Simulation time	965366532 ps
CPU time	5.91 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:10 PM PDT 24
Peak memory	200656 kb
Host	smart-d151ebee-a9ff-42d4-9db3-731c100ab100
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674513167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.674513167
Directory	/workspace/33.clkmgr_regwen/latest

Test location	/workspace/coverage/default/33.clkmgr_smoke.916277495
Short name	T693
Test name
Test status
Simulation time	19712700 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:50 PM PDT 24
Finished	Jul 12 05:50:53 PM PDT 24
Peak memory	200528 kb
Host	smart-3ad097c6-6e6e-46a2-9642-787d35bfb349
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916277495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.916277495
Directory	/workspace/33.clkmgr_smoke/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all.378014540
Short name	T9
Test name
Test status
Simulation time	3760214986 ps
CPU time	28.16 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200816 kb
Host	smart-cad113ba-08fe-4a5e-96f4-327d0d86c58a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378014540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.378014540
Directory	/workspace/33.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.2108139261
Short name	T565
Test name
Test status
Simulation time	126423674910 ps
CPU time	878.01 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 06:05:45 PM PDT 24
Peak memory	214624 kb
Host	smart-f7e831b5-d060-4413-bcc9-1cd7a9245c6b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2108139261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.2108139261
Directory	/workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.clkmgr_trans.53881538
Short name	T18
Test name
Test status
Simulation time	32613300 ps
CPU time	0.97 seconds
Started	Jul 12 05:50:53 PM PDT 24
Finished	Jul 12 05:50:55 PM PDT 24
Peak memory	200588 kb
Host	smart-c8f67be1-d181-4457-896a-737a4b9fb6d0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53881538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.53881538
Directory	/workspace/33.clkmgr_trans/latest

Test location	/workspace/coverage/default/34.clkmgr_alert_test.1498096856
Short name	T254
Test name
Test status
Simulation time	19783712 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:03 PM PDT 24
Peak memory	200676 kb
Host	smart-f4f0bdc8-763d-4632-8c6c-782fe11ba4ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498096856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk mgr_alert_test.1498096856
Directory	/workspace/34.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3700078369
Short name	T341
Test name
Test status
Simulation time	32772596 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200592 kb
Host	smart-565b8528-2bbc-45dc-8752-8ca2c5e9a25d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700078369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.3700078369
Directory	/workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_status.2891920952
Short name	T318
Test name
Test status
Simulation time	16008717 ps
CPU time	0.71 seconds
Started	Jul 12 05:50:58 PM PDT 24
Finished	Jul 12 05:51:00 PM PDT 24
Peak memory	199744 kb
Host	smart-077a2a95-029d-4aa8-89c0-fff436aa9bcf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891920952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2891920952
Directory	/workspace/34.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/34.clkmgr_div_intersig_mubi.2862805918
Short name	T296
Test name
Test status
Simulation time	26143430 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:05 PM PDT 24
Peak memory	200588 kb
Host	smart-19347486-b68c-46d3-b927-29c9c8ff796b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862805918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.2862805918
Directory	/workspace/34.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_extclk.1648953358
Short name	T467
Test name
Test status
Simulation time	16997413 ps
CPU time	0.79 seconds
Started	Jul 12 05:50:55 PM PDT 24
Finished	Jul 12 05:50:57 PM PDT 24
Peak memory	200552 kb
Host	smart-813ecec0-570b-4239-8464-a7a6d55da24e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648953358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.1648953358
Directory	/workspace/34.clkmgr_extclk/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency.2632921714
Short name	T360
Test name
Test status
Simulation time	1943707499 ps
CPU time	6.51 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200612 kb
Host	smart-4dce6d9e-1a62-4fc3-acec-73c30fce5d58
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632921714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2632921714
Directory	/workspace/34.clkmgr_frequency/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency_timeout.3347027753
Short name	T603
Test name
Test status
Simulation time	812658699 ps
CPU time	2.99 seconds
Started	Jul 12 05:50:57 PM PDT 24
Finished	Jul 12 05:51:01 PM PDT 24
Peak memory	200684 kb
Host	smart-fc9302a3-0432-4047-9c82-871dafe20616
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347027753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t imeout.3347027753
Directory	/workspace/34.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/34.clkmgr_idle_intersig_mubi.3287150725
Short name	T425
Test name
Test status
Simulation time	65877009 ps
CPU time	0.96 seconds
Started	Jul 12 05:51:03 PM PDT 24
Finished	Jul 12 05:51:07 PM PDT 24
Peak memory	200572 kb
Host	smart-b2b64370-20f1-4932-a5bf-30ddbe3d8a17
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287150725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.3287150725
Directory	/workspace/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1920756825
Short name	T174
Test name
Test status
Simulation time	31299290 ps
CPU time	0.84 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200552 kb
Host	smart-0c463dd5-6da9-4842-b578-3871944bc1d5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920756825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_clk_byp_req_intersig_mubi.1920756825
Directory	/workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.875419381
Short name	T615
Test name
Test status
Simulation time	27899611 ps
CPU time	0.91 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200556 kb
Host	smart-fe6ead36-bc4f-4443-a652-3d3ce1715a7f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875419381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.clkmgr_lc_ctrl_intersig_mubi.875419381
Directory	/workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_peri.1524327365
Short name	T596
Test name
Test status
Simulation time	16880358 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200560 kb
Host	smart-09e80287-466c-4c3f-804d-5d01b7e9887f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524327365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1524327365
Directory	/workspace/34.clkmgr_peri/latest

Test location	/workspace/coverage/default/34.clkmgr_regwen.527384131
Short name	T491
Test name
Test status
Simulation time	1245541680 ps
CPU time	4.77 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	200656 kb
Host	smart-534c0489-8522-4f43-bf70-74179a6cdc3a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527384131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.527384131
Directory	/workspace/34.clkmgr_regwen/latest

Test location	/workspace/coverage/default/34.clkmgr_smoke.2176314377
Short name	T299
Test name
Test status
Simulation time	17648654 ps
CPU time	0.81 seconds
Started	Jul 12 05:51:01 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200508 kb
Host	smart-a19106db-2c0a-4a56-b609-ed6bebd2e00c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176314377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2176314377
Directory	/workspace/34.clkmgr_smoke/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all.50295705
Short name	T475
Test name
Test status
Simulation time	5848942978 ps
CPU time	23.59 seconds
Started	Jul 12 05:51:07 PM PDT 24
Finished	Jul 12 05:51:32 PM PDT 24
Peak memory	200868 kb
Host	smart-dae6699d-9ff9-4ae4-ae89-deee94972ac1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50295705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.clkmgr_stress_all.50295705
Directory	/workspace/34.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3114256604
Short name	T136
Test name
Test status
Simulation time	248907873488 ps
CPU time	1421.09 seconds
Started	Jul 12 05:50:58 PM PDT 24
Finished	Jul 12 06:14:41 PM PDT 24
Peak memory	215032 kb
Host	smart-c85b1f3e-c88a-4b68-a35e-8c186290405f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3114256604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3114256604
Directory	/workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.clkmgr_trans.3300843438
Short name	T728
Test name
Test status
Simulation time	75666144 ps
CPU time	1.01 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:06 PM PDT 24
Peak memory	200560 kb
Host	smart-6e75f8ae-f934-41e5-831d-9d22fca7bc5c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300843438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.3300843438
Directory	/workspace/34.clkmgr_trans/latest

Test location	/workspace/coverage/default/35.clkmgr_alert_test.2095217578
Short name	T261
Test name
Test status
Simulation time	14363009 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200828 kb
Host	smart-f6a448f8-a1ba-40ca-9035-5eb8a87bc143
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095217578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.2095217578
Directory	/workspace/35.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.568860912
Short name	T754
Test name
Test status
Simulation time	31295466 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:01 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200524 kb
Host	smart-098b12c8-f7f2-43a5-96e4-4c3776ece4aa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568860912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.568860912
Directory	/workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_status.3170523639
Short name	T529
Test name
Test status
Simulation time	17888825 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:03 PM PDT 24
Finished	Jul 12 05:51:07 PM PDT 24
Peak memory	200416 kb
Host	smart-6ff86e96-3504-496b-a7fc-9201e07f767c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170523639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3170523639
Directory	/workspace/35.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/35.clkmgr_div_intersig_mubi.1428318498
Short name	T169
Test name
Test status
Simulation time	20076727 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200496 kb
Host	smart-278f6031-63ec-4929-86e1-94381ddc007f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428318498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.1428318498
Directory	/workspace/35.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_extclk.3856299151
Short name	T673
Test name
Test status
Simulation time	15110631 ps
CPU time	0.79 seconds
Started	Jul 12 05:51:01 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200584 kb
Host	smart-40eac875-a7e7-4795-a09e-e30cc7c11224
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856299151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3856299151
Directory	/workspace/35.clkmgr_extclk/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency.1819431444
Short name	T593
Test name
Test status
Simulation time	2236456988 ps
CPU time	16.06 seconds
Started	Jul 12 05:50:57 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	200812 kb
Host	smart-38c31ee6-0dff-4c90-86e1-4832f2c19c25
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819431444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1819431444
Directory	/workspace/35.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency_timeout.2524735311
Short name	T276
Test name
Test status
Simulation time	2300530104 ps
CPU time	15.83 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:21 PM PDT 24
Peak memory	200812 kb
Host	smart-11648e71-0a3b-43a5-8e8a-f77cbd3d75e7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524735311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t imeout.2524735311
Directory	/workspace/35.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3274360138
Short name	T568
Test name
Test status
Simulation time	65348316 ps
CPU time	1 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:03 PM PDT 24
Peak memory	200572 kb
Host	smart-b1621db1-7cf2-4d99-b03f-da83345bbfce
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274360138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.3274360138
Directory	/workspace/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3173297698
Short name	T170
Test name
Test status
Simulation time	13176221 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:19 PM PDT 24
Finished	Jul 12 05:51:22 PM PDT 24
Peak memory	200560 kb
Host	smart-06e16612-65d0-41ff-a4f3-512f75fc0dbb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173297698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_clk_byp_req_intersig_mubi.3173297698
Directory	/workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3754984632
Short name	T419
Test name
Test status
Simulation time	89332803 ps
CPU time	1.07 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200584 kb
Host	smart-b4c9862f-e37e-49e3-ad18-1c3cb9e70486
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754984632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_ctrl_intersig_mubi.3754984632
Directory	/workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_peri.1604882307
Short name	T664
Test name
Test status
Simulation time	17068304 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200368 kb
Host	smart-03c0da2e-609d-4631-84e4-e699c8248ac5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604882307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1604882307
Directory	/workspace/35.clkmgr_peri/latest

Test location	/workspace/coverage/default/35.clkmgr_regwen.1616437142
Short name	T470
Test name
Test status
Simulation time	1151110016 ps
CPU time	5.4 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200652 kb
Host	smart-7a657c7f-9f56-49a8-a4bb-d0ba21d3a5ed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616437142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.1616437142
Directory	/workspace/35.clkmgr_regwen/latest

Test location	/workspace/coverage/default/35.clkmgr_smoke.2179502242
Short name	T715
Test name
Test status
Simulation time	22305296 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200516 kb
Host	smart-c2f760c8-0c35-4326-971e-b1de1c35aa25
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179502242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2179502242
Directory	/workspace/35.clkmgr_smoke/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all.3879125130
Short name	T404
Test name
Test status
Simulation time	718739160 ps
CPU time	3.14 seconds
Started	Jul 12 05:50:56 PM PDT 24
Finished	Jul 12 05:51:01 PM PDT 24
Peak memory	200692 kb
Host	smart-35586ffc-2b4c-4fd5-bd8f-c8b4cfde378f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879125130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.3879125130
Directory	/workspace/35.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.867390760
Short name	T797
Test name
Test status
Simulation time	16142747655 ps
CPU time	236 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:55:11 PM PDT 24
Peak memory	209232 kb
Host	smart-81c76b49-8206-4a27-8ac0-fcc30385597c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=867390760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.867390760
Directory	/workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.clkmgr_trans.3620586353
Short name	T457
Test name
Test status
Simulation time	24342221 ps
CPU time	0.92 seconds
Started	Jul 12 05:50:57 PM PDT 24
Finished	Jul 12 05:50:59 PM PDT 24
Peak memory	200568 kb
Host	smart-7ef593ce-842a-40ae-9851-50b3150ebb63
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620586353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3620586353
Directory	/workspace/35.clkmgr_trans/latest

Test location	/workspace/coverage/default/36.clkmgr_alert_test.4264735475
Short name	T32
Test name
Test status
Simulation time	31210126 ps
CPU time	0.77 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:07 PM PDT 24
Peak memory	200664 kb
Host	smart-be75b305-0386-4a10-99b1-387ad73848e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264735475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.4264735475
Directory	/workspace/36.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.61347440
Short name	T243
Test name
Test status
Simulation time	59118491 ps
CPU time	0.94 seconds
Started	Jul 12 05:51:09 PM PDT 24
Finished	Jul 12 05:51:11 PM PDT 24
Peak memory	200576 kb
Host	smart-02b4fab2-dd9e-4383-9f85-058d801e183c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61347440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.clkmgr_clk_handshake_intersig_mubi.61347440
Directory	/workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_status.60346449
Short name	T554
Test name
Test status
Simulation time	19001212 ps
CPU time	0.69 seconds
Started	Jul 12 05:51:14 PM PDT 24
Finished	Jul 12 05:51:17 PM PDT 24
Peak memory	200436 kb
Host	smart-a560bd8d-9a85-489a-afe4-05cb8c48622f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60346449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.60346449
Directory	/workspace/36.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/36.clkmgr_div_intersig_mubi.4286247398
Short name	T199
Test name
Test status
Simulation time	26308568 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:13 PM PDT 24
Finished	Jul 12 05:51:17 PM PDT 24
Peak memory	200568 kb
Host	smart-e4b07825-9663-45f7-b1fa-7b0838e41234
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286247398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.4286247398
Directory	/workspace/36.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_extclk.1024399450
Short name	T431
Test name
Test status
Simulation time	88364792 ps
CPU time	1.09 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	200584 kb
Host	smart-dfe5d500-35ce-413a-a927-065a68f77cc2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024399450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1024399450
Directory	/workspace/36.clkmgr_extclk/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency.3593664930
Short name	T446
Test name
Test status
Simulation time	1188649895 ps
CPU time	5.03 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200132 kb
Host	smart-2465a5b3-25e8-4106-bbc2-719a626dea18
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593664930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.3593664930
Directory	/workspace/36.clkmgr_frequency/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency_timeout.2956329926
Short name	T332
Test name
Test status
Simulation time	706536293 ps
CPU time	2.82 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200672 kb
Host	smart-c0aac255-7fd5-42b0-90aa-10a2c2b068c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956329926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t imeout.2956329926
Directory	/workspace/36.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/36.clkmgr_idle_intersig_mubi.3998971325
Short name	T319
Test name
Test status
Simulation time	59693748 ps
CPU time	0.96 seconds
Started	Jul 12 05:51:01 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200560 kb
Host	smart-93935e28-9331-4a7f-9012-3a8a21867f7a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998971325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.3998971325
Directory	/workspace/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.2146118675
Short name	T661
Test name
Test status
Simulation time	39900353 ps
CPU time	0.84 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	200604 kb
Host	smart-91828bed-7df4-4ff0-a3d4-68f92a8734c8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146118675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_clk_byp_req_intersig_mubi.2146118675
Directory	/workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1937058840
Short name	T378
Test name
Test status
Simulation time	23255701 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:02 PM PDT 24
Peak memory	200584 kb
Host	smart-26db3291-a28a-4aea-8b28-03f5c0d2ad5e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937058840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_ctrl_intersig_mubi.1937058840
Directory	/workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_peri.31406077
Short name	T582
Test name
Test status
Simulation time	23768765 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200392 kb
Host	smart-6a5b8d5d-f964-4830-ac12-38636e9afb10
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31406077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.31406077
Directory	/workspace/36.clkmgr_peri/latest

Test location	/workspace/coverage/default/36.clkmgr_regwen.307675032
Short name	T450
Test name
Test status
Simulation time	188463455 ps
CPU time	1.63 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:06 PM PDT 24
Peak memory	199916 kb
Host	smart-a0d71c9d-b5a9-47fe-894f-3039796fac5b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307675032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.307675032
Directory	/workspace/36.clkmgr_regwen/latest

Test location	/workspace/coverage/default/36.clkmgr_smoke.3980815317
Short name	T201
Test name
Test status
Simulation time	53055680 ps
CPU time	0.93 seconds
Started	Jul 12 05:51:07 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200732 kb
Host	smart-b89de0f0-c2d3-4ed5-a774-18f1119008aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980815317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3980815317
Directory	/workspace/36.clkmgr_smoke/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all.3778367647
Short name	T104
Test name
Test status
Simulation time	9496420058 ps
CPU time	46.4 seconds
Started	Jul 12 05:51:09 PM PDT 24
Finished	Jul 12 05:51:56 PM PDT 24
Peak memory	200848 kb
Host	smart-7d6ce1d6-7f1c-4101-856d-6532f0de4d30
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778367647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.3778367647
Directory	/workspace/36.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.3809411984
Short name	T142
Test name
Test status
Simulation time	12489279929 ps
CPU time	180.08 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:54:19 PM PDT 24
Peak memory	209080 kb
Host	smart-8bb60a1b-f4fe-40e0-8dde-93d37a249302
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3809411984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.3809411984
Directory	/workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.clkmgr_trans.4115763778
Short name	T240
Test name
Test status
Simulation time	19178505 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200572 kb
Host	smart-5565c0aa-b384-43e9-a044-3a83d34f9c6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115763778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.4115763778
Directory	/workspace/36.clkmgr_trans/latest

Test location	/workspace/coverage/default/37.clkmgr_alert_test.3803810139
Short name	T815
Test name
Test status
Simulation time	88761144 ps
CPU time	0.99 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200696 kb
Host	smart-1e38a7c2-cda0-4a1d-90b7-679143827f90
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803810139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.3803810139
Directory	/workspace/37.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.893410230
Short name	T700
Test name
Test status
Simulation time	140995679 ps
CPU time	1.26 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200584 kb
Host	smart-4d1b9b83-99ce-4ebe-a974-8b4bb35881af
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893410230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.893410230
Directory	/workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_status.3692068722
Short name	T242
Test name
Test status
Simulation time	37876531 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200440 kb
Host	smart-a5125420-75af-4375-92f9-cf328faaa417
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692068722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3692068722
Directory	/workspace/37.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/37.clkmgr_div_intersig_mubi.72634518
Short name	T576
Test name
Test status
Simulation time	27651529 ps
CPU time	0.91 seconds
Started	Jul 12 05:51:10 PM PDT 24
Finished	Jul 12 05:51:12 PM PDT 24
Peak memory	200568 kb
Host	smart-fd7e5aca-feab-4aa7-ac40-2b25b9b9b0f6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72634518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .clkmgr_div_intersig_mubi.72634518
Directory	/workspace/37.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_extclk.2437040969
Short name	T694
Test name
Test status
Simulation time	33394036 ps
CPU time	0.85 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200464 kb
Host	smart-58364aa3-7ebd-43de-af2e-5d86862f8c8b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437040969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2437040969
Directory	/workspace/37.clkmgr_extclk/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency.1500148804
Short name	T777
Test name
Test status
Simulation time	1318765950 ps
CPU time	6.01 seconds
Started	Jul 12 05:51:13 PM PDT 24
Finished	Jul 12 05:51:22 PM PDT 24
Peak memory	200640 kb
Host	smart-a6bf6bb4-0b1c-4ca9-ba08-2d079f038626
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500148804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1500148804
Directory	/workspace/37.clkmgr_frequency/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency_timeout.2299369010
Short name	T227
Test name
Test status
Simulation time	624447318 ps
CPU time	3.44 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:05 PM PDT 24
Peak memory	200692 kb
Host	smart-0f287a9c-d93c-4a6f-b116-765aaaa4b012
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299369010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t imeout.2299369010
Directory	/workspace/37.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/37.clkmgr_idle_intersig_mubi.653455727
Short name	T665
Test name
Test status
Simulation time	211463634 ps
CPU time	1.56 seconds
Started	Jul 12 05:51:09 PM PDT 24
Finished	Jul 12 05:51:12 PM PDT 24
Peak memory	200496 kb
Host	smart-ec28f161-e7e6-4da5-bdee-28ec5befa391
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653455727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.clkmgr_idle_intersig_mubi.653455727
Directory	/workspace/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1748829587
Short name	T36
Test name
Test status
Simulation time	222748673 ps
CPU time	1.46 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200576 kb
Host	smart-d6b8ecf6-1783-4879-9d16-0cffbe3b36de
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748829587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1748829587
Directory	/workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2305771903
Short name	T98
Test name
Test status
Simulation time	17148651 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200520 kb
Host	smart-704361e0-3d6d-43a2-9049-6898a18d04f0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305771903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_ctrl_intersig_mubi.2305771903
Directory	/workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_peri.1767885348
Short name	T180
Test name
Test status
Simulation time	51199454 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:09 PM PDT 24
Finished	Jul 12 05:51:11 PM PDT 24
Peak memory	200364 kb
Host	smart-514d3515-d52d-4d41-9740-2efa23cda566
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767885348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1767885348
Directory	/workspace/37.clkmgr_peri/latest

Test location	/workspace/coverage/default/37.clkmgr_regwen.74623756
Short name	T362
Test name
Test status
Simulation time	894808830 ps
CPU time	3.11 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200724 kb
Host	smart-6db40704-6bc4-45dd-9f8e-54335d1d8720
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74623756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.74623756
Directory	/workspace/37.clkmgr_regwen/latest

Test location	/workspace/coverage/default/37.clkmgr_smoke.3208194785
Short name	T209
Test name
Test status
Simulation time	25034982 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200496 kb
Host	smart-0775b12b-cd8e-4fe5-adf4-fa1104c00ff9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208194785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3208194785
Directory	/workspace/37.clkmgr_smoke/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all.1480405430
Short name	T308
Test name
Test status
Simulation time	6588879515 ps
CPU time	46.41 seconds
Started	Jul 12 05:51:14 PM PDT 24
Finished	Jul 12 05:52:03 PM PDT 24
Peak memory	200816 kb
Host	smart-a4c4a58b-9cff-45c1-bb11-8f00331406e4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480405430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.1480405430
Directory	/workspace/37.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.3050269715
Short name	T60
Test name
Test status
Simulation time	129136290316 ps
CPU time	773.78 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 06:03:56 PM PDT 24
Peak memory	209200 kb
Host	smart-f413f08e-0d36-43be-820a-da6065d775e6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3050269715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.3050269715
Directory	/workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.clkmgr_trans.2764558994
Short name	T805
Test name
Test status
Simulation time	59622270 ps
CPU time	0.93 seconds
Started	Jul 12 05:51:01 PM PDT 24
Finished	Jul 12 05:51:04 PM PDT 24
Peak memory	200540 kb
Host	smart-212e5210-dc73-4a4d-98ed-2f1ea97a53d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764558994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2764558994
Directory	/workspace/37.clkmgr_trans/latest

Test location	/workspace/coverage/default/38.clkmgr_alert_test.1365865513
Short name	T30
Test name
Test status
Simulation time	30340404 ps
CPU time	0.84 seconds
Started	Jul 12 05:51:10 PM PDT 24
Finished	Jul 12 05:51:12 PM PDT 24
Peak memory	200700 kb
Host	smart-280eee54-3423-437d-a20f-aca8e45d2a0a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365865513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.1365865513
Directory	/workspace/38.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.4293671966
Short name	T327
Test name
Test status
Simulation time	122107836 ps
CPU time	1.08 seconds
Started	Jul 12 05:51:09 PM PDT 24
Finished	Jul 12 05:51:11 PM PDT 24
Peak memory	200616 kb
Host	smart-b8e501b1-efc9-456e-9f24-8fcd93342b04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293671966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.4293671966
Directory	/workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_status.3804658173
Short name	T395
Test name
Test status
Simulation time	16730526 ps
CPU time	0.73 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	199748 kb
Host	smart-bd628808-6f6d-4d85-85e6-3db1d75dc9e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804658173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3804658173
Directory	/workspace/38.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/38.clkmgr_div_intersig_mubi.524374675
Short name	T818
Test name
Test status
Simulation time	151320814 ps
CPU time	1.25 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200592 kb
Host	smart-916f1719-5213-4716-b96a-5b00e52f760b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524374675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.clkmgr_div_intersig_mubi.524374675
Directory	/workspace/38.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_extclk.2579679450
Short name	T5
Test name
Test status
Simulation time	21106206 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:27 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200532 kb
Host	smart-3bdc2419-965f-4e58-8a64-c763f91342d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579679450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2579679450
Directory	/workspace/38.clkmgr_extclk/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency.494972429
Short name	T528
Test name
Test status
Simulation time	809769154 ps
CPU time	4.83 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:13 PM PDT 24
Peak memory	200628 kb
Host	smart-6126daae-20cd-460f-a103-1f4a02aab82f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494972429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.494972429
Directory	/workspace/38.clkmgr_frequency/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency_timeout.3167269008
Short name	T631
Test name
Test status
Simulation time	153463509 ps
CPU time	1.45 seconds
Started	Jul 12 05:51:10 PM PDT 24
Finished	Jul 12 05:51:12 PM PDT 24
Peak memory	200584 kb
Host	smart-9206e517-8c27-4790-9aca-adb8873a0310
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167269008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t imeout.3167269008
Directory	/workspace/38.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3134487511
Short name	T375
Test name
Test status
Simulation time	69017379 ps
CPU time	1.1 seconds
Started	Jul 12 05:51:21 PM PDT 24
Finished	Jul 12 05:51:23 PM PDT 24
Peak memory	200464 kb
Host	smart-84a32e00-1b9b-485c-9efd-b33650744d40
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134487511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.3134487511
Directory	/workspace/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2117878769
Short name	T616
Test name
Test status
Simulation time	14652961 ps
CPU time	0.72 seconds
Started	Jul 12 05:51:13 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200448 kb
Host	smart-f36c2d47-ac00-4adc-8d08-dbc93565168b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117878769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2117878769
Directory	/workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3190338659
Short name	T551
Test name
Test status
Simulation time	20270659 ps
CPU time	0.81 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:24 PM PDT 24
Peak memory	200588 kb
Host	smart-40c40e2a-2413-4f4f-929d-acc736992002
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190338659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_ctrl_intersig_mubi.3190338659
Directory	/workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_peri.4169811137
Short name	T226
Test name
Test status
Simulation time	14673848 ps
CPU time	0.73 seconds
Started	Jul 12 05:51:00 PM PDT 24
Finished	Jul 12 05:51:03 PM PDT 24
Peak memory	200428 kb
Host	smart-a2387c8b-6f6a-4847-b144-0ae14e4cc444
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169811137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.4169811137
Directory	/workspace/38.clkmgr_peri/latest

Test location	/workspace/coverage/default/38.clkmgr_regwen.2017968206
Short name	T519
Test name
Test status
Simulation time	1140686102 ps
CPU time	6.51 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:21 PM PDT 24
Peak memory	200640 kb
Host	smart-810a8f1b-c529-4c4e-82a2-425b549c6a4d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017968206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2017968206
Directory	/workspace/38.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_smoke.3844801906
Short name	T330
Test name
Test status
Simulation time	43353952 ps
CPU time	0.91 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200512 kb
Host	smart-ac69093b-b998-43f9-b790-c20a8c2a7ed3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844801906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.3844801906
Directory	/workspace/38.clkmgr_smoke/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.1669911503
Short name	T155
Test name
Test status
Simulation time	58090491908 ps
CPU time	380.66 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:57:35 PM PDT 24
Peak memory	217316 kb
Host	smart-86c47b2a-381c-48ad-b298-cb6ca7b3368b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1669911503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1669911503
Directory	/workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.clkmgr_trans.2479987642
Short name	T422
Test name
Test status
Simulation time	65498815 ps
CPU time	1.06 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200560 kb
Host	smart-0f667fe0-1ad8-488c-a581-8ca926187b1b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479987642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2479987642
Directory	/workspace/38.clkmgr_trans/latest

Test location	/workspace/coverage/default/39.clkmgr_alert_test.45202994
Short name	T793
Test name
Test status
Simulation time	23382027 ps
CPU time	0.82 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200728 kb
Host	smart-0555b49b-6f3a-4ad3-a5fe-1d9777796553
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45202994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmg r_alert_test.45202994
Directory	/workspace/39.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.3459526474
Short name	T695
Test name
Test status
Simulation time	25696136 ps
CPU time	0.95 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200452 kb
Host	smart-fa4dacb3-1d4e-4072-bb7e-a9cc5ede0298
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459526474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.3459526474
Directory	/workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_status.727506682
Short name	T746
Test name
Test status
Simulation time	37736661 ps
CPU time	0.77 seconds
Started	Jul 12 05:51:10 PM PDT 24
Finished	Jul 12 05:51:12 PM PDT 24
Peak memory	200668 kb
Host	smart-eed418bf-ceaa-43e9-8013-b22c43bc2f38
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727506682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.727506682
Directory	/workspace/39.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/39.clkmgr_div_intersig_mubi.1421826578
Short name	T175
Test name
Test status
Simulation time	22867583 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200568 kb
Host	smart-a4ae5b03-7a54-47b8-8b6e-fd20009796d6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421826578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.1421826578
Directory	/workspace/39.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_extclk.1757774378
Short name	T259
Test name
Test status
Simulation time	16815117 ps
CPU time	0.73 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200412 kb
Host	smart-5f4e9881-577c-443a-a07b-e655e5f226bf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757774378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1757774378
Directory	/workspace/39.clkmgr_extclk/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency.1068890923
Short name	T105
Test name
Test status
Simulation time	1763924145 ps
CPU time	12.91 seconds
Started	Jul 12 05:51:31 PM PDT 24
Finished	Jul 12 05:51:45 PM PDT 24
Peak memory	200408 kb
Host	smart-5527dfc7-cf80-44a0-b6de-6bc8ccdff19b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068890923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1068890923
Directory	/workspace/39.clkmgr_frequency/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency_timeout.4147351232
Short name	T468
Test name
Test status
Simulation time	2341690504 ps
CPU time	8.86 seconds
Started	Jul 12 05:51:09 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	200788 kb
Host	smart-b5153e00-e028-491f-afe7-304f024667c2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147351232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t imeout.4147351232
Directory	/workspace/39.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1790619331
Short name	T713
Test name
Test status
Simulation time	147102823 ps
CPU time	1.38 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200584 kb
Host	smart-a8ee2951-9fa5-488a-b938-b9d48eee25c6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790619331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.1790619331
Directory	/workspace/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2221801179
Short name	T508
Test name
Test status
Simulation time	47229523 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:05 PM PDT 24
Finished	Jul 12 05:51:08 PM PDT 24
Peak memory	200576 kb
Host	smart-1e5ef106-cf57-4cb7-9204-7c9a6f852f6f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221801179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2221801179
Directory	/workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.2539979309
Short name	T282
Test name
Test status
Simulation time	27533341 ps
CPU time	0.76 seconds
Started	Jul 12 05:51:29 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200404 kb
Host	smart-9c97b4ca-2752-4f4a-af84-d4b86718a040
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539979309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_ctrl_intersig_mubi.2539979309
Directory	/workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_peri.2237762100
Short name	T740
Test name
Test status
Simulation time	18967569 ps
CPU time	0.74 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:13 PM PDT 24
Peak memory	200452 kb
Host	smart-bbdb2065-3fd5-47f1-8ebc-68f4674e21f0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237762100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.2237762100
Directory	/workspace/39.clkmgr_peri/latest

Test location	/workspace/coverage/default/39.clkmgr_regwen.1963049436
Short name	T279
Test name
Test status
Simulation time	1308870622 ps
CPU time	4.09 seconds
Started	Jul 12 05:51:02 PM PDT 24
Finished	Jul 12 05:51:09 PM PDT 24
Peak memory	200660 kb
Host	smart-e10fbc75-987e-4cee-bc84-8c088f95297d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963049436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1963049436
Directory	/workspace/39.clkmgr_regwen/latest

Test location	/workspace/coverage/default/39.clkmgr_smoke.1807705999
Short name	T794
Test name
Test status
Simulation time	83614712 ps
CPU time	1.1 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200540 kb
Host	smart-5ddac4de-0cab-4e5a-9e49-9fff77107d80
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807705999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1807705999
Directory	/workspace/39.clkmgr_smoke/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all.1082022189
Short name	T210
Test name
Test status
Simulation time	12326464057 ps
CPU time	50.39 seconds
Started	Jul 12 05:51:19 PM PDT 24
Finished	Jul 12 05:52:11 PM PDT 24
Peak memory	200760 kb
Host	smart-1c63d72a-9e0e-46b5-ba12-228298c39ce1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082022189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.1082022189
Directory	/workspace/39.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.3166546748
Short name	T581
Test name
Test status
Simulation time	76576035353 ps
CPU time	485.94 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:59:21 PM PDT 24
Peak memory	209184 kb
Host	smart-55f60fa5-e257-46ec-9500-371c76318edf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3166546748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3166546748
Directory	/workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.clkmgr_trans.2045604356
Short name	T813
Test name
Test status
Simulation time	29712348 ps
CPU time	0.91 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:14 PM PDT 24
Peak memory	200568 kb
Host	smart-130735a2-4dbf-43b6-9ee3-7929b1abb02d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045604356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2045604356
Directory	/workspace/39.clkmgr_trans/latest

Test location	/workspace/coverage/default/4.clkmgr_alert_test.4086273456
Short name	T270
Test name
Test status
Simulation time	54877636 ps
CPU time	0.88 seconds
Started	Jul 12 05:49:42 PM PDT 24
Finished	Jul 12 05:49:45 PM PDT 24
Peak memory	200692 kb
Host	smart-2643f656-f812-4fe3-831b-8af348813ccb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086273456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm gr_alert_test.4086273456
Directory	/workspace/4.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.432442129
Short name	T745
Test name
Test status
Simulation time	94830598 ps
CPU time	0.99 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:49:57 PM PDT 24
Peak memory	200536 kb
Host	smart-fe94ef5c-40a7-41a1-a5ae-386cdca3b8be
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432442129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.432442129
Directory	/workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_status.2192520718
Short name	T144
Test name
Test status
Simulation time	12600782 ps
CPU time	0.7 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	199748 kb
Host	smart-4373ffa5-22a7-493c-898d-f28bb73ae879
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192520718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.2192520718
Directory	/workspace/4.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/4.clkmgr_div_intersig_mubi.3562903400
Short name	T399
Test name
Test status
Simulation time	16755332 ps
CPU time	0.79 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:47 PM PDT 24
Peak memory	200568 kb
Host	smart-e5af4552-9762-4c02-ae9b-725edff5840d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562903400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.3562903400
Directory	/workspace/4.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_extclk.4219070314
Short name	T258
Test name
Test status
Simulation time	46526667 ps
CPU time	0.93 seconds
Started	Jul 12 05:49:40 PM PDT 24
Finished	Jul 12 05:49:44 PM PDT 24
Peak memory	200536 kb
Host	smart-517dbc20-66c6-4f79-989b-15ddbb2c1551
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219070314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.4219070314
Directory	/workspace/4.clkmgr_extclk/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency.3841367869
Short name	T543
Test name
Test status
Simulation time	1529749899 ps
CPU time	9.12 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:49:53 PM PDT 24
Peak memory	200600 kb
Host	smart-dc856a32-1f46-4c2c-93e7-59eb01e12204
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841367869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.3841367869
Directory	/workspace/4.clkmgr_frequency/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency_timeout.768634190
Short name	T724
Test name
Test status
Simulation time	1223772600 ps
CPU time	6.86 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:49:50 PM PDT 24
Peak memory	200656 kb
Host	smart-e89c62fe-e324-443f-b13c-e1ef971e9f0e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768634190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim eout.768634190
Directory	/workspace/4.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1295983270
Short name	T161
Test name
Test status
Simulation time	224363257 ps
CPU time	1.61 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200524 kb
Host	smart-3e5685fc-a387-465e-a84f-a17b78d76410
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295983270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.1295983270
Directory	/workspace/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.382236870
Short name	T525
Test name
Test status
Simulation time	16620896 ps
CPU time	0.86 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:47 PM PDT 24
Peak memory	200796 kb
Host	smart-ff15a335-fd9b-46a4-8a5c-2b5ed48307e3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382236870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.clkmgr_lc_clk_byp_req_intersig_mubi.382236870
Directory	/workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.4139961165
Short name	T306
Test name
Test status
Simulation time	19006511 ps
CPU time	0.81 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:40 PM PDT 24
Peak memory	200772 kb
Host	smart-fe933442-a62e-4288-8057-b60035fdc699
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139961165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.4139961165
Directory	/workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_peri.3404242840
Short name	T194
Test name
Test status
Simulation time	25032867 ps
CPU time	0.77 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:42 PM PDT 24
Peak memory	200440 kb
Host	smart-d3820b0c-5e51-4f2f-a191-6b301d2d0de0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404242840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3404242840
Directory	/workspace/4.clkmgr_peri/latest

Test location	/workspace/coverage/default/4.clkmgr_regwen.954771412
Short name	T784
Test name
Test status
Simulation time	635036164 ps
CPU time	2.87 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:49 PM PDT 24
Peak memory	200652 kb
Host	smart-c0d77da1-9df8-48d1-abfa-09eea031447b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954771412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.954771412
Directory	/workspace/4.clkmgr_regwen/latest

Test location	/workspace/coverage/default/4.clkmgr_sec_cm.1584498458
Short name	T39
Test name
Test status
Simulation time	346048171 ps
CPU time	3.39 seconds
Started	Jul 12 05:49:42 PM PDT 24
Finished	Jul 12 05:49:47 PM PDT 24
Peak memory	216104 kb
Host	smart-de481d89-6156-4108-ae43-85c731b893f9
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584498458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg r_sec_cm.1584498458
Directory	/workspace/4.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/4.clkmgr_smoke.3937327936
Short name	T354
Test name
Test status
Simulation time	34045293 ps
CPU time	0.86 seconds
Started	Jul 12 05:49:38 PM PDT 24
Finished	Jul 12 05:49:41 PM PDT 24
Peak memory	200520 kb
Host	smart-6898b255-0823-48ce-9905-828da5d36668
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937327936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3937327936
Directory	/workspace/4.clkmgr_smoke/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all.77008213
Short name	T845
Test name
Test status
Simulation time	3946578993 ps
CPU time	26.8 seconds
Started	Jul 12 05:49:40 PM PDT 24
Finished	Jul 12 05:50:08 PM PDT 24
Peak memory	200924 kb
Host	smart-f0a0d3a7-d6f0-423f-b4b2-ca846d747768
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77008213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .clkmgr_stress_all.77008213
Directory	/workspace/4.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.2706845527
Short name	T657
Test name
Test status
Simulation time	48035161227 ps
CPU time	743.13 seconds
Started	Jul 12 05:49:50 PM PDT 24
Finished	Jul 12 06:02:14 PM PDT 24
Peak memory	211888 kb
Host	smart-fe3212c7-6b25-45d3-b908-d4566e68dc08
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2706845527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.2706845527
Directory	/workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.clkmgr_trans.2446210377
Short name	T573
Test name
Test status
Simulation time	76759447 ps
CPU time	1.22 seconds
Started	Jul 12 05:49:47 PM PDT 24
Finished	Jul 12 05:49:49 PM PDT 24
Peak memory	200528 kb
Host	smart-bb67fd2f-72bb-44aa-a2fe-03f761046ad0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446210377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2446210377
Directory	/workspace/4.clkmgr_trans/latest

Test location	/workspace/coverage/default/40.clkmgr_alert_test.395548256
Short name	T567
Test name
Test status
Simulation time	18197589 ps
CPU time	0.76 seconds
Started	Jul 12 05:51:13 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200604 kb
Host	smart-202d7bdd-8d99-4503-bb7a-78129ac007d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395548256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkm gr_alert_test.395548256
Directory	/workspace/40.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3751631269
Short name	T812
Test name
Test status
Simulation time	66362810 ps
CPU time	0.92 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:14 PM PDT 24
Peak memory	200600 kb
Host	smart-0a64b063-1836-4375-ba95-9a87f34a368d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751631269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.3751631269
Directory	/workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_status.1822790109
Short name	T66
Test name
Test status
Simulation time	37549881 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	199680 kb
Host	smart-79b1532e-9cc5-4f28-9333-d451fa4b61bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822790109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1822790109
Directory	/workspace/40.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/40.clkmgr_div_intersig_mubi.1875270864
Short name	T388
Test name
Test status
Simulation time	17298638 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:13 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200564 kb
Host	smart-c865f575-8984-422e-9805-e00378d32aaa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875270864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.1875270864
Directory	/workspace/40.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_extclk.3093333736
Short name	T262
Test name
Test status
Simulation time	236594956 ps
CPU time	1.47 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200580 kb
Host	smart-ed2fd4e7-7b58-4a40-bc6e-8c39039f0b25
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093333736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.3093333736
Directory	/workspace/40.clkmgr_extclk/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency.3265922596
Short name	T514
Test name
Test status
Simulation time	1776965355 ps
CPU time	8.19 seconds
Started	Jul 12 05:51:19 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200656 kb
Host	smart-56aab109-5dcb-43ba-b673-ba77b30cf532
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265922596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.3265922596
Directory	/workspace/40.clkmgr_frequency/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency_timeout.729488249
Short name	T436
Test name
Test status
Simulation time	760831681 ps
CPU time	3.6 seconds
Started	Jul 12 05:51:24 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200644 kb
Host	smart-bd705f0b-2b6a-460a-af79-41f591e570a5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729488249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_ti meout.729488249
Directory	/workspace/40.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.3348037646
Short name	T162
Test name
Test status
Simulation time	37803423 ps
CPU time	1.04 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200556 kb
Host	smart-3cd5f9b2-8ee5-44bc-8120-568f9d23550b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348037646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3348037646
Directory	/workspace/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2157013526
Short name	T722
Test name
Test status
Simulation time	58047191 ps
CPU time	0.88 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200520 kb
Host	smart-a99d77d2-7cbc-441b-b2e0-62b054000493
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157013526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_clk_byp_req_intersig_mubi.2157013526
Directory	/workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.727588931
Short name	T385
Test name
Test status
Simulation time	26586517 ps
CPU time	0.9 seconds
Started	Jul 12 05:51:04 PM PDT 24
Finished	Jul 12 05:51:07 PM PDT 24
Peak memory	200564 kb
Host	smart-32cbac2e-a71b-4fae-94b9-c5eecf7ded24
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727588931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.clkmgr_lc_ctrl_intersig_mubi.727588931
Directory	/workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_peri.1763058082
Short name	T301
Test name
Test status
Simulation time	21366403 ps
CPU time	0.71 seconds
Started	Jul 12 05:51:10 PM PDT 24
Finished	Jul 12 05:51:12 PM PDT 24
Peak memory	200436 kb
Host	smart-3e0e13f6-6efd-4fbd-a72a-9fdd69a9e1e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763058082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1763058082
Directory	/workspace/40.clkmgr_peri/latest

Test location	/workspace/coverage/default/40.clkmgr_regwen.2647557491
Short name	T401
Test name
Test status
Simulation time	455053943 ps
CPU time	2.92 seconds
Started	Jul 12 05:51:06 PM PDT 24
Finished	Jul 12 05:51:11 PM PDT 24
Peak memory	200580 kb
Host	smart-7c76abf1-f6df-4a83-a90c-ad0305d7dfa7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647557491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.2647557491
Directory	/workspace/40.clkmgr_regwen/latest

Test location	/workspace/coverage/default/40.clkmgr_smoke.374516180
Short name	T239
Test name
Test status
Simulation time	50992156 ps
CPU time	0.87 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200460 kb
Host	smart-99906959-fb5b-4ea9-a686-bf32c6525185
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374516180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.374516180
Directory	/workspace/40.clkmgr_smoke/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all.1386294038
Short name	T294
Test name
Test status
Simulation time	6510675185 ps
CPU time	27.84 seconds
Started	Jul 12 05:51:14 PM PDT 24
Finished	Jul 12 05:51:44 PM PDT 24
Peak memory	200908 kb
Host	smart-2e05f45f-656e-40c2-9dbf-6d413c7f1e31
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386294038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.1386294038
Directory	/workspace/40.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.1065857739
Short name	T464
Test name
Test status
Simulation time	97551695945 ps
CPU time	647.91 seconds
Started	Jul 12 05:51:13 PM PDT 24
Finished	Jul 12 06:02:04 PM PDT 24
Peak memory	217280 kb
Host	smart-a2bf8521-424f-4ff3-8c63-6d76bb890f4d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1065857739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.1065857739
Directory	/workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.clkmgr_trans.1064634877
Short name	T366
Test name
Test status
Simulation time	40616830 ps
CPU time	0.97 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	200560 kb
Host	smart-47907591-0f7c-4fc5-90f6-0df6c7f4596d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064634877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.1064634877
Directory	/workspace/40.clkmgr_trans/latest

Test location	/workspace/coverage/default/41.clkmgr_alert_test.2604263156
Short name	T198
Test name
Test status
Simulation time	18635787 ps
CPU time	0.81 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200704 kb
Host	smart-b6b5fa58-deff-43ac-9db0-ee4659402e02
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604263156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk mgr_alert_test.2604263156
Directory	/workspace/41.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.985276310
Short name	T451
Test name
Test status
Simulation time	45779413 ps
CPU time	0.92 seconds
Started	Jul 12 05:51:31 PM PDT 24
Finished	Jul 12 05:51:33 PM PDT 24
Peak memory	200212 kb
Host	smart-cf6ba0ac-1fab-4c49-8a36-2111149006e1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985276310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.985276310
Directory	/workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_status.45901341
Short name	T709
Test name
Test status
Simulation time	17742758 ps
CPU time	0.72 seconds
Started	Jul 12 05:51:21 PM PDT 24
Finished	Jul 12 05:51:23 PM PDT 24
Peak memory	199780 kb
Host	smart-b359720e-886d-4998-88af-59c882ab03b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45901341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.45901341
Directory	/workspace/41.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/41.clkmgr_div_intersig_mubi.2456175027
Short name	T159
Test name
Test status
Simulation time	146604016 ps
CPU time	1.18 seconds
Started	Jul 12 05:51:24 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200392 kb
Host	smart-b8124093-4e47-4e5d-bc1d-3bf1a4e3cfd9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456175027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.2456175027
Directory	/workspace/41.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_extclk.2001231942
Short name	T151
Test name
Test status
Simulation time	92199356 ps
CPU time	1.17 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:34 PM PDT 24
Peak memory	200412 kb
Host	smart-47d28ca1-ad9c-47e8-b99e-1b3bbbaf27d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001231942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.2001231942
Directory	/workspace/41.clkmgr_extclk/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency.1990732791
Short name	T800
Test name
Test status
Simulation time	1880726277 ps
CPU time	10.1 seconds
Started	Jul 12 05:51:20 PM PDT 24
Finished	Jul 12 05:51:31 PM PDT 24
Peak memory	200720 kb
Host	smart-997d29b0-a190-41a7-b202-f04f67ec1698
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990732791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1990732791
Directory	/workspace/41.clkmgr_frequency/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency_timeout.949231296
Short name	T469
Test name
Test status
Simulation time	2181237454 ps
CPU time	15.11 seconds
Started	Jul 12 05:51:19 PM PDT 24
Finished	Jul 12 05:51:36 PM PDT 24
Peak memory	200816 kb
Host	smart-b2752aee-1eb2-4b74-8142-3db04e4944c4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949231296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti meout.949231296
Directory	/workspace/41.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/41.clkmgr_idle_intersig_mubi.3436300194
Short name	T681
Test name
Test status
Simulation time	171408379 ps
CPU time	1.36 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:27 PM PDT 24
Peak memory	200564 kb
Host	smart-ca44904e-8252-42d1-bb56-93475bb023e1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436300194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.3436300194
Directory	/workspace/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.1259382616
Short name	T803
Test name
Test status
Simulation time	22688626 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:31 PM PDT 24
Finished	Jul 12 05:51:33 PM PDT 24
Peak memory	200412 kb
Host	smart-fa01c814-ccf1-4627-aab8-c42f0a56f84f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259382616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_clk_byp_req_intersig_mubi.1259382616
Directory	/workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.1833071506
Short name	T671
Test name
Test status
Simulation time	25558787 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	200580 kb
Host	smart-913c94dc-7a9b-4cab-8140-b1e569862f06
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833071506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_ctrl_intersig_mubi.1833071506
Directory	/workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_peri.2758702972
Short name	T737
Test name
Test status
Simulation time	33339140 ps
CPU time	0.71 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:14 PM PDT 24
Peak memory	200252 kb
Host	smart-d05fbf8e-aaf6-4025-b439-1e60331c4f1a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758702972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2758702972
Directory	/workspace/41.clkmgr_peri/latest

Test location	/workspace/coverage/default/41.clkmgr_regwen.255080271
Short name	T663
Test name
Test status
Simulation time	1367857761 ps
CPU time	7.93 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200660 kb
Host	smart-baa2e084-b9c0-4ec4-b082-e18842141830
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255080271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.255080271
Directory	/workspace/41.clkmgr_regwen/latest

Test location	/workspace/coverage/default/41.clkmgr_smoke.2282102573
Short name	T608
Test name
Test status
Simulation time	73702250 ps
CPU time	0.99 seconds
Started	Jul 12 05:51:10 PM PDT 24
Finished	Jul 12 05:51:12 PM PDT 24
Peak memory	200536 kb
Host	smart-1a740675-d36e-4fe1-9f4e-4b689c3ec817
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282102573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2282102573
Directory	/workspace/41.clkmgr_smoke/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all.395379485
Short name	T613
Test name
Test status
Simulation time	116931405 ps
CPU time	1.19 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200584 kb
Host	smart-3a3ce9d8-d211-40c1-a8b3-83c79eaff139
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395379485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.395379485
Directory	/workspace/41.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.2222911607
Short name	T647
Test name
Test status
Simulation time	39769026092 ps
CPU time	247.31 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:55:21 PM PDT 24
Peak memory	217248 kb
Host	smart-22dfdb78-d52e-4801-8aca-e7c6005de68f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2222911607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.2222911607
Directory	/workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.clkmgr_trans.534693411
Short name	T359
Test name
Test status
Simulation time	24414872 ps
CPU time	0.85 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	200788 kb
Host	smart-1773caf3-dba0-49f2-befb-0f19f3e604d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534693411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.534693411
Directory	/workspace/41.clkmgr_trans/latest

Test location	/workspace/coverage/default/42.clkmgr_alert_test.3788269474
Short name	T632
Test name
Test status
Simulation time	19452156 ps
CPU time	0.81 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200704 kb
Host	smart-66b1d13b-8fd3-486c-8cfd-6d3d189cd100
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788269474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.3788269474
Directory	/workspace/42.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1566206979
Short name	T660
Test name
Test status
Simulation time	22901415 ps
CPU time	0.85 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200580 kb
Host	smart-1bdd3df8-30b8-4acc-ab0f-b74f0f21ade7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566206979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.1566206979
Directory	/workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_status.2310342144
Short name	T716
Test name
Test status
Simulation time	26016055 ps
CPU time	0.72 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	199752 kb
Host	smart-1e5f88d0-a826-46ef-920c-00ca87adbe38
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310342144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2310342144
Directory	/workspace/42.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/42.clkmgr_div_intersig_mubi.805158034
Short name	T542
Test name
Test status
Simulation time	21842308 ps
CPU time	0.84 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:34 PM PDT 24
Peak memory	200396 kb
Host	smart-3c859f2f-af69-4865-b2ca-c1d92289a1f5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805158034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.clkmgr_div_intersig_mubi.805158034
Directory	/workspace/42.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_extclk.3362614449
Short name	T16
Test name
Test status
Simulation time	56133712 ps
CPU time	0.85 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200372 kb
Host	smart-6a392160-1049-4b7e-9646-842a7801c306
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362614449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.3362614449
Directory	/workspace/42.clkmgr_extclk/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency.323743992
Short name	T376
Test name
Test status
Simulation time	465564138 ps
CPU time	2.59 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200636 kb
Host	smart-44a3b491-b655-4224-aca4-b7aaa7871ea0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323743992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.323743992
Directory	/workspace/42.clkmgr_frequency/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency_timeout.2928815797
Short name	T339
Test name
Test status
Simulation time	1819305072 ps
CPU time	12.72 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:45 PM PDT 24
Peak memory	200536 kb
Host	smart-2d6e038b-4aa6-4bfb-8c6f-699a3abd4148
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928815797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t imeout.2928815797
Directory	/workspace/42.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/42.clkmgr_idle_intersig_mubi.406367707
Short name	T821
Test name
Test status
Simulation time	20474307 ps
CPU time	0.73 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:24 PM PDT 24
Peak memory	200560 kb
Host	smart-1f7be128-2c4d-4773-8038-fcad59d97819
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406367707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.clkmgr_idle_intersig_mubi.406367707
Directory	/workspace/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.431066736
Short name	T165
Test name
Test status
Simulation time	15285621 ps
CPU time	0.79 seconds
Started	Jul 12 05:51:14 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200576 kb
Host	smart-5e763f70-4010-418b-8749-fde181f6d68d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431066736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.clkmgr_lc_clk_byp_req_intersig_mubi.431066736
Directory	/workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2789259006
Short name	T266
Test name
Test status
Simulation time	30553933 ps
CPU time	0.91 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	200584 kb
Host	smart-0047a8e8-4830-4f73-9708-72d55668daf6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789259006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_ctrl_intersig_mubi.2789259006
Directory	/workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_peri.689227158
Short name	T272
Test name
Test status
Simulation time	52225891 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:14 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200552 kb
Host	smart-6a755843-361c-4cee-8565-406138b4f4fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689227158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.689227158
Directory	/workspace/42.clkmgr_peri/latest

Test location	/workspace/coverage/default/42.clkmgr_regwen.3992643719
Short name	T641
Test name
Test status
Simulation time	1377459576 ps
CPU time	4.97 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:24 PM PDT 24
Peak memory	200668 kb
Host	smart-7b4182a4-3e3d-4daf-a5eb-8aecb77cb30a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992643719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.3992643719
Directory	/workspace/42.clkmgr_regwen/latest

Test location	/workspace/coverage/default/42.clkmgr_smoke.2867081512
Short name	T501
Test name
Test status
Simulation time	18203279 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200484 kb
Host	smart-bd6eb20f-f2e4-493e-82c9-86153b00e8a4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867081512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2867081512
Directory	/workspace/42.clkmgr_smoke/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all.2164173749
Short name	T705
Test name
Test status
Simulation time	111536304 ps
CPU time	1.05 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:18 PM PDT 24
Peak memory	200544 kb
Host	smart-7cd90797-a249-45a4-9f18-b1f6063596d8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164173749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.2164173749
Directory	/workspace/42.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.2629566725
Short name	T372
Test name
Test status
Simulation time	99311481235 ps
CPU time	593.94 seconds
Started	Jul 12 05:51:13 PM PDT 24
Finished	Jul 12 06:01:10 PM PDT 24
Peak memory	209088 kb
Host	smart-35183486-0af2-4d8a-9bd3-8a35d5a6af8f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2629566725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.2629566725
Directory	/workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.clkmgr_trans.2416214557
Short name	T840
Test name
Test status
Simulation time	29625646 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:33 PM PDT 24
Peak memory	200288 kb
Host	smart-2ef93571-d092-48af-83df-22d92fb47a56
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416214557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2416214557
Directory	/workspace/42.clkmgr_trans/latest

Test location	/workspace/coverage/default/43.clkmgr_alert_test.4136163098
Short name	T538
Test name
Test status
Simulation time	19230384 ps
CPU time	0.79 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200620 kb
Host	smart-c014ae7e-f8af-40b5-a9c1-6c0d85dd3dec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136163098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.4136163098
Directory	/workspace/43.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2687239610
Short name	T81
Test name
Test status
Simulation time	16171906 ps
CPU time	0.77 seconds
Started	Jul 12 05:51:21 PM PDT 24
Finished	Jul 12 05:51:23 PM PDT 24
Peak memory	200556 kb
Host	smart-0b288849-8fd9-4bbb-b6c6-d58ab5516646
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687239610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.2687239610
Directory	/workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_status.171369724
Short name	T232
Test name
Test status
Simulation time	21502269 ps
CPU time	0.72 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:15 PM PDT 24
Peak memory	199752 kb
Host	smart-02928a3b-d488-48e1-b463-84b50bb72b2c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171369724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.171369724
Directory	/workspace/43.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/43.clkmgr_div_intersig_mubi.2791796103
Short name	T186
Test name
Test status
Simulation time	45305156 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:19 PM PDT 24
Finished	Jul 12 05:51:22 PM PDT 24
Peak memory	200572 kb
Host	smart-0e900517-e0be-4e95-b05b-2043a74fc3b9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791796103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.2791796103
Directory	/workspace/43.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_extclk.2980958704
Short name	T410
Test name
Test status
Simulation time	36848568 ps
CPU time	0.88 seconds
Started	Jul 12 05:51:30 PM PDT 24
Finished	Jul 12 05:51:31 PM PDT 24
Peak memory	200576 kb
Host	smart-b1b7ee51-1e8b-488e-8f4c-636ecaf48f89
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980958704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2980958704
Directory	/workspace/43.clkmgr_extclk/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency.1450208835
Short name	T418
Test name
Test status
Simulation time	232166770 ps
CPU time	1.59 seconds
Started	Jul 12 05:51:12 PM PDT 24
Finished	Jul 12 05:51:16 PM PDT 24
Peak memory	200628 kb
Host	smart-6404f937-b463-4700-8225-8ef46b304c4b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450208835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1450208835
Directory	/workspace/43.clkmgr_frequency/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency_timeout.472486612
Short name	T334
Test name
Test status
Simulation time	657937785 ps
CPU time	2.98 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200508 kb
Host	smart-a8c97244-9f52-45a1-af4f-b7803ebac359
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472486612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_ti meout.472486612
Directory	/workspace/43.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/43.clkmgr_idle_intersig_mubi.3930986452
Short name	T409
Test name
Test status
Simulation time	33160980 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:15 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200592 kb
Host	smart-bd92bfee-9bad-4db3-a6dc-c533c56e05fd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930986452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.3930986452
Directory	/workspace/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.200557405
Short name	T164
Test name
Test status
Simulation time	25667243 ps
CPU time	0.79 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:24 PM PDT 24
Peak memory	200552 kb
Host	smart-85e481e4-a520-4c4c-a017-3e2590b84150
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200557405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.clkmgr_lc_clk_byp_req_intersig_mubi.200557405
Directory	/workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.728091888
Short name	T187
Test name
Test status
Simulation time	12887363 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200576 kb
Host	smart-7800a950-3e48-47dd-8f28-5cc34c019804
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728091888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.clkmgr_lc_ctrl_intersig_mubi.728091888
Directory	/workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_peri.636427560
Short name	T257
Test name
Test status
Simulation time	13469912 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:11 PM PDT 24
Finished	Jul 12 05:51:13 PM PDT 24
Peak memory	200436 kb
Host	smart-3158e08b-6b76-4aeb-9ada-4fd06490963e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636427560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.636427560
Directory	/workspace/43.clkmgr_peri/latest

Test location	/workspace/coverage/default/43.clkmgr_smoke.2290627405
Short name	T382
Test name
Test status
Simulation time	57518064 ps
CPU time	0.96 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200512 kb
Host	smart-36b4c7d9-0397-4697-95b6-8f583679eefa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290627405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2290627405
Directory	/workspace/43.clkmgr_smoke/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all.1696526263
Short name	T371
Test name
Test status
Simulation time	739713371 ps
CPU time	6.21 seconds
Started	Jul 12 05:51:20 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200688 kb
Host	smart-461860b8-b239-4901-8808-548a51a78096
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696526263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.1696526263
Directory	/workspace/43.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.1827452733
Short name	T63
Test name
Test status
Simulation time	32358140693 ps
CPU time	458.83 seconds
Started	Jul 12 05:51:20 PM PDT 24
Finished	Jul 12 05:59:00 PM PDT 24
Peak memory	217284 kb
Host	smart-fcd340e9-98e9-4329-b1e5-20656c9fe2d9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1827452733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1827452733
Directory	/workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.clkmgr_trans.1104220488
Short name	T758
Test name
Test status
Simulation time	13073647 ps
CPU time	0.71 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:33 PM PDT 24
Peak memory	200272 kb
Host	smart-0a198b86-5cb1-41b7-b913-cbd8f5978b76
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104220488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1104220488
Directory	/workspace/43.clkmgr_trans/latest

Test location	/workspace/coverage/default/44.clkmgr_alert_test.4086358510
Short name	T472
Test name
Test status
Simulation time	15898313 ps
CPU time	0.79 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200696 kb
Host	smart-af438c59-c65a-49e4-86c1-84fff869cc4b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086358510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk mgr_alert_test.4086358510
Directory	/workspace/44.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1918962257
Short name	T22
Test name
Test status
Simulation time	27146384 ps
CPU time	1.01 seconds
Started	Jul 12 05:51:41 PM PDT 24
Finished	Jul 12 05:51:44 PM PDT 24
Peak memory	200584 kb
Host	smart-b67c9cc1-88d0-4280-96e8-7f2214667d13
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918962257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.1918962257
Directory	/workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_status.2196564035
Short name	T381
Test name
Test status
Simulation time	15132061 ps
CPU time	0.71 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	199924 kb
Host	smart-a2c75c11-4966-4103-aa82-9ff1f3e31c2b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196564035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2196564035
Directory	/workspace/44.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/44.clkmgr_div_intersig_mubi.2491491213
Short name	T130
Test name
Test status
Simulation time	42000753 ps
CPU time	0.88 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200568 kb
Host	smart-95b95231-2613-4b31-beb4-303902b60d64
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491491213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.2491491213
Directory	/workspace/44.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_extclk.1051472943
Short name	T655
Test name
Test status
Simulation time	22592519 ps
CPU time	0.84 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200568 kb
Host	smart-741b6145-4e71-4090-bf1b-2344c2199b7d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051472943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.1051472943
Directory	/workspace/44.clkmgr_extclk/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency.488164647
Short name	T103
Test name
Test status
Simulation time	2486364754 ps
CPU time	13.99 seconds
Started	Jul 12 05:51:19 PM PDT 24
Finished	Jul 12 05:51:35 PM PDT 24
Peak memory	201016 kb
Host	smart-ed423707-dc03-4851-b190-4c846440baf6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488164647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.488164647
Directory	/workspace/44.clkmgr_frequency/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency_timeout.1144395536
Short name	T599
Test name
Test status
Simulation time	1937806092 ps
CPU time	11.72 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:39 PM PDT 24
Peak memory	200680 kb
Host	smart-c4e795e5-0d1e-4a52-ba24-c36e24af644d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144395536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.1144395536
Directory	/workspace/44.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.836271695
Short name	T421
Test name
Test status
Simulation time	40896564 ps
CPU time	0.95 seconds
Started	Jul 12 05:51:39 PM PDT 24
Finished	Jul 12 05:51:42 PM PDT 24
Peak memory	200572 kb
Host	smart-63863c36-e9f6-4a29-863f-8eb367e94ec1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836271695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.clkmgr_idle_intersig_mubi.836271695
Directory	/workspace/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1544740189
Short name	T648
Test name
Test status
Simulation time	21993899 ps
CPU time	0.84 seconds
Started	Jul 12 05:51:20 PM PDT 24
Finished	Jul 12 05:51:22 PM PDT 24
Peak memory	200572 kb
Host	smart-619a375c-5c71-458c-a6fc-063f46c83c7d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544740189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1544740189
Directory	/workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2374838571
Short name	T281
Test name
Test status
Simulation time	51432282 ps
CPU time	0.82 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200572 kb
Host	smart-66978bd1-7d44-4a80-b988-f5fb4765d69e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374838571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_ctrl_intersig_mubi.2374838571
Directory	/workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_peri.3619624141
Short name	T321
Test name
Test status
Simulation time	14737247 ps
CPU time	0.74 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	200452 kb
Host	smart-a0cb6ded-ee29-445f-b843-048139cadaba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619624141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3619624141
Directory	/workspace/44.clkmgr_peri/latest

Test location	/workspace/coverage/default/44.clkmgr_regwen.1567183477
Short name	T27
Test name
Test status
Simulation time	658788633 ps
CPU time	3.84 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200656 kb
Host	smart-ef827b97-d0b0-4701-b9ec-749151897094
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567183477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1567183477
Directory	/workspace/44.clkmgr_regwen/latest

Test location	/workspace/coverage/default/44.clkmgr_smoke.3752583257
Short name	T666
Test name
Test status
Simulation time	16671866 ps
CPU time	0.82 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200420 kb
Host	smart-00439570-99fa-4a2f-be5d-c4a55c864c0a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752583257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3752583257
Directory	/workspace/44.clkmgr_smoke/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all.2056734751
Short name	T207
Test name
Test status
Simulation time	5540993931 ps
CPU time	38.66 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:52:05 PM PDT 24
Peak memory	200760 kb
Host	smart-224ea192-3d98-45b9-a569-a88a77e48bcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056734751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.2056734751
Directory	/workspace/44.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.1418792342
Short name	T729
Test name
Test status
Simulation time	36411337828 ps
CPU time	549.57 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 06:00:37 PM PDT 24
Peak memory	217352 kb
Host	smart-9e37c793-1c6f-467f-903a-edf16da9bcb9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1418792342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.1418792342
Directory	/workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.clkmgr_trans.2144342342
Short name	T211
Test name
Test status
Simulation time	30048296 ps
CPU time	0.81 seconds
Started	Jul 12 05:51:21 PM PDT 24
Finished	Jul 12 05:51:23 PM PDT 24
Peak memory	200572 kb
Host	smart-c2ab4a60-d274-4ebe-bad9-8cd2525b39ff
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144342342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.2144342342
Directory	/workspace/44.clkmgr_trans/latest

Test location	/workspace/coverage/default/45.clkmgr_alert_test.282788886
Short name	T305
Test name
Test status
Simulation time	29531802 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:33 PM PDT 24
Finished	Jul 12 05:51:35 PM PDT 24
Peak memory	200700 kb
Host	smart-93ffd3ce-08f6-432e-8069-9778a7b769d0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282788886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkm gr_alert_test.282788886
Directory	/workspace/45.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2489451126
Short name	T322
Test name
Test status
Simulation time	22384580 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200796 kb
Host	smart-c2e124c4-c924-491d-be4b-60c73f30fbd9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489451126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.2489451126
Directory	/workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_status.1496321140
Short name	T592
Test name
Test status
Simulation time	45727052 ps
CPU time	0.78 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:20 PM PDT 24
Peak memory	199752 kb
Host	smart-2377693a-e9d5-46f7-9027-63ded46df1a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496321140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1496321140
Directory	/workspace/45.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/45.clkmgr_div_intersig_mubi.27046610
Short name	T212
Test name
Test status
Simulation time	65284865 ps
CPU time	0.95 seconds
Started	Jul 12 05:51:16 PM PDT 24
Finished	Jul 12 05:51:19 PM PDT 24
Peak memory	200548 kb
Host	smart-79f72dd4-0627-4769-b58e-a9c797315e26
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27046610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .clkmgr_div_intersig_mubi.27046610
Directory	/workspace/45.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_extclk.2736636301
Short name	T185
Test name
Test status
Simulation time	27491181 ps
CPU time	0.88 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200548 kb
Host	smart-433dbecd-24dc-4723-b548-0fd81967d35b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736636301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2736636301
Directory	/workspace/45.clkmgr_extclk/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency.813015322
Short name	T560
Test name
Test status
Simulation time	2368750830 ps
CPU time	13.01 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:36 PM PDT 24
Peak memory	200740 kb
Host	smart-ab17b6ce-bf36-4016-aeab-86e16ae95977
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813015322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.813015322
Directory	/workspace/45.clkmgr_frequency/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency_timeout.1108381269
Short name	T28
Test name
Test status
Simulation time	2442975448 ps
CPU time	9.51 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:28 PM PDT 24
Peak memory	200828 kb
Host	smart-0fb4cf7f-db9e-4af7-bdc0-f6da65263945
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108381269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t imeout.1108381269
Directory	/workspace/45.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_idle_intersig_mubi.1862301664
Short name	T192
Test name
Test status
Simulation time	25613016 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:24 PM PDT 24
Peak memory	200576 kb
Host	smart-bb045d71-9f1f-4003-b623-763db45ae2da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862301664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.1862301664
Directory	/workspace/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.190626339
Short name	T317
Test name
Test status
Simulation time	25593033 ps
CPU time	0.93 seconds
Started	Jul 12 05:51:19 PM PDT 24
Finished	Jul 12 05:51:22 PM PDT 24
Peak memory	200548 kb
Host	smart-86dc845a-58a6-4fdf-a6a9-f24e566cb5ce
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190626339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.clkmgr_lc_clk_byp_req_intersig_mubi.190626339
Directory	/workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1668510521
Short name	T520
Test name
Test status
Simulation time	39640495 ps
CPU time	0.9 seconds
Started	Jul 12 05:51:27 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200564 kb
Host	smart-8f794c5b-ad0e-4ca7-92a9-d1afcd4d9c3b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668510521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_ctrl_intersig_mubi.1668510521
Directory	/workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_peri.4217119863
Short name	T430
Test name
Test status
Simulation time	30269911 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200472 kb
Host	smart-7c510f0a-a7f0-4d76-836b-96fe8c373507
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217119863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.4217119863
Directory	/workspace/45.clkmgr_peri/latest

Test location	/workspace/coverage/default/45.clkmgr_regwen.2592040838
Short name	T166
Test name
Test status
Simulation time	702086631 ps
CPU time	3 seconds
Started	Jul 12 05:51:17 PM PDT 24
Finished	Jul 12 05:51:22 PM PDT 24
Peak memory	200680 kb
Host	smart-31a1a44a-23eb-4b10-8f54-002d2c97a2e7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592040838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2592040838
Directory	/workspace/45.clkmgr_regwen/latest

Test location	/workspace/coverage/default/45.clkmgr_smoke.3837607565
Short name	T129
Test name
Test status
Simulation time	40325855 ps
CPU time	0.92 seconds
Started	Jul 12 05:51:27 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200748 kb
Host	smart-819aa63c-9d52-4525-86f9-5ce3235b4ffa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837607565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3837607565
Directory	/workspace/45.clkmgr_smoke/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all.1220162850
Short name	T3
Test name
Test status
Simulation time	681602867 ps
CPU time	3.55 seconds
Started	Jul 12 05:51:27 PM PDT 24
Finished	Jul 12 05:51:31 PM PDT 24
Peak memory	200660 kb
Host	smart-330f4bfe-6e14-47b3-b323-9c876fc3c9b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220162850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.1220162850
Directory	/workspace/45.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.2964176393
Short name	T638
Test name
Test status
Simulation time	29504571450 ps
CPU time	449.5 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:58:56 PM PDT 24
Peak memory	209116 kb
Host	smart-f43eed8e-f54a-4437-ad58-8991b57302d7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2964176393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.2964176393
Directory	/workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.clkmgr_trans.1941767964
Short name	T539
Test name
Test status
Simulation time	140230858 ps
CPU time	1.11 seconds
Started	Jul 12 05:51:20 PM PDT 24
Finished	Jul 12 05:51:22 PM PDT 24
Peak memory	200568 kb
Host	smart-c98cb05c-0386-4a91-87cd-ab6771a9cf93
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941767964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1941767964
Directory	/workspace/45.clkmgr_trans/latest

Test location	/workspace/coverage/default/46.clkmgr_alert_test.3011960978
Short name	T178
Test name
Test status
Simulation time	79987255 ps
CPU time	0.95 seconds
Started	Jul 12 05:51:31 PM PDT 24
Finished	Jul 12 05:51:33 PM PDT 24
Peak memory	200712 kb
Host	smart-da063067-45e6-4a9d-adaa-428c491a0ba6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011960978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk mgr_alert_test.3011960978
Directory	/workspace/46.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1298839770
Short name	T747
Test name
Test status
Simulation time	336521557 ps
CPU time	1.88 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:29 PM PDT 24
Peak memory	200588 kb
Host	smart-bc8ae34a-e4a7-40ee-8a1c-1bb3f93fcf99
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298839770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.1298839770
Directory	/workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_status.3643885790
Short name	T380
Test name
Test status
Simulation time	18501905 ps
CPU time	0.72 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200452 kb
Host	smart-8190feeb-45a9-4890-83aa-05120b660ee3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643885790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3643885790
Directory	/workspace/46.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/46.clkmgr_div_intersig_mubi.2489380196
Short name	T780
Test name
Test status
Simulation time	49979201 ps
CPU time	0.91 seconds
Started	Jul 12 05:51:28 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200580 kb
Host	smart-2e89c5de-f421-4110-97e4-8b957db73929
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489380196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.2489380196
Directory	/workspace/46.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_extclk.68739397
Short name	T504
Test name
Test status
Simulation time	32690863 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:24 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200520 kb
Host	smart-6b40e53b-a448-4857-a7c0-c5537ac6817c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68739397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.68739397
Directory	/workspace/46.clkmgr_extclk/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency.669023471
Short name	T540
Test name
Test status
Simulation time	1044724067 ps
CPU time	6.4 seconds
Started	Jul 12 05:51:30 PM PDT 24
Finished	Jul 12 05:51:37 PM PDT 24
Peak memory	200628 kb
Host	smart-2e50a162-23d2-49f3-959f-75741c1c7449
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669023471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.669023471
Directory	/workspace/46.clkmgr_frequency/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency_timeout.1306380643
Short name	T600
Test name
Test status
Simulation time	2086193247 ps
CPU time	8.65 seconds
Started	Jul 12 05:51:26 PM PDT 24
Finished	Jul 12 05:51:36 PM PDT 24
Peak memory	200816 kb
Host	smart-39f98c8a-1974-418c-a3be-af38aa9a56fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306380643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t imeout.1306380643
Directory	/workspace/46.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1768153342
Short name	T511
Test name
Test status
Simulation time	33628145 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:34 PM PDT 24
Finished	Jul 12 05:51:37 PM PDT 24
Peak memory	200568 kb
Host	smart-13c04e49-3668-4afb-86d6-eb450fe93ec0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768153342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.1768153342
Directory	/workspace/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3491139973
Short name	T838
Test name
Test status
Simulation time	114050540 ps
CPU time	1.06 seconds
Started	Jul 12 05:51:30 PM PDT 24
Finished	Jul 12 05:51:32 PM PDT 24
Peak memory	200556 kb
Host	smart-0359a1c7-e761-4bd6-9f6d-756784e0eb93
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491139973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.3491139973
Directory	/workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.1532558043
Short name	T828
Test name
Test status
Simulation time	162061954 ps
CPU time	1.3 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200572 kb
Host	smart-82f8b68f-945c-49a9-adc3-6fb8921f195d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532558043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_ctrl_intersig_mubi.1532558043
Directory	/workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_peri.2983451822
Short name	T566
Test name
Test status
Simulation time	13604059 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:22 PM PDT 24
Finished	Jul 12 05:51:24 PM PDT 24
Peak memory	200508 kb
Host	smart-5d45b81e-ba82-454f-8625-54945fee15c1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983451822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.2983451822
Directory	/workspace/46.clkmgr_peri/latest

Test location	/workspace/coverage/default/46.clkmgr_regwen.541583237
Short name	T841
Test name
Test status
Simulation time	1229347457 ps
CPU time	4.82 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:31 PM PDT 24
Peak memory	200656 kb
Host	smart-e03f3d0f-6e03-43e0-8626-aea293e64823
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541583237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.541583237
Directory	/workspace/46.clkmgr_regwen/latest

Test location	/workspace/coverage/default/46.clkmgr_smoke.1942825632
Short name	T389
Test name
Test status
Simulation time	24865807 ps
CPU time	0.87 seconds
Started	Jul 12 05:51:23 PM PDT 24
Finished	Jul 12 05:51:25 PM PDT 24
Peak memory	200496 kb
Host	smart-db33af05-d9b0-4a04-8c8e-c2633daa1bd5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942825632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.1942825632
Directory	/workspace/46.clkmgr_smoke/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all.1184027320
Short name	T25
Test name
Test status
Simulation time	10396110119 ps
CPU time	73.83 seconds
Started	Jul 12 05:51:43 PM PDT 24
Finished	Jul 12 05:53:00 PM PDT 24
Peak memory	200852 kb
Host	smart-1fe54f4d-0ccc-48b9-9754-6a65f4f6016a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184027320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1184027320
Directory	/workspace/46.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.3177259476
Short name	T691
Test name
Test status
Simulation time	39269924990 ps
CPU time	357.16 seconds
Started	Jul 12 05:51:34 PM PDT 24
Finished	Jul 12 05:57:33 PM PDT 24
Peak memory	209152 kb
Host	smart-e0bada1f-e7a6-4584-8d69-f298674c6938
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3177259476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.3177259476
Directory	/workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.clkmgr_trans.2156493015
Short name	T459
Test name
Test status
Simulation time	105691244 ps
CPU time	1.14 seconds
Started	Jul 12 05:51:24 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200504 kb
Host	smart-4c138ad1-2f87-4c5a-9c9f-7edd8667c296
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156493015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2156493015
Directory	/workspace/46.clkmgr_trans/latest

Test location	/workspace/coverage/default/47.clkmgr_alert_test.2709738778
Short name	T439
Test name
Test status
Simulation time	15078576 ps
CPU time	0.81 seconds
Started	Jul 12 05:51:30 PM PDT 24
Finished	Jul 12 05:51:32 PM PDT 24
Peak memory	200700 kb
Host	smart-ded3ad3c-1f6c-4d2e-8589-d07854fa7feb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709738778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk mgr_alert_test.2709738778
Directory	/workspace/47.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2528475593
Short name	T78
Test name
Test status
Simulation time	67814449 ps
CPU time	0.99 seconds
Started	Jul 12 05:51:45 PM PDT 24
Finished	Jul 12 05:51:48 PM PDT 24
Peak memory	200588 kb
Host	smart-5916ce06-57d2-46da-81e0-21b90779078a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528475593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.2528475593
Directory	/workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_status.1717872318
Short name	T478
Test name
Test status
Simulation time	13698550 ps
CPU time	0.69 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200404 kb
Host	smart-a5a36bf4-06a1-4331-b482-e6b0cbe590fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717872318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1717872318
Directory	/workspace/47.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/47.clkmgr_div_intersig_mubi.2501627741
Short name	T598
Test name
Test status
Simulation time	47019819 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:42 PM PDT 24
Finished	Jul 12 05:51:45 PM PDT 24
Peak memory	200576 kb
Host	smart-ae707db3-22fc-45ec-a307-136359707212
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501627741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.2501627741
Directory	/workspace/47.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_extclk.1891809292
Short name	T247
Test name
Test status
Simulation time	21941874 ps
CPU time	0.82 seconds
Started	Jul 12 05:51:34 PM PDT 24
Finished	Jul 12 05:51:37 PM PDT 24
Peak memory	200560 kb
Host	smart-f9006d78-0037-4ae7-9239-cd244a4c0c9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891809292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1891809292
Directory	/workspace/47.clkmgr_extclk/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency.1284458399
Short name	T108
Test name
Test status
Simulation time	2358499791 ps
CPU time	17.03 seconds
Started	Jul 12 05:51:30 PM PDT 24
Finished	Jul 12 05:51:48 PM PDT 24
Peak memory	200788 kb
Host	smart-aa66257c-cc3c-48c6-9714-cebb3fdaacc9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284458399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1284458399
Directory	/workspace/47.clkmgr_frequency/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency_timeout.2820868538
Short name	T329
Test name
Test status
Simulation time	2153633652 ps
CPU time	8.51 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:35 PM PDT 24
Peak memory	200900 kb
Host	smart-32a064ac-eda9-4782-9812-019bd34396ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820868538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t imeout.2820868538
Directory	/workspace/47.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3942734824
Short name	T4
Test name
Test status
Simulation time	29909692 ps
CPU time	0.94 seconds
Started	Jul 12 05:51:28 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200596 kb
Host	smart-d0fc78a6-ea35-4e86-9282-af166269b80d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942734824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.3942734824
Directory	/workspace/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3665553150
Short name	T427
Test name
Test status
Simulation time	23885141 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:34 PM PDT 24
Finished	Jul 12 05:51:37 PM PDT 24
Peak memory	200700 kb
Host	smart-bf332331-918b-40ee-bd71-db8f2aedc355
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665553150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3665553150
Directory	/workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1956368314
Short name	T445
Test name
Test status
Simulation time	47570022 ps
CPU time	0.83 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:34 PM PDT 24
Peak memory	200548 kb
Host	smart-47e15067-cf34-410e-9b33-568d3e0ac093
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956368314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_ctrl_intersig_mubi.1956368314
Directory	/workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_peri.1251726116
Short name	T522
Test name
Test status
Simulation time	15573139 ps
CPU time	0.74 seconds
Started	Jul 12 05:51:33 PM PDT 24
Finished	Jul 12 05:51:35 PM PDT 24
Peak memory	200452 kb
Host	smart-e89da29b-87bb-4d9f-bc42-502495e0b950
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251726116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.1251726116
Directory	/workspace/47.clkmgr_peri/latest

Test location	/workspace/coverage/default/47.clkmgr_regwen.2527545331
Short name	T134
Test name
Test status
Simulation time	1718543578 ps
CPU time	6.02 seconds
Started	Jul 12 05:51:38 PM PDT 24
Finished	Jul 12 05:51:45 PM PDT 24
Peak memory	200652 kb
Host	smart-48405816-9fee-42b4-a965-661de27c50bc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527545331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2527545331
Directory	/workspace/47.clkmgr_regwen/latest

Test location	/workspace/coverage/default/47.clkmgr_smoke.2909692453
Short name	T402
Test name
Test status
Simulation time	15680046 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:41 PM PDT 24
Finished	Jul 12 05:51:44 PM PDT 24
Peak memory	200504 kb
Host	smart-852b8e54-2c9a-42c5-9a65-ae1f786c3668
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909692453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2909692453
Directory	/workspace/47.clkmgr_smoke/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all.246091251
Short name	T126
Test name
Test status
Simulation time	4432765659 ps
CPU time	35.5 seconds
Started	Jul 12 05:51:36 PM PDT 24
Finished	Jul 12 05:52:13 PM PDT 24
Peak memory	200912 kb
Host	smart-fb600f05-72cf-4950-8126-8ac092d061ee
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246091251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.246091251
Directory	/workspace/47.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.243788833
Short name	T718
Test name
Test status
Simulation time	33299162969 ps
CPU time	608.39 seconds
Started	Jul 12 05:51:35 PM PDT 24
Finished	Jul 12 06:01:45 PM PDT 24
Peak memory	209032 kb
Host	smart-9adbe277-51da-49ad-a985-1e7f220e30d5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=243788833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.243788833
Directory	/workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.clkmgr_trans.3664851644
Short name	T255
Test name
Test status
Simulation time	613667199 ps
CPU time	2.77 seconds
Started	Jul 12 05:51:27 PM PDT 24
Finished	Jul 12 05:51:31 PM PDT 24
Peak memory	200520 kb
Host	smart-a7eed91b-adc7-42ae-9e73-4f34c9b98bbe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664851644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3664851644
Directory	/workspace/47.clkmgr_trans/latest

Test location	/workspace/coverage/default/48.clkmgr_alert_test.1918548278
Short name	T384
Test name
Test status
Simulation time	16201919 ps
CPU time	0.79 seconds
Started	Jul 12 05:51:33 PM PDT 24
Finished	Jul 12 05:51:35 PM PDT 24
Peak memory	200712 kb
Host	smart-4e66a04d-5e91-44ff-8411-99f8de68a36a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918548278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk mgr_alert_test.1918548278
Directory	/workspace/48.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.387684848
Short name	T245
Test name
Test status
Simulation time	20217064 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:28 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200804 kb
Host	smart-8df8955e-6cf3-4741-98e9-e25af7a9ac08
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387684848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.387684848
Directory	/workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_status.4150247654
Short name	T685
Test name
Test status
Simulation time	16992358 ps
CPU time	0.74 seconds
Started	Jul 12 05:51:46 PM PDT 24
Finished	Jul 12 05:51:48 PM PDT 24
Peak memory	199748 kb
Host	smart-1c23b5aa-baa0-4269-94e5-70fa579e0630
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150247654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.4150247654
Directory	/workspace/48.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/48.clkmgr_div_intersig_mubi.2315424134
Short name	T774
Test name
Test status
Simulation time	98789931 ps
CPU time	1.18 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:35 PM PDT 24
Peak memory	200568 kb
Host	smart-14136f7d-e736-4e7d-9f86-f39d4f14cdd7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315424134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.2315424134
Directory	/workspace/48.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_extclk.3405853314
Short name	T557
Test name
Test status
Simulation time	25571495 ps
CPU time	1.02 seconds
Started	Jul 12 05:51:41 PM PDT 24
Finished	Jul 12 05:51:44 PM PDT 24
Peak memory	200564 kb
Host	smart-81fb9de8-7f1c-45de-8bc8-698da08687c1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405853314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.3405853314
Directory	/workspace/48.clkmgr_extclk/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency.503274496
Short name	T313
Test name
Test status
Simulation time	1762361322 ps
CPU time	14.04 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:47 PM PDT 24
Peak memory	200584 kb
Host	smart-c8ae3fb9-83f5-46ac-86c3-f169509eb1e4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503274496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.503274496
Directory	/workspace/48.clkmgr_frequency/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency_timeout.4217909291
Short name	T241
Test name
Test status
Simulation time	1242650019 ps
CPU time	4.38 seconds
Started	Jul 12 05:51:33 PM PDT 24
Finished	Jul 12 05:51:40 PM PDT 24
Peak memory	200656 kb
Host	smart-b08bd041-5a11-4dc8-bbc6-22fd82d0c28c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217909291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.4217909291
Directory	/workspace/48.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1629637305
Short name	T273
Test name
Test status
Simulation time	60999357 ps
CPU time	1.11 seconds
Started	Jul 12 05:51:35 PM PDT 24
Finished	Jul 12 05:51:38 PM PDT 24
Peak memory	200580 kb
Host	smart-20a562c6-9421-4a7e-9eb1-5e2693f1da0c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629637305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.1629637305
Directory	/workspace/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.985613282
Short name	T65
Test name
Test status
Simulation time	18964109 ps
CPU time	0.8 seconds
Started	Jul 12 05:51:42 PM PDT 24
Finished	Jul 12 05:51:49 PM PDT 24
Peak memory	200552 kb
Host	smart-0c252672-3438-4f6f-9291-4b5a0e09b919
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985613282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.clkmgr_lc_clk_byp_req_intersig_mubi.985613282
Directory	/workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1686568223
Short name	T833
Test name
Test status
Simulation time	27975417 ps
CPU time	0.9 seconds
Started	Jul 12 05:51:42 PM PDT 24
Finished	Jul 12 05:51:45 PM PDT 24
Peak memory	200564 kb
Host	smart-b7860f9b-0102-4466-95c3-d6b98f8b56c7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686568223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_ctrl_intersig_mubi.1686568223
Directory	/workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_peri.2577181688
Short name	T534
Test name
Test status
Simulation time	28740003 ps
CPU time	0.75 seconds
Started	Jul 12 05:51:29 PM PDT 24
Finished	Jul 12 05:51:31 PM PDT 24
Peak memory	200448 kb
Host	smart-8deb7546-4859-474f-876f-457fc04d5a10
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577181688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2577181688
Directory	/workspace/48.clkmgr_peri/latest

Test location	/workspace/coverage/default/48.clkmgr_regwen.135824426
Short name	T767
Test name
Test status
Simulation time	204000476 ps
CPU time	1.62 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:35 PM PDT 24
Peak memory	200528 kb
Host	smart-f05fa52c-edc9-42d2-8d5c-f7ce80da2206
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135824426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.135824426
Directory	/workspace/48.clkmgr_regwen/latest

Test location	/workspace/coverage/default/48.clkmgr_smoke.1039898587
Short name	T759
Test name
Test status
Simulation time	40599451 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:25 PM PDT 24
Finished	Jul 12 05:51:26 PM PDT 24
Peak memory	200480 kb
Host	smart-5125e851-9652-4ac9-8690-d2b6c7bf6805
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039898587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.1039898587
Directory	/workspace/48.clkmgr_smoke/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all.2074856898
Short name	T637
Test name
Test status
Simulation time	5303438075 ps
CPU time	40.63 seconds
Started	Jul 12 05:51:44 PM PDT 24
Finished	Jul 12 05:52:27 PM PDT 24
Peak memory	200892 kb
Host	smart-60a91ec4-c422-43bc-8a2d-6780dbd05071
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074856898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.2074856898
Directory	/workspace/48.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.3716032919
Short name	T62
Test name
Test status
Simulation time	35123428986 ps
CPU time	536.73 seconds
Started	Jul 12 05:51:38 PM PDT 24
Finished	Jul 12 06:00:36 PM PDT 24
Peak memory	209380 kb
Host	smart-633fa14d-d744-4f2c-820c-195b7b2d2144
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3716032919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.3716032919
Directory	/workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.clkmgr_trans.1429680179
Short name	T204
Test name
Test status
Simulation time	23071853 ps
CPU time	0.89 seconds
Started	Jul 12 05:51:40 PM PDT 24
Finished	Jul 12 05:51:42 PM PDT 24
Peak memory	200588 kb
Host	smart-5cbff489-05df-496d-b4b1-f29b02933ea8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429680179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1429680179
Directory	/workspace/48.clkmgr_trans/latest

Test location	/workspace/coverage/default/49.clkmgr_alert_test.3066193518
Short name	T591
Test name
Test status
Simulation time	120483491 ps
CPU time	1.1 seconds
Started	Jul 12 05:51:37 PM PDT 24
Finished	Jul 12 05:51:39 PM PDT 24
Peak memory	200700 kb
Host	smart-ce85071c-96a2-4181-adc9-079a04a61ad0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066193518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk mgr_alert_test.3066193518
Directory	/workspace/49.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.294100367
Short name	T624
Test name
Test status
Simulation time	33983086 ps
CPU time	0.85 seconds
Started	Jul 12 05:51:28 PM PDT 24
Finished	Jul 12 05:51:30 PM PDT 24
Peak memory	200580 kb
Host	smart-fb701188-ba69-4e15-a9ae-a262754a72a8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294100367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.294100367
Directory	/workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_status.2975567232
Short name	T820
Test name
Test status
Simulation time	16665637 ps
CPU time	0.73 seconds
Started	Jul 12 05:51:32 PM PDT 24
Finished	Jul 12 05:51:34 PM PDT 24
Peak memory	200432 kb
Host	smart-1f857345-799f-4a36-b31a-5e4fd46d1dc0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975567232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2975567232
Directory	/workspace/49.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_div_intersig_mubi.2080752111
Short name	T392
Test name
Test status
Simulation time	20373930 ps
CPU time	0.79 seconds
Started	Jul 12 05:51:34 PM PDT 24
Finished	Jul 12 05:51:36 PM PDT 24
Peak memory	200568 kb
Host	smart-1e4aa4e1-5128-4fad-b27d-b043aa4c2937
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080752111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.2080752111
Directory	/workspace/49.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_extclk.3457203050
Short name	T193
Test name
Test status
Simulation time	22487357 ps
CPU time	0.86 seconds
Started	Jul 12 05:51:39 PM PDT 24
Finished	Jul 12 05:51:41 PM PDT 24
Peak memory	200556 kb
Host	smart-0dc02228-0fc0-4f52-87c3-cd1868b72a3a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457203050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3457203050
Directory	/workspace/49.clkmgr_extclk/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency.1071790460
Short name	T405
Test name
Test status
Simulation time	1832057689 ps
CPU time	7.77 seconds
Started	Jul 12 05:51:27 PM PDT 24
Finished	Jul 12 05:51:36 PM PDT 24
Peak memory	200784 kb
Host	smart-8979242f-ffc8-4149-a6e3-d8c81e4272e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071790460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.1071790460
Directory	/workspace/49.clkmgr_frequency/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency_timeout.1595827045
Short name	T274
Test name
Test status
Simulation time	1468704511 ps
CPU time	6.98 seconds
Started	Jul 12 05:51:41 PM PDT 24
Finished	Jul 12 05:51:50 PM PDT 24
Peak memory	200676 kb
Host	smart-b8e760e7-588b-4727-992b-eb1450d0ad51
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595827045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t imeout.1595827045
Directory	/workspace/49.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.4172386204
Short name	T309
Test name
Test status
Simulation time	41656099 ps
CPU time	0.9 seconds
Started	Jul 12 05:51:38 PM PDT 24
Finished	Jul 12 05:51:41 PM PDT 24
Peak memory	200584 kb
Host	smart-969b1933-2127-4907-b123-573fdc1c110c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172386204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.4172386204
Directory	/workspace/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.1102452504
Short name	T550
Test name
Test status
Simulation time	40323984 ps
CPU time	0.82 seconds
Started	Jul 12 05:51:36 PM PDT 24
Finished	Jul 12 05:51:38 PM PDT 24
Peak memory	200572 kb
Host	smart-713ee945-9bc5-468b-9a6d-754af904012b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102452504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_clk_byp_req_intersig_mubi.1102452504
Directory	/workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2033943210
Short name	T739
Test name
Test status
Simulation time	18465015 ps
CPU time	0.77 seconds
Started	Jul 12 05:51:49 PM PDT 24
Finished	Jul 12 05:51:51 PM PDT 24
Peak memory	200544 kb
Host	smart-383d26d6-65d0-4e2d-8b9a-02639f6d92f6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033943210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_ctrl_intersig_mubi.2033943210
Directory	/workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_peri.362519812
Short name	T224
Test name
Test status
Simulation time	16519624 ps
CPU time	0.77 seconds
Started	Jul 12 05:51:48 PM PDT 24
Finished	Jul 12 05:51:50 PM PDT 24
Peak memory	200432 kb
Host	smart-f373ba16-9c93-4c69-861e-9839dfb022bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362519812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.362519812
Directory	/workspace/49.clkmgr_peri/latest

Test location	/workspace/coverage/default/49.clkmgr_regwen.3468268898
Short name	T298
Test name
Test status
Simulation time	536719512 ps
CPU time	2.34 seconds
Started	Jul 12 05:51:35 PM PDT 24
Finished	Jul 12 05:51:39 PM PDT 24
Peak memory	200644 kb
Host	smart-420a7b61-be3c-44c2-9733-34a8863ed421
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468268898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3468268898
Directory	/workspace/49.clkmgr_regwen/latest

Test location	/workspace/coverage/default/49.clkmgr_smoke.1440657048
Short name	T324
Test name
Test status
Simulation time	61289165 ps
CPU time	0.94 seconds
Started	Jul 12 05:51:35 PM PDT 24
Finished	Jul 12 05:51:38 PM PDT 24
Peak memory	200496 kb
Host	smart-9778720e-4790-4295-99c2-afd8e4197981
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440657048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.1440657048
Directory	/workspace/49.clkmgr_smoke/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all.3844915264
Short name	T288
Test name
Test status
Simulation time	400905179 ps
CPU time	4.69 seconds
Started	Jul 12 05:51:43 PM PDT 24
Finished	Jul 12 05:51:50 PM PDT 24
Peak memory	200776 kb
Host	smart-6fb4f983-3aa9-4b7d-a865-623f7e6fff65
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844915264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.3844915264
Directory	/workspace/49.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.291063973
Short name	T848
Test name
Test status
Simulation time	84222007000 ps
CPU time	514.43 seconds
Started	Jul 12 05:51:28 PM PDT 24
Finished	Jul 12 06:00:04 PM PDT 24
Peak memory	216560 kb
Host	smart-49409239-d36c-42b0-8ce1-3eb7724c4cbf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=291063973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.291063973
Directory	/workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_trans.2634092867
Short name	T435
Test name
Test status
Simulation time	95221911 ps
CPU time	1.13 seconds
Started	Jul 12 05:51:55 PM PDT 24
Finished	Jul 12 05:51:57 PM PDT 24
Peak memory	200560 kb
Host	smart-d165598a-7475-477e-bd13-b0f27214c816
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634092867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.2634092867
Directory	/workspace/49.clkmgr_trans/latest

Test location	/workspace/coverage/default/5.clkmgr_alert_test.333731011
Short name	T659
Test name
Test status
Simulation time	21588678 ps
CPU time	0.8 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200696 kb
Host	smart-c300d316-d6c4-4568-8767-6bda31cc1ec1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333731011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmg r_alert_test.333731011
Directory	/workspace/5.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1687129184
Short name	T443
Test name
Test status
Simulation time	42432691 ps
CPU time	0.83 seconds
Started	Jul 12 05:49:42 PM PDT 24
Finished	Jul 12 05:49:45 PM PDT 24
Peak memory	200572 kb
Host	smart-41c2ae6f-e760-47bf-b5ed-d90186c3ad45
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687129184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.1687129184
Directory	/workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_status.2968941790
Short name	T847
Test name
Test status
Simulation time	23671919 ps
CPU time	0.71 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:45 PM PDT 24
Peak memory	199764 kb
Host	smart-b70d143b-5952-4497-8b92-49ed363e9622
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968941790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2968941790
Directory	/workspace/5.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/5.clkmgr_div_intersig_mubi.1007982341
Short name	T292
Test name
Test status
Simulation time	20053368 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200424 kb
Host	smart-a843c4d7-22b7-4b92-b8e2-5aeb3d1057da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007982341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.1007982341
Directory	/workspace/5.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_extclk.440201712
Short name	T195
Test name
Test status
Simulation time	49735951 ps
CPU time	0.84 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:57 PM PDT 24
Peak memory	200516 kb
Host	smart-61b7b3c1-d124-4c5b-b2c7-5376e0e3b59b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440201712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.440201712
Directory	/workspace/5.clkmgr_extclk/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency.2008893626
Short name	T572
Test name
Test status
Simulation time	2135493673 ps
CPU time	12.01 seconds
Started	Jul 12 05:49:41 PM PDT 24
Finished	Jul 12 05:49:55 PM PDT 24
Peak memory	200712 kb
Host	smart-c778b47d-d38a-4ed9-b6b1-0907b1d4ab0b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008893626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2008893626
Directory	/workspace/5.clkmgr_frequency/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency_timeout.2245609737
Short name	T205
Test name
Test status
Simulation time	1575908480 ps
CPU time	11.77 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200688 kb
Host	smart-7cbfb961-1161-483e-9999-bcee9db0acd7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245609737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti meout.2245609737
Directory	/workspace/5.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1529972444
Short name	T336
Test name
Test status
Simulation time	48882195 ps
CPU time	1.01 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200572 kb
Host	smart-29f37aa9-b4f4-4c52-8f2c-d1dcda368343
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529972444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.1529972444
Directory	/workspace/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.671151588
Short name	T333
Test name
Test status
Simulation time	20897345 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:46 PM PDT 24
Finished	Jul 12 05:49:48 PM PDT 24
Peak memory	200596 kb
Host	smart-fbbaff8e-37ae-475e-ad9c-062095caa5e1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671151588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.clkmgr_lc_clk_byp_req_intersig_mubi.671151588
Directory	/workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2140878078
Short name	T252
Test name
Test status
Simulation time	44835782 ps
CPU time	0.88 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200564 kb
Host	smart-f49a1e14-d40e-4787-bfa3-50fa8296146f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140878078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_ctrl_intersig_mubi.2140878078
Directory	/workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_peri.333491883
Short name	T546
Test name
Test status
Simulation time	43841796 ps
CPU time	0.8 seconds
Started	Jul 12 05:49:47 PM PDT 24
Finished	Jul 12 05:49:49 PM PDT 24
Peak memory	200448 kb
Host	smart-1fbf5944-707a-4689-8556-256ca88206ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333491883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.333491883
Directory	/workspace/5.clkmgr_peri/latest

Test location	/workspace/coverage/default/5.clkmgr_regwen.2157806775
Short name	T275
Test name
Test status
Simulation time	1258223931 ps
CPU time	5.37 seconds
Started	Jul 12 05:49:49 PM PDT 24
Finished	Jul 12 05:49:55 PM PDT 24
Peak memory	200672 kb
Host	smart-70f45803-4bc4-49a6-8fef-733404036612
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157806775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2157806775
Directory	/workspace/5.clkmgr_regwen/latest

Test location	/workspace/coverage/default/5.clkmgr_smoke.967876084
Short name	T125
Test name
Test status
Simulation time	25742344 ps
CPU time	0.9 seconds
Started	Jul 12 05:49:44 PM PDT 24
Finished	Jul 12 05:49:47 PM PDT 24
Peak memory	200528 kb
Host	smart-df4ea53d-abd2-475e-a4a5-9e4e87a09826
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967876084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.967876084
Directory	/workspace/5.clkmgr_smoke/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all.1615885499
Short name	T374
Test name
Test status
Simulation time	7923642951 ps
CPU time	30.73 seconds
Started	Jul 12 05:49:50 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	200844 kb
Host	smart-a43b6d01-d2c6-45bc-8d11-302fc54e1668
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615885499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.1615885499
Directory	/workspace/5.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.586210542
Short name	T156
Test name
Test status
Simulation time	40772456334 ps
CPU time	754.87 seconds
Started	Jul 12 05:49:49 PM PDT 24
Finished	Jul 12 06:02:24 PM PDT 24
Peak memory	209168 kb
Host	smart-75ef64e3-f6d8-4697-937d-6dc558860e00
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=586210542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.586210542
Directory	/workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.clkmgr_trans.4066532409
Short name	T702
Test name
Test status
Simulation time	121237247 ps
CPU time	1.26 seconds
Started	Jul 12 05:49:39 PM PDT 24
Finished	Jul 12 05:49:43 PM PDT 24
Peak memory	200592 kb
Host	smart-a162d948-6c60-4d5b-8eb4-09c38afa6d0d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066532409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.4066532409
Directory	/workspace/5.clkmgr_trans/latest

Test location	/workspace/coverage/default/6.clkmgr_alert_test.172413229
Short name	T506
Test name
Test status
Simulation time	26280346 ps
CPU time	0.77 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:57 PM PDT 24
Peak memory	200692 kb
Host	smart-85b53ec4-7a76-4d9f-afd0-16940404da55
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172413229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg r_alert_test.172413229
Directory	/workspace/6.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1877142738
Short name	T586
Test name
Test status
Simulation time	143618049 ps
CPU time	1.2 seconds
Started	Jul 12 05:49:43 PM PDT 24
Finished	Jul 12 05:49:46 PM PDT 24
Peak memory	200564 kb
Host	smart-9ffab02c-652a-4cf8-b18c-f09dc0a84048
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877142738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.1877142738
Directory	/workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_status.1551650667
Short name	T368
Test name
Test status
Simulation time	45111891 ps
CPU time	0.77 seconds
Started	Jul 12 05:49:51 PM PDT 24
Finished	Jul 12 05:49:53 PM PDT 24
Peak memory	199768 kb
Host	smart-48ee5c86-cc88-476f-a9d0-4281bbfac814
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551650667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.1551650667
Directory	/workspace/6.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/6.clkmgr_div_intersig_mubi.1335859473
Short name	T489
Test name
Test status
Simulation time	54235564 ps
CPU time	0.86 seconds
Started	Jul 12 05:49:52 PM PDT 24
Finished	Jul 12 05:49:54 PM PDT 24
Peak memory	200544 kb
Host	smart-a2a10135-9cfa-4f85-b1c5-3ade6af4f707
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335859473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.1335859473
Directory	/workspace/6.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_extclk.1472956075
Short name	T463
Test name
Test status
Simulation time	66627211 ps
CPU time	1.01 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:48 PM PDT 24
Peak memory	200556 kb
Host	smart-a6a50d29-9cc2-46be-b5ac-c7cd0950336d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472956075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1472956075
Directory	/workspace/6.clkmgr_extclk/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency.1486659046
Short name	T373
Test name
Test status
Simulation time	230776685 ps
CPU time	1.62 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:49:56 PM PDT 24
Peak memory	200584 kb
Host	smart-06d601f9-95ed-4f54-ae7d-4f8d273c0621
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486659046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.1486659046
Directory	/workspace/6.clkmgr_frequency/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency_timeout.3678110425
Short name	T791
Test name
Test status
Simulation time	502692399 ps
CPU time	3.92 seconds
Started	Jul 12 05:49:47 PM PDT 24
Finished	Jul 12 05:49:52 PM PDT 24
Peak memory	200708 kb
Host	smart-6cc04d24-deac-48ca-a958-c299c0b44b65
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678110425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti meout.3678110425
Directory	/workspace/6.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1500758360
Short name	T590
Test name
Test status
Simulation time	148329432 ps
CPU time	1.23 seconds
Started	Jul 12 05:49:59 PM PDT 24
Finished	Jul 12 05:50:01 PM PDT 24
Peak memory	200576 kb
Host	smart-66b01cb9-e303-46f5-8166-4443bc1440d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500758360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.1500758360
Directory	/workspace/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3507335968
Short name	T438
Test name
Test status
Simulation time	35465190 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:49 PM PDT 24
Finished	Jul 12 05:49:51 PM PDT 24
Peak memory	200604 kb
Host	smart-1bd56b81-f348-4ee6-b325-ae587f1c39bd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507335968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_clk_byp_req_intersig_mubi.3507335968
Directory	/workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.143311641
Short name	T484
Test name
Test status
Simulation time	46295145 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:57 PM PDT 24
Finished	Jul 12 05:49:59 PM PDT 24
Peak memory	200556 kb
Host	smart-4de6cd7e-7cdf-4fa5-a137-03536a2ee641
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143311641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.clkmgr_lc_ctrl_intersig_mubi.143311641
Directory	/workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_peri.1957762543
Short name	T219
Test name
Test status
Simulation time	16902949 ps
CPU time	0.72 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:49:56 PM PDT 24
Peak memory	200452 kb
Host	smart-b14251c5-49da-4ba6-8b4f-17681b7fe67e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957762543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1957762543
Directory	/workspace/6.clkmgr_peri/latest

Test location	/workspace/coverage/default/6.clkmgr_regwen.2208625433
Short name	T256
Test name
Test status
Simulation time	576708333 ps
CPU time	2.18 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:59 PM PDT 24
Peak memory	200532 kb
Host	smart-713439c7-ea21-44e5-8dc3-45e1488d0460
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208625433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2208625433
Directory	/workspace/6.clkmgr_regwen/latest

Test location	/workspace/coverage/default/6.clkmgr_smoke.3552255362
Short name	T636
Test name
Test status
Simulation time	40982792 ps
CPU time	0.87 seconds
Started	Jul 12 05:49:48 PM PDT 24
Finished	Jul 12 05:49:49 PM PDT 24
Peak memory	200524 kb
Host	smart-2005ba38-9b74-482c-b20c-aeee08a224ff
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552255362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3552255362
Directory	/workspace/6.clkmgr_smoke/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.93112111
Short name	T140
Test name
Test status
Simulation time	133868974369 ps
CPU time	783.67 seconds
Started	Jul 12 05:49:50 PM PDT 24
Finished	Jul 12 06:02:54 PM PDT 24
Peak memory	209188 kb
Host	smart-e1e72c98-09d8-41b0-bcef-f61c4097838a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=93112111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.93112111
Directory	/workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.clkmgr_trans.1794920102
Short name	T558
Test name
Test status
Simulation time	197008411 ps
CPU time	1.52 seconds
Started	Jul 12 05:49:57 PM PDT 24
Finished	Jul 12 05:50:01 PM PDT 24
Peak memory	200580 kb
Host	smart-e420eedf-1dbb-4c6c-9a1f-66eab966e058
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794920102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1794920102
Directory	/workspace/6.clkmgr_trans/latest

Test location	/workspace/coverage/default/7.clkmgr_alert_test.2089131535
Short name	T628
Test name
Test status
Simulation time	36797149 ps
CPU time	0.78 seconds
Started	Jul 12 05:49:57 PM PDT 24
Finished	Jul 12 05:49:59 PM PDT 24
Peak memory	200712 kb
Host	smart-bdf765f6-87e8-47bf-a181-fefdc722aaac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089131535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm gr_alert_test.2089131535
Directory	/workspace/7.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3161428926
Short name	T77
Test name
Test status
Simulation time	14297990 ps
CPU time	0.76 seconds
Started	Jul 12 05:50:01 PM PDT 24
Finished	Jul 12 05:50:03 PM PDT 24
Peak memory	200552 kb
Host	smart-d770986f-6c1e-444e-85c4-b6afde973ae2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161428926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.3161428926
Directory	/workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_status.1821074497
Short name	T400
Test name
Test status
Simulation time	48849825 ps
CPU time	0.81 seconds
Started	Jul 12 05:49:50 PM PDT 24
Finished	Jul 12 05:49:52 PM PDT 24
Peak memory	199680 kb
Host	smart-4d2d7b84-6ef3-4938-af3b-ff5d6c07e8fe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821074497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1821074497
Directory	/workspace/7.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/7.clkmgr_div_intersig_mubi.2887083325
Short name	T680
Test name
Test status
Simulation time	23088541 ps
CPU time	0.85 seconds
Started	Jul 12 05:49:56 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200520 kb
Host	smart-5d41229d-2481-45a3-99d1-f30c97489721
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887083325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.2887083325
Directory	/workspace/7.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_extclk.2094831695
Short name	T268
Test name
Test status
Simulation time	54620200 ps
CPU time	0.97 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:47 PM PDT 24
Peak memory	200552 kb
Host	smart-374eeaf0-d1cf-4881-ab38-d95185a9ce90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094831695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.2094831695
Directory	/workspace/7.clkmgr_extclk/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency.3673456954
Short name	T562
Test name
Test status
Simulation time	1284187880 ps
CPU time	7.97 seconds
Started	Jul 12 05:49:45 PM PDT 24
Finished	Jul 12 05:49:54 PM PDT 24
Peak memory	200648 kb
Host	smart-94472b25-e454-46eb-bb0b-017d412a6f6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673456954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3673456954
Directory	/workspace/7.clkmgr_frequency/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency_timeout.2567288509
Short name	T824
Test name
Test status
Simulation time	1104826915 ps
CPU time	7.5 seconds
Started	Jul 12 05:50:00 PM PDT 24
Finished	Jul 12 05:50:09 PM PDT 24
Peak memory	200616 kb
Host	smart-5f3e7bee-075d-42dc-b948-67b5a68265ce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567288509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti meout.2567288509
Directory	/workspace/7.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3214403575
Short name	T574
Test name
Test status
Simulation time	20680606 ps
CPU time	0.71 seconds
Started	Jul 12 05:50:00 PM PDT 24
Finished	Jul 12 05:50:01 PM PDT 24
Peak memory	200524 kb
Host	smart-58e2490e-97e6-4c2c-a364-b5c0122e0dc4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214403575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.3214403575
Directory	/workspace/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.196748865
Short name	T618
Test name
Test status
Simulation time	17611818 ps
CPU time	0.77 seconds
Started	Jul 12 05:50:11 PM PDT 24
Finished	Jul 12 05:50:13 PM PDT 24
Peak memory	200592 kb
Host	smart-92ae4dd7-27cb-4ae6-bf6d-9bc8cec3cf3f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196748865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.clkmgr_lc_clk_byp_req_intersig_mubi.196748865
Directory	/workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.385238504
Short name	T264
Test name
Test status
Simulation time	19926257 ps
CPU time	0.73 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200560 kb
Host	smart-f3697fa4-f401-47f6-8b66-ec5e867f95be
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385238504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.clkmgr_lc_ctrl_intersig_mubi.385238504
Directory	/workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_peri.907501514
Short name	T462
Test name
Test status
Simulation time	39362789 ps
CPU time	0.82 seconds
Started	Jul 12 05:49:50 PM PDT 24
Finished	Jul 12 05:49:52 PM PDT 24
Peak memory	200400 kb
Host	smart-dc2deca2-9866-484d-8d80-34d0893e09bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907501514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.907501514
Directory	/workspace/7.clkmgr_peri/latest

Test location	/workspace/coverage/default/7.clkmgr_regwen.1055315549
Short name	T497
Test name
Test status
Simulation time	693524059 ps
CPU time	2.82 seconds
Started	Jul 12 05:50:02 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200656 kb
Host	smart-61c60e96-1d1a-4977-b4fe-3b7e65e2ae43
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055315549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1055315549
Directory	/workspace/7.clkmgr_regwen/latest

Test location	/workspace/coverage/default/7.clkmgr_smoke.3350601503
Short name	T752
Test name
Test status
Simulation time	72219946 ps
CPU time	1.06 seconds
Started	Jul 12 05:49:53 PM PDT 24
Finished	Jul 12 05:49:55 PM PDT 24
Peak memory	200468 kb
Host	smart-35184719-681f-4e85-933b-156cef5b4c21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350601503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3350601503
Directory	/workspace/7.clkmgr_smoke/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all.1698392326
Short name	T625
Test name
Test status
Simulation time	4579788890 ps
CPU time	19.64 seconds
Started	Jul 12 05:49:49 PM PDT 24
Finished	Jul 12 05:50:10 PM PDT 24
Peak memory	200828 kb
Host	smart-cbaf747f-0b5c-4244-ae41-8a59d101e3c5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698392326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.1698392326
Directory	/workspace/7.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.348785638
Short name	T849
Test name
Test status
Simulation time	35560717783 ps
CPU time	642.79 seconds
Started	Jul 12 05:50:00 PM PDT 24
Finished	Jul 12 06:00:44 PM PDT 24
Peak memory	209168 kb
Host	smart-f5dc5e1e-758b-4bbb-ba54-82106eb9d7d2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=348785638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.348785638
Directory	/workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.clkmgr_trans.2122290037
Short name	T496
Test name
Test status
Simulation time	48308347 ps
CPU time	1.04 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:49:55 PM PDT 24
Peak memory	200580 kb
Host	smart-1aafc30b-467c-48ce-9c00-446302804b30
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122290037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2122290037
Directory	/workspace/7.clkmgr_trans/latest

Test location	/workspace/coverage/default/8.clkmgr_alert_test.201101403
Short name	T183
Test name
Test status
Simulation time	17376014 ps
CPU time	0.8 seconds
Started	Jul 12 05:49:57 PM PDT 24
Finished	Jul 12 05:49:59 PM PDT 24
Peak memory	200688 kb
Host	smart-e02f87e1-4f45-4103-827c-a19ce95d3f7c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201101403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg r_alert_test.201101403
Directory	/workspace/8.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1242200696
Short name	T704
Test name
Test status
Simulation time	19211279 ps
CPU time	0.87 seconds
Started	Jul 12 05:50:05 PM PDT 24
Finished	Jul 12 05:50:07 PM PDT 24
Peak memory	200604 kb
Host	smart-03d16166-aa9c-4351-9857-dac164c00777
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242200696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.1242200696
Directory	/workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_status.543029606
Short name	T43
Test name
Test status
Simulation time	20561018 ps
CPU time	0.73 seconds
Started	Jul 12 05:50:00 PM PDT 24
Finished	Jul 12 05:50:02 PM PDT 24
Peak memory	200468 kb
Host	smart-2a7fb970-9020-4d72-b1fc-bc39b3675340
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543029606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.543029606
Directory	/workspace/8.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/8.clkmgr_div_intersig_mubi.4183205499
Short name	T662
Test name
Test status
Simulation time	118154786 ps
CPU time	1.14 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200572 kb
Host	smart-e403a4ab-6931-4693-91f8-dbefa20d080d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183205499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.4183205499
Directory	/workspace/8.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_extclk.3483569319
Short name	T733
Test name
Test status
Simulation time	17791330 ps
CPU time	0.78 seconds
Started	Jul 12 05:49:51 PM PDT 24
Finished	Jul 12 05:49:52 PM PDT 24
Peak memory	200560 kb
Host	smart-0ff5b49f-5480-4d55-913b-65db243b7cfa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483569319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3483569319
Directory	/workspace/8.clkmgr_extclk/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency.4184729480
Short name	T391
Test name
Test status
Simulation time	1042572108 ps
CPU time	8.3 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:50:03 PM PDT 24
Peak memory	200632 kb
Host	smart-b74423b5-0c34-4405-b190-15ec65006d79
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184729480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.4184729480
Directory	/workspace/8.clkmgr_frequency/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency_timeout.3368917008
Short name	T344
Test name
Test status
Simulation time	2475034630 ps
CPU time	9.28 seconds
Started	Jul 12 05:50:01 PM PDT 24
Finished	Jul 12 05:50:11 PM PDT 24
Peak memory	200892 kb
Host	smart-885d9381-d775-4b83-a523-7d45365e5cf9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368917008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti meout.3368917008
Directory	/workspace/8.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/8.clkmgr_idle_intersig_mubi.3921407147
Short name	T533
Test name
Test status
Simulation time	22714423 ps
CPU time	0.78 seconds
Started	Jul 12 05:49:53 PM PDT 24
Finished	Jul 12 05:49:55 PM PDT 24
Peak memory	200592 kb
Host	smart-4542d540-48a7-491b-9924-929fae1c552a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921407147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.3921407147
Directory	/workspace/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1613877198
Short name	T688
Test name
Test status
Simulation time	20439877 ps
CPU time	0.84 seconds
Started	Jul 12 05:49:53 PM PDT 24
Finished	Jul 12 05:49:54 PM PDT 24
Peak memory	200452 kb
Host	smart-9941d76d-0461-42b4-aaec-dad69ae5446b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613877198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1613877198
Directory	/workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1526490730
Short name	T386
Test name
Test status
Simulation time	92094240 ps
CPU time	1.14 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:50:01 PM PDT 24
Peak memory	200572 kb
Host	smart-2427ca78-983d-4651-8f48-38e27a79d7ba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526490730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_ctrl_intersig_mubi.1526490730
Directory	/workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_peri.2301747500
Short name	T293
Test name
Test status
Simulation time	26305628 ps
CPU time	0.8 seconds
Started	Jul 12 05:49:48 PM PDT 24
Finished	Jul 12 05:49:50 PM PDT 24
Peak memory	200436 kb
Host	smart-4a9940f2-5bd1-45cf-bab4-f236ad10f34d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301747500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2301747500
Directory	/workspace/8.clkmgr_peri/latest

Test location	/workspace/coverage/default/8.clkmgr_regwen.2799880669
Short name	T133
Test name
Test status
Simulation time	347314632 ps
CPU time	1.81 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200504 kb
Host	smart-0f8bae37-f02c-4f81-bf2a-4ae1facc38d2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799880669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2799880669
Directory	/workspace/8.clkmgr_regwen/latest

Test location	/workspace/coverage/default/8.clkmgr_smoke.4108234093
Short name	T88
Test name
Test status
Simulation time	34736222 ps
CPU time	0.88 seconds
Started	Jul 12 05:49:59 PM PDT 24
Finished	Jul 12 05:50:01 PM PDT 24
Peak memory	200476 kb
Host	smart-ce03cb7a-d510-4e0e-b5ba-198773597677
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108234093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.4108234093
Directory	/workspace/8.clkmgr_smoke/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all.3133506197
Short name	T768
Test name
Test status
Simulation time	2022856341 ps
CPU time	11.28 seconds
Started	Jul 12 05:50:07 PM PDT 24
Finished	Jul 12 05:50:19 PM PDT 24
Peak memory	200760 kb
Host	smart-9395ad51-f459-4e1d-ae75-1516fba5344d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133506197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.3133506197
Directory	/workspace/8.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.3354358415
Short name	T64
Test name
Test status
Simulation time	21451812877 ps
CPU time	389.3 seconds
Started	Jul 12 05:49:52 PM PDT 24
Finished	Jul 12 05:56:22 PM PDT 24
Peak memory	209168 kb
Host	smart-66bc0121-d137-4ae7-be43-28c6f3bd2c06
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3354358415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.3354358415
Directory	/workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.clkmgr_trans.3003712868
Short name	T535
Test name
Test status
Simulation time	113914372 ps
CPU time	1.18 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200540 kb
Host	smart-90ca24a3-e7d4-49f5-ac87-5f6e5534c0ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003712868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3003712868
Directory	/workspace/8.clkmgr_trans/latest

Test location	/workspace/coverage/default/9.clkmgr_alert_test.2162771446
Short name	T181
Test name
Test status
Simulation time	31475496 ps
CPU time	0.8 seconds
Started	Jul 12 05:50:04 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200924 kb
Host	smart-13fe85cf-d55d-491a-84e4-03f35b65494b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162771446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.2162771446
Directory	/workspace/9.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.705910693
Short name	T606
Test name
Test status
Simulation time	61526464 ps
CPU time	0.89 seconds
Started	Jul 12 05:49:58 PM PDT 24
Finished	Jul 12 05:50:00 PM PDT 24
Peak memory	200576 kb
Host	smart-4442eb72-ff9e-4112-bcaa-7192e01b02c5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705910693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.705910693
Directory	/workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_status.243430695
Short name	T605
Test name
Test status
Simulation time	93543670 ps
CPU time	0.86 seconds
Started	Jul 12 05:50:02 PM PDT 24
Finished	Jul 12 05:50:05 PM PDT 24
Peak memory	199780 kb
Host	smart-bbd7fd41-752f-4f49-a04c-c55fd4a62838
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243430695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.243430695
Directory	/workspace/9.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/9.clkmgr_div_intersig_mubi.1644006088
Short name	T563
Test name
Test status
Simulation time	26450012 ps
CPU time	0.91 seconds
Started	Jul 12 05:49:56 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200708 kb
Host	smart-bdb6f570-af8d-42d5-b5e7-6aa9ec63402e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644006088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.1644006088
Directory	/workspace/9.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_extclk.3168280365
Short name	T379
Test name
Test status
Simulation time	112808084 ps
CPU time	1.08 seconds
Started	Jul 12 05:49:55 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200544 kb
Host	smart-b4943597-a42e-4ad6-bf30-b66414b2b551
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168280365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.3168280365
Directory	/workspace/9.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency.2079151408
Short name	T442
Test name
Test status
Simulation time	1756419210 ps
CPU time	13.93 seconds
Started	Jul 12 05:50:12 PM PDT 24
Finished	Jul 12 05:50:27 PM PDT 24
Peak memory	200708 kb
Host	smart-33785900-5926-4dd4-b5db-dfa0509dcfda
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079151408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2079151408
Directory	/workspace/9.clkmgr_frequency/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency_timeout.2146542089
Short name	T307
Test name
Test status
Simulation time	858647355 ps
CPU time	6.24 seconds
Started	Jul 12 05:49:58 PM PDT 24
Finished	Jul 12 05:50:06 PM PDT 24
Peak memory	200632 kb
Host	smart-50c22fc8-82de-4b95-9dc0-aa42c3a42c33
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146542089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti meout.2146542089
Directory	/workspace/9.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/9.clkmgr_idle_intersig_mubi.2898169800
Short name	T672
Test name
Test status
Simulation time	52504135 ps
CPU time	0.93 seconds
Started	Jul 12 05:50:15 PM PDT 24
Finished	Jul 12 05:50:18 PM PDT 24
Peak memory	200484 kb
Host	smart-657783ec-58ff-4149-a10b-151356ce4374
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898169800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.2898169800
Directory	/workspace/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.3999525431
Short name	T479
Test name
Test status
Simulation time	16650183 ps
CPU time	0.78 seconds
Started	Jul 12 05:49:54 PM PDT 24
Finished	Jul 12 05:49:56 PM PDT 24
Peak memory	200564 kb
Host	smart-a86f81b5-3050-41eb-b35c-d9284fd56c60
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999525431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_clk_byp_req_intersig_mubi.3999525431
Directory	/workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.741611237
Short name	T172
Test name
Test status
Simulation time	70462316 ps
CPU time	1.03 seconds
Started	Jul 12 05:50:19 PM PDT 24
Finished	Jul 12 05:50:21 PM PDT 24
Peak memory	200584 kb
Host	smart-1d13190a-3872-4893-b249-f736c54b5844
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741611237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.clkmgr_lc_ctrl_intersig_mubi.741611237
Directory	/workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_peri.359688163
Short name	T416
Test name
Test status
Simulation time	27225485 ps
CPU time	0.81 seconds
Started	Jul 12 05:49:56 PM PDT 24
Finished	Jul 12 05:49:58 PM PDT 24
Peak memory	200356 kb
Host	smart-0e59344e-1f0f-415e-b8cd-fd3c73c794e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359688163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.359688163
Directory	/workspace/9.clkmgr_peri/latest

Test location	/workspace/coverage/default/9.clkmgr_regwen.4172948163
Short name	T683
Test name
Test status
Simulation time	189325873 ps
CPU time	1.34 seconds
Started	Jul 12 05:49:57 PM PDT 24
Finished	Jul 12 05:50:00 PM PDT 24
Peak memory	200464 kb
Host	smart-d9d0fd0a-4843-426e-91c8-1d123abccb22
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172948163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.4172948163
Directory	/workspace/9.clkmgr_regwen/latest

Test location	/workspace/coverage/default/9.clkmgr_smoke.1948822991
Short name	T734
Test name
Test status
Simulation time	29681585 ps
CPU time	0.91 seconds
Started	Jul 12 05:50:11 PM PDT 24
Finished	Jul 12 05:50:14 PM PDT 24
Peak memory	200496 kb
Host	smart-c7b5b6ac-bf1f-4070-b466-3072c1365b1e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948822991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1948822991
Directory	/workspace/9.clkmgr_smoke/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all.589368958
Short name	T11
Test name
Test status
Simulation time	6464653994 ps
CPU time	34.43 seconds
Started	Jul 12 05:50:00 PM PDT 24
Finished	Jul 12 05:50:35 PM PDT 24
Peak memory	200824 kb
Host	smart-a6ce118a-d4c6-4e3a-99fd-984d2de30e3d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589368958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.589368958
Directory	/workspace/9.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.2584976785
Short name	T707
Test name
Test status
Simulation time	35432749938 ps
CPU time	523.56 seconds
Started	Jul 12 05:50:11 PM PDT 24
Finished	Jul 12 05:58:56 PM PDT 24
Peak memory	209676 kb
Host	smart-89dd1ea9-6fe6-4b24-9b07-04382f73d251
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2584976785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2584976785
Directory	/workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.clkmgr_trans.1297768310
Short name	T267
Test name
Test status
Simulation time	89520191 ps
CPU time	1.19 seconds
Started	Jul 12 05:49:56 PM PDT 24
Finished	Jul 12 05:49:59 PM PDT 24
Peak memory	200792 kb
Host	smart-944ca6f3-0f88-4fa4-80a6-3198ca7940a4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297768310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1297768310
Directory	/workspace/9.clkmgr_trans/latest

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