Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314948920

1

T4

1734

T5

2230

T1

119700

auto[1]

420622

1

T4

190

T17

124

T18

660

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314952294

1

T4

1766

T5

2214

T1

119700

auto[1]

417248

1

T4

158

T5

16

T17

114

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314880208

1

T4

1766

T5

2214

T1

119700

auto[1]

489334

1

T4

158

T5

16

T17

48

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289998440

1

T4

222

T5

48

T1

119700

auto[1]

25371102

1

T4

1702

T5

2182

T18

3518

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187905082

1

T4

1924

T5

2210

T1

119680

auto[1]

127464460

1

T5

20

T1

20

T13

16

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

171222508

1

T4

128

T5

28

T1

119680

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

118422854

1

T5

20

T1

20

T13

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

31134

1

T4

4

T17

2

T18

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7328

1

T17

12

T36

68

T6

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

16077898

1

T4

1580

T5

2158

T18

2922

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8929964

1

T2

168

T72

1320

T73

198

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50552

1

T4

54

T18

80

T2

370

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11954

1

T2

36

T87

38

T172

30

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

68334

1

T18

8

T22

2998

T36

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1390

1

T17

2

T18

8

T36

48

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12900

1

T36

112

T88

120

T142

84

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3456

1

T17

64

T36

110

T143

102

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11060

1

T5

8

T18

18

T2

64

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2070

1

T87

10

T10

44

T150

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

22008

1

T18

48

T2

198

T86

40

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4798

1

T87

60

T10

146

T21

66

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49192

1

T18

40

T2

6

T36

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3604

1

T73

42

T6

22

T88

24

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33408

1

T18

38

T2

170

T36

58

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7828

1

T6

110

T88

110

T143

130

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29220

1

T5

8

T18

14

T2

90

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7148

1

T2

2

T72

16

T73

20

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

53918

1

T18

44

T2

126

T87

48

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13784

1

T2

72

T172

74

T173

158

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63448

1

T4

18

T17

2

T18

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6504

1

T2

34

T36

20

T89

22

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53516

1

T4

72

T17

46

T18

120

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11036

1

T36

70

T8

346

T9

74

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43164

1

T4

8

T5

8

T18

68

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10562

1

T2

6

T73

30

T86

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

82822

1

T4

60

T18

324

T2

236

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20180

1

T2

58

T87

42

T25

64