Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332212364

1

T6

2168

T4

8338

T7

2938

auto[1]

452476

1

T26

180

T19

1056

T2

1950

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332246534

1

T6

2168

T4

2496

T7

2938

auto[1]

418306

1

T4

5842

T26

74

T19

530

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332114270

1

T6

2168

T4

8338

T7

2938

auto[1]

550570

1

T26

184

T19

1012

T2

1944

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321081688

1

T6

2168

T4

8338

T7

2938

auto[1]

11583152

1

T26

2468

T19

374

T2

6856

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195896678

1

T6

2168

T4

8316

T7

100

auto[1]

136768162

1

T4

22

T7

2838

T25

64

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

185114920

1

T6

2168

T4

2474

T7

100

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

135603942

1

T4

22

T7

2838

T25

64

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

33044

1

T19

254

T2

134

T3

18

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8694

1

T19

132

T12

6

T181

16

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

10146744

1

T26

2256

T19

160

T2

4880

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1036446

1

T2

262

T3

1858

T12

322

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57418

1

T26

28

T19

24

T2

276

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14674

1

T2

88

T3

16

T12

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39750

1

T4

5842

T19

46

T2

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1342

1

T3

14

T181

18

T154

22

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

13106

1

T2

86

T3

56

T12

118

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2694

1

T3

50

T181

46

T154

82

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10932

1

T2

38

T3

34

T12

16

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3238

1

T3

2

T182

28

T68

18

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21056

1

T2

156

T3

40

T12

178

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6270

1

T3

58

T68

114

T69

92

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

64922

1

T19

152

T2

190

T3

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5348

1

T19

66

T12

8

T154

106

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34758

1

T19

250

T2

190

T3

84

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9176

1

T19

60

T12

92

T157

96

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33646

1

T26

22

T2

208

T3

52

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7472

1

T2

8

T12

24

T54

30

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

61066

1

T26

88

T2

464

T3

154

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14264

1

T2

72

T12

102

T13

84

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

75580

1

T19

80

T2

202

T3

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7462

1

T19

42

T3

6

T12

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53524

1

T19

172

T2

206

T3

46

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13426

1

T3

54

T154

176

T157

72

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48696

1

T26

10

T19

26

T2

106

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11924

1

T2

20

T3

18

T12

60

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

87516

1

T26

64

T19

164

T2

222

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21790

1

T2

56

T3

90

T54

140