Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 301775112 1 T5 7534 T6 1468 T7 4958
auto[1] 438564 1 T6 68 T1 1278 T2 12136


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 301781786 1 T5 7534 T6 1500 T7 4958
auto[1] 431890 1 T6 36 T1 636 T2 8878


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 301670198 1 T5 7534 T6 1424 T7 4958
auto[1] 543478 1 T6 112 T1 872 T2 12136


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 279746298 1 T5 7534 T6 42 T7 4958
auto[1] 22467378 1 T6 1494 T1 4812 T2 138403


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 169081638 1 T5 4600 T6 1536 T7 1704
auto[1] 133132038 1 T5 2934 T7 3254 T1 135136


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 149997680 1 T5 4600 T6 42 T7 1704
auto[0] auto[0] auto[0] auto[0] auto[1] 129380922 1 T5 2934 T7 3254 T1 134586
auto[0] auto[0] auto[0] auto[1] auto[0] 33514 1 T1 56 T2 656 T17 20
auto[0] auto[0] auto[0] auto[1] auto[1] 7764 1 T1 100 T2 156 T19 102
auto[0] auto[0] auto[1] auto[0] auto[0] 18450386 1 T6 1372 T1 3752 T2 136743
auto[0] auto[0] auto[1] auto[0] auto[1] 3626728 1 T1 246 T2 5132 T17 188
auto[0] auto[0] auto[1] auto[1] auto[0] 56842 1 T6 10 T1 112 T2 1860
auto[0] auto[0] auto[1] auto[1] auto[1] 14738 1 T1 74 T2 318 T20 32
auto[0] auto[1] auto[0] auto[0] auto[0] 44240 1 T1 12 T2 158 T17 24
auto[0] auto[1] auto[0] auto[0] auto[1] 2152 1 T2 92 T17 8 T19 20
auto[0] auto[1] auto[0] auto[1] auto[0] 12766 1 T1 114 T2 176 T19 78
auto[0] auto[1] auto[0] auto[1] auto[1] 4204 1 T2 276 T19 50 T87 72
auto[0] auto[1] auto[1] auto[0] auto[0] 9478 1 T1 30 T2 130 T23 32
auto[0] auto[1] auto[1] auto[0] auto[1] 3388 1 T2 72 T21 8 T3 70
auto[0] auto[1] auto[1] auto[1] auto[0] 19916 1 T1 100 T2 502 T23 100
auto[0] auto[1] auto[1] auto[1] auto[1] 5480 1 T2 176 T3 122 T171 56
auto[1] auto[0] auto[0] auto[0] auto[0] 54260 1 T1 16 T2 366 T17 8
auto[1] auto[0] auto[0] auto[0] auto[1] 4182 1 T2 60 T20 58 T21 8
auto[1] auto[0] auto[0] auto[1] auto[0] 31762 1 T1 96 T2 812 T19 336
auto[1] auto[0] auto[0] auto[1] auto[1] 8086 1 T2 178 T3 144 T59 72
auto[1] auto[0] auto[1] auto[0] auto[0] 31060 1 T6 18 T1 62 T2 912
auto[1] auto[0] auto[1] auto[0] auto[1] 8636 1 T1 8 T2 260 T17 8
auto[1] auto[0] auto[1] auto[1] auto[0] 60270 1 T6 58 T1 310 T2 1662
auto[1] auto[0] auto[1] auto[1] auto[1] 14956 1 T2 590 T20 82 T3 192
auto[1] auto[1] auto[0] auto[0] auto[0] 95846 1 T1 36 T2 662 T17 18
auto[1] auto[1] auto[0] auto[0] auto[1] 5612 1 T1 4 T2 168 T19 8
auto[1] auto[1] auto[0] auto[1] auto[0] 52624 1 T1 112 T2 1272 T17 64
auto[1] auto[1] auto[0] auto[1] auto[1] 10684 1 T1 110 T2 216 T19 84
auto[1] auto[1] auto[1] auto[0] auto[0] 47864 1 T6 36 T1 16 T2 1574
auto[1] auto[1] auto[1] auto[0] auto[1] 12678 1 T1 8 T2 118 T17 8
auto[1] auto[1] auto[1] auto[1] auto[0] 83130 1 T1 94 T2 2856 T19 78
auto[1] auto[1] auto[1] auto[1] auto[1] 21828 1 T2 430 T3 432 T54 64

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%