Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 328523806 1 T1 238928 T6 4638 T5 417226
auto[1] 439066 1 T1 1072 T2 6498 T20 48


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 328517900 1 T1 238939 T6 4638 T5 417226
auto[1] 444972 1 T1 964 T4 316 T2 4068


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 328453810 1 T1 238909 T6 4638 T5 417226
auto[1] 509062 1 T1 1258 T2 5672 T20 54


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 304192118 1 T1 238590 T6 4638 T5 417226
auto[1] 24770754 1 T1 4454 T2 769446 T20 128


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 198787998 1 T1 139447 T6 1188 T5 417226
auto[1] 130174874 1 T1 995884 T6 3450 T17 2232


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 176160756 1 T1 139199 T6 1188 T5 417226
auto[0] auto[0] auto[0] auto[0] auto[1] 127667458 1 T1 993512 T6 3450 T17 2232
auto[0] auto[0] auto[0] auto[1] auto[0] 31746 1 T1 38 T2 208 T34 34
auto[0] auto[0] auto[0] auto[1] auto[1] 8236 1 T2 76 T10 34 T68 12
auto[0] auto[0] auto[1] auto[0] auto[0] 22001202 1 T1 1226 T2 759832 T20 78
auto[0] auto[0] auto[1] auto[0] auto[1] 2383728 1 T1 1942 T2 4150 T35 70
auto[0] auto[0] auto[1] auto[1] auto[0] 55378 1 T1 208 T2 698 T20 4
auto[0] auto[0] auto[1] auto[1] auto[1] 13228 1 T1 58 T2 200 T35 12
auto[0] auto[1] auto[0] auto[0] auto[0] 73008 1 T1 32 T4 316 T2 54
auto[0] auto[1] auto[0] auto[0] auto[1] 1344 1 T2 2 T78 28 T13 34
auto[0] auto[1] auto[0] auto[1] auto[0] 13214 1 T2 104 T10 128 T78 48
auto[0] auto[1] auto[0] auto[1] auto[1] 2840 1 T2 58 T78 46 T140 78
auto[0] auto[1] auto[1] auto[0] auto[0] 10896 1 T1 44 T2 114 T35 22
auto[0] auto[1] auto[1] auto[0] auto[1] 3364 1 T1 46 T2 28 T10 32
auto[0] auto[1] auto[1] auto[1] auto[0] 20876 1 T2 428 T35 52 T10 236
auto[0] auto[1] auto[1] auto[1] auto[1] 6536 1 T2 210 T10 148 T11 182
auto[1] auto[0] auto[0] auto[0] auto[0] 37406 1 T1 20 T2 104 T35 8
auto[1] auto[0] auto[0] auto[0] auto[1] 4522 1 T2 52 T10 50 T11 70
auto[1] auto[0] auto[0] auto[1] auto[0] 34324 1 T1 78 T2 634 T34 66
auto[1] auto[0] auto[0] auto[1] auto[1] 8748 1 T2 164 T10 154 T11 124
auto[1] auto[0] auto[1] auto[0] auto[0] 30202 1 T1 62 T2 246 T35 64
auto[1] auto[0] auto[1] auto[0] auto[1] 8170 1 T1 8 T2 64 T35 2
auto[1] auto[0] auto[1] auto[1] auto[0] 58660 1 T1 168 T2 1086 T35 278
auto[1] auto[0] auto[1] auto[1] auto[1] 14136 1 T1 80 T2 252 T35 64
auto[1] auto[1] auto[0] auto[0] auto[0] 77908 1 T1 54 T2 172 T20 8
auto[1] auto[1] auto[0] auto[0] auto[1] 6348 1 T1 68 T2 16 T10 22
auto[1] auto[1] auto[0] auto[1] auto[0] 51774 1 T1 108 T2 648 T35 140
auto[1] auto[1] auto[0] auto[1] auto[1] 12486 1 T2 96 T10 236 T68 66
auto[1] auto[1] auto[1] auto[0] auto[0] 46230 1 T1 222 T2 456 T20 2
auto[1] auto[1] auto[1] auto[0] auto[1] 11264 1 T1 56 T2 46 T10 142
auto[1] auto[1] auto[1] auto[1] auto[0] 84418 1 T1 220 T2 1402 T20 44
auto[1] auto[1] auto[1] auto[1] auto[1] 22466 1 T1 114 T2 234 T10 468

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