Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 302999094 1 T6 2348 T7 2114 T1 252698
auto[1] 433542 1 T15 496 T18 746 T20 1076


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 303034590 1 T6 2348 T7 2114 T1 252698
auto[1] 398046 1 T15 266 T4 1810 T17 3204


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 302941412 1 T6 2348 T7 2114 T1 252698
auto[1] 491224 1 T15 472 T4 1810 T5 674


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 284197824 1 T6 2348 T7 2114 T1 252698
auto[1] 19234812 1 T15 2132 T18 1588 T20 1718


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 182146550 1 T6 2348 T7 2008 T1 252676
auto[1] 121286086 1 T7 106 T1 22 T15 1930


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 164462780 1 T6 2348 T7 2008 T1 252676
auto[0] auto[0] auto[0] auto[0] auto[1] 119412636 1 T7 106 T1 22 T4 104
auto[0] auto[0] auto[0] auto[1] auto[0] 32088 1 T15 16 T18 10 T20 220
auto[0] auto[0] auto[0] auto[1] auto[1] 8584 1 T18 6 T20 138 T127 16
auto[0] auto[0] auto[1] auto[0] auto[0] 17109394 1 T15 86 T18 822 T20 1622
auto[0] auto[0] auto[1] auto[0] auto[1] 1745078 1 T15 1564 T18 208 T40 2190
auto[0] auto[0] auto[1] auto[1] auto[0] 53958 1 T15 26 T18 30 T20 78
auto[0] auto[0] auto[1] auto[1] auto[1] 14518 1 T15 72 T18 12 T40 18
auto[0] auto[1] auto[0] auto[0] auto[0] 40360 1 T18 16 T20 38 T40 8
auto[0] auto[1] auto[0] auto[0] auto[1] 2006 1 T40 20 T127 20 T86 4
auto[0] auto[1] auto[0] auto[1] auto[0] 13622 1 T18 62 T20 70 T40 50
auto[0] auto[1] auto[0] auto[1] auto[1] 4414 1 T127 64 T86 66 T162 60
auto[0] auto[1] auto[1] auto[0] auto[0] 11846 1 T41 26 T86 114 T128 28
auto[0] auto[1] auto[1] auto[0] auto[1] 2694 1 T18 24 T128 8 T8 26
auto[0] auto[1] auto[1] auto[1] auto[0] 21958 1 T41 152 T86 64 T128 102
auto[0] auto[1] auto[1] auto[1] auto[1] 5476 1 T128 64 T9 98 T187 40
auto[1] auto[0] auto[0] auto[0] auto[0] 42096 1 T5 674 T18 2 T20 66
auto[1] auto[0] auto[0] auto[0] auto[1] 4326 1 T20 12 T74 30 T129 36
auto[1] auto[0] auto[0] auto[1] auto[0] 33998 1 T18 62 T20 160 T8 558
auto[1] auto[0] auto[0] auto[1] auto[1] 8770 1 T20 134 T8 152 T9 54
auto[1] auto[0] auto[1] auto[0] auto[0] 29044 1 T18 48 T40 54 T74 172
auto[1] auto[0] auto[1] auto[0] auto[1] 8546 1 T15 44 T74 42 T128 62
auto[1] auto[0] auto[1] auto[1] auto[0] 52958 1 T18 194 T41 68 T127 58
auto[1] auto[0] auto[1] auto[1] auto[1] 15816 1 T15 162 T128 62 T8 294
auto[1] auto[1] auto[0] auto[0] auto[0] 65458 1 T15 20 T4 1810 T17 3204
auto[1] auto[1] auto[0] auto[0] auto[1] 6338 1 T18 2 T20 26 T40 14
auto[1] auto[1] auto[0] auto[1] auto[0] 48106 1 T15 68 T18 116 T20 160
auto[1] auto[1] auto[0] auto[1] auto[1] 12242 1 T18 50 T20 116 T8 72
auto[1] auto[1] auto[1] auto[0] auto[0] 44990 1 T15 4 T18 28 T20 18
auto[1] auto[1] auto[1] auto[0] auto[1] 11502 1 T15 22 T18 18 T40 26
auto[1] auto[1] auto[1] auto[1] auto[0] 83894 1 T15 86 T18 92 T41 122
auto[1] auto[1] auto[1] auto[1] auto[1] 23140 1 T15 66 T18 112 T40 66

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