Unified Coverage Report :: Tests

Tests

dashboard | hierarchy | modlist | groups | tests | asserts

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.47	99.11	95.68	100.00	100.00	98.71	97.02	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1002	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3791321146			Jul 18 06:31:08 PM PDT 24	Jul 18 06:31:16 PM PDT 24	36860034 ps
T1003	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.272211444			Jul 18 06:31:07 PM PDT 24	Jul 18 06:31:14 PM PDT 24	29869233 ps
T117	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1787674966			Jul 18 06:30:57 PM PDT 24	Jul 18 06:31:06 PM PDT 24	225365812 ps
T1004	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.292531338			Jul 18 06:30:58 PM PDT 24	Jul 18 06:31:05 PM PDT 24	49822977 ps
T1005	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2141326374			Jul 18 06:31:20 PM PDT 24	Jul 18 06:31:22 PM PDT 24	41937601 ps
T1006	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2839196367			Jul 18 06:31:08 PM PDT 24	Jul 18 06:31:15 PM PDT 24	47527474 ps
T1007	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.4065115890			Jul 18 06:30:59 PM PDT 24	Jul 18 06:31:08 PM PDT 24	26037055 ps
T1008	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1286671327			Jul 18 06:31:07 PM PDT 24	Jul 18 06:31:14 PM PDT 24	87598855 ps
T1009	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3122282739			Jul 18 06:31:06 PM PDT 24	Jul 18 06:31:14 PM PDT 24	98750222 ps
T1010	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.626668706			Jul 18 06:30:58 PM PDT 24	Jul 18 06:31:09 PM PDT 24	655773433 ps

Test location	/workspace/coverage/default/46.clkmgr_frequency.999005189
Short name	T1
Test name
Test status
Simulation time	2007380451 ps
CPU time	12.58 seconds
Started	Jul 18 06:44:10 PM PDT 24
Finished	Jul 18 06:44:30 PM PDT 24
Peak memory	201316 kb
Host	smart-429d8f61-fb80-470e-858e-e2ac03917554
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999005189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.999005189
Directory	/workspace/46.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.3166076888
Short name	T8
Test name
Test status
Simulation time	66641509511 ps
CPU time	401.49 seconds
Started	Jul 18 06:43:38 PM PDT 24
Finished	Jul 18 06:50:24 PM PDT 24
Peak memory	209780 kb
Host	smart-060db40e-2e91-4bc0-a2e5-9cbde1f0be79
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3166076888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.3166076888
Directory	/workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2523500344
Short name	T20
Test name
Test status
Simulation time	94600807 ps
CPU time	1.1 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:03 PM PDT 24
Peak memory	201100 kb
Host	smart-340ece71-0ffa-4949-b33c-36ff4e7dd614
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523500344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_ctrl_intersig_mubi.2523500344
Directory	/workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_status.2489625591
Short name	T16
Test name
Test status
Simulation time	14919857 ps
CPU time	0.69 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	200964 kb
Host	smart-bb86392a-4340-4248-9ca8-c64e726b45f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489625591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2489625591
Directory	/workspace/3.clkmgr_clk_status/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2272624438
Short name	T68
Test name
Test status
Simulation time	195257388 ps
CPU time	2.13 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:22 PM PDT 24
Peak memory	208544 kb
Host	smart-e0749c49-7f06-4c51-ba89-4a5545798aaf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272624438 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.clkmgr_shadow_reg_errors.2272624438
Directory	/workspace/14.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/37.clkmgr_regwen.2674708775
Short name	T4
Test name
Test status
Simulation time	322765050 ps
CPU time	2.3 seconds
Started	Jul 18 06:43:37 PM PDT 24
Finished	Jul 18 06:43:44 PM PDT 24
Peak memory	201056 kb
Host	smart-6e6065f8-912a-47b9-aa37-91d6078b580d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674708775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.2674708775
Directory	/workspace/37.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_sec_cm.478353523
Short name	T45
Test name
Test status
Simulation time	152113568 ps
CPU time	1.95 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:36 PM PDT 24
Peak memory	216300 kb
Host	smart-72832a63-8e9e-43af-9fa0-d0789ea294da
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478353523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr _sec_cm.478353523
Directory	/workspace/1.clkmgr_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1088290388
Short name	T67
Test name
Test status
Simulation time	105925822 ps
CPU time	2.45 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	210420 kb
Host	smart-99ea040f-1b23-480d-a59c-d083daf19f74
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088290388 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.1088290388
Directory	/workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/15.clkmgr_idle_intersig_mubi.480142994
Short name	T179
Test name
Test status
Simulation time	438341380 ps
CPU time	2.18 seconds
Started	Jul 18 06:41:56 PM PDT 24
Finished	Jul 18 06:41:59 PM PDT 24
Peak memory	201044 kb
Host	smart-5c5bbb61-9d28-4a44-9ddf-3973639dab0f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480142994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_idle_intersig_mubi.480142994
Directory	/workspace/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_alert_test.3363042543
Short name	T32
Test name
Test status
Simulation time	16810229 ps
CPU time	0.78 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:35 PM PDT 24
Peak memory	201408 kb
Host	smart-2f71b6da-c28f-481e-afa5-76ef5fc520f9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363042543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm gr_alert_test.3363042543
Directory	/workspace/1.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.1232281433
Short name	T77
Test name
Test status
Simulation time	55156730080 ps
CPU time	468.35 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:49:06 PM PDT 24
Peak memory	209780 kb
Host	smart-9ee6572b-3c51-491e-808e-93001d1b5db7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1232281433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1232281433
Directory	/workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3541572040
Short name	T114
Test name
Test status
Simulation time	53909105 ps
CPU time	1.54 seconds
Started	Jul 18 06:30:52 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200692 kb
Host	smart-1bb1571d-818f-4daf-86c5-e4420c5ec8d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541572040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.3541572040
Directory	/workspace/10.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all.3140038189
Short name	T9
Test name
Test status
Simulation time	9993296912 ps
CPU time	72.01 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:43:40 PM PDT 24
Peak memory	201448 kb
Host	smart-3369d837-c333-4416-9648-0e14ba70c96a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140038189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.3140038189
Directory	/workspace/17.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.2298553699
Short name	T153
Test name
Test status
Simulation time	15587837863 ps
CPU time	137.76 seconds
Started	Jul 18 06:41:49 PM PDT 24
Finished	Jul 18 06:44:09 PM PDT 24
Peak memory	209784 kb
Host	smart-9d82f5fd-234b-466c-bfd4-1afbbf8a0323
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2298553699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.2298553699
Directory	/workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1820755858
Short name	T145
Test name
Test status
Simulation time	65370925 ps
CPU time	1.24 seconds
Started	Jul 18 06:30:51 PM PDT 24
Finished	Jul 18 06:30:55 PM PDT 24
Peak memory	200832 kb
Host	smart-e7842283-cec1-4dd5-9946-79ab45c3af80
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820755858 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.clkmgr_shadow_reg_errors.1820755858
Directory	/workspace/5.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.539501351
Short name	T121
Test name
Test status
Simulation time	240095214 ps
CPU time	2.93 seconds
Started	Jul 18 06:30:39 PM PDT 24
Finished	Jul 18 06:30:50 PM PDT 24
Peak memory	200692 kb
Host	smart-94b377d3-50a0-4146-bc07-a2adffa3ff86
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539501351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.clkmgr_tl_intg_err.539501351
Directory	/workspace/0.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2793474982
Short name	T128
Test name
Test status
Simulation time	50845635 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:22 PM PDT 24
Finished	Jul 18 06:41:25 PM PDT 24
Peak memory	201084 kb
Host	smart-ce342318-3f42-4482-a3b7-e7db78a7ee0b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793474982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.2793474982
Directory	/workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2450869371
Short name	T147
Test name
Test status
Simulation time	135372558 ps
CPU time	2.32 seconds
Started	Jul 18 06:30:51 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	209292 kb
Host	smart-ed489b1a-781a-40a9-a1af-f237c6a0a8de
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450869371 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.clkmgr_shadow_reg_errors.2450869371
Directory	/workspace/1.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3329058126
Short name	T139
Test name
Test status
Simulation time	92241554 ps
CPU time	1.8 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	201016 kb
Host	smart-342cfcc7-c095-4058-92e3-49d12b8c2513
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329058126 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.3329058126
Directory	/workspace/15.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.277240775
Short name	T112
Test name
Test status
Simulation time	26769638 ps
CPU time	0.92 seconds
Started	Jul 18 06:41:37 PM PDT 24
Finished	Jul 18 06:41:44 PM PDT 24
Peak memory	201072 kb
Host	smart-663c87e3-4f1c-4be4-8569-b58284013455
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277240775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.277240775
Directory	/workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2264966003
Short name	T148
Test name
Test status
Simulation time	68943367 ps
CPU time	1.37 seconds
Started	Jul 18 06:30:38 PM PDT 24
Finished	Jul 18 06:30:48 PM PDT 24
Peak memory	200852 kb
Host	smart-505140cf-61f5-4732-81c8-48b9ce87f590
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264966003 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.clkmgr_shadow_reg_errors.2264966003
Directory	/workspace/0.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1692107169
Short name	T122
Test name
Test status
Simulation time	230422191 ps
CPU time	2.06 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200624 kb
Host	smart-807c7df5-2ec2-4596-8d76-b03ba1b74d10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692107169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 1.clkmgr_tl_intg_err.1692107169
Directory	/workspace/1.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all.2879475736
Short name	T38
Test name
Test status
Simulation time	6667081932 ps
CPU time	28.65 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:50 PM PDT 24
Peak memory	201428 kb
Host	smart-02d0bb88-6037-415f-9a43-19321c7cc27c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879475736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.2879475736
Directory	/workspace/19.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/11.clkmgr_regwen.970363977
Short name	T391
Test name
Test status
Simulation time	208146464 ps
CPU time	1.66 seconds
Started	Jul 18 06:41:35 PM PDT 24
Finished	Jul 18 06:41:42 PM PDT 24
Peak memory	201048 kb
Host	smart-7cd9b492-f570-402d-93ba-65d446a58855
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970363977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.970363977
Directory	/workspace/11.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3578956044
Short name	T946
Test name
Test status
Simulation time	77835635 ps
CPU time	1.83 seconds
Started	Jul 18 06:30:37 PM PDT 24
Finished	Jul 18 06:30:47 PM PDT 24
Peak memory	200876 kb
Host	smart-4f2e5aee-3762-466d-8f92-6e3a76d055a0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578956044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_aliasing.3578956044
Directory	/workspace/0.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3013898645
Short name	T954
Test name
Test status
Simulation time	675376210 ps
CPU time	5.28 seconds
Started	Jul 18 06:30:40 PM PDT 24
Finished	Jul 18 06:30:54 PM PDT 24
Peak memory	200604 kb
Host	smart-1135f6df-af8e-4a21-b478-191b8163614d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013898645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_bit_bash.3013898645
Directory	/workspace/0.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.4175560356
Short name	T939
Test name
Test status
Simulation time	56748745 ps
CPU time	0.87 seconds
Started	Jul 18 06:30:39 PM PDT 24
Finished	Jul 18 06:30:49 PM PDT 24
Peak memory	200556 kb
Host	smart-6b07a50c-50a3-4aa6-92eb-dc803bf2e25b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175560356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_hw_reset.4175560356
Directory	/workspace/0.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1790801324
Short name	T873
Test name
Test status
Simulation time	53575475 ps
CPU time	1.3 seconds
Started	Jul 18 06:30:50 PM PDT 24
Finished	Jul 18 06:30:54 PM PDT 24
Peak memory	200644 kb
Host	smart-07836226-e2b1-4de7-a4c9-198e7bf3e312
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790801324 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.1790801324
Directory	/workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3717895663
Short name	T968
Test name
Test status
Simulation time	69045991 ps
CPU time	0.98 seconds
Started	Jul 18 06:30:38 PM PDT 24
Finished	Jul 18 06:30:47 PM PDT 24
Peak memory	200560 kb
Host	smart-a71e1827-c1de-4442-9cb6-612acae5599a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717895663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. clkmgr_csr_rw.3717895663
Directory	/workspace/0.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.427316088
Short name	T915
Test name
Test status
Simulation time	13567258 ps
CPU time	0.68 seconds
Started	Jul 18 06:30:35 PM PDT 24
Finished	Jul 18 06:30:44 PM PDT 24
Peak memory	199104 kb
Host	smart-33f6bb52-3854-4038-8248-62ee407bbea0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427316088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm gr_intr_test.427316088
Directory	/workspace/0.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.393210996
Short name	T956
Test name
Test status
Simulation time	87201038 ps
CPU time	1.15 seconds
Started	Jul 18 06:30:50 PM PDT 24
Finished	Jul 18 06:30:54 PM PDT 24
Peak memory	200524 kb
Host	smart-84dca3e3-883d-4045-9dd0-30e00cfa0683
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393210996 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.clkmgr_same_csr_outstanding.393210996
Directory	/workspace/0.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2445266137
Short name	T998
Test name
Test status
Simulation time	729261443 ps
CPU time	3.57 seconds
Started	Jul 18 06:30:37 PM PDT 24
Finished	Jul 18 06:30:49 PM PDT 24
Peak memory	209348 kb
Host	smart-31288cd0-6588-4d3c-a989-320564d2509d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445266137 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.2445266137
Directory	/workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4073581002
Short name	T870
Test name
Test status
Simulation time	80561054 ps
CPU time	2.72 seconds
Started	Jul 18 06:30:34 PM PDT 24
Finished	Jul 18 06:30:42 PM PDT 24
Peak memory	200652 kb
Host	smart-fdbf064c-2825-4ab5-805b-b70d218aa77e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073581002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_tl_errors.4073581002
Directory	/workspace/0.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2082995587
Short name	T876
Test name
Test status
Simulation time	44868150 ps
CPU time	1.25 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200444 kb
Host	smart-21704499-46c7-4a6c-96f8-15dd7586d929
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082995587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_aliasing.2082995587
Directory	/workspace/1.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3750048497
Short name	T868
Test name
Test status
Simulation time	345957243 ps
CPU time	3.87 seconds
Started	Jul 18 06:30:52 PM PDT 24
Finished	Jul 18 06:30:59 PM PDT 24
Peak memory	200680 kb
Host	smart-f6e5e333-b925-42cf-ae8f-e1029eed7a7a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750048497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_bit_bash.3750048497
Directory	/workspace/1.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3014824638
Short name	T901
Test name
Test status
Simulation time	24226369 ps
CPU time	0.91 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:04 PM PDT 24
Peak memory	200516 kb
Host	smart-ea208620-0141-42c5-bf3a-44906fcf8343
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014824638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_hw_reset.3014824638
Directory	/workspace/1.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2347930855
Short name	T932
Test name
Test status
Simulation time	39846573 ps
CPU time	1.35 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200512 kb
Host	smart-07f58f73-7b33-4687-97e4-0e8edf133ccd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347930855 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.2347930855
Directory	/workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1267778365
Short name	T961
Test name
Test status
Simulation time	35758685 ps
CPU time	0.85 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:57 PM PDT 24
Peak memory	200524 kb
Host	smart-1ffe5fb1-79ae-480f-bba7-fff10dd40093
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267778365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. clkmgr_csr_rw.1267778365
Directory	/workspace/1.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1157003265
Short name	T951
Test name
Test status
Simulation time	14954989 ps
CPU time	0.69 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:30:59 PM PDT 24
Peak memory	199092 kb
Host	smart-8e242891-6603-4f07-8231-e48f6a631bcc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157003265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_intr_test.1157003265
Directory	/workspace/1.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.140285992
Short name	T888
Test name
Test status
Simulation time	89077075 ps
CPU time	1.59 seconds
Started	Jul 18 06:30:52 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200664 kb
Host	smart-e4e746de-3b06-437e-9c21-85b583e5cb5f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140285992 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.clkmgr_same_csr_outstanding.140285992
Directory	/workspace/1.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3940132204
Short name	T949
Test name
Test status
Simulation time	174955296 ps
CPU time	3.09 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	217188 kb
Host	smart-c3257cba-3204-43e8-af98-52e455d5d7c2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940132204 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.3940132204
Directory	/workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.4263756386
Short name	T975
Test name
Test status
Simulation time	270713137 ps
CPU time	2.95 seconds
Started	Jul 18 06:30:56 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200664 kb
Host	smart-daa2653b-7439-4d06-aa56-0d6f587a821d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263756386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_tl_errors.4263756386
Directory	/workspace/1.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2620198518
Short name	T922
Test name
Test status
Simulation time	36898610 ps
CPU time	1.92 seconds
Started	Jul 18 06:30:52 PM PDT 24
Finished	Jul 18 06:30:58 PM PDT 24
Peak memory	200720 kb
Host	smart-77228f83-100d-46d0-a4a8-fbb9a1564368
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620198518 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2620198518
Directory	/workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1192899688
Short name	T896
Test name
Test status
Simulation time	65206073 ps
CPU time	0.88 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:30:58 PM PDT 24
Peak memory	200524 kb
Host	smart-6342bdd0-e8c1-4d77-be8d-d6f7a9b4da94
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192899688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .clkmgr_csr_rw.1192899688
Directory	/workspace/10.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2771710352
Short name	T970
Test name
Test status
Simulation time	11030785 ps
CPU time	0.67 seconds
Started	Jul 18 06:31:00 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	199068 kb
Host	smart-12be1b0a-77c6-4523-8cbd-e7292ad9f2e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771710352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_intr_test.2771710352
Directory	/workspace/10.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3546121740
Short name	T886
Test name
Test status
Simulation time	62631899 ps
CPU time	1.5 seconds
Started	Jul 18 06:30:52 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200668 kb
Host	smart-faf23503-3cdf-422c-aeed-2b3342fff0fd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546121740 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.clkmgr_same_csr_outstanding.3546121740
Directory	/workspace/10.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2792385321
Short name	T138
Test name
Test status
Simulation time	69371361 ps
CPU time	1.23 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200884 kb
Host	smart-84d9fca8-c295-4782-bc0e-102f23091bd9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792385321 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.clkmgr_shadow_reg_errors.2792385321
Directory	/workspace/10.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.626668706
Short name	T1010
Test name
Test status
Simulation time	655773433 ps
CPU time	3.07 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	201028 kb
Host	smart-a5b35eda-2d10-441e-b695-f4d1e66108e1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626668706 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.626668706
Directory	/workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.3480458642
Short name	T927
Test name
Test status
Simulation time	118743159 ps
CPU time	3.58 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	200632 kb
Host	smart-24f9574e-57cd-430b-a6a5-f14bf311d558
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480458642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_tl_errors.3480458642
Directory	/workspace/10.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3657964681
Short name	T979
Test name
Test status
Simulation time	38277438 ps
CPU time	1.28 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200616 kb
Host	smart-29063d3a-6290-4b22-ab15-3d45e1ac7b0a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657964681 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3657964681
Directory	/workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2742428012
Short name	T913
Test name
Test status
Simulation time	26343440 ps
CPU time	0.89 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	200540 kb
Host	smart-dc63f8f4-38a6-4540-808d-47bb2fcf2528
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742428012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .clkmgr_csr_rw.2742428012
Directory	/workspace/11.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.683621733
Short name	T952
Test name
Test status
Simulation time	34888963 ps
CPU time	0.73 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	199096 kb
Host	smart-2265dd09-704e-477f-a37c-3de191467bb8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683621733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk mgr_intr_test.683621733
Directory	/workspace/11.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.349906306
Short name	T890
Test name
Test status
Simulation time	35284438 ps
CPU time	1.12 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200568 kb
Host	smart-ef937327-a107-48b0-966f-c6ef1abbeca8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349906306 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 11.clkmgr_same_csr_outstanding.349906306
Directory	/workspace/11.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2330171560
Short name	T136
Test name
Test status
Simulation time	62928431 ps
CPU time	1.27 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:57 PM PDT 24
Peak memory	200892 kb
Host	smart-17ccbcd3-c7b3-450e-81c9-bfdbe4ca6955
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330171560 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.clkmgr_shadow_reg_errors.2330171560
Directory	/workspace/11.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3768077213
Short name	T988
Test name
Test status
Simulation time	111063989 ps
CPU time	2.59 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:58 PM PDT 24
Peak memory	209188 kb
Host	smart-03c9c345-55db-4dba-b9f3-98be47124d1b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768077213 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3768077213
Directory	/workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3895936968
Short name	T898
Test name
Test status
Simulation time	1272566300 ps
CPU time	5.11 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:31:02 PM PDT 24
Peak memory	200624 kb
Host	smart-a00a1a36-c475-4926-9e38-40db92acf1ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895936968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_tl_errors.3895936968
Directory	/workspace/11.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1463114896
Short name	T893
Test name
Test status
Simulation time	95088557 ps
CPU time	1.85 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:58 PM PDT 24
Peak memory	200696 kb
Host	smart-167aef7d-0e19-4787-ac7e-d1bc8d68e45c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463114896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 11.clkmgr_tl_intg_err.1463114896
Directory	/workspace/11.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1110626821
Short name	T903
Test name
Test status
Simulation time	67959162 ps
CPU time	1.05 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200652 kb
Host	smart-1c009cab-3ef3-47cf-96d1-a174b497e77c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110626821 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.1110626821
Directory	/workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1479971309
Short name	T948
Test name
Test status
Simulation time	55079599 ps
CPU time	0.82 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200532 kb
Host	smart-6875de34-7ecb-4514-9f8c-3eb062def855
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479971309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .clkmgr_csr_rw.1479971309
Directory	/workspace/12.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1784770915
Short name	T930
Test name
Test status
Simulation time	14718140 ps
CPU time	0.66 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	199060 kb
Host	smart-674f19d7-4e67-4eab-aa12-03d60087fccb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784770915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.1784770915
Directory	/workspace/12.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.4091453227
Short name	T982
Test name
Test status
Simulation time	154576838 ps
CPU time	1.59 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200676 kb
Host	smart-698ed47f-5af5-4737-9d5a-973b6eda2f8e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091453227 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.clkmgr_same_csr_outstanding.4091453227
Directory	/workspace/12.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1740883979
Short name	T69
Test name
Test status
Simulation time	106799366 ps
CPU time	2.07 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	217152 kb
Host	smart-4260a88f-baf5-4431-bb37-3f96fafacdc3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740883979 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 12.clkmgr_shadow_reg_errors.1740883979
Directory	/workspace/12.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2811129753
Short name	T976
Test name
Test status
Simulation time	401140658 ps
CPU time	2.67 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:10 PM PDT 24
Peak memory	201060 kb
Host	smart-e360452a-446e-4c64-ac81-fe71ea206009
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811129753 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.2811129753
Directory	/workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1669651800
Short name	T867
Test name
Test status
Simulation time	26559720 ps
CPU time	1.79 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200620 kb
Host	smart-cd6ca4de-c7d1-4a4d-8802-1d76d5a8a1c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669651800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_tl_errors.1669651800
Directory	/workspace/12.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1228877451
Short name	T124
Test name
Test status
Simulation time	391496100 ps
CPU time	3.17 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	200632 kb
Host	smart-4d381d81-2ce1-4176-b968-48d0cd41c977
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228877451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.clkmgr_tl_intg_err.1228877451
Directory	/workspace/12.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2833737400
Short name	T854
Test name
Test status
Simulation time	24480462 ps
CPU time	0.94 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:13 PM PDT 24
Peak memory	200612 kb
Host	smart-ec1a7e82-25a5-4f23-9e0d-ff58a1badba7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833737400 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.2833737400
Directory	/workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2051245918
Short name	T969
Test name
Test status
Simulation time	34460176 ps
CPU time	0.94 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	200532 kb
Host	smart-2b6b2646-23c7-435b-83c7-4bb31f9cca67
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051245918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .clkmgr_csr_rw.2051245918
Directory	/workspace/13.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.679797148
Short name	T995
Test name
Test status
Simulation time	26077377 ps
CPU time	0.7 seconds
Started	Jul 18 06:31:10 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	199156 kb
Host	smart-05847d16-b93a-4581-bd20-2484a51da130
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679797148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk mgr_intr_test.679797148
Directory	/workspace/13.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4285230053
Short name	T891
Test name
Test status
Simulation time	89662511 ps
CPU time	1.5 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200524 kb
Host	smart-59106e07-7ffb-465f-88ee-85bb455535bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285230053 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.clkmgr_same_csr_outstanding.4285230053
Directory	/workspace/13.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3221363200
Short name	T149
Test name
Test status
Simulation time	291007101 ps
CPU time	2.22 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:22 PM PDT 24
Peak memory	200488 kb
Host	smart-f7805150-763e-40e2-9e73-855b84216a55
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221363200 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.3221363200
Directory	/workspace/13.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.228502768
Short name	T72
Test name
Test status
Simulation time	266886237 ps
CPU time	3.67 seconds
Started	Jul 18 06:31:09 PM PDT 24
Finished	Jul 18 06:31:18 PM PDT 24
Peak memory	209000 kb
Host	smart-17d084b6-f4b4-4b16-8339-614cebf5a7e8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228502768 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.228502768
Directory	/workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2026950459
Short name	T964
Test name
Test status
Simulation time	173026524 ps
CPU time	3.12 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:17 PM PDT 24
Peak memory	200752 kb
Host	smart-faa6624e-5e27-4a04-90aa-945a43971355
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026950459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_tl_errors.2026950459
Directory	/workspace/13.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.501697188
Short name	T120
Test name
Test status
Simulation time	102851820 ps
CPU time	2.53 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	200576 kb
Host	smart-61dae103-3807-40ce-a684-bf9dda8e46b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501697188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.clkmgr_tl_intg_err.501697188
Directory	/workspace/13.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1286671327
Short name	T1008
Test name
Test status
Simulation time	87598855 ps
CPU time	1.62 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	200668 kb
Host	smart-2227c164-f2b5-4708-af0a-af751202ca55
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286671327 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.1286671327
Directory	/workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2592599567
Short name	T985
Test name
Test status
Simulation time	76709469 ps
CPU time	0.97 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:13 PM PDT 24
Peak memory	200520 kb
Host	smart-91315b71-e681-4157-9322-08075666561d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592599567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .clkmgr_csr_rw.2592599567
Directory	/workspace/14.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.266979493
Short name	T933
Test name
Test status
Simulation time	33373420 ps
CPU time	0.72 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	199084 kb
Host	smart-4a273d9b-af06-453a-b814-d07135c9808f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266979493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk mgr_intr_test.266979493
Directory	/workspace/14.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1825399915
Short name	T955
Test name
Test status
Simulation time	31391556 ps
CPU time	1.06 seconds
Started	Jul 18 06:31:12 PM PDT 24
Finished	Jul 18 06:31:18 PM PDT 24
Peak memory	200560 kb
Host	smart-8531ebe4-df74-4f33-ac65-bb2a497ce391
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825399915 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.clkmgr_same_csr_outstanding.1825399915
Directory	/workspace/14.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3334444043
Short name	T141
Test name
Test status
Simulation time	464672214 ps
CPU time	3.8 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	201320 kb
Host	smart-2d545865-8f28-4d0b-a73b-455116f00db2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334444043 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.3334444043
Directory	/workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2949541763
Short name	T907
Test name
Test status
Simulation time	467958092 ps
CPU time	4 seconds
Started	Jul 18 06:31:10 PM PDT 24
Finished	Jul 18 06:31:19 PM PDT 24
Peak memory	200704 kb
Host	smart-a99cdb1e-e539-4ba6-850c-c4e9e1b652af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949541763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.2949541763
Directory	/workspace/14.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2837229467
Short name	T116
Test name
Test status
Simulation time	1051657418 ps
CPU time	4.71 seconds
Started	Jul 18 06:31:05 PM PDT 24
Finished	Jul 18 06:31:17 PM PDT 24
Peak memory	200644 kb
Host	smart-87f88449-d492-41f3-800d-87d115d1c9a8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837229467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.clkmgr_tl_intg_err.2837229467
Directory	/workspace/14.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3740692570
Short name	T991
Test name
Test status
Simulation time	30162802 ps
CPU time	1.52 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:22 PM PDT 24
Peak memory	200600 kb
Host	smart-6fcd150a-db9c-4c4d-a983-09460361fce8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740692570 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.3740692570
Directory	/workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.3918375872
Short name	T899
Test name
Test status
Simulation time	52591993 ps
CPU time	0.88 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200528 kb
Host	smart-9ed6c6a1-5135-4d66-b5d9-1643d6e95270
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918375872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .clkmgr_csr_rw.3918375872
Directory	/workspace/15.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.272211444
Short name	T1003
Test name
Test status
Simulation time	29869233 ps
CPU time	0.73 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	199092 kb
Host	smart-7dc8dabb-8267-4913-a9b3-10c0b36e78d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272211444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk mgr_intr_test.272211444
Directory	/workspace/15.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1846388913
Short name	T93
Test name
Test status
Simulation time	59802530 ps
CPU time	1.13 seconds
Started	Jul 18 06:31:10 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	200476 kb
Host	smart-b29084a0-ed41-4bf0-ab8a-01866c46d30a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846388913 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.clkmgr_same_csr_outstanding.1846388913
Directory	/workspace/15.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.212514621
Short name	T137
Test name
Test status
Simulation time	98498549 ps
CPU time	1.96 seconds
Started	Jul 18 06:31:05 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	209284 kb
Host	smart-afd96c9f-2b61-4435-aeab-f1a10f18ac2c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212514621 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.212514621
Directory	/workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.943170336
Short name	T953
Test name
Test status
Simulation time	69308815 ps
CPU time	2.07 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200608 kb
Host	smart-053733db-7bea-484c-8005-3298c7d32b8f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943170336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk mgr_tl_errors.943170336
Directory	/workspace/15.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1461531768
Short name	T123
Test name
Test status
Simulation time	136016026 ps
CPU time	2.71 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	200680 kb
Host	smart-1f25e3eb-3e81-4ce1-a335-74da6abd9861
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461531768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.clkmgr_tl_intg_err.1461531768
Directory	/workspace/15.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3791321146
Short name	T1002
Test name
Test status
Simulation time	36860034 ps
CPU time	1.86 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	200776 kb
Host	smart-e788566a-683c-48e1-a8ab-5b4309aa0196
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791321146 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3791321146
Directory	/workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2679790751
Short name	T871
Test name
Test status
Simulation time	32536002 ps
CPU time	0.76 seconds
Started	Jul 18 06:31:09 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200424 kb
Host	smart-fbf0b6f4-4889-4d02-bc89-053a3494ac2d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679790751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .clkmgr_csr_rw.2679790751
Directory	/workspace/16.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3372872991
Short name	T894
Test name
Test status
Simulation time	27707178 ps
CPU time	0.69 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:21 PM PDT 24
Peak memory	199108 kb
Host	smart-b34991a6-5526-4b68-9e5f-a9959ac31688
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372872991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_intr_test.3372872991
Directory	/workspace/16.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1245188926
Short name	T877
Test name
Test status
Simulation time	158223676 ps
CPU time	1.49 seconds
Started	Jul 18 06:31:17 PM PDT 24
Finished	Jul 18 06:31:20 PM PDT 24
Peak memory	200588 kb
Host	smart-cf94c73a-1748-4100-881b-d04374aa5901
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245188926 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.clkmgr_same_csr_outstanding.1245188926
Directory	/workspace/16.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3122282739
Short name	T1009
Test name
Test status
Simulation time	98750222 ps
CPU time	1.44 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	200912 kb
Host	smart-c5ae73e4-56f1-42e5-814b-52b2e7411503
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122282739 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.clkmgr_shadow_reg_errors.3122282739
Directory	/workspace/16.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2050658040
Short name	T966
Test name
Test status
Simulation time	66328437 ps
CPU time	1.71 seconds
Started	Jul 18 06:31:04 PM PDT 24
Finished	Jul 18 06:31:13 PM PDT 24
Peak memory	201040 kb
Host	smart-8c165e63-86a4-4ef0-85a3-efb392521d3c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050658040 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2050658040
Directory	/workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.4079653262
Short name	T947
Test name
Test status
Simulation time	338563670 ps
CPU time	3.18 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:23 PM PDT 24
Peak memory	200632 kb
Host	smart-f90c1765-bcfa-4188-b00c-32e81c933f2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079653262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_tl_errors.4079653262
Directory	/workspace/16.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2983421463
Short name	T113
Test name
Test status
Simulation time	388326029 ps
CPU time	2.56 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200668 kb
Host	smart-5a4c69c2-a1b1-4bdc-a369-42c296317847
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983421463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.clkmgr_tl_intg_err.2983421463
Directory	/workspace/16.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.2898533349
Short name	T937
Test name
Test status
Simulation time	127128383 ps
CPU time	1.47 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:21 PM PDT 24
Peak memory	200636 kb
Host	smart-ae73bb52-5cac-4da5-802e-61859248ca15
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898533349 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.2898533349
Directory	/workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2931096204
Short name	T89
Test name
Test status
Simulation time	18399214 ps
CPU time	0.81 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	200516 kb
Host	smart-d0f121cf-76dd-4d65-9c81-5bccf3132213
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931096204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .clkmgr_csr_rw.2931096204
Directory	/workspace/17.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1034098944
Short name	T875
Test name
Test status
Simulation time	13074772 ps
CPU time	0.67 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	199040 kb
Host	smart-c47bc503-1fb0-400e-85d5-69ec8a4592ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034098944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_intr_test.1034098944
Directory	/workspace/17.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1474862042
Short name	T91
Test name
Test status
Simulation time	100813801 ps
CPU time	1.19 seconds
Started	Jul 18 06:31:05 PM PDT 24
Finished	Jul 18 06:31:13 PM PDT 24
Peak memory	200544 kb
Host	smart-61521749-8101-4c5c-bfd6-adcf3235492f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474862042 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.clkmgr_same_csr_outstanding.1474862042
Directory	/workspace/17.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3539604980
Short name	T146
Test name
Test status
Simulation time	164117398 ps
CPU time	1.77 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200872 kb
Host	smart-6488f6b8-7f8e-4cef-8ce0-65af4092b918
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539604980 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.clkmgr_shadow_reg_errors.3539604980
Directory	/workspace/17.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2652067166
Short name	T980
Test name
Test status
Simulation time	231413284 ps
CPU time	3.26 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	209200 kb
Host	smart-15c9a5ec-2751-44f9-bade-200e4bea5d0d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652067166 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2652067166
Directory	/workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.494606675
Short name	T920
Test name
Test status
Simulation time	82746503 ps
CPU time	1.71 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200764 kb
Host	smart-d2997d54-076a-4bc1-b017-cc05a7eaaa6a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494606675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk mgr_tl_errors.494606675
Directory	/workspace/17.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.928090108
Short name	T185
Test name
Test status
Simulation time	95229168 ps
CPU time	2.49 seconds
Started	Jul 18 06:31:13 PM PDT 24
Finished	Jul 18 06:31:19 PM PDT 24
Peak memory	200636 kb
Host	smart-67b3b5d4-c19f-46d4-9621-d1f644177276
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928090108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.clkmgr_tl_intg_err.928090108
Directory	/workspace/17.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2839196367
Short name	T1006
Test name
Test status
Simulation time	47527474 ps
CPU time	1.07 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:15 PM PDT 24
Peak memory	200648 kb
Host	smart-cff78ba5-e151-47d7-af62-e8fa9e8b1071
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839196367 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.2839196367
Directory	/workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1468163660
Short name	T94
Test name
Test status
Simulation time	148745312 ps
CPU time	1.07 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:21 PM PDT 24
Peak memory	200092 kb
Host	smart-01280d2c-15a3-4d00-9b15-ffbeba2f4cc8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468163660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .clkmgr_csr_rw.1468163660
Directory	/workspace/18.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1624253459
Short name	T974
Test name
Test status
Simulation time	19165211 ps
CPU time	0.67 seconds
Started	Jul 18 06:31:07 PM PDT 24
Finished	Jul 18 06:31:14 PM PDT 24
Peak memory	199096 kb
Host	smart-0d0bbe17-af44-4e82-a655-c3f6c6d07fe0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624253459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_intr_test.1624253459
Directory	/workspace/18.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3576477254
Short name	T993
Test name
Test status
Simulation time	95007076 ps
CPU time	1.36 seconds
Started	Jul 18 06:31:10 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	200620 kb
Host	smart-a557e4eb-16d6-444a-a76e-5401dfb7ca08
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576477254 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.clkmgr_same_csr_outstanding.3576477254
Directory	/workspace/18.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1615966414
Short name	T135
Test name
Test status
Simulation time	146242521 ps
CPU time	1.9 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	209304 kb
Host	smart-0ea911cf-f25d-47eb-9292-623ae5b1b232
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615966414 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.clkmgr_shadow_reg_errors.1615966414
Directory	/workspace/18.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.544461431
Short name	T73
Test name
Test status
Simulation time	70364557 ps
CPU time	1.59 seconds
Started	Jul 18 06:31:17 PM PDT 24
Finished	Jul 18 06:31:19 PM PDT 24
Peak memory	201148 kb
Host	smart-33ce2e70-46f1-4ec8-8f07-c53c997a17c8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544461431 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.544461431
Directory	/workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.694939170
Short name	T936
Test name
Test status
Simulation time	399648050 ps
CPU time	3.35 seconds
Started	Jul 18 06:31:06 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	200644 kb
Host	smart-298eec88-cbcd-489c-aecf-0400122f1622
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694939170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk mgr_tl_errors.694939170
Directory	/workspace/18.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.66156177
Short name	T115
Test name
Test status
Simulation time	287741956 ps
CPU time	2.75 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:23 PM PDT 24
Peak memory	200660 kb
Host	smart-ed66d4f0-62db-4619-ac2f-ef23c51b55e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66156177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.clkmgr_tl_intg_err.66156177
Directory	/workspace/18.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1609107614
Short name	T855
Test name
Test status
Simulation time	162698014 ps
CPU time	1.36 seconds
Started	Jul 18 06:31:21 PM PDT 24
Finished	Jul 18 06:31:23 PM PDT 24
Peak memory	200640 kb
Host	smart-0eec989a-70f5-4e83-abd5-80bb530360fa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609107614 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.1609107614
Directory	/workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.30126983
Short name	T944
Test name
Test status
Simulation time	25083723 ps
CPU time	0.77 seconds
Started	Jul 18 06:31:24 PM PDT 24
Finished	Jul 18 06:31:27 PM PDT 24
Peak memory	200412 kb
Host	smart-953a8d4e-de9c-4778-859e-879849282aeb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30126983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_ SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.c lkmgr_csr_rw.30126983
Directory	/workspace/19.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3238736924
Short name	T897
Test name
Test status
Simulation time	21125386 ps
CPU time	0.66 seconds
Started	Jul 18 06:31:17 PM PDT 24
Finished	Jul 18 06:31:20 PM PDT 24
Peak memory	199108 kb
Host	smart-94e0f040-fb7e-4acf-9534-4cf50fdb95e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238736924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_intr_test.3238736924
Directory	/workspace/19.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.4279651041
Short name	T934
Test name
Test status
Simulation time	78999328 ps
CPU time	1.13 seconds
Started	Jul 18 06:31:24 PM PDT 24
Finished	Jul 18 06:31:28 PM PDT 24
Peak memory	200520 kb
Host	smart-6bc19b97-647f-470c-bdaf-ae7d3ae53f33
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279651041 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.clkmgr_same_csr_outstanding.4279651041
Directory	/workspace/19.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.4027317027
Short name	T65
Test name
Test status
Simulation time	244386504 ps
CPU time	2.22 seconds
Started	Jul 18 06:31:08 PM PDT 24
Finished	Jul 18 06:31:16 PM PDT 24
Peak memory	209336 kb
Host	smart-4d16ffad-e4ad-4aa7-bd3d-d577c0a38cf5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027317027 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.clkmgr_shadow_reg_errors.4027317027
Directory	/workspace/19.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3582791625
Short name	T926
Test name
Test status
Simulation time	194438413 ps
CPU time	1.79 seconds
Started	Jul 18 06:31:18 PM PDT 24
Finished	Jul 18 06:31:22 PM PDT 24
Peak memory	200560 kb
Host	smart-95b6bb48-961a-44a3-aafe-6a5f57b49b82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582791625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_tl_errors.3582791625
Directory	/workspace/19.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.858682848
Short name	T965
Test name
Test status
Simulation time	178591168 ps
CPU time	1.92 seconds
Started	Jul 18 06:31:17 PM PDT 24
Finished	Jul 18 06:31:21 PM PDT 24
Peak memory	200664 kb
Host	smart-7af68677-86fc-4e1f-a445-e9ae6b649589
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858682848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.clkmgr_tl_intg_err.858682848
Directory	/workspace/19.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3370883352
Short name	T864
Test name
Test status
Simulation time	68690501 ps
CPU time	1.25 seconds
Started	Jul 18 06:30:49 PM PDT 24
Finished	Jul 18 06:30:54 PM PDT 24
Peak memory	200544 kb
Host	smart-42ce769c-13e4-4df9-8c1a-56930b51daa9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370883352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_aliasing.3370883352
Directory	/workspace/2.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.521508305
Short name	T972
Test name
Test status
Simulation time	394702381 ps
CPU time	6.67 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:10 PM PDT 24
Peak memory	200592 kb
Host	smart-b02818ec-5072-4d9c-8e33-faedf1c8bf99
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521508305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.clkmgr_csr_bit_bash.521508305
Directory	/workspace/2.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1795202555
Short name	T119
Test name
Test status
Simulation time	56611052 ps
CPU time	0.89 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200528 kb
Host	smart-d919d5f4-3076-42ea-9a2b-cf8cd5ff4231
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795202555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_hw_reset.1795202555
Directory	/workspace/2.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1091820236
Short name	T860
Test name
Test status
Simulation time	163207192 ps
CPU time	1.65 seconds
Started	Jul 18 06:30:51 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200612 kb
Host	smart-091cb8c0-997a-4ef4-8b89-9f50ce405cf2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091820236 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1091820236
Directory	/workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.341797576
Short name	T996
Test name
Test status
Simulation time	17304360 ps
CPU time	0.86 seconds
Started	Jul 18 06:30:49 PM PDT 24
Finished	Jul 18 06:30:53 PM PDT 24
Peak memory	200516 kb
Host	smart-36220a75-5d86-46f5-9a77-5bd9379590b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341797576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.c lkmgr_csr_rw.341797576
Directory	/workspace/2.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3198062967
Short name	T910
Test name
Test status
Simulation time	23192630 ps
CPU time	0.66 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:57 PM PDT 24
Peak memory	199076 kb
Host	smart-42706a21-3af1-45a6-975c-ef51b18d33ad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198062967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_intr_test.3198062967
Directory	/workspace/2.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.477876832
Short name	T989
Test name
Test status
Simulation time	48822482 ps
CPU time	1.04 seconds
Started	Jul 18 06:30:52 PM PDT 24
Finished	Jul 18 06:30:55 PM PDT 24
Peak memory	200568 kb
Host	smart-493c24ae-a1ef-400d-a5d9-a2f3769da383
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477876832 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.clkmgr_same_csr_outstanding.477876832
Directory	/workspace/2.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1510975760
Short name	T70
Test name
Test status
Simulation time	75318522 ps
CPU time	1.4 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200876 kb
Host	smart-725ed1ed-acf7-401a-a593-b36d38533e85
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510975760 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.clkmgr_shadow_reg_errors.1510975760
Directory	/workspace/2.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1847054070
Short name	T66
Test name
Test status
Simulation time	134990736 ps
CPU time	1.85 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	201076 kb
Host	smart-7f57fab2-7640-4e73-8927-625a1dc162da
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847054070 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.1847054070
Directory	/workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.4248497703
Short name	T906
Test name
Test status
Simulation time	903189288 ps
CPU time	5.19 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:10 PM PDT 24
Peak memory	200620 kb
Host	smart-04ef32de-d480-4db9-af60-e0440d4abc8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248497703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_tl_errors.4248497703
Directory	/workspace/2.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.2383990388
Short name	T126
Test name
Test status
Simulation time	153711812 ps
CPU time	2.98 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200652 kb
Host	smart-82227c36-3616-4506-a8cb-0a905b6a98e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383990388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.clkmgr_tl_intg_err.2383990388
Directory	/workspace/2.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3635624116
Short name	T994
Test name
Test status
Simulation time	19147895 ps
CPU time	0.7 seconds
Started	Jul 18 06:31:22 PM PDT 24
Finished	Jul 18 06:31:25 PM PDT 24
Peak memory	199164 kb
Host	smart-3a430f72-10c2-4e0b-a679-a35d5bdb9d4e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635624116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl kmgr_intr_test.3635624116
Directory	/workspace/20.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.632080415
Short name	T931
Test name
Test status
Simulation time	20396057 ps
CPU time	0.7 seconds
Started	Jul 18 06:31:21 PM PDT 24
Finished	Jul 18 06:31:23 PM PDT 24
Peak memory	199124 kb
Host	smart-d5572990-fdde-4d3d-9829-3eb35710b051
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632080415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clk mgr_intr_test.632080415
Directory	/workspace/21.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.2129954381
Short name	T984
Test name
Test status
Simulation time	76638432 ps
CPU time	0.86 seconds
Started	Jul 18 06:31:25 PM PDT 24
Finished	Jul 18 06:31:28 PM PDT 24
Peak memory	199108 kb
Host	smart-b81c3e0e-9fe7-4028-9108-7e49ba856d34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129954381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl kmgr_intr_test.2129954381
Directory	/workspace/22.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2141326374
Short name	T1005
Test name
Test status
Simulation time	41937601 ps
CPU time	0.76 seconds
Started	Jul 18 06:31:20 PM PDT 24
Finished	Jul 18 06:31:22 PM PDT 24
Peak memory	199108 kb
Host	smart-5c0043cd-7946-49cc-8608-7fd343b16f29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141326374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl kmgr_intr_test.2141326374
Directory	/workspace/23.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.133007160
Short name	T887
Test name
Test status
Simulation time	16776430 ps
CPU time	0.69 seconds
Started	Jul 18 06:31:25 PM PDT 24
Finished	Jul 18 06:31:28 PM PDT 24
Peak memory	199176 kb
Host	smart-be04125d-ffc5-4da2-a28c-31095fae5fce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133007160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk mgr_intr_test.133007160
Directory	/workspace/24.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.134112576
Short name	T957
Test name
Test status
Simulation time	14391013 ps
CPU time	0.72 seconds
Started	Jul 18 06:31:22 PM PDT 24
Finished	Jul 18 06:31:25 PM PDT 24
Peak memory	199176 kb
Host	smart-d75751dd-744c-45eb-8f0e-9a3200064828
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134112576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk mgr_intr_test.134112576
Directory	/workspace/25.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.4233146522
Short name	T884
Test name
Test status
Simulation time	12985201 ps
CPU time	0.66 seconds
Started	Jul 18 06:31:25 PM PDT 24
Finished	Jul 18 06:31:28 PM PDT 24
Peak memory	199092 kb
Host	smart-7f77a482-d67a-44c3-942f-a121634567d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233146522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl kmgr_intr_test.4233146522
Directory	/workspace/26.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.321509476
Short name	T904
Test name
Test status
Simulation time	14074834 ps
CPU time	0.66 seconds
Started	Jul 18 06:31:21 PM PDT 24
Finished	Jul 18 06:31:24 PM PDT 24
Peak memory	199080 kb
Host	smart-3631503c-8d79-4cb0-b1fb-9be0d45bd0ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321509476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clk mgr_intr_test.321509476
Directory	/workspace/27.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1645393869
Short name	T981
Test name
Test status
Simulation time	13011710 ps
CPU time	0.7 seconds
Started	Jul 18 06:31:21 PM PDT 24
Finished	Jul 18 06:31:24 PM PDT 24
Peak memory	199096 kb
Host	smart-3f6b233c-29b8-40c3-9d2c-f91f4a615fd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645393869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl kmgr_intr_test.1645393869
Directory	/workspace/28.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.474429331
Short name	T990
Test name
Test status
Simulation time	26647041 ps
CPU time	0.73 seconds
Started	Jul 18 06:31:24 PM PDT 24
Finished	Jul 18 06:31:27 PM PDT 24
Peak memory	199268 kb
Host	smart-af592e86-4c17-4e8a-8deb-4de692c94e35
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474429331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk mgr_intr_test.474429331
Directory	/workspace/29.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.429400294
Short name	T882
Test name
Test status
Simulation time	28327724 ps
CPU time	1.48 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200636 kb
Host	smart-90bb7989-594e-4a1b-b556-a8fbdb22da87
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429400294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.clkmgr_csr_aliasing.429400294
Directory	/workspace/3.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.579100155
Short name	T118
Test name
Test status
Simulation time	1369806723 ps
CPU time	8.57 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:11 PM PDT 24
Peak memory	200640 kb
Host	smart-bfd3b0b2-9b6a-4bb2-94d2-c53bc2124776
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579100155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.clkmgr_csr_bit_bash.579100155
Directory	/workspace/3.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2287769975
Short name	T918
Test name
Test status
Simulation time	42934572 ps
CPU time	0.86 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:30:59 PM PDT 24
Peak memory	200468 kb
Host	smart-2d1d5f50-4070-457e-b8c7-a2df94b386a4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287769975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.2287769975
Directory	/workspace/3.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.536179341
Short name	T919
Test name
Test status
Simulation time	33966643 ps
CPU time	1.15 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:30:58 PM PDT 24
Peak memory	200648 kb
Host	smart-04b55867-7183-40f2-bc0b-2d49e56f0419
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536179341 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.536179341
Directory	/workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3511333197
Short name	T905
Test name
Test status
Simulation time	21209878 ps
CPU time	0.82 seconds
Started	Jul 18 06:30:52 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200512 kb
Host	smart-7fc5cc9a-5597-4616-9279-7bcdc64cf55e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511333197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. clkmgr_csr_rw.3511333197
Directory	/workspace/3.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1349826776
Short name	T921
Test name
Test status
Simulation time	13769992 ps
CPU time	0.71 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	199064 kb
Host	smart-46db1472-11e7-4a39-9ce5-a83adf3dc05e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349826776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_intr_test.1349826776
Directory	/workspace/3.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1883420877
Short name	T986
Test name
Test status
Simulation time	47905350 ps
CPU time	0.99 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:58 PM PDT 24
Peak memory	200484 kb
Host	smart-81f51b18-79cc-4f15-8fc4-ceaa17558f6e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883420877 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.clkmgr_same_csr_outstanding.1883420877
Directory	/workspace/3.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.78094923
Short name	T1000
Test name
Test status
Simulation time	235401396 ps
CPU time	2.16 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:31:00 PM PDT 24
Peak memory	209200 kb
Host	smart-d0061510-8d0e-4708-adee-3f373863248a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78094923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_ test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.clkmgr_shadow_reg_errors.78094923
Directory	/workspace/3.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2928419844
Short name	T997
Test name
Test status
Simulation time	82870817 ps
CPU time	1.83 seconds
Started	Jul 18 06:30:51 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	209136 kb
Host	smart-93564a95-a091-41ec-a82d-07b3d133f8e6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928419844 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.2928419844
Directory	/workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2611448214
Short name	T895
Test name
Test status
Simulation time	264565891 ps
CPU time	2.42 seconds
Started	Jul 18 06:30:55 PM PDT 24
Finished	Jul 18 06:31:02 PM PDT 24
Peak memory	200668 kb
Host	smart-8fe5aeba-46bc-4d4b-8025-35009338c658
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611448214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_tl_errors.2611448214
Directory	/workspace/3.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.672405149
Short name	T942
Test name
Test status
Simulation time	172663962 ps
CPU time	2.83 seconds
Started	Jul 18 06:30:50 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200748 kb
Host	smart-7c10ed9e-d575-4728-8b6f-808c530ea9e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672405149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.clkmgr_tl_intg_err.672405149
Directory	/workspace/3.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2051696055
Short name	T945
Test name
Test status
Simulation time	39123173 ps
CPU time	0.72 seconds
Started	Jul 18 06:31:22 PM PDT 24
Finished	Jul 18 06:31:25 PM PDT 24
Peak memory	199088 kb
Host	smart-287093b1-2d18-4955-baa9-024f73d1aedb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051696055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl kmgr_intr_test.2051696055
Directory	/workspace/30.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3498442009
Short name	T914
Test name
Test status
Simulation time	17255571 ps
CPU time	0.67 seconds
Started	Jul 18 06:31:23 PM PDT 24
Finished	Jul 18 06:31:26 PM PDT 24
Peak memory	199096 kb
Host	smart-bf2c7b40-20d7-41ea-83a1-8db504f7dac1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498442009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl kmgr_intr_test.3498442009
Directory	/workspace/31.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1321039087
Short name	T977
Test name
Test status
Simulation time	11770193 ps
CPU time	0.67 seconds
Started	Jul 18 06:31:23 PM PDT 24
Finished	Jul 18 06:31:26 PM PDT 24
Peak memory	199084 kb
Host	smart-f5f53098-58c8-4cb8-ace0-1961ec10c543
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321039087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl kmgr_intr_test.1321039087
Directory	/workspace/32.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.207112680
Short name	T858
Test name
Test status
Simulation time	20314404 ps
CPU time	0.66 seconds
Started	Jul 18 06:31:24 PM PDT 24
Finished	Jul 18 06:31:27 PM PDT 24
Peak memory	199096 kb
Host	smart-d862f06a-9ec9-4cca-a064-bffe97780924
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207112680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clk mgr_intr_test.207112680
Directory	/workspace/33.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1523306391
Short name	T963
Test name
Test status
Simulation time	25238607 ps
CPU time	0.69 seconds
Started	Jul 18 06:31:28 PM PDT 24
Finished	Jul 18 06:31:30 PM PDT 24
Peak memory	199172 kb
Host	smart-0d667cec-946c-485e-bd37-8d1189613f95
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523306391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl kmgr_intr_test.1523306391
Directory	/workspace/34.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.120099635
Short name	T967
Test name
Test status
Simulation time	13739544 ps
CPU time	0.69 seconds
Started	Jul 18 06:31:23 PM PDT 24
Finished	Jul 18 06:31:27 PM PDT 24
Peak memory	199156 kb
Host	smart-1a4ba476-38fb-42f3-a828-c5e9a4f58fdb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120099635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk mgr_intr_test.120099635
Directory	/workspace/35.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4113778598
Short name	T938
Test name
Test status
Simulation time	15748068 ps
CPU time	0.64 seconds
Started	Jul 18 06:31:24 PM PDT 24
Finished	Jul 18 06:31:27 PM PDT 24
Peak memory	199092 kb
Host	smart-c199d1d8-37e9-4469-8187-5844e733f0c2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113778598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl kmgr_intr_test.4113778598
Directory	/workspace/36.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2941518439
Short name	T943
Test name
Test status
Simulation time	156503947 ps
CPU time	1 seconds
Started	Jul 18 06:31:23 PM PDT 24
Finished	Jul 18 06:31:27 PM PDT 24
Peak memory	199056 kb
Host	smart-0e13c2a7-38f0-45c3-ad34-a9bc3b9d9442
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941518439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl kmgr_intr_test.2941518439
Directory	/workspace/37.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.252132109
Short name	T859
Test name
Test status
Simulation time	29669752 ps
CPU time	0.71 seconds
Started	Jul 18 06:31:26 PM PDT 24
Finished	Jul 18 06:31:29 PM PDT 24
Peak memory	199208 kb
Host	smart-154d7c50-0900-4273-be7d-44ced2284cd7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252132109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clk mgr_intr_test.252132109
Directory	/workspace/38.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1167012262
Short name	T987
Test name
Test status
Simulation time	24787401 ps
CPU time	0.68 seconds
Started	Jul 18 06:31:24 PM PDT 24
Finished	Jul 18 06:31:27 PM PDT 24
Peak memory	198988 kb
Host	smart-0a07b210-65f7-4a6f-8a60-41bcb7951302
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167012262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl kmgr_intr_test.1167012262
Directory	/workspace/39.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.4247115836
Short name	T902
Test name
Test status
Simulation time	79713042 ps
CPU time	1.39 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	200464 kb
Host	smart-061cb07c-24af-41df-9f2e-e2c2c93ceb93
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247115836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_aliasing.4247115836
Directory	/workspace/4.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.873380402
Short name	T883
Test name
Test status
Simulation time	538438407 ps
CPU time	8.73 seconds
Started	Jul 18 06:30:51 PM PDT 24
Finished	Jul 18 06:31:02 PM PDT 24
Peak memory	200824 kb
Host	smart-78195067-9db4-43cb-83c5-7a72fc14bf68
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873380402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.clkmgr_csr_bit_bash.873380402
Directory	/workspace/4.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.632586636
Short name	T878
Test name
Test status
Simulation time	208750774 ps
CPU time	1.25 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:30:59 PM PDT 24
Peak memory	200500 kb
Host	smart-4fdd2953-c8a0-444a-af4f-c706ae058cd9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632586636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.clkmgr_csr_hw_reset.632586636
Directory	/workspace/4.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3839785735
Short name	T925
Test name
Test status
Simulation time	28210052 ps
CPU time	1.33 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200644 kb
Host	smart-1dd907ea-9e17-4e08-9940-bf9d112df0c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839785735 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.3839785735
Directory	/workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.4267817706
Short name	T971
Test name
Test status
Simulation time	57734218 ps
CPU time	0.89 seconds
Started	Jul 18 06:30:56 PM PDT 24
Finished	Jul 18 06:31:03 PM PDT 24
Peak memory	200512 kb
Host	smart-414ee745-75c2-44c1-820f-bbed1916ed4a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267817706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.4267817706
Directory	/workspace/4.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1163131025
Short name	T909
Test name
Test status
Simulation time	35686458 ps
CPU time	0.72 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	199092 kb
Host	smart-df639b94-bd4f-46d8-96ed-f4f5c4d0c4d9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163131025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.1163131025
Directory	/workspace/4.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3081655088
Short name	T95
Test name
Test status
Simulation time	97116638 ps
CPU time	1.17 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:30:58 PM PDT 24
Peak memory	200564 kb
Host	smart-2f3d1e00-0e8d-4123-8818-4ffdc09b2eb2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081655088 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.clkmgr_same_csr_outstanding.3081655088
Directory	/workspace/4.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.832560387
Short name	T928
Test name
Test status
Simulation time	66308389 ps
CPU time	1.48 seconds
Started	Jul 18 06:30:54 PM PDT 24
Finished	Jul 18 06:31:00 PM PDT 24
Peak memory	209068 kb
Host	smart-c11e1ba3-c709-4c56-86cf-0a7510026a83
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832560387 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.clkmgr_shadow_reg_errors.832560387
Directory	/workspace/4.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2551737094
Short name	T71
Test name
Test status
Simulation time	120572411 ps
CPU time	2.41 seconds
Started	Jul 18 06:30:50 PM PDT 24
Finished	Jul 18 06:30:55 PM PDT 24
Peak memory	201296 kb
Host	smart-850338ac-a5c3-4641-ba1f-ee509606a5a5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551737094 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2551737094
Directory	/workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2495459206
Short name	T941
Test name
Test status
Simulation time	45782925 ps
CPU time	2.6 seconds
Started	Jul 18 06:30:55 PM PDT 24
Finished	Jul 18 06:31:02 PM PDT 24
Peak memory	200660 kb
Host	smart-baa5680d-b942-4b05-ae49-d2eb6c07c303
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495459206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.2495459206
Directory	/workspace/4.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1787674966
Short name	T117
Test name
Test status
Simulation time	225365812 ps
CPU time	2.1 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200584 kb
Host	smart-151825a2-49ca-4cfd-9b2d-5460309617ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787674966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.1787674966
Directory	/workspace/4.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3124359643
Short name	T857
Test name
Test status
Simulation time	11463408 ps
CPU time	0.66 seconds
Started	Jul 18 06:31:20 PM PDT 24
Finished	Jul 18 06:31:22 PM PDT 24
Peak memory	199052 kb
Host	smart-a4a95b63-9976-4f45-935f-876df3301c7a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124359643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl kmgr_intr_test.3124359643
Directory	/workspace/40.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.909014794
Short name	T869
Test name
Test status
Simulation time	12398419 ps
CPU time	0.66 seconds
Started	Jul 18 06:31:22 PM PDT 24
Finished	Jul 18 06:31:25 PM PDT 24
Peak memory	199160 kb
Host	smart-049c6f82-f33e-4eb6-96f2-d9fb052b4027
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909014794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk mgr_intr_test.909014794
Directory	/workspace/41.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.4123571685
Short name	T923
Test name
Test status
Simulation time	22924090 ps
CPU time	0.68 seconds
Started	Jul 18 06:31:21 PM PDT 24
Finished	Jul 18 06:31:22 PM PDT 24
Peak memory	199140 kb
Host	smart-2cec83a7-f98b-4a88-86d8-49bfb234d7a0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123571685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl kmgr_intr_test.4123571685
Directory	/workspace/42.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1790518214
Short name	T962
Test name
Test status
Simulation time	25408235 ps
CPU time	0.69 seconds
Started	Jul 18 06:31:45 PM PDT 24
Finished	Jul 18 06:31:49 PM PDT 24
Peak memory	199160 kb
Host	smart-84ef237d-ee67-43bb-934f-bfa6438d7eb2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790518214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl kmgr_intr_test.1790518214
Directory	/workspace/43.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1630112447
Short name	T866
Test name
Test status
Simulation time	22403042 ps
CPU time	0.74 seconds
Started	Jul 18 06:31:48 PM PDT 24
Finished	Jul 18 06:31:52 PM PDT 24
Peak memory	199124 kb
Host	smart-047c42df-2033-4024-a02c-260f98fee319
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630112447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl kmgr_intr_test.1630112447
Directory	/workspace/44.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2552554578
Short name	T862
Test name
Test status
Simulation time	18293858 ps
CPU time	0.69 seconds
Started	Jul 18 06:31:42 PM PDT 24
Finished	Jul 18 06:31:46 PM PDT 24
Peak memory	199080 kb
Host	smart-7aa5e6d0-aec9-4ebd-8acd-caf54047d13f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552554578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl kmgr_intr_test.2552554578
Directory	/workspace/45.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1080675276
Short name	T917
Test name
Test status
Simulation time	39576360 ps
CPU time	0.76 seconds
Started	Jul 18 06:31:41 PM PDT 24
Finished	Jul 18 06:31:44 PM PDT 24
Peak memory	199192 kb
Host	smart-a4c40349-c93a-4b3f-bc31-ffd2fca8a098
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080675276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl kmgr_intr_test.1080675276
Directory	/workspace/46.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1285884797
Short name	T853
Test name
Test status
Simulation time	26041823 ps
CPU time	0.68 seconds
Started	Jul 18 06:31:50 PM PDT 24
Finished	Jul 18 06:31:54 PM PDT 24
Peak memory	199076 kb
Host	smart-1881e83e-1ed2-45b0-bc50-c4bf866c7d2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285884797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.1285884797
Directory	/workspace/47.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.4055170312
Short name	T880
Test name
Test status
Simulation time	32566770 ps
CPU time	0.76 seconds
Started	Jul 18 06:31:47 PM PDT 24
Finished	Jul 18 06:31:52 PM PDT 24
Peak memory	199072 kb
Host	smart-17906384-0c1c-4302-947f-c49f6cb82ec0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055170312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl kmgr_intr_test.4055170312
Directory	/workspace/48.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1054918047
Short name	T863
Test name
Test status
Simulation time	13962827 ps
CPU time	0.72 seconds
Started	Jul 18 06:31:48 PM PDT 24
Finished	Jul 18 06:31:52 PM PDT 24
Peak memory	199060 kb
Host	smart-2d08e7d9-1c98-41aa-93cd-52beee5eeb6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054918047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl kmgr_intr_test.1054918047
Directory	/workspace/49.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.4065115890
Short name	T1007
Test name
Test status
Simulation time	26037055 ps
CPU time	1.05 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200568 kb
Host	smart-0dbce2f3-cd20-46ec-a7ed-1369d61b293f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065115890 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.4065115890
Directory	/workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2202118308
Short name	T1001
Test name
Test status
Simulation time	36167039 ps
CPU time	0.9 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	200452 kb
Host	smart-206aa360-c5cf-469e-8927-5bc12a8c0cc0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202118308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.2202118308
Directory	/workspace/5.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2021585560
Short name	T940
Test name
Test status
Simulation time	14586813 ps
CPU time	0.67 seconds
Started	Jul 18 06:30:56 PM PDT 24
Finished	Jul 18 06:31:03 PM PDT 24
Peak memory	199080 kb
Host	smart-8afdf845-1c76-4055-b3c5-c2452ae1b3b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021585560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_intr_test.2021585560
Directory	/workspace/5.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2916810951
Short name	T908
Test name
Test status
Simulation time	33855730 ps
CPU time	1 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200580 kb
Host	smart-a1c27b26-8a98-415d-acdb-910aed569767
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916810951 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.clkmgr_same_csr_outstanding.2916810951
Directory	/workspace/5.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2594158361
Short name	T142
Test name
Test status
Simulation time	384761282 ps
CPU time	2.54 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200992 kb
Host	smart-18489acd-ab80-48f8-bfb0-e6e00894d1b8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594158361 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2594158361
Directory	/workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2062514576
Short name	T881
Test name
Test status
Simulation time	202104051 ps
CPU time	1.71 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:59 PM PDT 24
Peak memory	200644 kb
Host	smart-a8bddfd8-09c6-436b-9fac-3df2d0f8ed10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062514576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_tl_errors.2062514576
Directory	/workspace/5.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1331853823
Short name	T125
Test name
Test status
Simulation time	202071651 ps
CPU time	2.78 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	200636 kb
Host	smart-542376f0-52a0-4133-9d59-ca06849dff0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331853823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 5.clkmgr_tl_intg_err.1331853823
Directory	/workspace/5.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.4075848587
Short name	T912
Test name
Test status
Simulation time	16642680 ps
CPU time	0.83 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200548 kb
Host	smart-6d965a58-6f93-408a-b844-940504989ad2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075848587 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.4075848587
Directory	/workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.253048408
Short name	T885
Test name
Test status
Simulation time	157893491 ps
CPU time	1.17 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200404 kb
Host	smart-722c8b04-9a5f-4c65-b458-58bd00dcd979
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253048408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.c lkmgr_csr_rw.253048408
Directory	/workspace/6.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2562332336
Short name	T856
Test name
Test status
Simulation time	38379746 ps
CPU time	0.7 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	199064 kb
Host	smart-4c531c79-549a-4baa-bca9-1a6004cb436d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562332336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_intr_test.2562332336
Directory	/workspace/6.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4099809869
Short name	T90
Test name
Test status
Simulation time	64613739 ps
CPU time	1.05 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200356 kb
Host	smart-53878691-073c-4cd3-ba7c-36533c5d942a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099809869 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.clkmgr_same_csr_outstanding.4099809869
Directory	/workspace/6.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.399380889
Short name	T959
Test name
Test status
Simulation time	165621336 ps
CPU time	1.55 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200876 kb
Host	smart-2807e86a-e26d-408e-bb9b-af19d7a6ce63
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399380889 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 6.clkmgr_shadow_reg_errors.399380889
Directory	/workspace/6.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3939452455
Short name	T958
Test name
Test status
Simulation time	84602589 ps
CPU time	1.85 seconds
Started	Jul 18 06:31:01 PM PDT 24
Finished	Jul 18 06:31:11 PM PDT 24
Peak memory	201100 kb
Host	smart-830ee8c2-1818-42f1-8cad-5e8960104da8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939452455 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.3939452455
Directory	/workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2498354851
Short name	T978
Test name
Test status
Simulation time	62716000 ps
CPU time	2.36 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200632 kb
Host	smart-6c00ab4d-e0e0-4fdf-a638-91386e940665
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498354851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_tl_errors.2498354851
Directory	/workspace/6.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1954756152
Short name	T911
Test name
Test status
Simulation time	1652518182 ps
CPU time	6.54 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:13 PM PDT 24
Peak memory	200668 kb
Host	smart-d91c3e9f-28d1-4931-9a40-77ff269db538
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954756152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.1954756152
Directory	/workspace/6.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3307481734
Short name	T879
Test name
Test status
Simulation time	102669309 ps
CPU time	1.58 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200508 kb
Host	smart-c498f285-6ae7-460a-b052-e2bd24d70b95
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307481734 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.3307481734
Directory	/workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.474774142
Short name	T916
Test name
Test status
Simulation time	16616095 ps
CPU time	0.79 seconds
Started	Jul 18 06:31:00 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200464 kb
Host	smart-00db461a-3dcf-4085-b4f6-dee8b89e7f30
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474774142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.c lkmgr_csr_rw.474774142
Directory	/workspace/7.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.4055990050
Short name	T924
Test name
Test status
Simulation time	15934948 ps
CPU time	0.73 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	199052 kb
Host	smart-04de40ea-0ebe-42ae-89d4-7bb062692924
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055990050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_intr_test.4055990050
Directory	/workspace/7.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.410602637
Short name	T892
Test name
Test status
Simulation time	32703050 ps
CPU time	1.11 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200584 kb
Host	smart-fe0ec1b5-115e-45df-92ab-b45bbcbb2cfe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410602637 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.clkmgr_same_csr_outstanding.410602637
Directory	/workspace/7.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1481818422
Short name	T144
Test name
Test status
Simulation time	190966250 ps
CPU time	2.09 seconds
Started	Jul 18 06:30:51 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200980 kb
Host	smart-0f0f5a72-0ad3-4476-a61e-6159f22631fc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481818422 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.clkmgr_shadow_reg_errors.1481818422
Directory	/workspace/7.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3116403598
Short name	T92
Test name
Test status
Simulation time	214084753 ps
CPU time	2.01 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	209060 kb
Host	smart-9808ee9e-140b-4124-b06d-0062cb57238d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116403598 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3116403598
Directory	/workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3110101445
Short name	T889
Test name
Test status
Simulation time	590424169 ps
CPU time	4.79 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	200488 kb
Host	smart-e9ac0415-ae9c-4623-b0b4-f52ed17972f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110101445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_tl_errors.3110101445
Directory	/workspace/7.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2230472087
Short name	T929
Test name
Test status
Simulation time	199974450 ps
CPU time	3.02 seconds
Started	Jul 18 06:30:50 PM PDT 24
Finished	Jul 18 06:30:56 PM PDT 24
Peak memory	200672 kb
Host	smart-bbc2c5b8-bf93-4a84-a53c-3cac2916f081
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230472087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.2230472087
Directory	/workspace/7.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1372734049
Short name	T872
Test name
Test status
Simulation time	127503750 ps
CPU time	1.33 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	200636 kb
Host	smart-8a3ec833-6be4-4fe3-b6d0-7c61efdcc693
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372734049 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.1372734049
Directory	/workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4277193463
Short name	T865
Test name
Test status
Simulation time	16232667 ps
CPU time	0.78 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200444 kb
Host	smart-30a971db-733c-49b3-8b84-757c28e0d4b4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277193463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. clkmgr_csr_rw.4277193463
Directory	/workspace/8.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.292531338
Short name	T1004
Test name
Test status
Simulation time	49822977 ps
CPU time	0.72 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	199104 kb
Host	smart-05554540-9078-4f18-be75-c5d84808266e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292531338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm gr_intr_test.292531338
Directory	/workspace/8.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.4067486124
Short name	T960
Test name
Test status
Simulation time	62311431 ps
CPU time	1.44 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	200632 kb
Host	smart-0375114d-53e1-43ca-8254-8b4aa5e8ffa7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067486124 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.clkmgr_same_csr_outstanding.4067486124
Directory	/workspace/8.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3265898655
Short name	T140
Test name
Test status
Simulation time	530525679 ps
CPU time	2.72 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	209168 kb
Host	smart-9c551cbf-0ea0-4aff-9e89-4618f0e7935f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265898655 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.clkmgr_shadow_reg_errors.3265898655
Directory	/workspace/8.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2106339233
Short name	T143
Test name
Test status
Simulation time	76759236 ps
CPU time	1.78 seconds
Started	Jul 18 06:30:55 PM PDT 24
Finished	Jul 18 06:31:02 PM PDT 24
Peak memory	209136 kb
Host	smart-8366a333-0161-4136-947e-ee22e145aed8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106339233 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2106339233
Directory	/workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1303109092
Short name	T861
Test name
Test status
Simulation time	255769305 ps
CPU time	2.44 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	200620 kb
Host	smart-40156fa0-adcb-4927-aead-649ddb03b04a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303109092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_tl_errors.1303109092
Directory	/workspace/8.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.413070177
Short name	T186
Test name
Test status
Simulation time	237297022 ps
CPU time	2.69 seconds
Started	Jul 18 06:30:58 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	200720 kb
Host	smart-e0925a71-8c28-40dd-b776-0e6f4b373591
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413070177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.clkmgr_tl_intg_err.413070177
Directory	/workspace/8.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.271667853
Short name	T999
Test name
Test status
Simulation time	55976806 ps
CPU time	0.94 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200536 kb
Host	smart-0afa4f80-1dc0-4e30-b51b-b4294e2f4498
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271667853 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.271667853
Directory	/workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2261729808
Short name	T973
Test name
Test status
Simulation time	17399300 ps
CPU time	0.89 seconds
Started	Jul 18 06:31:00 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200500 kb
Host	smart-a5317970-b038-47e4-a7d3-829738131282
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261729808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. clkmgr_csr_rw.2261729808
Directory	/workspace/9.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1747135629
Short name	T874
Test name
Test status
Simulation time	28336867 ps
CPU time	0.69 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:07 PM PDT 24
Peak memory	199096 kb
Host	smart-2b3c8b47-6710-461e-b153-6922962bd5e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747135629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_intr_test.1747135629
Directory	/workspace/9.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1742478717
Short name	T935
Test name
Test status
Simulation time	34911232 ps
CPU time	1.23 seconds
Started	Jul 18 06:31:00 PM PDT 24
Finished	Jul 18 06:31:09 PM PDT 24
Peak memory	200640 kb
Host	smart-2f566654-7fa2-4eec-b341-ba53a85df4ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742478717 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.clkmgr_same_csr_outstanding.1742478717
Directory	/workspace/9.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.4275034006
Short name	T950
Test name
Test status
Simulation time	55116662 ps
CPU time	1.25 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:05 PM PDT 24
Peak memory	200700 kb
Host	smart-8466729a-2e92-46ba-b900-94207881ed16
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275034006 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.clkmgr_shadow_reg_errors.4275034006
Directory	/workspace/9.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3838367301
Short name	T983
Test name
Test status
Simulation time	513341793 ps
CPU time	2.75 seconds
Started	Jul 18 06:30:57 PM PDT 24
Finished	Jul 18 06:31:06 PM PDT 24
Peak memory	201184 kb
Host	smart-be1c8d99-946e-4afd-86a5-046256d0fa19
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838367301 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.3838367301
Directory	/workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.72142278
Short name	T900
Test name
Test status
Simulation time	56756005 ps
CPU time	1.69 seconds
Started	Jul 18 06:30:53 PM PDT 24
Finished	Jul 18 06:30:57 PM PDT 24
Peak memory	200668 kb
Host	smart-4e278830-8737-44ab-82fc-b8342cc24585
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72142278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmg r_tl_errors.72142278
Directory	/workspace/9.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3817557395
Short name	T992
Test name
Test status
Simulation time	55096686 ps
CPU time	1.58 seconds
Started	Jul 18 06:30:59 PM PDT 24
Finished	Jul 18 06:31:08 PM PDT 24
Peak memory	200452 kb
Host	smart-8e6f87de-0f77-4380-9579-2129543796f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817557395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 9.clkmgr_tl_intg_err.3817557395
Directory	/workspace/9.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_alert_test.3186214756
Short name	T242
Test name
Test status
Simulation time	79261982 ps
CPU time	0.88 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:34 PM PDT 24
Peak memory	201196 kb
Host	smart-1bc806b5-9830-47b8-91d1-b1cc59ec1aef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186214756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm gr_alert_test.3186214756
Directory	/workspace/0.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.2753599923
Short name	T610
Test name
Test status
Simulation time	36315638 ps
CPU time	0.76 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:30 PM PDT 24
Peak memory	201064 kb
Host	smart-27fc83e3-99dc-4823-9994-9ddcbe97954a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753599923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.2753599923
Directory	/workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_status.2510164763
Short name	T588
Test name
Test status
Simulation time	25828781 ps
CPU time	0.73 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:32 PM PDT 24
Peak memory	200968 kb
Host	smart-22a0df70-14c6-4e67-a2fc-2ef7c7a9447c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510164763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2510164763
Directory	/workspace/0.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_div_intersig_mubi.2812265187
Short name	T266
Test name
Test status
Simulation time	33946507 ps
CPU time	0.86 seconds
Started	Jul 18 06:40:35 PM PDT 24
Finished	Jul 18 06:40:39 PM PDT 24
Peak memory	201100 kb
Host	smart-6605adb9-1dde-480a-84c7-e81ddce2443b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812265187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.2812265187
Directory	/workspace/0.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_extclk.3596438952
Short name	T593
Test name
Test status
Simulation time	47827899 ps
CPU time	0.97 seconds
Started	Jul 18 06:40:33 PM PDT 24
Finished	Jul 18 06:40:38 PM PDT 24
Peak memory	201076 kb
Host	smart-a5db4a39-087f-4c1e-b1bf-44676b3039ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596438952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3596438952
Directory	/workspace/0.clkmgr_extclk/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency.3520979701
Short name	T132
Test name
Test status
Simulation time	1402243368 ps
CPU time	7.87 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:41 PM PDT 24
Peak memory	201172 kb
Host	smart-fc00e6c8-482c-4168-9cfa-a87285cf0e3d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520979701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3520979701
Directory	/workspace/0.clkmgr_frequency/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency_timeout.444461341
Short name	T35
Test name
Test status
Simulation time	523374936 ps
CPU time	2.66 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:34 PM PDT 24
Peak memory	201204 kb
Host	smart-80790c5a-954f-401d-8287-a092ebeb7adf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444461341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_tim eout.444461341
Directory	/workspace/0.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/0.clkmgr_idle_intersig_mubi.1142121091
Short name	T131
Test name
Test status
Simulation time	95631137 ps
CPU time	0.98 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:35 PM PDT 24
Peak memory	201088 kb
Host	smart-fdecef46-a487-4314-becc-ad4334c79dc4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142121091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.1142121091
Directory	/workspace/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.662340527
Short name	T597
Test name
Test status
Simulation time	14695496 ps
CPU time	0.76 seconds
Started	Jul 18 06:40:31 PM PDT 24
Finished	Jul 18 06:40:36 PM PDT 24
Peak memory	201124 kb
Host	smart-4ffdb498-1796-495c-9e0f-cc405bcb3a54
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662340527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.clkmgr_lc_clk_byp_req_intersig_mubi.662340527
Directory	/workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2265774712
Short name	T834
Test name
Test status
Simulation time	23745495 ps
CPU time	0.86 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:34 PM PDT 24
Peak memory	201120 kb
Host	smart-f30e5593-b5e4-46e8-ba93-2e72e6348beb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265774712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_ctrl_intersig_mubi.2265774712
Directory	/workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_peri.2034362289
Short name	T346
Test name
Test status
Simulation time	20605557 ps
CPU time	0.7 seconds
Started	Jul 18 06:40:34 PM PDT 24
Finished	Jul 18 06:40:38 PM PDT 24
Peak memory	201044 kb
Host	smart-dfa31967-282b-49db-b061-d13ba3ee72c9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034362289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2034362289
Directory	/workspace/0.clkmgr_peri/latest

Test location	/workspace/coverage/default/0.clkmgr_regwen.3309264615
Short name	T488
Test name
Test status
Simulation time	899198544 ps
CPU time	3.6 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:36 PM PDT 24
Peak memory	201264 kb
Host	smart-81282575-2fac-4237-baca-2650b557a431
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309264615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3309264615
Directory	/workspace/0.clkmgr_regwen/latest

Test location	/workspace/coverage/default/0.clkmgr_sec_cm.1234526737
Short name	T55
Test name
Test status
Simulation time	412928005 ps
CPU time	2.45 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:40:39 PM PDT 24
Peak memory	216352 kb
Host	smart-82a01b91-6268-45ac-9d93-2d0ce439fc1a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234526737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_sec_cm.1234526737
Directory	/workspace/0.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/0.clkmgr_smoke.4018638489
Short name	T827
Test name
Test status
Simulation time	17390232 ps
CPU time	0.83 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:35 PM PDT 24
Peak memory	201056 kb
Host	smart-300f80d0-7087-4aad-aa9f-d39cb35cc95c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018638489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.4018638489
Directory	/workspace/0.clkmgr_smoke/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all.4019319145
Short name	T546
Test name
Test status
Simulation time	1565426232 ps
CPU time	11.79 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:45 PM PDT 24
Peak memory	201368 kb
Host	smart-5ef2969b-423b-44b0-ba7a-4c230bbc3af7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019319145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.4019319145
Directory	/workspace/0.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.1935563462
Short name	T633
Test name
Test status
Simulation time	17364512575 ps
CPU time	113.2 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:42:30 PM PDT 24
Peak memory	215304 kb
Host	smart-b9fe1297-b502-44d1-a000-a39fc3846d5c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1935563462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.1935563462
Directory	/workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_trans.1218516400
Short name	T63
Test name
Test status
Simulation time	45027379 ps
CPU time	0.85 seconds
Started	Jul 18 06:40:33 PM PDT 24
Finished	Jul 18 06:40:38 PM PDT 24
Peak memory	201068 kb
Host	smart-58f4f345-c077-42b8-bfd4-01c986878013
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218516400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.1218516400
Directory	/workspace/0.clkmgr_trans/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.1322115808
Short name	T784
Test name
Test status
Simulation time	18350279 ps
CPU time	0.77 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:35 PM PDT 24
Peak memory	201092 kb
Host	smart-01c8ae2f-c430-4a8a-baff-60713a0f4329
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322115808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.1322115808
Directory	/workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_status.3860913738
Short name	T595
Test name
Test status
Simulation time	40736302 ps
CPU time	0.77 seconds
Started	Jul 18 06:40:33 PM PDT 24
Finished	Jul 18 06:40:38 PM PDT 24
Peak memory	199724 kb
Host	smart-b98611b6-caf8-4ed3-ba02-52381e6a5078
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860913738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3860913738
Directory	/workspace/1.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/1.clkmgr_div_intersig_mubi.4199546062
Short name	T62
Test name
Test status
Simulation time	47165748 ps
CPU time	0.88 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:40:38 PM PDT 24
Peak memory	201060 kb
Host	smart-f4c4a73f-7325-419a-9699-64d07fb60b42
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199546062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.4199546062
Directory	/workspace/1.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_extclk.1054937556
Short name	T310
Test name
Test status
Simulation time	74732182 ps
CPU time	1.01 seconds
Started	Jul 18 06:40:34 PM PDT 24
Finished	Jul 18 06:40:39 PM PDT 24
Peak memory	201084 kb
Host	smart-20a19703-5a4e-4610-a3cf-310fa4705b24
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054937556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1054937556
Directory	/workspace/1.clkmgr_extclk/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency.1079436812
Short name	T709
Test name
Test status
Simulation time	2496223315 ps
CPU time	11.04 seconds
Started	Jul 18 06:40:36 PM PDT 24
Finished	Jul 18 06:40:50 PM PDT 24
Peak memory	201548 kb
Host	smart-aa189bfe-a11b-44e5-beb3-8d842bd93f31
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079436812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1079436812
Directory	/workspace/1.clkmgr_frequency/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency_timeout.3576690449
Short name	T811
Test name
Test status
Simulation time	1096295619 ps
CPU time	7.79 seconds
Started	Jul 18 06:40:34 PM PDT 24
Finished	Jul 18 06:40:46 PM PDT 24
Peak memory	201200 kb
Host	smart-3a1c3c10-aa51-4305-8cfa-808dd5efeeef
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576690449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.3576690449
Directory	/workspace/1.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/1.clkmgr_idle_intersig_mubi.1199522075
Short name	T641
Test name
Test status
Simulation time	326226233 ps
CPU time	1.82 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:33 PM PDT 24
Peak memory	201036 kb
Host	smart-e49aa621-dd87-4076-a90d-de9a5a748873
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199522075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.1199522075
Directory	/workspace/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.915305934
Short name	T417
Test name
Test status
Simulation time	68457655 ps
CPU time	0.94 seconds
Started	Jul 18 06:40:33 PM PDT 24
Finished	Jul 18 06:40:38 PM PDT 24
Peak memory	201084 kb
Host	smart-711f0285-964b-4d7b-b584-e21c9fb3c48e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915305934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.clkmgr_lc_clk_byp_req_intersig_mubi.915305934
Directory	/workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1029303475
Short name	T398
Test name
Test status
Simulation time	17874383 ps
CPU time	0.78 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:33 PM PDT 24
Peak memory	201076 kb
Host	smart-2df0be5e-520b-4b05-8b66-e9d89523a41e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029303475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.1029303475
Directory	/workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_peri.890404163
Short name	T445
Test name
Test status
Simulation time	20500477 ps
CPU time	0.79 seconds
Started	Jul 18 06:40:36 PM PDT 24
Finished	Jul 18 06:40:40 PM PDT 24
Peak memory	201064 kb
Host	smart-f3f514e7-fd2a-4480-b085-f99cb43e6233
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890404163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.890404163
Directory	/workspace/1.clkmgr_peri/latest

Test location	/workspace/coverage/default/1.clkmgr_regwen.2387020672
Short name	T365
Test name
Test status
Simulation time	599061432 ps
CPU time	3.85 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:37 PM PDT 24
Peak memory	201292 kb
Host	smart-bb451ef4-fa03-423d-95fb-6a78f1363fee
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387020672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2387020672
Directory	/workspace/1.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_smoke.187146508
Short name	T511
Test name
Test status
Simulation time	42979645 ps
CPU time	0.92 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:33 PM PDT 24
Peak memory	201024 kb
Host	smart-c1cd7b98-5d4d-48d8-9fd2-2e6acb9b08e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187146508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.187146508
Directory	/workspace/1.clkmgr_smoke/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all.1198413746
Short name	T696
Test name
Test status
Simulation time	4469783253 ps
CPU time	32.88 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:41:06 PM PDT 24
Peak memory	201452 kb
Host	smart-e2ddfacf-3a77-4ec6-ac85-1140ed222b39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198413746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.1198413746
Directory	/workspace/1.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.3624262064
Short name	T58
Test name
Test status
Simulation time	29317655724 ps
CPU time	265.89 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:45:02 PM PDT 24
Peak memory	209748 kb
Host	smart-5a2a1edb-a748-4c3f-97c1-aff52e98233e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3624262064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.3624262064
Directory	/workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.clkmgr_trans.3862439573
Short name	T103
Test name
Test status
Simulation time	22312573 ps
CPU time	0.82 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:40:37 PM PDT 24
Peak memory	201064 kb
Host	smart-3e58df9c-da17-4fe1-a9ff-b2565e41f7d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862439573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3862439573
Directory	/workspace/1.clkmgr_trans/latest

Test location	/workspace/coverage/default/10.clkmgr_alert_test.1980477342
Short name	T357
Test name
Test status
Simulation time	14054971 ps
CPU time	0.75 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:35 PM PDT 24
Peak memory	201228 kb
Host	smart-194df59a-2ccd-46c7-ac0c-a8bab4fe298a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980477342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk mgr_alert_test.1980477342
Directory	/workspace/10.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.611628046
Short name	T761
Test name
Test status
Simulation time	16118724 ps
CPU time	0.79 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:36 PM PDT 24
Peak memory	201260 kb
Host	smart-369ca0b9-1f02-4457-8181-3c95671d94ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611628046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.611628046
Directory	/workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_status.1945889726
Short name	T384
Test name
Test status
Simulation time	48795090 ps
CPU time	0.81 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	201000 kb
Host	smart-7cd855d0-2f00-4036-88a2-f4e09693d7ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945889726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.1945889726
Directory	/workspace/10.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/10.clkmgr_div_intersig_mubi.3167918871
Short name	T416
Test name
Test status
Simulation time	50222091 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	201096 kb
Host	smart-1603f777-1218-43fa-ac0c-be4dda12f18b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167918871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.3167918871
Directory	/workspace/10.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_extclk.2275218305
Short name	T512
Test name
Test status
Simulation time	52064738 ps
CPU time	0.87 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:35 PM PDT 24
Peak memory	201092 kb
Host	smart-824ed120-6bf9-41dc-ad6a-41034761e14e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275218305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2275218305
Directory	/workspace/10.clkmgr_extclk/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency.755459970
Short name	T672
Test name
Test status
Simulation time	1874720203 ps
CPU time	13.96 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:46 PM PDT 24
Peak memory	201320 kb
Host	smart-0aebc2cf-02d6-4fb0-8789-4d3a699d146d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755459970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.755459970
Directory	/workspace/10.clkmgr_frequency/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency_timeout.1753853684
Short name	T533
Test name
Test status
Simulation time	2415731253 ps
CPU time	16.95 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:50 PM PDT 24
Peak memory	201476 kb
Host	smart-8e273a70-4fcd-4b4c-95d1-b0b1703928fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753853684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t imeout.1753853684
Directory	/workspace/10.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/10.clkmgr_idle_intersig_mubi.3459159947
Short name	T428
Test name
Test status
Simulation time	32706783 ps
CPU time	0.85 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	201096 kb
Host	smart-c250e31a-d497-4bef-b09d-da8b34466c51
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459159947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.3459159947
Directory	/workspace/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3204058238
Short name	T797
Test name
Test status
Simulation time	22253340 ps
CPU time	0.86 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:32 PM PDT 24
Peak memory	201108 kb
Host	smart-9d41e632-e728-4324-8b69-54c888249ba4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204058238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_clk_byp_req_intersig_mubi.3204058238
Directory	/workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3807658510
Short name	T295
Test name
Test status
Simulation time	155053311 ps
CPU time	1.15 seconds
Started	Jul 18 06:41:28 PM PDT 24
Finished	Jul 18 06:41:30 PM PDT 24
Peak memory	201056 kb
Host	smart-9ebb187d-ad34-4a17-be28-4b2c5a1ecdb4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807658510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.3807658510
Directory	/workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_peri.2366656181
Short name	T509
Test name
Test status
Simulation time	24473492 ps
CPU time	0.78 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:37 PM PDT 24
Peak memory	201212 kb
Host	smart-67e67d00-9929-4b0f-849f-997833afc643
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366656181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.2366656181
Directory	/workspace/10.clkmgr_peri/latest

Test location	/workspace/coverage/default/10.clkmgr_regwen.2396909258
Short name	T420
Test name
Test status
Simulation time	839659414 ps
CPU time	3.91 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:44 PM PDT 24
Peak memory	201320 kb
Host	smart-7bb88106-237d-41c1-b6ca-6aabc8e3752e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396909258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2396909258
Directory	/workspace/10.clkmgr_regwen/latest

Test location	/workspace/coverage/default/10.clkmgr_smoke.245419545
Short name	T485
Test name
Test status
Simulation time	21984833 ps
CPU time	0.84 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:32 PM PDT 24
Peak memory	201056 kb
Host	smart-9eca9685-6f65-4bf5-8d5c-7786f8c5a950
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245419545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.245419545
Directory	/workspace/10.clkmgr_smoke/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all.4241953917
Short name	T553
Test name
Test status
Simulation time	4388967990 ps
CPU time	31.81 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:42:07 PM PDT 24
Peak memory	201616 kb
Host	smart-32f55397-5c2b-4788-b184-b3b154e74b31
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241953917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.4241953917
Directory	/workspace/10.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.3725510912
Short name	T589
Test name
Test status
Simulation time	86760034464 ps
CPU time	918.25 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:56:51 PM PDT 24
Peak memory	209780 kb
Host	smart-364c99b1-a9fc-4668-98b3-8afe8d7a3808
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3725510912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.3725510912
Directory	/workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.clkmgr_trans.1172842732
Short name	T190
Test name
Test status
Simulation time	14911825 ps
CPU time	0.77 seconds
Started	Jul 18 06:41:33 PM PDT 24
Finished	Jul 18 06:41:39 PM PDT 24
Peak memory	201068 kb
Host	smart-26b4e324-59e8-47f4-b27a-ff1f384d455d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172842732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.1172842732
Directory	/workspace/10.clkmgr_trans/latest

Test location	/workspace/coverage/default/11.clkmgr_alert_test.3895890495
Short name	T498
Test name
Test status
Simulation time	18055646 ps
CPU time	0.74 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	201228 kb
Host	smart-58d00da9-34bf-4d5c-b20f-00b323fbfff2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895890495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk mgr_alert_test.3895890495
Directory	/workspace/11.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_status.2563156600
Short name	T409
Test name
Test status
Simulation time	24695030 ps
CPU time	0.74 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:40 PM PDT 24
Peak memory	200976 kb
Host	smart-7a60851a-bca9-484c-a01f-473a92ea213d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563156600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.2563156600
Directory	/workspace/11.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/11.clkmgr_div_intersig_mubi.1226071309
Short name	T452
Test name
Test status
Simulation time	33531325 ps
CPU time	0.82 seconds
Started	Jul 18 06:41:28 PM PDT 24
Finished	Jul 18 06:41:30 PM PDT 24
Peak memory	201060 kb
Host	smart-b610b4b8-eac7-4fc7-a772-ef3d343f348b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226071309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.1226071309
Directory	/workspace/11.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_extclk.2144337573
Short name	T287
Test name
Test status
Simulation time	18796088 ps
CPU time	0.76 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:40 PM PDT 24
Peak memory	201088 kb
Host	smart-879aff71-339c-40f8-b8ca-db1a1b5091ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144337573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2144337573
Directory	/workspace/11.clkmgr_extclk/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency.4206861793
Short name	T3
Test name
Test status
Simulation time	2122772762 ps
CPU time	12.17 seconds
Started	Jul 18 06:41:27 PM PDT 24
Finished	Jul 18 06:41:40 PM PDT 24
Peak memory	201348 kb
Host	smart-4c7af349-b753-4c93-9ced-3b654fd7f31a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206861793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.4206861793
Directory	/workspace/11.clkmgr_frequency/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency_timeout.2782800396
Short name	T247
Test name
Test status
Simulation time	758299505 ps
CPU time	3.57 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:44 PM PDT 24
Peak memory	201236 kb
Host	smart-43cb1b58-c972-4790-adc0-8da8bba0521a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782800396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t imeout.2782800396
Directory	/workspace/11.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/11.clkmgr_idle_intersig_mubi.3407234168
Short name	T762
Test name
Test status
Simulation time	74379823 ps
CPU time	1.19 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:32 PM PDT 24
Peak memory	201064 kb
Host	smart-95249944-1bf8-4697-bfc7-f77cf00e35f3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407234168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.3407234168
Directory	/workspace/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.312905604
Short name	T268
Test name
Test status
Simulation time	95121032 ps
CPU time	1.03 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	201096 kb
Host	smart-c8eedae8-c62c-4f9d-9691-3f0aa9ba358a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312905604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.clkmgr_lc_clk_byp_req_intersig_mubi.312905604
Directory	/workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.4012202049
Short name	T605
Test name
Test status
Simulation time	60588781 ps
CPU time	0.87 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	201128 kb
Host	smart-ee69abd4-9d08-46b5-8787-14b8f1ac0cb2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012202049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_ctrl_intersig_mubi.4012202049
Directory	/workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_peri.3137083995
Short name	T554
Test name
Test status
Simulation time	52762085 ps
CPU time	0.78 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:40 PM PDT 24
Peak memory	201096 kb
Host	smart-7a0983f9-82a9-4913-bcf1-f6c69740ebce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137083995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.3137083995
Directory	/workspace/11.clkmgr_peri/latest

Test location	/workspace/coverage/default/11.clkmgr_smoke.3256288097
Short name	T169
Test name
Test status
Simulation time	21251165 ps
CPU time	0.86 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:32 PM PDT 24
Peak memory	201056 kb
Host	smart-91f1eda4-6e00-4317-bad5-06752f4091de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256288097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.3256288097
Directory	/workspace/11.clkmgr_smoke/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all.1376589068
Short name	T156
Test name
Test status
Simulation time	4337045266 ps
CPU time	32.45 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:42:08 PM PDT 24
Peak memory	201472 kb
Host	smart-523e4c93-ccfe-4fa5-9488-7fc4d39c163d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376589068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.1376589068
Directory	/workspace/11.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.2577465007
Short name	T259
Test name
Test status
Simulation time	33570548087 ps
CPU time	508.86 seconds
Started	Jul 18 06:41:35 PM PDT 24
Finished	Jul 18 06:50:10 PM PDT 24
Peak memory	210324 kb
Host	smart-1bd6ed94-38ed-4ca2-92f0-ae4310dfabb6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2577465007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.2577465007
Directory	/workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_trans.867051772
Short name	T582
Test name
Test status
Simulation time	49778076 ps
CPU time	0.82 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	201072 kb
Host	smart-ee9bbde9-ab46-4ac0-87b9-e8e0f0994cfd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867051772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.867051772
Directory	/workspace/11.clkmgr_trans/latest

Test location	/workspace/coverage/default/12.clkmgr_alert_test.499606319
Short name	T424
Test name
Test status
Simulation time	16053079 ps
CPU time	0.75 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:34 PM PDT 24
Peak memory	201312 kb
Host	smart-a5e48a14-2bf1-425c-8889-e508e2bc921f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499606319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkm gr_alert_test.499606319
Directory	/workspace/12.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_status.3013506348
Short name	T293
Test name
Test status
Simulation time	19048403 ps
CPU time	0.7 seconds
Started	Jul 18 06:41:33 PM PDT 24
Finished	Jul 18 06:41:39 PM PDT 24
Peak memory	200284 kb
Host	smart-b8aa0328-1065-49b5-b046-b5078d64f3b9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013506348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3013506348
Directory	/workspace/12.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/12.clkmgr_div_intersig_mubi.1033787781
Short name	T545
Test name
Test status
Simulation time	63540164 ps
CPU time	0.97 seconds
Started	Jul 18 06:41:37 PM PDT 24
Finished	Jul 18 06:41:43 PM PDT 24
Peak memory	201084 kb
Host	smart-ad9f9c51-1e0a-492a-a629-92e77fb69768
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033787781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.1033787781
Directory	/workspace/12.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_extclk.1391229871
Short name	T848
Test name
Test status
Simulation time	39281187 ps
CPU time	0.88 seconds
Started	Jul 18 06:41:37 PM PDT 24
Finished	Jul 18 06:41:44 PM PDT 24
Peak memory	201076 kb
Host	smart-a049b8f1-8c5a-42ee-a162-00c29a09904a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391229871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1391229871
Directory	/workspace/12.clkmgr_extclk/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency.1199108454
Short name	T298
Test name
Test status
Simulation time	1994191960 ps
CPU time	15.38 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:53 PM PDT 24
Peak memory	201356 kb
Host	smart-51db84c0-664d-4916-9595-9c0e2eaf8451
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199108454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.1199108454
Directory	/workspace/12.clkmgr_frequency/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency_timeout.1224944487
Short name	T568
Test name
Test status
Simulation time	910970070 ps
CPU time	4.08 seconds
Started	Jul 18 06:41:28 PM PDT 24
Finished	Jul 18 06:41:33 PM PDT 24
Peak memory	201220 kb
Host	smart-acf1522a-2877-47be-ba86-d2191ef0187b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224944487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t imeout.1224944487
Directory	/workspace/12.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/12.clkmgr_idle_intersig_mubi.1753802411
Short name	T244
Test name
Test status
Simulation time	38540907 ps
CPU time	1.04 seconds
Started	Jul 18 06:41:37 PM PDT 24
Finished	Jul 18 06:41:43 PM PDT 24
Peak memory	201084 kb
Host	smart-52e325c2-5cf2-4f9c-8694-c4a9805a3280
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753802411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.1753802411
Directory	/workspace/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1865052062
Short name	T643
Test name
Test status
Simulation time	24146208 ps
CPU time	0.87 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:40 PM PDT 24
Peak memory	201100 kb
Host	smart-e2221e5b-ef0c-4c21-b9ca-af613baaee25
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865052062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1865052062
Directory	/workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1605510890
Short name	T816
Test name
Test status
Simulation time	77554413 ps
CPU time	1.01 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	201124 kb
Host	smart-59f86831-9e7f-4d75-9d8d-1c11eb27835c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605510890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.1605510890
Directory	/workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_peri.2384621911
Short name	T194
Test name
Test status
Simulation time	17186860 ps
CPU time	0.79 seconds
Started	Jul 18 06:41:33 PM PDT 24
Finished	Jul 18 06:41:39 PM PDT 24
Peak memory	201032 kb
Host	smart-abef9fbd-ddec-4a33-ad8b-cd67c933a50d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384621911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2384621911
Directory	/workspace/12.clkmgr_peri/latest

Test location	/workspace/coverage/default/12.clkmgr_regwen.1014327298
Short name	T522
Test name
Test status
Simulation time	147463565 ps
CPU time	1.27 seconds
Started	Jul 18 06:41:37 PM PDT 24
Finished	Jul 18 06:41:43 PM PDT 24
Peak memory	201036 kb
Host	smart-1b97e0ee-829d-4083-9001-96886e55f31f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014327298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1014327298
Directory	/workspace/12.clkmgr_regwen/latest

Test location	/workspace/coverage/default/12.clkmgr_smoke.1960953903
Short name	T798
Test name
Test status
Simulation time	22875162 ps
CPU time	0.91 seconds
Started	Jul 18 06:41:33 PM PDT 24
Finished	Jul 18 06:41:40 PM PDT 24
Peak memory	201040 kb
Host	smart-ceeed99d-5503-47ce-8e7c-da2717dc3876
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960953903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1960953903
Directory	/workspace/12.clkmgr_smoke/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all.3329619594
Short name	T791
Test name
Test status
Simulation time	7967047962 ps
CPU time	55.25 seconds
Started	Jul 18 06:41:36 PM PDT 24
Finished	Jul 18 06:42:37 PM PDT 24
Peak memory	201468 kb
Host	smart-461cfa12-b16f-4165-acd1-bb2fedfd4e05
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329619594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.3329619594
Directory	/workspace/12.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.1612726470
Short name	T421
Test name
Test status
Simulation time	19104030164 ps
CPU time	290.81 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:46:30 PM PDT 24
Peak memory	209832 kb
Host	smart-2d5a9b1f-211e-4d3a-b9cd-8beda6b78ae8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1612726470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.1612726470
Directory	/workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.clkmgr_trans.1832534354
Short name	T812
Test name
Test status
Simulation time	99111910 ps
CPU time	1.12 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	201080 kb
Host	smart-f3e1fc62-ed8c-42bd-8ad0-1c1efb7a303d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832534354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1832534354
Directory	/workspace/12.clkmgr_trans/latest

Test location	/workspace/coverage/default/13.clkmgr_alert_test.3947922674
Short name	T411
Test name
Test status
Simulation time	19543188 ps
CPU time	0.77 seconds
Started	Jul 18 06:47:44 PM PDT 24
Finished	Jul 18 06:47:51 PM PDT 24
Peak memory	201220 kb
Host	smart-c9cc119c-33ba-42b7-80db-e6acfe72e3f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947922674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk mgr_alert_test.3947922674
Directory	/workspace/13.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2079664218
Short name	T777
Test name
Test status
Simulation time	45100822 ps
CPU time	1.04 seconds
Started	Jul 18 06:41:45 PM PDT 24
Finished	Jul 18 06:41:49 PM PDT 24
Peak memory	201120 kb
Host	smart-03538c6d-2087-499d-a0b1-3300bb8be42f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079664218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.2079664218
Directory	/workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_status.1446369171
Short name	T221
Test name
Test status
Simulation time	15097008 ps
CPU time	0.68 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:35 PM PDT 24
Peak memory	200392 kb
Host	smart-06e0b49b-a57a-44b6-b2ab-9dc31785a76f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446369171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1446369171
Directory	/workspace/13.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/13.clkmgr_div_intersig_mubi.1422717511
Short name	T187
Test name
Test status
Simulation time	73780422 ps
CPU time	0.88 seconds
Started	Jul 18 06:41:45 PM PDT 24
Finished	Jul 18 06:41:49 PM PDT 24
Peak memory	201124 kb
Host	smart-b4e15e24-e5eb-4438-84d9-f9c059ed7d7c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422717511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.1422717511
Directory	/workspace/13.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_extclk.93974169
Short name	T743
Test name
Test status
Simulation time	19046444 ps
CPU time	0.74 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:40 PM PDT 24
Peak memory	201112 kb
Host	smart-5e7ce7ec-c52d-4523-b429-b034c757eeb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93974169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.93974169
Directory	/workspace/13.clkmgr_extclk/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency.2049416310
Short name	T437
Test name
Test status
Simulation time	1402060779 ps
CPU time	10.95 seconds
Started	Jul 18 06:41:35 PM PDT 24
Finished	Jul 18 06:41:52 PM PDT 24
Peak memory	201180 kb
Host	smart-36ad10ea-27d7-4cc9-afaa-f8230ab9bed7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049416310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.2049416310
Directory	/workspace/13.clkmgr_frequency/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency_timeout.2330454163
Short name	T201
Test name
Test status
Simulation time	1412694315 ps
CPU time	5.6 seconds
Started	Jul 18 06:41:35 PM PDT 24
Finished	Jul 18 06:41:47 PM PDT 24
Peak memory	201220 kb
Host	smart-c06e6650-5a95-477f-bbbd-cd8e65e912cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330454163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t imeout.2330454163
Directory	/workspace/13.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3640995703
Short name	T541
Test name
Test status
Simulation time	33379954 ps
CPU time	0.95 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:39 PM PDT 24
Peak memory	201096 kb
Host	smart-eeed6815-71e6-49b4-9917-d851b01a04b0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640995703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.3640995703
Directory	/workspace/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2903037266
Short name	T735
Test name
Test status
Simulation time	37863092 ps
CPU time	0.75 seconds
Started	Jul 18 06:41:46 PM PDT 24
Finished	Jul 18 06:41:49 PM PDT 24
Peak memory	201112 kb
Host	smart-c247a41b-762c-49ad-a974-29ed5e00d407
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903037266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2903037266
Directory	/workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.4035486180
Short name	T410
Test name
Test status
Simulation time	96830716 ps
CPU time	1.1 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:39 PM PDT 24
Peak memory	201100 kb
Host	smart-4b3e9fff-33f5-42d1-9110-ed56b3d9472f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035486180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_ctrl_intersig_mubi.4035486180
Directory	/workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_peri.2804062690
Short name	T506
Test name
Test status
Simulation time	33059383 ps
CPU time	0.74 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:35 PM PDT 24
Peak memory	201120 kb
Host	smart-897deb70-d2d0-4e2b-9b4f-6e3c83cdd5ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804062690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.2804062690
Directory	/workspace/13.clkmgr_peri/latest

Test location	/workspace/coverage/default/13.clkmgr_regwen.769381198
Short name	T436
Test name
Test status
Simulation time	142812084 ps
CPU time	1.36 seconds
Started	Jul 18 06:41:42 PM PDT 24
Finished	Jul 18 06:41:47 PM PDT 24
Peak memory	201128 kb
Host	smart-554b879a-7953-4f96-9f66-3c4f42792d0b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769381198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.769381198
Directory	/workspace/13.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_smoke.3026955321
Short name	T776
Test name
Test status
Simulation time	39548659 ps
CPU time	0.87 seconds
Started	Jul 18 06:41:35 PM PDT 24
Finished	Jul 18 06:41:42 PM PDT 24
Peak memory	201064 kb
Host	smart-10d97235-0306-45ea-9238-19c042e76c64
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026955321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3026955321
Directory	/workspace/13.clkmgr_smoke/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all.2315143087
Short name	T646
Test name
Test status
Simulation time	2428258936 ps
CPU time	15.74 seconds
Started	Jul 18 06:41:50 PM PDT 24
Finished	Jul 18 06:42:07 PM PDT 24
Peak memory	201488 kb
Host	smart-126ff949-3e03-4552-9d91-441d1547a58f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315143087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.2315143087
Directory	/workspace/13.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.3665459576
Short name	T76
Test name
Test status
Simulation time	122109335930 ps
CPU time	747.94 seconds
Started	Jul 18 06:41:46 PM PDT 24
Finished	Jul 18 06:54:17 PM PDT 24
Peak memory	209844 kb
Host	smart-d73ea407-04f6-4081-8e99-ecf947b9f286
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3665459576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.3665459576
Directory	/workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.clkmgr_trans.911110879
Short name	T299
Test name
Test status
Simulation time	66190881 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	201096 kb
Host	smart-426fcb9f-1069-4bcc-a25f-d767d2b3be1e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911110879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.911110879
Directory	/workspace/13.clkmgr_trans/latest

Test location	/workspace/coverage/default/14.clkmgr_alert_test.3935068492
Short name	T53
Test name
Test status
Simulation time	145224836 ps
CPU time	1.14 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:42:00 PM PDT 24
Peak memory	201220 kb
Host	smart-564acf18-443b-479f-a889-fde2a1f5502e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935068492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk mgr_alert_test.3935068492
Directory	/workspace/14.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1110671184
Short name	T105
Test name
Test status
Simulation time	197691039 ps
CPU time	1.47 seconds
Started	Jul 18 06:41:42 PM PDT 24
Finished	Jul 18 06:41:47 PM PDT 24
Peak memory	201120 kb
Host	smart-2102d5b5-c8f0-4deb-935f-38edbffbf164
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110671184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.1110671184
Directory	/workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_status.2050523761
Short name	T813
Test name
Test status
Simulation time	46961690 ps
CPU time	0.78 seconds
Started	Jul 18 06:41:46 PM PDT 24
Finished	Jul 18 06:41:50 PM PDT 24
Peak memory	200284 kb
Host	smart-03a6f86a-18a3-471d-ab1c-7e8458970594
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050523761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.2050523761
Directory	/workspace/14.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/14.clkmgr_div_intersig_mubi.707825390
Short name	T580
Test name
Test status
Simulation time	22785455 ps
CPU time	0.84 seconds
Started	Jul 18 06:41:45 PM PDT 24
Finished	Jul 18 06:41:49 PM PDT 24
Peak memory	201096 kb
Host	smart-fc71bd0f-649f-4f24-b5f5-19740cb47362
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707825390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.clkmgr_div_intersig_mubi.707825390
Directory	/workspace/14.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_extclk.2549886583
Short name	T15
Test name
Test status
Simulation time	49069319 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:42 PM PDT 24
Finished	Jul 18 06:41:46 PM PDT 24
Peak memory	201104 kb
Host	smart-c5ba0e12-4bf9-424b-a3aa-d5f8e1fd7e38
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549886583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.2549886583
Directory	/workspace/14.clkmgr_extclk/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency.2751030354
Short name	T681
Test name
Test status
Simulation time	1753625656 ps
CPU time	13.13 seconds
Started	Jul 18 06:41:50 PM PDT 24
Finished	Jul 18 06:42:05 PM PDT 24
Peak memory	201160 kb
Host	smart-b6ae1c4b-67fa-4565-b934-0d1f2b7a2c5d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751030354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2751030354
Directory	/workspace/14.clkmgr_frequency/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency_timeout.1487391738
Short name	T499
Test name
Test status
Simulation time	405070881 ps
CPU time	2.11 seconds
Started	Jul 18 06:41:42 PM PDT 24
Finished	Jul 18 06:41:48 PM PDT 24
Peak memory	201204 kb
Host	smart-1e794a7e-2390-465c-a674-5a3bab37f66e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487391738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t imeout.1487391738
Directory	/workspace/14.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1781340778
Short name	T829
Test name
Test status
Simulation time	88147760 ps
CPU time	1.08 seconds
Started	Jul 18 06:41:46 PM PDT 24
Finished	Jul 18 06:41:50 PM PDT 24
Peak memory	201088 kb
Host	smart-885344e4-96b1-4c77-b556-93e9fac4a5e0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781340778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.1781340778
Directory	/workspace/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.2745291410
Short name	T700
Test name
Test status
Simulation time	34054815 ps
CPU time	0.86 seconds
Started	Jul 18 06:41:41 PM PDT 24
Finished	Jul 18 06:41:46 PM PDT 24
Peak memory	201108 kb
Host	smart-0259f15f-5f6a-4b2b-871f-250b0f6473da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745291410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_clk_byp_req_intersig_mubi.2745291410
Directory	/workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.4293730180
Short name	T377
Test name
Test status
Simulation time	39931445 ps
CPU time	0.87 seconds
Started	Jul 18 06:41:50 PM PDT 24
Finished	Jul 18 06:41:52 PM PDT 24
Peak memory	201108 kb
Host	smart-f73a5b20-3298-4028-8fe4-d8e0eabbaec3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293730180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_ctrl_intersig_mubi.4293730180
Directory	/workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_peri.581243459
Short name	T674
Test name
Test status
Simulation time	39305262 ps
CPU time	0.77 seconds
Started	Jul 18 06:41:42 PM PDT 24
Finished	Jul 18 06:41:46 PM PDT 24
Peak memory	201000 kb
Host	smart-6a70d0d9-f33c-4904-af7c-7b62568b3e79
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581243459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.581243459
Directory	/workspace/14.clkmgr_peri/latest

Test location	/workspace/coverage/default/14.clkmgr_regwen.2140973891
Short name	T341
Test name
Test status
Simulation time	146864809 ps
CPU time	1.33 seconds
Started	Jul 18 06:41:49 PM PDT 24
Finished	Jul 18 06:41:53 PM PDT 24
Peak memory	201044 kb
Host	smart-daa29d2c-853f-4d12-aa7c-87163f355072
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140973891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2140973891
Directory	/workspace/14.clkmgr_regwen/latest

Test location	/workspace/coverage/default/14.clkmgr_smoke.1097059219
Short name	T768
Test name
Test status
Simulation time	121682710 ps
CPU time	1.12 seconds
Started	Jul 18 06:41:42 PM PDT 24
Finished	Jul 18 06:41:47 PM PDT 24
Peak memory	201028 kb
Host	smart-c63bfa72-f909-4bf7-b3d5-66707c95bf23
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097059219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1097059219
Directory	/workspace/14.clkmgr_smoke/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all.2835511401
Short name	T503
Test name
Test status
Simulation time	11865476378 ps
CPU time	86.26 seconds
Started	Jul 18 06:41:56 PM PDT 24
Finished	Jul 18 06:43:24 PM PDT 24
Peak memory	201464 kb
Host	smart-46ec14ef-fa03-4f9d-b80c-b8f831b5c132
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835511401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.2835511401
Directory	/workspace/14.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_trans.1138831977
Short name	T767
Test name
Test status
Simulation time	20832400 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:50 PM PDT 24
Finished	Jul 18 06:41:53 PM PDT 24
Peak memory	201088 kb
Host	smart-a430b7b0-60b0-4680-a263-a061f3cf74da
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138831977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.1138831977
Directory	/workspace/14.clkmgr_trans/latest

Test location	/workspace/coverage/default/15.clkmgr_alert_test.2298986771
Short name	T678
Test name
Test status
Simulation time	37397536 ps
CPU time	0.85 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:42:00 PM PDT 24
Peak memory	201216 kb
Host	smart-a4b50fa1-d4ff-44ab-9494-83ca5487f338
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298986771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk mgr_alert_test.2298986771
Directory	/workspace/15.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2671636543
Short name	T730
Test name
Test status
Simulation time	21329037 ps
CPU time	0.75 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:41:59 PM PDT 24
Peak memory	201096 kb
Host	smart-de6ae1e6-b355-4322-b80a-424aa5d44e06
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671636543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.2671636543
Directory	/workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_status.1647965893
Short name	T301
Test name
Test status
Simulation time	13154330 ps
CPU time	0.7 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:42:00 PM PDT 24
Peak memory	200288 kb
Host	smart-6636a1fa-e777-48ce-9d6a-702f4fab0562
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647965893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1647965893
Directory	/workspace/15.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/15.clkmgr_div_intersig_mubi.3442626617
Short name	T552
Test name
Test status
Simulation time	69587991 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:56 PM PDT 24
Finished	Jul 18 06:41:59 PM PDT 24
Peak memory	201108 kb
Host	smart-0a7bde6b-5177-43f5-ad2d-9ad8bd65bb52
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442626617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.3442626617
Directory	/workspace/15.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_extclk.181313445
Short name	T821
Test name
Test status
Simulation time	22789035 ps
CPU time	0.86 seconds
Started	Jul 18 06:41:55 PM PDT 24
Finished	Jul 18 06:41:56 PM PDT 24
Peak memory	201036 kb
Host	smart-9e0330c5-939a-4c3f-9c52-8c8f71a22b14
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181313445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.181313445
Directory	/workspace/15.clkmgr_extclk/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency.3240614721
Short name	T46
Test name
Test status
Simulation time	198843553 ps
CPU time	2.07 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:42:01 PM PDT 24
Peak memory	201108 kb
Host	smart-b7885d1f-8244-43b8-bbe5-38e309def8dd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240614721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.3240614721
Directory	/workspace/15.clkmgr_frequency/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency_timeout.4183990346
Short name	T31
Test name
Test status
Simulation time	2425654763 ps
CPU time	12.46 seconds
Started	Jul 18 06:41:58 PM PDT 24
Finished	Jul 18 06:42:12 PM PDT 24
Peak memory	201652 kb
Host	smart-9beded8a-56b8-4544-bf6b-1e775f29cc03
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183990346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.4183990346
Directory	/workspace/15.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2666391075
Short name	T839
Test name
Test status
Simulation time	15170965 ps
CPU time	0.76 seconds
Started	Jul 18 06:41:58 PM PDT 24
Finished	Jul 18 06:42:00 PM PDT 24
Peak memory	201116 kb
Host	smart-a90fc155-8216-4d08-8654-9416dc6942bb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666391075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2666391075
Directory	/workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3018690058
Short name	T243
Test name
Test status
Simulation time	19497833 ps
CPU time	0.87 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:41:59 PM PDT 24
Peak memory	201100 kb
Host	smart-d0f79fc3-2147-4ecf-86bb-370997cb37da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018690058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.3018690058
Directory	/workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_peri.721248918
Short name	T656
Test name
Test status
Simulation time	40109953 ps
CPU time	0.82 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:42:00 PM PDT 24
Peak memory	201012 kb
Host	smart-53ce0459-364b-4ce3-ab78-4eecead9ef22
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721248918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.721248918
Directory	/workspace/15.clkmgr_peri/latest

Test location	/workspace/coverage/default/15.clkmgr_regwen.1203401291
Short name	T273
Test name
Test status
Simulation time	36606199 ps
CPU time	0.91 seconds
Started	Jul 18 06:41:56 PM PDT 24
Finished	Jul 18 06:41:59 PM PDT 24
Peak memory	201028 kb
Host	smart-437ed4ad-c099-4b17-a2a8-ba74845387d7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203401291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1203401291
Directory	/workspace/15.clkmgr_regwen/latest

Test location	/workspace/coverage/default/15.clkmgr_smoke.2276333017
Short name	T80
Test name
Test status
Simulation time	57618388 ps
CPU time	0.92 seconds
Started	Jul 18 06:41:55 PM PDT 24
Finished	Jul 18 06:41:57 PM PDT 24
Peak memory	201028 kb
Host	smart-0e392bde-2afa-470a-b32f-c932a0ac20cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276333017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.2276333017
Directory	/workspace/15.clkmgr_smoke/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all.519276735
Short name	T446
Test name
Test status
Simulation time	2456447661 ps
CPU time	13.91 seconds
Started	Jul 18 06:41:59 PM PDT 24
Finished	Jul 18 06:42:14 PM PDT 24
Peak memory	201464 kb
Host	smart-930b9d96-c546-4916-8f89-e8701b1bce03
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519276735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.519276735
Directory	/workspace/15.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.3098139127
Short name	T171
Test name
Test status
Simulation time	666546856480 ps
CPU time	2332.37 seconds
Started	Jul 18 06:41:56 PM PDT 24
Finished	Jul 18 07:20:50 PM PDT 24
Peak memory	217884 kb
Host	smart-1d352860-3824-4c54-9dd9-09bfeb5a1a27
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3098139127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3098139127
Directory	/workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.clkmgr_trans.1084695717
Short name	T668
Test name
Test status
Simulation time	27336999 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:56 PM PDT 24
Finished	Jul 18 06:41:58 PM PDT 24
Peak memory	201080 kb
Host	smart-e7c622b0-efce-4ba5-89d5-15e1e0ec95c2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084695717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1084695717
Directory	/workspace/15.clkmgr_trans/latest

Test location	/workspace/coverage/default/16.clkmgr_alert_test.3107570459
Short name	T347
Test name
Test status
Simulation time	19266002 ps
CPU time	0.78 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:22 PM PDT 24
Peak memory	201220 kb
Host	smart-de59a2f2-8179-4ea5-b628-d22b4a9f236c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107570459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk mgr_alert_test.3107570459
Directory	/workspace/16.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1053124764
Short name	T751
Test name
Test status
Simulation time	43536611 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:20 PM PDT 24
Peak memory	201080 kb
Host	smart-fa9b9357-a8a7-45e1-bb6d-746321a93e4a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053124764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.1053124764
Directory	/workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_status.1753494106
Short name	T673
Test name
Test status
Simulation time	18541311 ps
CPU time	0.74 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:20 PM PDT 24
Peak memory	201076 kb
Host	smart-8513b5eb-4dfc-447d-8b43-20792540a58a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753494106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1753494106
Directory	/workspace/16.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/16.clkmgr_div_intersig_mubi.3718070087
Short name	T828
Test name
Test status
Simulation time	23235572 ps
CPU time	0.89 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:23 PM PDT 24
Peak memory	201056 kb
Host	smart-500004c8-c73a-4cf9-8c02-7197a7ceb84f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718070087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.3718070087
Directory	/workspace/16.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_extclk.381853116
Short name	T753
Test name
Test status
Simulation time	60052605 ps
CPU time	1.08 seconds
Started	Jul 18 06:41:56 PM PDT 24
Finished	Jul 18 06:41:58 PM PDT 24
Peak memory	201076 kb
Host	smart-84181c85-1388-4d26-8158-f964264de5b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381853116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.381853116
Directory	/workspace/16.clkmgr_extclk/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency.337000969
Short name	T289
Test name
Test status
Simulation time	1299167473 ps
CPU time	6.18 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:42:05 PM PDT 24
Peak memory	201144 kb
Host	smart-4943b6b1-5b52-4e6e-a1b1-f760644f161a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337000969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.337000969
Directory	/workspace/16.clkmgr_frequency/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency_timeout.485421247
Short name	T649
Test name
Test status
Simulation time	1708769286 ps
CPU time	7.28 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201144 kb
Host	smart-2a73016f-fe9b-45de-9804-82d17a1030a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485421247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_ti meout.485421247
Directory	/workspace/16.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2955192508
Short name	T81
Test name
Test status
Simulation time	40229436 ps
CPU time	1.08 seconds
Started	Jul 18 06:42:19 PM PDT 24
Finished	Jul 18 06:42:24 PM PDT 24
Peak memory	201120 kb
Host	smart-d80f9571-ca4c-4f15-baf2-cfc134bb4d88
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955192508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.2955192508
Directory	/workspace/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2846498197
Short name	T442
Test name
Test status
Simulation time	33255352 ps
CPU time	0.86 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:19 PM PDT 24
Peak memory	201120 kb
Host	smart-572c77ef-eb25-450d-909f-c40bff9777df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846498197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_clk_byp_req_intersig_mubi.2846498197
Directory	/workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.335073596
Short name	T680
Test name
Test status
Simulation time	80105131 ps
CPU time	1.04 seconds
Started	Jul 18 06:42:19 PM PDT 24
Finished	Jul 18 06:42:24 PM PDT 24
Peak memory	201088 kb
Host	smart-37aa05c8-3927-471a-adff-1f905d12a5de
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335073596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.clkmgr_lc_ctrl_intersig_mubi.335073596
Directory	/workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_peri.2407012464
Short name	T846
Test name
Test status
Simulation time	25716519 ps
CPU time	0.75 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:20 PM PDT 24
Peak memory	201024 kb
Host	smart-83fe7ea3-9c9c-4ce4-9edf-8cebac3de3d0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407012464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2407012464
Directory	/workspace/16.clkmgr_peri/latest

Test location	/workspace/coverage/default/16.clkmgr_regwen.1486352523
Short name	T638
Test name
Test status
Simulation time	371452362 ps
CPU time	2.82 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:24 PM PDT 24
Peak memory	201252 kb
Host	smart-fa3e3bda-2d63-4f74-a04b-f634ca75980c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486352523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1486352523
Directory	/workspace/16.clkmgr_regwen/latest

Test location	/workspace/coverage/default/16.clkmgr_smoke.1374077676
Short name	T613
Test name
Test status
Simulation time	17382602 ps
CPU time	0.78 seconds
Started	Jul 18 06:41:57 PM PDT 24
Finished	Jul 18 06:42:00 PM PDT 24
Peak memory	200932 kb
Host	smart-ad83ec8f-dde3-4172-afa9-f66a6fb7f67b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374077676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.1374077676
Directory	/workspace/16.clkmgr_smoke/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all.3599025772
Short name	T462
Test name
Test status
Simulation time	14116802238 ps
CPU time	98.83 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:44:04 PM PDT 24
Peak memory	201476 kb
Host	smart-7078fd0a-a182-474e-8e33-6dac5e379955
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599025772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.3599025772
Directory	/workspace/16.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.1047569521
Short name	T355
Test name
Test status
Simulation time	68138963656 ps
CPU time	472.93 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:50:18 PM PDT 24
Peak memory	217872 kb
Host	smart-b0f63a3c-4382-4e04-abdd-d14efb5acf70
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1047569521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.1047569521
Directory	/workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.clkmgr_trans.2152805299
Short name	T284
Test name
Test status
Simulation time	78703009 ps
CPU time	1.16 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:21 PM PDT 24
Peak memory	201132 kb
Host	smart-68bed05c-ebca-4623-9c8c-c76b8ec77388
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152805299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.2152805299
Directory	/workspace/16.clkmgr_trans/latest

Test location	/workspace/coverage/default/17.clkmgr_alert_test.2144620699
Short name	T100
Test name
Test status
Simulation time	62874903 ps
CPU time	0.98 seconds
Started	Jul 18 06:42:22 PM PDT 24
Finished	Jul 18 06:42:28 PM PDT 24
Peak memory	201216 kb
Host	smart-852b0a39-34ae-43bf-9ae4-1b43e593ee7d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144620699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.2144620699
Directory	/workspace/17.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2030985109
Short name	T460
Test name
Test status
Simulation time	42642181 ps
CPU time	0.78 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:20 PM PDT 24
Peak memory	201004 kb
Host	smart-dfd11639-c76e-40cf-8069-b3f46e2417f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030985109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.2030985109
Directory	/workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_status.868589678
Short name	T275
Test name
Test status
Simulation time	19590548 ps
CPU time	0.69 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:21 PM PDT 24
Peak memory	200944 kb
Host	smart-5118f502-efbc-499d-a1c9-aeaa3ad92123
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868589678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.868589678
Directory	/workspace/17.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/17.clkmgr_div_intersig_mubi.2825406274
Short name	T654
Test name
Test status
Simulation time	70155391 ps
CPU time	0.96 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:25 PM PDT 24
Peak memory	201100 kb
Host	smart-b259acfa-1beb-4bb0-b222-f3adcf7ac2da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825406274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.2825406274
Directory	/workspace/17.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_extclk.3543114415
Short name	T475
Test name
Test status
Simulation time	92523044 ps
CPU time	1.07 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201172 kb
Host	smart-b275de6e-c059-4b8a-a3f2-4a5accd0d03d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543114415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3543114415
Directory	/workspace/17.clkmgr_extclk/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency.1363830027
Short name	T716
Test name
Test status
Simulation time	2236628632 ps
CPU time	16.52 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:37 PM PDT 24
Peak memory	201388 kb
Host	smart-e315dadf-a60e-48db-a30c-5a0db3412c16
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363830027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1363830027
Directory	/workspace/17.clkmgr_frequency/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency_timeout.4222179230
Short name	T28
Test name
Test status
Simulation time	2066078610 ps
CPU time	11.03 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:36 PM PDT 24
Peak memory	201416 kb
Host	smart-b282feed-f658-401b-96e2-cb0c3f48872d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222179230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t imeout.4222179230
Directory	/workspace/17.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3024141316
Short name	T650
Test name
Test status
Simulation time	53020399 ps
CPU time	0.95 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:25 PM PDT 24
Peak memory	201084 kb
Host	smart-4d55c1f3-2d72-49cd-80c8-7b825ef515a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024141316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.3024141316
Directory	/workspace/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2195726601
Short name	T413
Test name
Test status
Simulation time	51915058 ps
CPU time	0.91 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201104 kb
Host	smart-f37963a9-20e5-4977-b148-3c0bd3098170
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195726601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_clk_byp_req_intersig_mubi.2195726601
Directory	/workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1273109446
Short name	T551
Test name
Test status
Simulation time	34412332 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:22 PM PDT 24
Peak memory	201124 kb
Host	smart-7dae1b7b-c392-4221-a926-89e7fb94d87f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273109446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_ctrl_intersig_mubi.1273109446
Directory	/workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_peri.1686680501
Short name	T49
Test name
Test status
Simulation time	42924819 ps
CPU time	0.82 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:25 PM PDT 24
Peak memory	201212 kb
Host	smart-e77c32ee-7e2f-4a76-8a1a-82329420459f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686680501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1686680501
Directory	/workspace/17.clkmgr_peri/latest

Test location	/workspace/coverage/default/17.clkmgr_regwen.697520836
Short name	T164
Test name
Test status
Simulation time	162631661 ps
CPU time	1.3 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:28 PM PDT 24
Peak memory	201044 kb
Host	smart-189d637b-8367-4a21-9b30-85df14c50c1a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697520836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.697520836
Directory	/workspace/17.clkmgr_regwen/latest

Test location	/workspace/coverage/default/17.clkmgr_smoke.3413245212
Short name	T838
Test name
Test status
Simulation time	105381679 ps
CPU time	1.06 seconds
Started	Jul 18 06:42:25 PM PDT 24
Finished	Jul 18 06:42:30 PM PDT 24
Peak memory	201064 kb
Host	smart-05fb09a0-963b-4a83-ac8e-ed85414c0714
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413245212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3413245212
Directory	/workspace/17.clkmgr_smoke/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.2245964538
Short name	T12
Test name
Test status
Simulation time	21307415072 ps
CPU time	388.09 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:48:54 PM PDT 24
Peak memory	217872 kb
Host	smart-ad560d63-fe56-4c27-bd68-a3db6641759f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2245964538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.2245964538
Directory	/workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.clkmgr_trans.3486661523
Short name	T367
Test name
Test status
Simulation time	19509982 ps
CPU time	0.73 seconds
Started	Jul 18 06:42:25 PM PDT 24
Finished	Jul 18 06:42:30 PM PDT 24
Peak memory	201056 kb
Host	smart-c3e3506f-c1e7-4c79-a26c-26f255c0d024
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486661523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.3486661523
Directory	/workspace/17.clkmgr_trans/latest

Test location	/workspace/coverage/default/18.clkmgr_alert_test.55120958
Short name	T790
Test name
Test status
Simulation time	44998831 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:42:29 PM PDT 24
Peak memory	201212 kb
Host	smart-8a6d51ba-eaef-438d-908b-9d4cd308615d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55120958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmg r_alert_test.55120958
Directory	/workspace/18.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3368713140
Short name	T86
Test name
Test status
Simulation time	23176995 ps
CPU time	0.86 seconds
Started	Jul 18 06:42:24 PM PDT 24
Finished	Jul 18 06:42:30 PM PDT 24
Peak memory	201088 kb
Host	smart-623c6bb7-bb4b-4894-9abd-f8709001793c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368713140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.3368713140
Directory	/workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_status.1094591557
Short name	T60
Test name
Test status
Simulation time	17386214 ps
CPU time	0.72 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:26 PM PDT 24
Peak memory	200340 kb
Host	smart-aaf7851c-2d16-4a20-bf49-784c4cced442
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094591557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.1094591557
Directory	/workspace/18.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/18.clkmgr_div_intersig_mubi.3361672625
Short name	T269
Test name
Test status
Simulation time	26355699 ps
CPU time	0.9 seconds
Started	Jul 18 06:42:24 PM PDT 24
Finished	Jul 18 06:42:30 PM PDT 24
Peak memory	201088 kb
Host	smart-5c60e4d9-ef8a-4571-a2aa-970081d1dc1d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361672625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.3361672625
Directory	/workspace/18.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_extclk.101187743
Short name	T199
Test name
Test status
Simulation time	21565821 ps
CPU time	0.85 seconds
Started	Jul 18 06:42:19 PM PDT 24
Finished	Jul 18 06:42:23 PM PDT 24
Peak memory	201092 kb
Host	smart-e76aa26f-c6a9-4935-b281-cdcc518ea9ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101187743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.101187743
Directory	/workspace/18.clkmgr_extclk/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency.1858285044
Short name	T441
Test name
Test status
Simulation time	678294154 ps
CPU time	5.64 seconds
Started	Jul 18 06:42:24 PM PDT 24
Finished	Jul 18 06:42:34 PM PDT 24
Peak memory	201176 kb
Host	smart-41a41229-0c4f-4eca-8d18-c31c88c0c8d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858285044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1858285044
Directory	/workspace/18.clkmgr_frequency/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency_timeout.2310810268
Short name	T537
Test name
Test status
Simulation time	1718425310 ps
CPU time	7.24 seconds
Started	Jul 18 06:42:19 PM PDT 24
Finished	Jul 18 06:42:31 PM PDT 24
Peak memory	201260 kb
Host	smart-6cd3530c-2afd-41b4-b2e5-48d6fc976bd2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310810268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.2310810268
Directory	/workspace/18.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2487436031
Short name	T683
Test name
Test status
Simulation time	19757512 ps
CPU time	0.79 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:42:29 PM PDT 24
Peak memory	201084 kb
Host	smart-55f8a2de-7c7d-42ce-bbff-55136cf9fc4f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487436031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.2487436031
Directory	/workspace/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2865414821
Short name	T433
Test name
Test status
Simulation time	16555101 ps
CPU time	0.79 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:20 PM PDT 24
Peak memory	201120 kb
Host	smart-6b56f256-7960-44b5-a9e9-fe349c118661
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865414821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_clk_byp_req_intersig_mubi.2865414821
Directory	/workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3038251786
Short name	T233
Test name
Test status
Simulation time	94408853 ps
CPU time	1.02 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:42:29 PM PDT 24
Peak memory	201096 kb
Host	smart-4d8401c0-af3d-4121-a31d-89dbcd1e0a69
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038251786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_ctrl_intersig_mubi.3038251786
Directory	/workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_peri.2821908825
Short name	T741
Test name
Test status
Simulation time	43332660 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:25 PM PDT 24
Finished	Jul 18 06:42:30 PM PDT 24
Peak memory	201072 kb
Host	smart-1604f531-3da2-47be-9871-ff4f5fc2484b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821908825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2821908825
Directory	/workspace/18.clkmgr_peri/latest

Test location	/workspace/coverage/default/18.clkmgr_regwen.1280826206
Short name	T21
Test name
Test status
Simulation time	1404330171 ps
CPU time	5.11 seconds
Started	Jul 18 06:42:24 PM PDT 24
Finished	Jul 18 06:42:34 PM PDT 24
Peak memory	201276 kb
Host	smart-65ddf17e-8dba-4c62-b9fa-0826f053e695
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280826206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.1280826206
Directory	/workspace/18.clkmgr_regwen/latest

Test location	/workspace/coverage/default/18.clkmgr_smoke.2367572512
Short name	T154
Test name
Test status
Simulation time	24228831 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:22 PM PDT 24
Peak memory	201036 kb
Host	smart-31b54eac-0eb6-4513-a550-5bc6d2ffa28d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367572512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2367572512
Directory	/workspace/18.clkmgr_smoke/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all.214559869
Short name	T378
Test name
Test status
Simulation time	12659927441 ps
CPU time	52.52 seconds
Started	Jul 18 06:42:24 PM PDT 24
Finished	Jul 18 06:43:22 PM PDT 24
Peak memory	201452 kb
Host	smart-f1683c03-fe0f-4a76-96a4-cb46f2a6ab46
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214559869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.214559869
Directory	/workspace/18.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.1196868878
Short name	T845
Test name
Test status
Simulation time	86601661257 ps
CPU time	938.02 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:58:06 PM PDT 24
Peak memory	209768 kb
Host	smart-84d6c1f4-29c1-42d0-89c0-9c5dc8800318
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1196868878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.1196868878
Directory	/workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.clkmgr_trans.355308433
Short name	T240
Test name
Test status
Simulation time	129026891 ps
CPU time	1.33 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:28 PM PDT 24
Peak memory	201084 kb
Host	smart-c0ebaa09-8ab3-4658-b778-8c760cbbe5b1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355308433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.355308433
Directory	/workspace/18.clkmgr_trans/latest

Test location	/workspace/coverage/default/19.clkmgr_alert_test.136356689
Short name	T757
Test name
Test status
Simulation time	38576281 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201224 kb
Host	smart-194d2c4a-65fb-43e6-9bc1-b0871d0c9521
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136356689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkm gr_alert_test.136356689
Directory	/workspace/19.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.983112999
Short name	T549
Test name
Test status
Simulation time	20467350 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:17 PM PDT 24
Finished	Jul 18 06:42:19 PM PDT 24
Peak memory	201100 kb
Host	smart-216bf1dd-c58a-47fd-963d-bda29ad65d96
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983112999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.983112999
Directory	/workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_status.1910904254
Short name	T317
Test name
Test status
Simulation time	50052649 ps
CPU time	0.75 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:42:29 PM PDT 24
Peak memory	200976 kb
Host	smart-97d53bd8-a812-4fbb-9eee-31b0d3876ca9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910904254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1910904254
Directory	/workspace/19.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/19.clkmgr_div_intersig_mubi.1100165843
Short name	T756
Test name
Test status
Simulation time	92350467 ps
CPU time	1.07 seconds
Started	Jul 18 06:42:16 PM PDT 24
Finished	Jul 18 06:42:18 PM PDT 24
Peak memory	201168 kb
Host	smart-7c132b5b-e4d1-46da-8b36-6080234def24
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100165843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.1100165843
Directory	/workspace/19.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_extclk.2611650250
Short name	T564
Test name
Test status
Simulation time	25744571 ps
CPU time	0.79 seconds
Started	Jul 18 06:42:22 PM PDT 24
Finished	Jul 18 06:42:29 PM PDT 24
Peak memory	201080 kb
Host	smart-308f9d94-9ae1-4369-86db-bc8254faaaa2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611650250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2611650250
Directory	/workspace/19.clkmgr_extclk/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency.3277393089
Short name	T22
Test name
Test status
Simulation time	367692821 ps
CPU time	2.08 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:42:30 PM PDT 24
Peak memory	201164 kb
Host	smart-186683ff-1063-404d-8577-bff120932d03
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277393089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3277393089
Directory	/workspace/19.clkmgr_frequency/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency_timeout.2750340714
Short name	T590
Test name
Test status
Simulation time	2598045976 ps
CPU time	8.1 seconds
Started	Jul 18 06:42:24 PM PDT 24
Finished	Jul 18 06:42:37 PM PDT 24
Peak memory	201464 kb
Host	smart-4d9fdc4b-076a-4c05-aa55-c2d26ffff518
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750340714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t imeout.2750340714
Directory	/workspace/19.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/19.clkmgr_idle_intersig_mubi.3401871603
Short name	T747
Test name
Test status
Simulation time	67563241 ps
CPU time	0.99 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:22 PM PDT 24
Peak memory	201096 kb
Host	smart-60778346-7495-45e1-8ba9-b5b49451d314
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401871603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.3401871603
Directory	/workspace/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.1487979130
Short name	T300
Test name
Test status
Simulation time	12080958 ps
CPU time	0.7 seconds
Started	Jul 18 06:42:16 PM PDT 24
Finished	Jul 18 06:42:17 PM PDT 24
Peak memory	201100 kb
Host	smart-0a6cd9ab-5e48-4651-8fef-d3281e0cb7b1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487979130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_clk_byp_req_intersig_mubi.1487979130
Directory	/workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.772181401
Short name	T256
Test name
Test status
Simulation time	26353468 ps
CPU time	0.91 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:23 PM PDT 24
Peak memory	201280 kb
Host	smart-2d996e63-0ad5-48c0-a1f2-f13530cc9174
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772181401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.clkmgr_lc_ctrl_intersig_mubi.772181401
Directory	/workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_peri.624533574
Short name	T794
Test name
Test status
Simulation time	40685972 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201028 kb
Host	smart-7d919270-946b-4646-9a53-94a89fae0044
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624533574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.624533574
Directory	/workspace/19.clkmgr_peri/latest

Test location	/workspace/coverage/default/19.clkmgr_regwen.850270078
Short name	T722
Test name
Test status
Simulation time	697890278 ps
CPU time	3.94 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:26 PM PDT 24
Peak memory	201268 kb
Host	smart-820187fd-49c6-4636-8956-23db6f9348dc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850270078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.850270078
Directory	/workspace/19.clkmgr_regwen/latest

Test location	/workspace/coverage/default/19.clkmgr_smoke.167920214
Short name	T705
Test name
Test status
Simulation time	35778227 ps
CPU time	0.91 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:42:29 PM PDT 24
Peak memory	201024 kb
Host	smart-a605020f-bab1-4132-b06d-d80ac83f956e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167920214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.167920214
Directory	/workspace/19.clkmgr_smoke/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.2894003556
Short name	T524
Test name
Test status
Simulation time	47134457710 ps
CPU time	424.74 seconds
Started	Jul 18 06:42:24 PM PDT 24
Finished	Jul 18 06:49:33 PM PDT 24
Peak memory	209888 kb
Host	smart-8d921778-d1fd-4b56-8679-94a3fe6c9937
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2894003556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.2894003556
Directory	/workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.clkmgr_trans.3728713413
Short name	T713
Test name
Test status
Simulation time	25093131 ps
CPU time	0.91 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:42:29 PM PDT 24
Peak memory	201100 kb
Host	smart-744c2549-74ea-4cff-bd36-162b43ce906e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728713413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3728713413
Directory	/workspace/19.clkmgr_trans/latest

Test location	/workspace/coverage/default/2.clkmgr_alert_test.2540904801
Short name	T360
Test name
Test status
Simulation time	21935999 ps
CPU time	0.73 seconds
Started	Jul 18 06:40:31 PM PDT 24
Finished	Jul 18 06:40:36 PM PDT 24
Peak memory	201208 kb
Host	smart-6088e118-2b06-4879-930d-3c19d6098cc2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540904801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm gr_alert_test.2540904801
Directory	/workspace/2.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1652195679
Short name	T318
Test name
Test status
Simulation time	14152216 ps
CPU time	0.7 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:34 PM PDT 24
Peak memory	201080 kb
Host	smart-68f57d0b-d33f-40ef-8cac-fa6342299340
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652195679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.1652195679
Directory	/workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_status.3237487128
Short name	T501
Test name
Test status
Simulation time	38634119 ps
CPU time	0.76 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:34 PM PDT 24
Peak memory	200288 kb
Host	smart-f5cbd43e-e4cd-47ca-b47d-9ce60e4163e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237487128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.3237487128
Directory	/workspace/2.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/2.clkmgr_div_intersig_mubi.4285217967
Short name	T744
Test name
Test status
Simulation time	43515172 ps
CPU time	0.82 seconds
Started	Jul 18 06:40:31 PM PDT 24
Finished	Jul 18 06:40:36 PM PDT 24
Peak memory	201108 kb
Host	smart-57ff1d38-80df-43c4-9e34-83373166c653
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285217967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.4285217967
Directory	/workspace/2.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_extclk.536463340
Short name	T581
Test name
Test status
Simulation time	23568189 ps
CPU time	0.83 seconds
Started	Jul 18 06:40:36 PM PDT 24
Finished	Jul 18 06:40:40 PM PDT 24
Peak memory	200960 kb
Host	smart-09afc147-9fe3-440f-9dc5-ed31f9bb9a1d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536463340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.536463340
Directory	/workspace/2.clkmgr_extclk/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency.634746997
Short name	T133
Test name
Test status
Simulation time	200253967 ps
CPU time	1.74 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:35 PM PDT 24
Peak memory	201068 kb
Host	smart-9342173b-9358-4d81-af99-20396a841247
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634746997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.634746997
Directory	/workspace/2.clkmgr_frequency/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency_timeout.2938426259
Short name	T629
Test name
Test status
Simulation time	2018977454 ps
CPU time	8.13 seconds
Started	Jul 18 06:40:33 PM PDT 24
Finished	Jul 18 06:40:45 PM PDT 24
Peak memory	201196 kb
Host	smart-99c32a79-433f-4c5e-bf93-4cfed409f7e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938426259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti meout.2938426259
Directory	/workspace/2.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/2.clkmgr_idle_intersig_mubi.103863593
Short name	T749
Test name
Test status
Simulation time	28554940 ps
CPU time	0.89 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:34 PM PDT 24
Peak memory	201152 kb
Host	smart-0f5611ae-d335-415f-86b4-bd2e1f9f8241
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103863593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .clkmgr_idle_intersig_mubi.103863593
Directory	/workspace/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3048026890
Short name	T405
Test name
Test status
Simulation time	16911882 ps
CPU time	0.75 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:40:37 PM PDT 24
Peak memory	201116 kb
Host	smart-ad18ae61-cde9-4db3-a4c2-65f376d0d936
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048026890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.3048026890
Directory	/workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3333587026
Short name	T603
Test name
Test status
Simulation time	123091293 ps
CPU time	1.19 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:34 PM PDT 24
Peak memory	201092 kb
Host	smart-5e2113bf-8b85-4e9f-a800-a9fbc2d74e40
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333587026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.3333587026
Directory	/workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_peri.3407241072
Short name	T802
Test name
Test status
Simulation time	45508947 ps
CPU time	0.81 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:35 PM PDT 24
Peak memory	201032 kb
Host	smart-9603c07e-a930-44f2-9d63-e90c0202cc2d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407241072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.3407241072
Directory	/workspace/2.clkmgr_peri/latest

Test location	/workspace/coverage/default/2.clkmgr_regwen.1869454770
Short name	T468
Test name
Test status
Simulation time	95119440 ps
CPU time	1.06 seconds
Started	Jul 18 06:40:33 PM PDT 24
Finished	Jul 18 06:40:38 PM PDT 24
Peak memory	200556 kb
Host	smart-58df2558-7dc3-4c82-a429-bf2744583a99
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869454770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1869454770
Directory	/workspace/2.clkmgr_regwen/latest

Test location	/workspace/coverage/default/2.clkmgr_sec_cm.4098375212
Short name	T43
Test name
Test status
Simulation time	158451087 ps
CPU time	2.07 seconds
Started	Jul 18 06:40:34 PM PDT 24
Finished	Jul 18 06:40:40 PM PDT 24
Peak memory	216304 kb
Host	smart-ebb1fcbc-d092-41cd-a30a-7e64c7cafa7f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098375212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg r_sec_cm.4098375212
Directory	/workspace/2.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/2.clkmgr_smoke.1146762252
Short name	T150
Test name
Test status
Simulation time	26390519 ps
CPU time	0.89 seconds
Started	Jul 18 06:40:29 PM PDT 24
Finished	Jul 18 06:40:33 PM PDT 24
Peak memory	201036 kb
Host	smart-b24569da-64d9-4b23-8bf3-5a0b6d4a0779
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146762252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.1146762252
Directory	/workspace/2.clkmgr_smoke/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all.1076881523
Short name	T841
Test name
Test status
Simulation time	6026946050 ps
CPU time	42.25 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:41:18 PM PDT 24
Peak memory	201476 kb
Host	smart-c0509fa5-28bf-4aaa-bb22-8f000b4792f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076881523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.1076881523
Directory	/workspace/2.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.2677031375
Short name	T237
Test name
Test status
Simulation time	15224365672 ps
CPU time	91.76 seconds
Started	Jul 18 06:40:32 PM PDT 24
Finished	Jul 18 06:42:08 PM PDT 24
Peak memory	209784 kb
Host	smart-9dfa2864-b885-4bfb-a4cd-3e815a53812e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2677031375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2677031375
Directory	/workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_trans.2351091184
Short name	T261
Test name
Test status
Simulation time	80375524 ps
CPU time	1 seconds
Started	Jul 18 06:40:36 PM PDT 24
Finished	Jul 18 06:40:40 PM PDT 24
Peak memory	201240 kb
Host	smart-eb7212c2-13dd-41ff-aa24-800a19bd591d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351091184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2351091184
Directory	/workspace/2.clkmgr_trans/latest

Test location	/workspace/coverage/default/20.clkmgr_alert_test.1251571099
Short name	T27
Test name
Test status
Simulation time	77336554 ps
CPU time	0.9 seconds
Started	Jul 18 06:42:19 PM PDT 24
Finished	Jul 18 06:42:25 PM PDT 24
Peak memory	201224 kb
Host	smart-50baf1cd-5910-4e56-9b78-d1d04040938c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251571099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk mgr_alert_test.1251571099
Directory	/workspace/20.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3709777468
Short name	T18
Test name
Test status
Simulation time	23385623 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:25 PM PDT 24
Peak memory	201108 kb
Host	smart-83f36876-f972-4d51-83a2-849dabe2bbaa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709777468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3709777468
Directory	/workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_status.1363303959
Short name	T742
Test name
Test status
Simulation time	108376346 ps
CPU time	0.96 seconds
Started	Jul 18 06:42:19 PM PDT 24
Finished	Jul 18 06:42:24 PM PDT 24
Peak memory	200472 kb
Host	smart-e7fec794-4aac-48dd-b8b4-c763fa07143d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363303959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1363303959
Directory	/workspace/20.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/20.clkmgr_div_intersig_mubi.3205822332
Short name	T249
Test name
Test status
Simulation time	56623024 ps
CPU time	0.94 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:25 PM PDT 24
Peak memory	201084 kb
Host	smart-ec5a6415-078d-4968-9414-a556586e0f3c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205822332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.3205822332
Directory	/workspace/20.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_extclk.1347755400
Short name	T750
Test name
Test status
Simulation time	50315252 ps
CPU time	0.99 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:26 PM PDT 24
Peak memory	201024 kb
Host	smart-d2214ab6-9f57-45df-b3b8-70c1779bbf18
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347755400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1347755400
Directory	/workspace/20.clkmgr_extclk/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency.111817760
Short name	T260
Test name
Test status
Simulation time	2411674453 ps
CPU time	10.78 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:32 PM PDT 24
Peak memory	201412 kb
Host	smart-d2b20882-7217-4ca4-a6cf-cbf0d47016c9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111817760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.111817760
Directory	/workspace/20.clkmgr_frequency/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency_timeout.3408520447
Short name	T585
Test name
Test status
Simulation time	1456722858 ps
CPU time	10.72 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:36 PM PDT 24
Peak memory	201224 kb
Host	smart-60376763-3e55-4804-95d2-ca377343ca52
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408520447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t imeout.3408520447
Directory	/workspace/20.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1250977326
Short name	T54
Test name
Test status
Simulation time	104512407 ps
CPU time	0.98 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:23 PM PDT 24
Peak memory	201048 kb
Host	smart-4e5aadfc-fd98-43b6-bd18-368ce48faf43
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250977326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.1250977326
Directory	/workspace/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2454248422
Short name	T563
Test name
Test status
Simulation time	15933900 ps
CPU time	0.74 seconds
Started	Jul 18 06:42:18 PM PDT 24
Finished	Jul 18 06:42:21 PM PDT 24
Peak memory	201120 kb
Host	smart-fc5808ae-2d62-45ba-89b4-dd8690f2daa3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454248422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2454248422
Directory	/workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1190914791
Short name	T600
Test name
Test status
Simulation time	101220965 ps
CPU time	1.13 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201188 kb
Host	smart-c7203ba3-269e-420c-9889-f841aafa9929
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190914791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_ctrl_intersig_mubi.1190914791
Directory	/workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_peri.169007152
Short name	T272
Test name
Test status
Simulation time	20828853 ps
CPU time	0.76 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201152 kb
Host	smart-160d36a9-8047-4280-abd4-b36fc635e481
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169007152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.169007152
Directory	/workspace/20.clkmgr_peri/latest

Test location	/workspace/coverage/default/20.clkmgr_regwen.4230876491
Short name	T682
Test name
Test status
Simulation time	935540058 ps
CPU time	4.23 seconds
Started	Jul 18 06:42:19 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201256 kb
Host	smart-80193bf6-f01b-4410-a6fb-6b9a2dc437f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230876491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.4230876491
Directory	/workspace/20.clkmgr_regwen/latest

Test location	/workspace/coverage/default/20.clkmgr_smoke.3493634135
Short name	T591
Test name
Test status
Simulation time	22035208 ps
CPU time	0.89 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 06:42:27 PM PDT 24
Peak memory	201040 kb
Host	smart-d0f44072-d61b-486a-8df8-eefe75cde95f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493634135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3493634135
Directory	/workspace/20.clkmgr_smoke/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all.1842110269
Short name	T663
Test name
Test status
Simulation time	6386426436 ps
CPU time	35.1 seconds
Started	Jul 18 06:42:23 PM PDT 24
Finished	Jul 18 06:43:03 PM PDT 24
Peak memory	201452 kb
Host	smart-5f900a91-c860-4838-b932-de06d10d7e57
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842110269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.1842110269
Directory	/workspace/20.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.218579770
Short name	T780
Test name
Test status
Simulation time	148483390457 ps
CPU time	1078.46 seconds
Started	Jul 18 06:42:21 PM PDT 24
Finished	Jul 18 07:00:25 PM PDT 24
Peak memory	217992 kb
Host	smart-70992a1c-10ac-48a7-9308-b79316766c9c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=218579770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.218579770
Directory	/workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.clkmgr_trans.3431305668
Short name	T229
Test name
Test status
Simulation time	338656336 ps
CPU time	1.82 seconds
Started	Jul 18 06:42:16 PM PDT 24
Finished	Jul 18 06:42:19 PM PDT 24
Peak memory	201088 kb
Host	smart-8d1ed105-35c6-4655-9408-249b3c8fdc06
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431305668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.3431305668
Directory	/workspace/20.clkmgr_trans/latest

Test location	/workspace/coverage/default/21.clkmgr_alert_test.3275253903
Short name	T313
Test name
Test status
Simulation time	29126202 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201224 kb
Host	smart-6bdc1d6e-03ff-4955-aa59-96788cdda088
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275253903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.3275253903
Directory	/workspace/21.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2965217585
Short name	T796
Test name
Test status
Simulation time	71647400 ps
CPU time	0.94 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:45 PM PDT 24
Peak memory	201096 kb
Host	smart-9a2eed44-8f9d-4d77-9370-49d5fe05d6a7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965217585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.2965217585
Directory	/workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_status.376961891
Short name	T799
Test name
Test status
Simulation time	14044206 ps
CPU time	0.7 seconds
Started	Jul 18 06:42:33 PM PDT 24
Finished	Jul 18 06:42:35 PM PDT 24
Peak memory	200216 kb
Host	smart-abaf2c75-1fa5-4db6-ad11-cd85c63e1f59
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376961891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.376961891
Directory	/workspace/21.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/21.clkmgr_div_intersig_mubi.3926421783
Short name	T393
Test name
Test status
Simulation time	13182275 ps
CPU time	0.72 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:44 PM PDT 24
Peak memory	201096 kb
Host	smart-0b6c3500-e200-44d8-8699-791efcfb3ab9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926421783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.3926421783
Directory	/workspace/21.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_extclk.3615996987
Short name	T544
Test name
Test status
Simulation time	18075802 ps
CPU time	0.79 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:26 PM PDT 24
Peak memory	201080 kb
Host	smart-a2f46377-1a49-4856-8e6b-17d5a7d4aef8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615996987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.3615996987
Directory	/workspace/21.clkmgr_extclk/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency.3074431502
Short name	T252
Test name
Test status
Simulation time	571619919 ps
CPU time	3.81 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:48 PM PDT 24
Peak memory	201156 kb
Host	smart-c2df6975-69d5-4990-86bd-7943cced20d9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074431502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3074431502
Directory	/workspace/21.clkmgr_frequency/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency_timeout.3255418135
Short name	T542
Test name
Test status
Simulation time	500521558 ps
CPU time	3.12 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201236 kb
Host	smart-7753e4d3-e6f9-4b6a-ada1-e1284a4a503f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255418135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t imeout.3255418135
Directory	/workspace/21.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_idle_intersig_mubi.4136113390
Short name	T288
Test name
Test status
Simulation time	37545433 ps
CPU time	0.99 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:39 PM PDT 24
Peak memory	201180 kb
Host	smart-8f0fe218-1bb0-4bc2-a38f-e5e476ea5204
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136113390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.4136113390
Directory	/workspace/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.118586663
Short name	T690
Test name
Test status
Simulation time	50051991 ps
CPU time	0.89 seconds
Started	Jul 18 06:42:33 PM PDT 24
Finished	Jul 18 06:42:35 PM PDT 24
Peak memory	201120 kb
Host	smart-3a30396f-b9ec-4f52-b276-2a3155628d25
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118586663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.clkmgr_lc_clk_byp_req_intersig_mubi.118586663
Directory	/workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1685950144
Short name	T565
Test name
Test status
Simulation time	26289540 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:39 PM PDT 24
Peak memory	201076 kb
Host	smart-7e95af8e-004c-4bfe-8466-83920eee9524
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685950144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_ctrl_intersig_mubi.1685950144
Directory	/workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_peri.2381709778
Short name	T223
Test name
Test status
Simulation time	42921176 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201040 kb
Host	smart-40c7e31d-d319-4a75-960e-cab30af42c46
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381709778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2381709778
Directory	/workspace/21.clkmgr_peri/latest

Test location	/workspace/coverage/default/21.clkmgr_regwen.1515713910
Short name	T160
Test name
Test status
Simulation time	1290570530 ps
CPU time	5.7 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:50 PM PDT 24
Peak memory	201264 kb
Host	smart-e643428c-58ab-44ae-8e70-0d4958c67efb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515713910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1515713910
Directory	/workspace/21.clkmgr_regwen/latest

Test location	/workspace/coverage/default/21.clkmgr_smoke.113744774
Short name	T725
Test name
Test status
Simulation time	67338740 ps
CPU time	0.96 seconds
Started	Jul 18 06:42:20 PM PDT 24
Finished	Jul 18 06:42:25 PM PDT 24
Peak memory	201112 kb
Host	smart-b8ed2562-416e-452a-be2f-abf60e38fdf5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113744774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.113744774
Directory	/workspace/21.clkmgr_smoke/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all.3016655376
Short name	T525
Test name
Test status
Simulation time	13137818722 ps
CPU time	94.08 seconds
Started	Jul 18 06:42:33 PM PDT 24
Finished	Jul 18 06:44:09 PM PDT 24
Peak memory	201468 kb
Host	smart-3d65a7a4-32eb-4309-9bdc-88de8e78053b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016655376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.3016655376
Directory	/workspace/21.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.2459205922
Short name	T321
Test name
Test status
Simulation time	229772912404 ps
CPU time	1126.12 seconds
Started	Jul 18 06:42:34 PM PDT 24
Finished	Jul 18 07:01:22 PM PDT 24
Peak memory	209776 kb
Host	smart-76d04f83-39cb-439e-b3d9-ef79c2556ce8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2459205922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.2459205922
Directory	/workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.clkmgr_trans.4001183056
Short name	T706
Test name
Test status
Simulation time	34231109 ps
CPU time	1.03 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:40 PM PDT 24
Peak memory	201092 kb
Host	smart-d94032f5-e967-4a1c-8000-2e5f9a98ac36
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001183056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.4001183056
Directory	/workspace/21.clkmgr_trans/latest

Test location	/workspace/coverage/default/22.clkmgr_alert_test.3451021969
Short name	T771
Test name
Test status
Simulation time	28713300 ps
CPU time	0.78 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:39 PM PDT 24
Peak memory	201132 kb
Host	smart-6851ae7b-b164-4120-b0e9-172416ca8927
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451021969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk mgr_alert_test.3451021969
Directory	/workspace/22.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.3361530277
Short name	T769
Test name
Test status
Simulation time	36495944 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201108 kb
Host	smart-73e674fa-b474-4d34-8cbc-c6bc614cbe02
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361530277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.3361530277
Directory	/workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_status.2918315203
Short name	T692
Test name
Test status
Simulation time	30084677 ps
CPU time	0.74 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:40 PM PDT 24
Peak memory	200968 kb
Host	smart-f2ec69f5-450f-4de0-83df-6ca2fbec835a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918315203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2918315203
Directory	/workspace/22.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/22.clkmgr_div_intersig_mubi.3655116932
Short name	T669
Test name
Test status
Simulation time	159802702 ps
CPU time	1.16 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:44 PM PDT 24
Peak memory	201076 kb
Host	smart-65211674-441b-45e8-aae6-e4e0046304fe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655116932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.3655116932
Directory	/workspace/22.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_extclk.2065396289
Short name	T517
Test name
Test status
Simulation time	15191036 ps
CPU time	0.75 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:40 PM PDT 24
Peak memory	201080 kb
Host	smart-6bb72d2a-f892-48d9-9721-f3c209d6e1e2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065396289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2065396289
Directory	/workspace/22.clkmgr_extclk/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency.1747233660
Short name	T2
Test name
Test status
Simulation time	2497533561 ps
CPU time	10.36 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	201408 kb
Host	smart-47db0db1-f7fd-410f-871d-eed247933fa2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747233660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.1747233660
Directory	/workspace/22.clkmgr_frequency/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency_timeout.1917145567
Short name	T440
Test name
Test status
Simulation time	1838733101 ps
CPU time	7.75 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:46 PM PDT 24
Peak memory	201176 kb
Host	smart-dcffbb0f-45c1-44c3-b5e4-3d89f85c5a44
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917145567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t imeout.1917145567
Directory	/workspace/22.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/22.clkmgr_idle_intersig_mubi.2380315686
Short name	T274
Test name
Test status
Simulation time	37586183 ps
CPU time	1.02 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:46 PM PDT 24
Peak memory	201092 kb
Host	smart-8dd964cc-0323-4563-baca-a9d07f6bbe8d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380315686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.2380315686
Directory	/workspace/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2472413991
Short name	T623
Test name
Test status
Simulation time	44391523 ps
CPU time	0.87 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:45 PM PDT 24
Peak memory	201108 kb
Host	smart-470ad119-25b5-44e2-9619-92479dd489ff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472413991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2472413991
Directory	/workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1396542676
Short name	T163
Test name
Test status
Simulation time	21613559 ps
CPU time	0.92 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:44 PM PDT 24
Peak memory	201108 kb
Host	smart-e2d73f10-338b-4bc5-9728-58bc5d9c421a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396542676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_ctrl_intersig_mubi.1396542676
Directory	/workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_peri.3938832352
Short name	T847
Test name
Test status
Simulation time	41590851 ps
CPU time	0.83 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:47 PM PDT 24
Peak memory	201044 kb
Host	smart-e5e623b5-d357-44c5-9655-72f1ef629ee6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938832352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3938832352
Directory	/workspace/22.clkmgr_peri/latest

Test location	/workspace/coverage/default/22.clkmgr_regwen.2998865251
Short name	T454
Test name
Test status
Simulation time	132103277 ps
CPU time	1.23 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:48 PM PDT 24
Peak memory	201044 kb
Host	smart-1bacb6be-5c02-4c57-b63e-d557dc3d7740
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998865251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2998865251
Directory	/workspace/22.clkmgr_regwen/latest

Test location	/workspace/coverage/default/22.clkmgr_smoke.1798467039
Short name	T412
Test name
Test status
Simulation time	26051151 ps
CPU time	0.88 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:41 PM PDT 24
Peak memory	201040 kb
Host	smart-83cf73e3-655b-4a1b-a304-cf9dfcccda3a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798467039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1798467039
Directory	/workspace/22.clkmgr_smoke/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all.3961899435
Short name	T414
Test name
Test status
Simulation time	6421586195 ps
CPU time	40.37 seconds
Started	Jul 18 06:42:34 PM PDT 24
Finished	Jul 18 06:43:17 PM PDT 24
Peak memory	201464 kb
Host	smart-6b701649-01b4-4862-8013-5bb6e7f9a990
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961899435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.3961899435
Directory	/workspace/22.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.2983009530
Short name	T314
Test name
Test status
Simulation time	76801445486 ps
CPU time	464.45 seconds
Started	Jul 18 06:42:42 PM PDT 24
Finished	Jul 18 06:50:34 PM PDT 24
Peak memory	217900 kb
Host	smart-0cdcf642-7052-4a2c-afc0-e67583460258
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2983009530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.2983009530
Directory	/workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.clkmgr_trans.2681956525
Short name	T788
Test name
Test status
Simulation time	34980901 ps
CPU time	1.05 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201072 kb
Host	smart-624a6d42-738e-46a9-8ba2-c8727d3d28cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681956525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2681956525
Directory	/workspace/22.clkmgr_trans/latest

Test location	/workspace/coverage/default/23.clkmgr_alert_test.129502
Short name	T529
Test name
Test status
Simulation time	16776989 ps
CPU time	0.78 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:47 PM PDT 24
Peak memory	201244 kb
Host	smart-a0727ed6-6af2-4efb-981d-9fcedffc1e47
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_ SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_ alert_test.129502
Directory	/workspace/23.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1414740073
Short name	T453
Test name
Test status
Simulation time	18278353 ps
CPU time	0.83 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:47 PM PDT 24
Peak memory	201032 kb
Host	smart-7de41343-1c22-488e-8b6b-bac6c202cfa0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414740073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.1414740073
Directory	/workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_status.2675055326
Short name	T257
Test name
Test status
Simulation time	30505002 ps
CPU time	0.74 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	199828 kb
Host	smart-8e59cd15-4b2d-4ea3-aeb0-16912b42d0f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675055326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.2675055326
Directory	/workspace/23.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/23.clkmgr_div_intersig_mubi.3361306208
Short name	T818
Test name
Test status
Simulation time	45147475 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	200816 kb
Host	smart-a861b4a9-91f5-4124-8886-3069409a2b0a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361306208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.3361306208
Directory	/workspace/23.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_extclk.1739370547
Short name	T212
Test name
Test status
Simulation time	17433768 ps
CPU time	0.72 seconds
Started	Jul 18 06:42:43 PM PDT 24
Finished	Jul 18 06:42:50 PM PDT 24
Peak memory	201112 kb
Host	smart-0f49bbd9-f75b-4a13-8eba-027720ca1f95
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739370547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.1739370547
Directory	/workspace/23.clkmgr_extclk/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency.2306463110
Short name	T687
Test name
Test status
Simulation time	1557842792 ps
CPU time	7.1 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:55 PM PDT 24
Peak memory	201148 kb
Host	smart-f5c28c4b-a197-412d-b25a-bbfc2ecd88d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306463110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2306463110
Directory	/workspace/23.clkmgr_frequency/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency_timeout.3379567635
Short name	T528
Test name
Test status
Simulation time	1235302423 ps
CPU time	5.28 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201208 kb
Host	smart-b8923638-56b6-4162-9ce7-4f6616cb7adc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379567635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t imeout.3379567635
Directory	/workspace/23.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2331163296
Short name	T84
Test name
Test status
Simulation time	62222085 ps
CPU time	1.09 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	201072 kb
Host	smart-d3a86067-ffb8-4e84-ac2d-baf31f733c07
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331163296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.2331163296
Directory	/workspace/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3725870789
Short name	T456
Test name
Test status
Simulation time	18677150 ps
CPU time	0.83 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	201068 kb
Host	smart-41cf075c-be46-4411-ac95-ed1f8489a5f8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725870789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3725870789
Directory	/workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2109338690
Short name	T292
Test name
Test status
Simulation time	18533665 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:47 PM PDT 24
Peak memory	201032 kb
Host	smart-fa08b35a-a8ad-4126-b0dd-b741493eb952
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109338690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_ctrl_intersig_mubi.2109338690
Directory	/workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_peri.320284401
Short name	T474
Test name
Test status
Simulation time	42382724 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	201004 kb
Host	smart-874f6692-ab77-4148-9c0d-20fadae9ffd3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320284401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.320284401
Directory	/workspace/23.clkmgr_peri/latest

Test location	/workspace/coverage/default/23.clkmgr_regwen.3436996129
Short name	T397
Test name
Test status
Simulation time	349378049 ps
CPU time	2.42 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:48 PM PDT 24
Peak memory	201100 kb
Host	smart-188dfe7e-560c-4a19-8e5f-bda55d4aac0d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436996129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3436996129
Directory	/workspace/23.clkmgr_regwen/latest

Test location	/workspace/coverage/default/23.clkmgr_smoke.791714049
Short name	T688
Test name
Test status
Simulation time	20143293 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:42 PM PDT 24
Finished	Jul 18 06:42:50 PM PDT 24
Peak memory	201040 kb
Host	smart-2da8e593-0d53-4ec1-bef3-a8fc7a95e2f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791714049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.791714049
Directory	/workspace/23.clkmgr_smoke/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all.2665596582
Short name	T220
Test name
Test status
Simulation time	20061077 ps
CPU time	0.76 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:45 PM PDT 24
Peak memory	201072 kb
Host	smart-728c6479-a4b0-4068-9be4-67d8b1eba099
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665596582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.2665596582
Directory	/workspace/23.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.1546961838
Short name	T634
Test name
Test status
Simulation time	111503854637 ps
CPU time	708.83 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:54:28 PM PDT 24
Peak memory	213728 kb
Host	smart-f325c9cf-8b41-4193-be21-4bbf9e360865
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1546961838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.1546961838
Directory	/workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.clkmgr_trans.2118851940
Short name	T130
Test name
Test status
Simulation time	26122045 ps
CPU time	0.78 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	200768 kb
Host	smart-c2ba1824-ab0e-4f75-957a-24412cea1d3d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118851940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2118851940
Directory	/workspace/23.clkmgr_trans/latest

Test location	/workspace/coverage/default/24.clkmgr_alert_test.2174679340
Short name	T689
Test name
Test status
Simulation time	15560990 ps
CPU time	0.74 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:40 PM PDT 24
Peak memory	201204 kb
Host	smart-fff981e5-73de-496f-b129-3c0d31019782
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174679340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk mgr_alert_test.2174679340
Directory	/workspace/24.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1909405708
Short name	T740
Test name
Test status
Simulation time	20981389 ps
CPU time	0.89 seconds
Started	Jul 18 06:42:46 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	201236 kb
Host	smart-f5f903bb-de84-4d65-b82f-f3577e434d7c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909405708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.1909405708
Directory	/workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_status.541098186
Short name	T214
Test name
Test status
Simulation time	48747721 ps
CPU time	0.76 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:41 PM PDT 24
Peak memory	200284 kb
Host	smart-5d9a6aae-df86-4a0e-8dfd-b45084cd87d2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541098186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.541098186
Directory	/workspace/24.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/24.clkmgr_div_intersig_mubi.2228851113
Short name	T570
Test name
Test status
Simulation time	26787646 ps
CPU time	0.9 seconds
Started	Jul 18 06:42:34 PM PDT 24
Finished	Jul 18 06:42:36 PM PDT 24
Peak memory	201100 kb
Host	smart-217e3298-28e5-4968-af83-4c495b3892f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228851113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.2228851113
Directory	/workspace/24.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_extclk.1018953601
Short name	T467
Test name
Test status
Simulation time	17529089 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:46 PM PDT 24
Peak memory	201084 kb
Host	smart-fe61e78d-b350-4c29-960c-b86d55cf57f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018953601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1018953601
Directory	/workspace/24.clkmgr_extclk/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency.785090973
Short name	T770
Test name
Test status
Simulation time	1158235456 ps
CPU time	9.49 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:50 PM PDT 24
Peak memory	201140 kb
Host	smart-5cb5e4b6-243a-48f1-a0b1-ea6470a6d6e4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785090973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.785090973
Directory	/workspace/24.clkmgr_frequency/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency_timeout.2748496119
Short name	T191
Test name
Test status
Simulation time	1227262055 ps
CPU time	6.44 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:47 PM PDT 24
Peak memory	201184 kb
Host	smart-97da554e-3d6b-4bb2-a2a4-8cc66f04eaae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748496119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t imeout.2748496119
Directory	/workspace/24.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2444258788
Short name	T208
Test name
Test status
Simulation time	15880656 ps
CPU time	0.77 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:41 PM PDT 24
Peak memory	201096 kb
Host	smart-f34ce84f-631d-454d-a0b5-6f343f733150
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444258788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.2444258788
Directory	/workspace/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.4148984589
Short name	T74
Test name
Test status
Simulation time	29694314 ps
CPU time	0.91 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:41 PM PDT 24
Peak memory	201108 kb
Host	smart-950c3620-285f-4b5d-8b29-ea8db28a2ce2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148984589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_clk_byp_req_intersig_mubi.4148984589
Directory	/workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.1868584249
Short name	T502
Test name
Test status
Simulation time	46551051 ps
CPU time	1.01 seconds
Started	Jul 18 06:42:33 PM PDT 24
Finished	Jul 18 06:42:35 PM PDT 24
Peak memory	201088 kb
Host	smart-8aaee0e4-47cf-41ea-8547-87674d04bac7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868584249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_ctrl_intersig_mubi.1868584249
Directory	/workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_peri.3075771659
Short name	T353
Test name
Test status
Simulation time	19431598 ps
CPU time	0.76 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:40 PM PDT 24
Peak memory	201044 kb
Host	smart-169f3230-01cf-46d4-b4c5-853630de85e0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075771659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3075771659
Directory	/workspace/24.clkmgr_peri/latest

Test location	/workspace/coverage/default/24.clkmgr_regwen.4221445005
Short name	T5
Test name
Test status
Simulation time	849530890 ps
CPU time	3.88 seconds
Started	Jul 18 06:42:34 PM PDT 24
Finished	Jul 18 06:42:40 PM PDT 24
Peak memory	201272 kb
Host	smart-2261fe1a-cfd5-4dd6-b077-1689bf145182
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221445005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.4221445005
Directory	/workspace/24.clkmgr_regwen/latest

Test location	/workspace/coverage/default/24.clkmgr_smoke.3163780501
Short name	T516
Test name
Test status
Simulation time	43219053 ps
CPU time	0.91 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:46 PM PDT 24
Peak memory	201060 kb
Host	smart-b2bc8446-15f5-4ba4-85d6-39fbce08efe3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163780501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3163780501
Directory	/workspace/24.clkmgr_smoke/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all.1713953930
Short name	T609
Test name
Test status
Simulation time	3555248072 ps
CPU time	20.18 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:58 PM PDT 24
Peak memory	201580 kb
Host	smart-489f5129-d73e-4d45-8967-9054b523d53c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713953930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1713953930
Directory	/workspace/24.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.211283502
Short name	T14
Test name
Test status
Simulation time	93128917075 ps
CPU time	619.35 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:53:01 PM PDT 24
Peak memory	209772 kb
Host	smart-046bde66-5383-42a6-b16b-16e070dedd4e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=211283502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.211283502
Directory	/workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.clkmgr_trans.3352036364
Short name	T614
Test name
Test status
Simulation time	49119182 ps
CPU time	1.08 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:43 PM PDT 24
Peak memory	201044 kb
Host	smart-fb5523fa-0986-4e48-bce6-7cf0e472354e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352036364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.3352036364
Directory	/workspace/24.clkmgr_trans/latest

Test location	/workspace/coverage/default/25.clkmgr_alert_test.2314065450
Short name	T219
Test name
Test status
Simulation time	55281457 ps
CPU time	0.98 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:44 PM PDT 24
Peak memory	201224 kb
Host	smart-76b447de-c5ae-41e5-b755-5ee1b5248cb8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314065450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk mgr_alert_test.2314065450
Directory	/workspace/25.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.4208768006
Short name	T231
Test name
Test status
Simulation time	49378125 ps
CPU time	0.89 seconds
Started	Jul 18 06:42:43 PM PDT 24
Finished	Jul 18 06:42:51 PM PDT 24
Peak memory	201144 kb
Host	smart-5594d79d-43cd-4277-9f0d-fcc7de2cccbf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208768006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.4208768006
Directory	/workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_status.1099997030
Short name	T463
Test name
Test status
Simulation time	150568689 ps
CPU time	1.01 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:41 PM PDT 24
Peak memory	200248 kb
Host	smart-e2413a48-581c-479a-992c-7e95f0476061
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099997030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.1099997030
Directory	/workspace/25.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/25.clkmgr_div_intersig_mubi.2653812034
Short name	T515
Test name
Test status
Simulation time	48395807 ps
CPU time	0.83 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:45 PM PDT 24
Peak memory	201080 kb
Host	smart-2249a72f-4c07-45ac-9cdc-5c2db28162c0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653812034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.2653812034
Directory	/workspace/25.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_extclk.3418889948
Short name	T438
Test name
Test status
Simulation time	29269986 ps
CPU time	0.78 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:39 PM PDT 24
Peak memory	201072 kb
Host	smart-9ab85e33-b7e4-4c5a-8237-84e6dde45380
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418889948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3418889948
Directory	/workspace/25.clkmgr_extclk/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency.158482522
Short name	T23
Test name
Test status
Simulation time	801845444 ps
CPU time	6.61 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:44 PM PDT 24
Peak memory	201148 kb
Host	smart-b0fa3c14-c7ae-4443-a220-40255b94ac69
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158482522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.158482522
Directory	/workspace/25.clkmgr_frequency/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency_timeout.1607407555
Short name	T286
Test name
Test status
Simulation time	396223097 ps
CPU time	2.18 seconds
Started	Jul 18 06:42:40 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	201236 kb
Host	smart-0d884427-4a9a-4c86-90b7-1c6cbd7ab9e3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607407555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t imeout.1607407555
Directory	/workspace/25.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/25.clkmgr_idle_intersig_mubi.2773008065
Short name	T222
Test name
Test status
Simulation time	49641170 ps
CPU time	0.99 seconds
Started	Jul 18 06:42:33 PM PDT 24
Finished	Jul 18 06:42:34 PM PDT 24
Peak memory	201020 kb
Host	smart-61d2f0a8-fc99-44c1-9a2f-ad7441f63ad6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773008065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.2773008065
Directory	/workspace/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1495132270
Short name	T808
Test name
Test status
Simulation time	103656308 ps
CPU time	1.19 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:41 PM PDT 24
Peak memory	201088 kb
Host	smart-1731c78d-e688-4830-a09f-37bdb94d5d3f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495132270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1495132270
Directory	/workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2406654379
Short name	T333
Test name
Test status
Simulation time	13686143 ps
CPU time	0.72 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201060 kb
Host	smart-5185c431-525c-40ee-9671-4020290f0f37
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406654379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_ctrl_intersig_mubi.2406654379
Directory	/workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_peri.1932054424
Short name	T158
Test name
Test status
Simulation time	21426482 ps
CPU time	0.82 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:45 PM PDT 24
Peak memory	201040 kb
Host	smart-5521f335-f87a-487a-9f61-84ff1cba8151
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932054424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.1932054424
Directory	/workspace/25.clkmgr_peri/latest

Test location	/workspace/coverage/default/25.clkmgr_regwen.3314759740
Short name	T819
Test name
Test status
Simulation time	901234944 ps
CPU time	3.64 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:49 PM PDT 24
Peak memory	201252 kb
Host	smart-0d236c04-2e60-49d9-9922-f5de53a520e2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314759740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3314759740
Directory	/workspace/25.clkmgr_regwen/latest

Test location	/workspace/coverage/default/25.clkmgr_smoke.1599939778
Short name	T326
Test name
Test status
Simulation time	22291820 ps
CPU time	0.86 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:42:47 PM PDT 24
Peak memory	201028 kb
Host	smart-1d8b4b6d-0e0b-4d2d-a393-87cf8950df52
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599939778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.1599939778
Directory	/workspace/25.clkmgr_smoke/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all.2156772619
Short name	T37
Test name
Test status
Simulation time	12134794581 ps
CPU time	49.45 seconds
Started	Jul 18 06:42:39 PM PDT 24
Finished	Jul 18 06:43:35 PM PDT 24
Peak memory	201468 kb
Host	smart-268b2a84-7345-4118-87d0-2fb542c50b3f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156772619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.2156772619
Directory	/workspace/25.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.4259124381
Short name	T543
Test name
Test status
Simulation time	30625824735 ps
CPU time	450.32 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:50:13 PM PDT 24
Peak memory	209828 kb
Host	smart-792e3105-f5cf-4b1d-99ec-d4df91441bda
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4259124381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.4259124381
Directory	/workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.clkmgr_trans.173472699
Short name	T395
Test name
Test status
Simulation time	62944220 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:35 PM PDT 24
Finished	Jul 18 06:42:39 PM PDT 24
Peak memory	201084 kb
Host	smart-b1c6e5b8-7a26-4912-be58-3cd4df818079
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173472699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.173472699
Directory	/workspace/25.clkmgr_trans/latest

Test location	/workspace/coverage/default/26.clkmgr_alert_test.1326083523
Short name	T253
Test name
Test status
Simulation time	47377377 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:46 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	201212 kb
Host	smart-86aa1e38-1b33-4e1b-a06d-5492f5db1877
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326083523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.1326083523
Directory	/workspace/26.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.1244544355
Short name	T50
Test name
Test status
Simulation time	65332470 ps
CPU time	0.94 seconds
Started	Jul 18 06:42:44 PM PDT 24
Finished	Jul 18 06:42:51 PM PDT 24
Peak memory	201232 kb
Host	smart-27727f99-18a1-45c0-a604-a1d288fb6498
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244544355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.1244544355
Directory	/workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_status.104508698
Short name	T815
Test name
Test status
Simulation time	15475752 ps
CPU time	0.7 seconds
Started	Jul 18 06:42:49 PM PDT 24
Finished	Jul 18 06:42:55 PM PDT 24
Peak memory	200260 kb
Host	smart-26b29316-51c0-4e0f-9224-91ef7bfb45b6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104508698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.104508698
Directory	/workspace/26.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/26.clkmgr_div_intersig_mubi.3780454063
Short name	T246
Test name
Test status
Simulation time	91379598 ps
CPU time	1.04 seconds
Started	Jul 18 06:42:44 PM PDT 24
Finished	Jul 18 06:42:52 PM PDT 24
Peak memory	201088 kb
Host	smart-f484d2c3-09a7-4a82-b913-26c5d8375b41
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780454063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.3780454063
Directory	/workspace/26.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_extclk.1531561335
Short name	T746
Test name
Test status
Simulation time	25119110 ps
CPU time	0.79 seconds
Started	Jul 18 06:42:36 PM PDT 24
Finished	Jul 18 06:42:40 PM PDT 24
Peak memory	201108 kb
Host	smart-4f314039-0eeb-4001-8cca-1ce35a16e7b6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531561335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1531561335
Directory	/workspace/26.clkmgr_extclk/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency.4166772566
Short name	T88
Test name
Test status
Simulation time	1395283475 ps
CPU time	10.42 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:54 PM PDT 24
Peak memory	201168 kb
Host	smart-d486d829-e7ab-43bc-b237-20d88f12df74
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166772566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.4166772566
Directory	/workspace/26.clkmgr_frequency/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency_timeout.4010793651
Short name	T322
Test name
Test status
Simulation time	379736173 ps
CPU time	3.05 seconds
Started	Jul 18 06:42:41 PM PDT 24
Finished	Jul 18 06:42:50 PM PDT 24
Peak memory	201208 kb
Host	smart-e37f283b-3937-4aa2-8ee6-ad5dccc31a56
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010793651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t imeout.4010793651
Directory	/workspace/26.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/26.clkmgr_idle_intersig_mubi.3785112506
Short name	T557
Test name
Test status
Simulation time	78415327 ps
CPU time	1.2 seconds
Started	Jul 18 06:42:49 PM PDT 24
Finished	Jul 18 06:42:55 PM PDT 24
Peak memory	201008 kb
Host	smart-730ed0bd-4c20-4619-ad2e-9ac7eaeac2e5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785112506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.3785112506
Directory	/workspace/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.1368158794
Short name	T324
Test name
Test status
Simulation time	21694660 ps
CPU time	0.83 seconds
Started	Jul 18 06:42:48 PM PDT 24
Finished	Jul 18 06:42:54 PM PDT 24
Peak memory	201120 kb
Host	smart-d4fa82fa-0d05-4836-9ded-f731b20dd813
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368158794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_clk_byp_req_intersig_mubi.1368158794
Directory	/workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.958138571
Short name	T494
Test name
Test status
Simulation time	24238183 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:48 PM PDT 24
Finished	Jul 18 06:42:55 PM PDT 24
Peak memory	201100 kb
Host	smart-62d14308-50c3-4c83-a803-f38016250e89
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958138571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.clkmgr_lc_ctrl_intersig_mubi.958138571
Directory	/workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_peri.9233140
Short name	T102
Test name
Test status
Simulation time	39269606 ps
CPU time	0.79 seconds
Started	Jul 18 06:42:40 PM PDT 24
Finished	Jul 18 06:42:48 PM PDT 24
Peak memory	200992 kb
Host	smart-55eb0b19-8076-4a00-9c2b-44cfb256dc19
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9233140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.9233140
Directory	/workspace/26.clkmgr_peri/latest

Test location	/workspace/coverage/default/26.clkmgr_regwen.3756472774
Short name	T408
Test name
Test status
Simulation time	699005909 ps
CPU time	2.91 seconds
Started	Jul 18 06:42:54 PM PDT 24
Finished	Jul 18 06:43:01 PM PDT 24
Peak memory	201316 kb
Host	smart-6f9885c8-b2e7-4c24-8980-6055d78fd704
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756472774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3756472774
Directory	/workspace/26.clkmgr_regwen/latest

Test location	/workspace/coverage/default/26.clkmgr_smoke.2010559402
Short name	T152
Test name
Test status
Simulation time	84292091 ps
CPU time	1.06 seconds
Started	Jul 18 06:42:37 PM PDT 24
Finished	Jul 18 06:42:42 PM PDT 24
Peak memory	201040 kb
Host	smart-2fb98c96-e864-4d5c-a901-eec5dce00200
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010559402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2010559402
Directory	/workspace/26.clkmgr_smoke/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all.668200903
Short name	T390
Test name
Test status
Simulation time	3389828118 ps
CPU time	26.06 seconds
Started	Jul 18 06:42:48 PM PDT 24
Finished	Jul 18 06:43:19 PM PDT 24
Peak memory	201468 kb
Host	smart-5b8b63af-a9cc-4edd-a529-d58778503633
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668200903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.668200903
Directory	/workspace/26.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.3157551283
Short name	T418
Test name
Test status
Simulation time	111882586967 ps
CPU time	660.69 seconds
Started	Jul 18 06:42:49 PM PDT 24
Finished	Jul 18 06:53:55 PM PDT 24
Peak memory	209832 kb
Host	smart-b7e2953b-db32-4b26-a1d1-3f9af6298ba5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3157551283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.3157551283
Directory	/workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.clkmgr_trans.1154548760
Short name	T443
Test name
Test status
Simulation time	55117327 ps
CPU time	0.85 seconds
Started	Jul 18 06:42:38 PM PDT 24
Finished	Jul 18 06:42:44 PM PDT 24
Peak memory	201096 kb
Host	smart-e9953b5b-0f81-4a7c-ad5f-522522389e43
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154548760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1154548760
Directory	/workspace/26.clkmgr_trans/latest

Test location	/workspace/coverage/default/27.clkmgr_alert_test.4181207261
Short name	T251
Test name
Test status
Simulation time	16787031 ps
CPU time	0.76 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:42:56 PM PDT 24
Peak memory	201204 kb
Host	smart-b3f7223c-b2dc-407c-bdce-abfef07b08a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181207261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk mgr_alert_test.4181207261
Directory	/workspace/27.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1234102888
Short name	T451
Test name
Test status
Simulation time	61716942 ps
CPU time	0.9 seconds
Started	Jul 18 06:42:47 PM PDT 24
Finished	Jul 18 06:42:54 PM PDT 24
Peak memory	201144 kb
Host	smart-a2ae7cf3-134f-446e-9af7-fcbeb6b6949a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234102888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1234102888
Directory	/workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_status.3528112964
Short name	T182
Test name
Test status
Simulation time	34511967 ps
CPU time	0.76 seconds
Started	Jul 18 06:42:46 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	200980 kb
Host	smart-021c6fde-b65b-4bcf-b3df-254e6d45490a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528112964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.3528112964
Directory	/workspace/27.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/27.clkmgr_div_intersig_mubi.3314716779
Short name	T667
Test name
Test status
Simulation time	49238288 ps
CPU time	0.98 seconds
Started	Jul 18 06:42:54 PM PDT 24
Finished	Jul 18 06:42:59 PM PDT 24
Peak memory	201096 kb
Host	smart-f2bd195f-fac8-4da8-87c1-1609ef381bf0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314716779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.3314716779
Directory	/workspace/27.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_extclk.1616543722
Short name	T162
Test name
Test status
Simulation time	343787198 ps
CPU time	1.88 seconds
Started	Jul 18 06:42:47 PM PDT 24
Finished	Jul 18 06:42:55 PM PDT 24
Peak memory	201280 kb
Host	smart-d13dd440-a749-4669-a47f-9ff8c73347b1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616543722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.1616543722
Directory	/workspace/27.clkmgr_extclk/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency.209747882
Short name	T230
Test name
Test status
Simulation time	1639554822 ps
CPU time	12.41 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:43:07 PM PDT 24
Peak memory	201144 kb
Host	smart-6492331f-f0ad-4c18-b964-05834c485060
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209747882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.209747882
Directory	/workspace/27.clkmgr_frequency/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency_timeout.3843253937
Short name	T645
Test name
Test status
Simulation time	1238070931 ps
CPU time	5.43 seconds
Started	Jul 18 06:42:45 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	201164 kb
Host	smart-e8cd2b91-48d6-4b38-9b94-d30f9ba91f8a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843253937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t imeout.3843253937
Directory	/workspace/27.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/27.clkmgr_idle_intersig_mubi.2881689295
Short name	T363
Test name
Test status
Simulation time	17234807 ps
CPU time	0.74 seconds
Started	Jul 18 06:42:46 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	201080 kb
Host	smart-2afb2b9c-fba2-4a08-be4d-5984983ac833
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881689295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.2881689295
Directory	/workspace/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.266868614
Short name	T556
Test name
Test status
Simulation time	44364160 ps
CPU time	0.92 seconds
Started	Jul 18 06:42:47 PM PDT 24
Finished	Jul 18 06:42:54 PM PDT 24
Peak memory	201112 kb
Host	smart-a68a92cd-42b3-43ee-b3c3-64d2a3f47597
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266868614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.clkmgr_lc_clk_byp_req_intersig_mubi.266868614
Directory	/workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2415145472
Short name	T79
Test name
Test status
Simulation time	58612515 ps
CPU time	0.92 seconds
Started	Jul 18 06:42:51 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	201084 kb
Host	smart-237fa405-575d-4f0c-934c-080afd535845
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415145472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_ctrl_intersig_mubi.2415145472
Directory	/workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_peri.1749814405
Short name	T576
Test name
Test status
Simulation time	49008184 ps
CPU time	0.89 seconds
Started	Jul 18 06:42:51 PM PDT 24
Finished	Jul 18 06:42:56 PM PDT 24
Peak memory	201036 kb
Host	smart-facf46e8-f601-46cd-85fc-d2d5a9938bf2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749814405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1749814405
Directory	/workspace/27.clkmgr_peri/latest

Test location	/workspace/coverage/default/27.clkmgr_regwen.1136849679
Short name	T748
Test name
Test status
Simulation time	116283725 ps
CPU time	1.27 seconds
Started	Jul 18 06:42:44 PM PDT 24
Finished	Jul 18 06:42:52 PM PDT 24
Peak memory	201040 kb
Host	smart-132c7262-e9c9-4126-8905-fad6c93f1eb7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136849679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1136849679
Directory	/workspace/27.clkmgr_regwen/latest

Test location	/workspace/coverage/default/27.clkmgr_smoke.4011634333
Short name	T6
Test name
Test status
Simulation time	50499489 ps
CPU time	0.86 seconds
Started	Jul 18 06:42:46 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	201040 kb
Host	smart-ab1bad30-4ba9-49bb-b6d3-f23233ba2c79
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011634333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.4011634333
Directory	/workspace/27.clkmgr_smoke/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all.2279062923
Short name	T351
Test name
Test status
Simulation time	84137259 ps
CPU time	1.05 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:42:56 PM PDT 24
Peak memory	201112 kb
Host	smart-f6ba9e3f-57c6-4b05-90ab-e1842133d4d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279062923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.2279062923
Directory	/workspace/27.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.993755771
Short name	T75
Test name
Test status
Simulation time	27735805464 ps
CPU time	510.22 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:51:26 PM PDT 24
Peak memory	210536 kb
Host	smart-33735650-7f0e-4a88-8412-a10626b66361
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=993755771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.993755771
Directory	/workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.clkmgr_trans.2522642795
Short name	T228
Test name
Test status
Simulation time	152634837 ps
CPU time	1.35 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	201012 kb
Host	smart-9e906dc3-ae9e-4552-acc5-0b760ffd1945
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522642795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.2522642795
Directory	/workspace/27.clkmgr_trans/latest

Test location	/workspace/coverage/default/28.clkmgr_alert_test.2506142142
Short name	T389
Test name
Test status
Simulation time	49936157 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:51 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	201196 kb
Host	smart-fb466688-ca06-4e1e-b4c5-1151ef1e0f7b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506142142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk mgr_alert_test.2506142142
Directory	/workspace/28.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3273172098
Short name	T635
Test name
Test status
Simulation time	27570104 ps
CPU time	0.95 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:42:56 PM PDT 24
Peak memory	201084 kb
Host	smart-52112421-e337-4ef3-9967-618ce3a6920e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273172098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.3273172098
Directory	/workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_status.1458177984
Short name	T661
Test name
Test status
Simulation time	36982438 ps
CPU time	0.73 seconds
Started	Jul 18 06:42:51 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	200272 kb
Host	smart-eb57be84-2e61-48b8-ac51-f8104c483d22
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458177984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1458177984
Directory	/workspace/28.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/28.clkmgr_div_intersig_mubi.3264475269
Short name	T238
Test name
Test status
Simulation time	31808832 ps
CPU time	0.84 seconds
Started	Jul 18 06:42:52 PM PDT 24
Finished	Jul 18 06:42:58 PM PDT 24
Peak memory	201096 kb
Host	smart-67a95e86-906f-47cd-bef2-603a9c2723d1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264475269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.3264475269
Directory	/workspace/28.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_extclk.2913825106
Short name	T773
Test name
Test status
Simulation time	152029933 ps
CPU time	1.24 seconds
Started	Jul 18 06:42:51 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	201084 kb
Host	smart-5c176485-b5d4-4f99-8652-2a8f3e01b069
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913825106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.2913825106
Directory	/workspace/28.clkmgr_extclk/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency.4119556812
Short name	T484
Test name
Test status
Simulation time	3087199489 ps
CPU time	11.06 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:43:06 PM PDT 24
Peak memory	201372 kb
Host	smart-52b81876-cba3-40e7-a51d-cee886c6c533
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119556812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.4119556812
Directory	/workspace/28.clkmgr_frequency/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency_timeout.1481123449
Short name	T577
Test name
Test status
Simulation time	868457392 ps
CPU time	5.04 seconds
Started	Jul 18 06:42:49 PM PDT 24
Finished	Jul 18 06:42:59 PM PDT 24
Peak memory	201216 kb
Host	smart-16de2dae-e419-4f65-a15a-19cabe01273b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481123449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t imeout.1481123449
Directory	/workspace/28.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/28.clkmgr_idle_intersig_mubi.4278491386
Short name	T338
Test name
Test status
Simulation time	26710270 ps
CPU time	0.72 seconds
Started	Jul 18 06:42:52 PM PDT 24
Finished	Jul 18 06:42:58 PM PDT 24
Peak memory	201084 kb
Host	smart-031bcae3-95fd-4de5-8db6-0ff9361cac42
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278491386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.4278491386
Directory	/workspace/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.3984729948
Short name	T276
Test name
Test status
Simulation time	22435971 ps
CPU time	0.81 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:42:56 PM PDT 24
Peak memory	201084 kb
Host	smart-a785f2da-8a6d-4178-97f0-43f2bf84130d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984729948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_clk_byp_req_intersig_mubi.3984729948
Directory	/workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.658080115
Short name	T562
Test name
Test status
Simulation time	13978121 ps
CPU time	0.71 seconds
Started	Jul 18 06:42:51 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	200936 kb
Host	smart-c3385f53-3bef-4aa7-b34f-e49ed9bb4bda
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658080115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.clkmgr_lc_ctrl_intersig_mubi.658080115
Directory	/workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_peri.2200198782
Short name	T331
Test name
Test status
Simulation time	38933362 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:53 PM PDT 24
Finished	Jul 18 06:42:58 PM PDT 24
Peak memory	201028 kb
Host	smart-7d079d1f-f926-4224-83cf-f7dbdc9627a9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200198782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2200198782
Directory	/workspace/28.clkmgr_peri/latest

Test location	/workspace/coverage/default/28.clkmgr_regwen.4215859602
Short name	T538
Test name
Test status
Simulation time	1060959026 ps
CPU time	4.17 seconds
Started	Jul 18 06:42:51 PM PDT 24
Finished	Jul 18 06:43:00 PM PDT 24
Peak memory	201268 kb
Host	smart-c079202a-84f1-4dfd-9401-4f4be6105df1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215859602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.4215859602
Directory	/workspace/28.clkmgr_regwen/latest

Test location	/workspace/coverage/default/28.clkmgr_smoke.3187486848
Short name	T793
Test name
Test status
Simulation time	139076366 ps
CPU time	1.16 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	201016 kb
Host	smart-902e9a9a-b182-43fd-ba09-bfbab9ec3635
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187486848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3187486848
Directory	/workspace/28.clkmgr_smoke/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all.3535999768
Short name	T319
Test name
Test status
Simulation time	4308110837 ps
CPU time	31.93 seconds
Started	Jul 18 06:42:53 PM PDT 24
Finished	Jul 18 06:43:29 PM PDT 24
Peak memory	201476 kb
Host	smart-edc18102-599c-4446-96b7-592c80d4027f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535999768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.3535999768
Directory	/workspace/28.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.2936562601
Short name	T379
Test name
Test status
Simulation time	66176404241 ps
CPU time	467.85 seconds
Started	Jul 18 06:42:53 PM PDT 24
Finished	Jul 18 06:50:45 PM PDT 24
Peak memory	217884 kb
Host	smart-80feacab-6a57-4a6b-a742-3f2b06035b0e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2936562601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.2936562601
Directory	/workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.clkmgr_trans.2656975708
Short name	T258
Test name
Test status
Simulation time	24706410 ps
CPU time	0.76 seconds
Started	Jul 18 06:42:46 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	201104 kb
Host	smart-5f798cfb-f043-4587-ba4d-d6f2db4d0667
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656975708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2656975708
Directory	/workspace/28.clkmgr_trans/latest

Test location	/workspace/coverage/default/29.clkmgr_alert_test.3666830749
Short name	T804
Test name
Test status
Simulation time	17109285 ps
CPU time	0.77 seconds
Started	Jul 18 06:43:03 PM PDT 24
Finished	Jul 18 06:43:05 PM PDT 24
Peak memory	201236 kb
Host	smart-fab7d9f5-fbce-48d2-a546-fd7b751925d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666830749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk mgr_alert_test.3666830749
Directory	/workspace/29.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2093699049
Short name	T48
Test name
Test status
Simulation time	24431862 ps
CPU time	0.81 seconds
Started	Jul 18 06:43:05 PM PDT 24
Finished	Jul 18 06:43:06 PM PDT 24
Peak memory	201280 kb
Host	smart-044434b6-44ac-450a-8a92-6f2fd0612dfd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093699049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.2093699049
Directory	/workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_status.2684068596
Short name	T352
Test name
Test status
Simulation time	13043808 ps
CPU time	0.68 seconds
Started	Jul 18 06:42:52 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	200116 kb
Host	smart-f6061adc-5a37-429a-8973-8dc276f1d4d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684068596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2684068596
Directory	/workspace/29.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/29.clkmgr_div_intersig_mubi.3588986050
Short name	T550
Test name
Test status
Simulation time	19156754 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:01 PM PDT 24
Peak memory	201096 kb
Host	smart-eab8a657-fdd3-49c4-a501-0a8dd22850bd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588986050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.3588986050
Directory	/workspace/29.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_extclk.582393657
Short name	T432
Test name
Test status
Simulation time	30956298 ps
CPU time	0.82 seconds
Started	Jul 18 06:42:48 PM PDT 24
Finished	Jul 18 06:42:55 PM PDT 24
Peak memory	201084 kb
Host	smart-a83ad95c-42a5-4c6b-930c-18ba06554464
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582393657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.582393657
Directory	/workspace/29.clkmgr_extclk/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency.1499350667
Short name	T602
Test name
Test status
Simulation time	1888960059 ps
CPU time	10.73 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:43:06 PM PDT 24
Peak memory	201360 kb
Host	smart-00e7a82a-816f-4623-b67b-8b670bb739ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499350667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.1499350667
Directory	/workspace/29.clkmgr_frequency/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency_timeout.3204610602
Short name	T598
Test name
Test status
Simulation time	2361418073 ps
CPU time	7.48 seconds
Started	Jul 18 06:42:47 PM PDT 24
Finished	Jul 18 06:43:01 PM PDT 24
Peak memory	201504 kb
Host	smart-833b8878-cf23-4aa1-99c0-5156bbee0ac0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204610602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t imeout.3204610602
Directory	/workspace/29.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/29.clkmgr_idle_intersig_mubi.404597511
Short name	T496
Test name
Test status
Simulation time	43664004 ps
CPU time	0.89 seconds
Started	Jul 18 06:42:49 PM PDT 24
Finished	Jul 18 06:42:55 PM PDT 24
Peak memory	201092 kb
Host	smart-ba36bd88-02b2-4390-98e1-11edd99205d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404597511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.clkmgr_idle_intersig_mubi.404597511
Directory	/workspace/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1698572778
Short name	T471
Test name
Test status
Simulation time	21904854 ps
CPU time	0.83 seconds
Started	Jul 18 06:43:00 PM PDT 24
Finished	Jul 18 06:43:03 PM PDT 24
Peak memory	201100 kb
Host	smart-cde5fb27-1f7f-4784-b6ec-e9977657a2f6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698572778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1698572778
Directory	/workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_peri.2720588407
Short name	T567
Test name
Test status
Simulation time	23535484 ps
CPU time	0.8 seconds
Started	Jul 18 06:42:50 PM PDT 24
Finished	Jul 18 06:42:56 PM PDT 24
Peak memory	201088 kb
Host	smart-88c72f5a-df74-49ae-b40d-7cd65aa0f942
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720588407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2720588407
Directory	/workspace/29.clkmgr_peri/latest

Test location	/workspace/coverage/default/29.clkmgr_regwen.3557253390
Short name	T234
Test name
Test status
Simulation time	941463751 ps
CPU time	3.85 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:05 PM PDT 24
Peak memory	201268 kb
Host	smart-b68541fa-271e-425b-9e3c-887e47cb7e90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557253390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3557253390
Directory	/workspace/29.clkmgr_regwen/latest

Test location	/workspace/coverage/default/29.clkmgr_smoke.2452668887
Short name	T840
Test name
Test status
Simulation time	40425583 ps
CPU time	0.85 seconds
Started	Jul 18 06:42:52 PM PDT 24
Finished	Jul 18 06:42:57 PM PDT 24
Peak memory	201056 kb
Host	smart-bebf8127-1a0b-484f-a55f-d7080a692232
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452668887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.2452668887
Directory	/workspace/29.clkmgr_smoke/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all.87565348
Short name	T47
Test name
Test status
Simulation time	9724241199 ps
CPU time	51.17 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:52 PM PDT 24
Peak memory	201532 kb
Host	smart-3ac79c7e-c7f5-433d-9748-c1e1373eb021
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87565348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.clkmgr_stress_all.87565348
Directory	/workspace/29.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.1913896753
Short name	T368
Test name
Test status
Simulation time	31830585885 ps
CPU time	575.43 seconds
Started	Jul 18 06:42:58 PM PDT 24
Finished	Jul 18 06:52:35 PM PDT 24
Peak memory	217960 kb
Host	smart-12940a33-6b6d-4950-bdf9-b399f250c5b4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1913896753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.1913896753
Directory	/workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_trans.1218062378
Short name	T518
Test name
Test status
Simulation time	18887198 ps
CPU time	0.75 seconds
Started	Jul 18 06:42:46 PM PDT 24
Finished	Jul 18 06:42:53 PM PDT 24
Peak memory	201104 kb
Host	smart-44769755-e314-4723-a2ca-90fc9c662f18
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218062378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1218062378
Directory	/workspace/29.clkmgr_trans/latest

Test location	/workspace/coverage/default/3.clkmgr_alert_test.3591792113
Short name	T851
Test name
Test status
Simulation time	40737519 ps
CPU time	0.79 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:12 PM PDT 24
Peak memory	201312 kb
Host	smart-ac88d37c-a2e8-4004-a30c-bb1e2e3383a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591792113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm gr_alert_test.3591792113
Directory	/workspace/3.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3495395995
Short name	T805
Test name
Test status
Simulation time	74367295 ps
CPU time	1.07 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:17 PM PDT 24
Peak memory	201104 kb
Host	smart-e688c792-738f-473c-b089-6d5a61349550
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495395995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.3495395995
Directory	/workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_div_intersig_mubi.1385952864
Short name	T599
Test name
Test status
Simulation time	65966226 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:15 PM PDT 24
Peak memory	201108 kb
Host	smart-aece3ac1-07c7-4121-b50f-e1e21baac355
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385952864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.1385952864
Directory	/workspace/3.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_extclk.1382850433
Short name	T653
Test name
Test status
Simulation time	29371023 ps
CPU time	0.9 seconds
Started	Jul 18 06:40:30 PM PDT 24
Finished	Jul 18 06:40:35 PM PDT 24
Peak memory	201076 kb
Host	smart-bb72d0a2-44ce-4b9f-932e-4d54f7ffcdb3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382850433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1382850433
Directory	/workspace/3.clkmgr_extclk/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency.4034842632
Short name	T361
Test name
Test status
Simulation time	1083464970 ps
CPU time	5.55 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:20 PM PDT 24
Peak memory	201148 kb
Host	smart-304355a3-32ff-4d3f-b28e-21157a89b763
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034842632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.4034842632
Directory	/workspace/3.clkmgr_frequency/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency_timeout.575367593
Short name	T87
Test name
Test status
Simulation time	2318817715 ps
CPU time	8.79 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:23 PM PDT 24
Peak memory	201428 kb
Host	smart-3ba2cd91-206b-4ad4-a591-28630f9bb8f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575367593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_tim eout.575367593
Directory	/workspace/3.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3347952031
Short name	T765
Test name
Test status
Simulation time	64275616 ps
CPU time	0.94 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:17 PM PDT 24
Peak memory	201184 kb
Host	smart-ac81da60-2b68-447b-b9bf-3cb9416d7f9b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347952031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.3347952031
Directory	/workspace/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1950408262
Short name	T305
Test name
Test status
Simulation time	16763899 ps
CPU time	0.78 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:18 PM PDT 24
Peak memory	201104 kb
Host	smart-2b0fc76e-f268-4199-b590-99a04771faa8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950408262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_clk_byp_req_intersig_mubi.1950408262
Directory	/workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3982887219
Short name	T628
Test name
Test status
Simulation time	24715800 ps
CPU time	0.86 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:17 PM PDT 24
Peak memory	201180 kb
Host	smart-1c4a7122-4b3a-42af-a71e-635ec666f690
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982887219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_ctrl_intersig_mubi.3982887219
Directory	/workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_peri.2113430577
Short name	T7
Test name
Test status
Simulation time	43596732 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:18 PM PDT 24
Peak memory	201060 kb
Host	smart-e858ebc1-67a6-47f2-84c0-01ba3d0a3a08
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113430577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2113430577
Directory	/workspace/3.clkmgr_peri/latest

Test location	/workspace/coverage/default/3.clkmgr_regwen.3846648904
Short name	T731
Test name
Test status
Simulation time	1046451338 ps
CPU time	3.78 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:18 PM PDT 24
Peak memory	201268 kb
Host	smart-cbd6386d-08b1-4171-b44b-28ff02ada06d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846648904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3846648904
Directory	/workspace/3.clkmgr_regwen/latest

Test location	/workspace/coverage/default/3.clkmgr_sec_cm.667820143
Short name	T56
Test name
Test status
Simulation time	582738180 ps
CPU time	2.94 seconds
Started	Jul 18 06:45:27 PM PDT 24
Finished	Jul 18 06:45:35 PM PDT 24
Peak memory	220436 kb
Host	smart-d79691e3-125f-4aa4-bd29-12c2ffcbfcb3
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667820143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr _sec_cm.667820143
Directory	/workspace/3.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.clkmgr_smoke.619852102
Short name	T697
Test name
Test status
Simulation time	47394738 ps
CPU time	0.88 seconds
Started	Jul 18 06:40:31 PM PDT 24
Finished	Jul 18 06:40:36 PM PDT 24
Peak memory	201028 kb
Host	smart-020ea727-f502-4f23-b5b1-43182ce9b8b4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619852102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.619852102
Directory	/workspace/3.clkmgr_smoke/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all.2800299802
Short name	T572
Test name
Test status
Simulation time	1293058623 ps
CPU time	5.67 seconds
Started	Jul 18 06:41:08 PM PDT 24
Finished	Jul 18 06:41:14 PM PDT 24
Peak memory	201148 kb
Host	smart-0fb1e39e-f1f3-4a60-b728-a1f2b0d83979
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800299802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.2800299802
Directory	/workspace/3.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.1934262728
Short name	T636
Test name
Test status
Simulation time	52180504461 ps
CPU time	947.35 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:56:57 PM PDT 24
Peak memory	209772 kb
Host	smart-d0cb8915-4737-46f0-9fe4-6b4b8a9fb659
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1934262728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.1934262728
Directory	/workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.clkmgr_trans.1728698880
Short name	T548
Test name
Test status
Simulation time	83607446 ps
CPU time	1.08 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:14 PM PDT 24
Peak memory	201268 kb
Host	smart-817064ad-38b8-42f2-97ce-277b4ca3ea9d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728698880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1728698880
Directory	/workspace/3.clkmgr_trans/latest

Test location	/workspace/coverage/default/30.clkmgr_alert_test.1877154942
Short name	T270
Test name
Test status
Simulation time	23957484 ps
CPU time	0.79 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	201392 kb
Host	smart-eec20be2-a258-4873-92a4-54d8ef58374e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877154942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk mgr_alert_test.1877154942
Directory	/workspace/30.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.555691736
Short name	T110
Test name
Test status
Simulation time	14987185 ps
CPU time	0.77 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:02 PM PDT 24
Peak memory	201056 kb
Host	smart-8f595bfd-0b04-4a46-a675-7ba7d623149c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555691736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.555691736
Directory	/workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_status.3158453444
Short name	T764
Test name
Test status
Simulation time	12706887 ps
CPU time	0.68 seconds
Started	Jul 18 06:43:00 PM PDT 24
Finished	Jul 18 06:43:03 PM PDT 24
Peak memory	200952 kb
Host	smart-e9fd1fa0-e263-4a35-8775-fc1a05e107c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158453444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.3158453444
Directory	/workspace/30.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/30.clkmgr_div_intersig_mubi.4261314844
Short name	T344
Test name
Test status
Simulation time	13042373 ps
CPU time	0.69 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:02 PM PDT 24
Peak memory	200996 kb
Host	smart-580a8756-e51a-4eb2-905d-bc06fc048a57
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261314844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.4261314844
Directory	/workspace/30.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_extclk.4283152372
Short name	T226
Test name
Test status
Simulation time	28668763 ps
CPU time	0.92 seconds
Started	Jul 18 06:42:58 PM PDT 24
Finished	Jul 18 06:43:00 PM PDT 24
Peak memory	201088 kb
Host	smart-67681660-ad00-4ae8-be98-6977c608201a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283152372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.4283152372
Directory	/workspace/30.clkmgr_extclk/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency.3628529820
Short name	T566
Test name
Test status
Simulation time	933196779 ps
CPU time	4.79 seconds
Started	Jul 18 06:43:05 PM PDT 24
Finished	Jul 18 06:43:10 PM PDT 24
Peak memory	201144 kb
Host	smart-64e36959-548d-460c-8716-60b560f28e04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628529820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3628529820
Directory	/workspace/30.clkmgr_frequency/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency_timeout.2077311355
Short name	T693
Test name
Test status
Simulation time	511513023 ps
CPU time	2.76 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:04 PM PDT 24
Peak memory	201192 kb
Host	smart-97655ca0-9419-4e10-af3d-1b380236c3b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077311355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t imeout.2077311355
Directory	/workspace/30.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/30.clkmgr_idle_intersig_mubi.4184899683
Short name	T198
Test name
Test status
Simulation time	18806612 ps
CPU time	0.79 seconds
Started	Jul 18 06:43:02 PM PDT 24
Finished	Jul 18 06:43:04 PM PDT 24
Peak memory	201088 kb
Host	smart-66bff164-8eed-4042-a8fa-e98abeb76190
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184899683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.4184899683
Directory	/workspace/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.4288548995
Short name	T282
Test name
Test status
Simulation time	23703118 ps
CPU time	0.77 seconds
Started	Jul 18 06:42:58 PM PDT 24
Finished	Jul 18 06:43:00 PM PDT 24
Peak memory	201104 kb
Host	smart-c6e06e06-68e1-4882-be57-bdc452e02ee5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288548995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_clk_byp_req_intersig_mubi.4288548995
Directory	/workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1860331650
Short name	T500
Test name
Test status
Simulation time	30375819 ps
CPU time	0.88 seconds
Started	Jul 18 06:43:00 PM PDT 24
Finished	Jul 18 06:43:03 PM PDT 24
Peak memory	201124 kb
Host	smart-2f8cb7c8-c64c-4f3c-ae2c-ca4309537673
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860331650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_ctrl_intersig_mubi.1860331650
Directory	/workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_peri.2215025215
Short name	T419
Test name
Test status
Simulation time	15569503 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:04 PM PDT 24
Finished	Jul 18 06:43:06 PM PDT 24
Peak memory	201212 kb
Host	smart-280dc1d6-75c8-4be7-bb0f-f86b9cb17ace
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215025215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2215025215
Directory	/workspace/30.clkmgr_peri/latest

Test location	/workspace/coverage/default/30.clkmgr_regwen.4185899430
Short name	T52
Test name
Test status
Simulation time	472079102 ps
CPU time	2 seconds
Started	Jul 18 06:43:01 PM PDT 24
Finished	Jul 18 06:43:05 PM PDT 24
Peak memory	201116 kb
Host	smart-59ecf92f-b35f-4d81-93f4-cb098f1910c8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185899430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.4185899430
Directory	/workspace/30.clkmgr_regwen/latest

Test location	/workspace/coverage/default/30.clkmgr_smoke.3396020434
Short name	T39
Test name
Test status
Simulation time	75450729 ps
CPU time	1.03 seconds
Started	Jul 18 06:43:01 PM PDT 24
Finished	Jul 18 06:43:04 PM PDT 24
Peak memory	201040 kb
Host	smart-5760d8b9-7559-4bfb-9d7b-89cc771b3731
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396020434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3396020434
Directory	/workspace/30.clkmgr_smoke/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all.1476302108
Short name	T13
Test name
Test status
Simulation time	13811753998 ps
CPU time	48.38 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201512 kb
Host	smart-e6430781-3122-4869-9b41-b996ffc39b66
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476302108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.1476302108
Directory	/workspace/30.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.1129199022
Short name	T173
Test name
Test status
Simulation time	94604511956 ps
CPU time	563.73 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:52:25 PM PDT 24
Peak memory	212480 kb
Host	smart-971c1724-ab0c-407f-8583-ead742088891
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1129199022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.1129199022
Directory	/workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.clkmgr_trans.1278762404
Short name	T561
Test name
Test status
Simulation time	28887888 ps
CPU time	0.94 seconds
Started	Jul 18 06:42:59 PM PDT 24
Finished	Jul 18 06:43:02 PM PDT 24
Peak memory	201080 kb
Host	smart-84ea80a6-6c70-4775-84c6-84167ed3951f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278762404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1278762404
Directory	/workspace/30.clkmgr_trans/latest

Test location	/workspace/coverage/default/31.clkmgr_alert_test.4156990521
Short name	T621
Test name
Test status
Simulation time	25784504 ps
CPU time	0.79 seconds
Started	Jul 18 06:43:20 PM PDT 24
Finished	Jul 18 06:43:22 PM PDT 24
Peak memory	201184 kb
Host	smart-b5f9338c-6b2e-4c6f-92c4-a3277ede383a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156990521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk mgr_alert_test.4156990521
Directory	/workspace/31.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2864576343
Short name	T106
Test name
Test status
Simulation time	74586075 ps
CPU time	1.07 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:24 PM PDT 24
Peak memory	201104 kb
Host	smart-b2fb24c0-d517-41fd-a16b-98fa684f9c1a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864576343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.2864576343
Directory	/workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_status.3340988895
Short name	T218
Test name
Test status
Simulation time	51680822 ps
CPU time	0.8 seconds
Started	Jul 18 06:43:19 PM PDT 24
Finished	Jul 18 06:43:21 PM PDT 24
Peak memory	200268 kb
Host	smart-882073b2-3dc5-4244-bae7-8e50b4c399d0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340988895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3340988895
Directory	/workspace/31.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/31.clkmgr_div_intersig_mubi.2548658438
Short name	T824
Test name
Test status
Simulation time	27440796 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:24 PM PDT 24
Peak memory	201004 kb
Host	smart-fd3d2956-89d3-4282-93dd-ace08f010669
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548658438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.2548658438
Directory	/workspace/31.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_extclk.3755728256
Short name	T422
Test name
Test status
Simulation time	36115021 ps
CPU time	0.83 seconds
Started	Jul 18 06:43:19 PM PDT 24
Finished	Jul 18 06:43:21 PM PDT 24
Peak memory	201080 kb
Host	smart-e2fe8fe5-797b-4167-a9e3-9c516d46863a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755728256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3755728256
Directory	/workspace/31.clkmgr_extclk/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency.3724763758
Short name	T457
Test name
Test status
Simulation time	809588291 ps
CPU time	4.95 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:28 PM PDT 24
Peak memory	201164 kb
Host	smart-c5d54562-7833-47c1-a4a1-cd82b1b18eb7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724763758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3724763758
Directory	/workspace/31.clkmgr_frequency/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency_timeout.3322278367
Short name	T631
Test name
Test status
Simulation time	1337179074 ps
CPU time	10.05 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:40 PM PDT 24
Peak memory	201172 kb
Host	smart-bf4be5ec-50f8-4755-9c7d-e2320b51fde0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322278367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t imeout.3322278367
Directory	/workspace/31.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1681743363
Short name	T481
Test name
Test status
Simulation time	101139361 ps
CPU time	1.18 seconds
Started	Jul 18 06:43:23 PM PDT 24
Finished	Jul 18 06:43:30 PM PDT 24
Peak memory	201088 kb
Host	smart-3bd67a95-34f1-4b87-ae06-f029d165ffea
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681743363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.1681743363
Directory	/workspace/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.545204655
Short name	T495
Test name
Test status
Simulation time	40337909 ps
CPU time	0.91 seconds
Started	Jul 18 06:43:19 PM PDT 24
Finished	Jul 18 06:43:21 PM PDT 24
Peak memory	201116 kb
Host	smart-fb80d528-7591-4142-904e-cf31b02ea517
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545204655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.clkmgr_lc_clk_byp_req_intersig_mubi.545204655
Directory	/workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.3026825677
Short name	T774
Test name
Test status
Simulation time	62941776 ps
CPU time	0.86 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:25 PM PDT 24
Peak memory	201120 kb
Host	smart-1f77d6cd-83e0-4354-a2db-d01074ef4dbf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026825677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_ctrl_intersig_mubi.3026825677
Directory	/workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_peri.724233075
Short name	T843
Test name
Test status
Simulation time	50755188 ps
CPU time	0.82 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	200968 kb
Host	smart-621d82fe-76fc-42f4-bb15-4197a194c5d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724233075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.724233075
Directory	/workspace/31.clkmgr_peri/latest

Test location	/workspace/coverage/default/31.clkmgr_regwen.728125966
Short name	T335
Test name
Test status
Simulation time	1067923725 ps
CPU time	4.96 seconds
Started	Jul 18 06:43:23 PM PDT 24
Finished	Jul 18 06:43:33 PM PDT 24
Peak memory	201268 kb
Host	smart-a5e9a7d0-eeff-4cb5-9bf5-e85f0e7e7c4d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728125966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.728125966
Directory	/workspace/31.clkmgr_regwen/latest

Test location	/workspace/coverage/default/31.clkmgr_smoke.3932594041
Short name	T508
Test name
Test status
Simulation time	38589554 ps
CPU time	0.84 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:28 PM PDT 24
Peak memory	201056 kb
Host	smart-ea6cbdab-c756-476d-85bd-cf4b899820a5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932594041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3932594041
Directory	/workspace/31.clkmgr_smoke/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all.2163910187
Short name	T574
Test name
Test status
Simulation time	5112191994 ps
CPU time	39.78 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:44:06 PM PDT 24
Peak memory	201476 kb
Host	smart-49e82d44-37e4-4483-bb16-f70f2fba396e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163910187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.2163910187
Directory	/workspace/31.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2451420694
Short name	T30
Test name
Test status
Simulation time	34983922261 ps
CPU time	654.99 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:54:20 PM PDT 24
Peak memory	209804 kb
Host	smart-7d34d65d-241f-4720-8808-63b8a95a6c75
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2451420694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.2451420694
Directory	/workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.clkmgr_trans.3832473152
Short name	T200
Test name
Test status
Simulation time	32570589 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:25 PM PDT 24
Peak memory	201096 kb
Host	smart-f3970dc3-62b5-4fda-9b7b-0f09198cbe68
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832473152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3832473152
Directory	/workspace/31.clkmgr_trans/latest

Test location	/workspace/coverage/default/32.clkmgr_alert_test.3236658745
Short name	T644
Test name
Test status
Simulation time	61797461 ps
CPU time	0.88 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:26 PM PDT 24
Peak memory	201224 kb
Host	smart-4b014526-6538-4f98-9632-d91025378944
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236658745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk mgr_alert_test.3236658745
Directory	/workspace/32.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.1712906402
Short name	T560
Test name
Test status
Simulation time	11578073 ps
CPU time	0.73 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:27 PM PDT 24
Peak memory	201100 kb
Host	smart-6856c630-a9b6-498a-81c4-5114a376d2c2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712906402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.1712906402
Directory	/workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_status.3726586427
Short name	T738
Test name
Test status
Simulation time	45155484 ps
CPU time	0.81 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:26 PM PDT 24
Peak memory	200280 kb
Host	smart-1890c84a-f57f-475e-a3a0-e3889df7d9bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726586427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3726586427
Directory	/workspace/32.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/32.clkmgr_div_intersig_mubi.4150581823
Short name	T724
Test name
Test status
Simulation time	50450609 ps
CPU time	0.82 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:30 PM PDT 24
Peak memory	201056 kb
Host	smart-ccc943d4-a03b-40a3-8347-ae58e081ed2a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150581823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.4150581823
Directory	/workspace/32.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_extclk.2747143723
Short name	T356
Test name
Test status
Simulation time	90862738 ps
CPU time	1.11 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201092 kb
Host	smart-5917af55-6369-401b-94a4-c4f23a2e064e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747143723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2747143723
Directory	/workspace/32.clkmgr_extclk/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency.1583720498
Short name	T227
Test name
Test status
Simulation time	1764091923 ps
CPU time	10.2 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:37 PM PDT 24
Peak memory	201336 kb
Host	smart-d666aa47-9971-4a77-b7cf-b47f8053c109
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583720498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1583720498
Directory	/workspace/32.clkmgr_frequency/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency_timeout.259271352
Short name	T691
Test name
Test status
Simulation time	520296708 ps
CPU time	2.58 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:29 PM PDT 24
Peak memory	201160 kb
Host	smart-6125960b-379e-4fd8-9ea0-e329b8a1b533
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259271352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti meout.259271352
Directory	/workspace/32.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/32.clkmgr_idle_intersig_mubi.2548462117
Short name	T205
Test name
Test status
Simulation time	22227462 ps
CPU time	0.75 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201072 kb
Host	smart-5246f66a-fdad-4bb9-a677-cec109d5dbfe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548462117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.2548462117
Directory	/workspace/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3625248784
Short name	T280
Test name
Test status
Simulation time	56395555 ps
CPU time	0.88 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	201076 kb
Host	smart-92233f4d-d17c-4b17-a2f8-5ecfaaaaf8f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625248784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3625248784
Directory	/workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.840075521
Short name	T732
Test name
Test status
Simulation time	45596621 ps
CPU time	0.97 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201120 kb
Host	smart-09f33f68-cccd-4418-b668-b80b6531cc57
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840075521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.clkmgr_lc_ctrl_intersig_mubi.840075521
Directory	/workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_peri.2778102105
Short name	T763
Test name
Test status
Simulation time	18742676 ps
CPU time	0.8 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	200988 kb
Host	smart-d64c392d-5f78-47bd-9092-696e8a3f37d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778102105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.2778102105
Directory	/workspace/32.clkmgr_peri/latest

Test location	/workspace/coverage/default/32.clkmgr_regwen.3977066759
Short name	T197
Test name
Test status
Simulation time	138262940 ps
CPU time	1.35 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:28 PM PDT 24
Peak memory	201044 kb
Host	smart-ba93dd48-3fec-47a1-8f36-c52bf9e353e6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977066759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3977066759
Directory	/workspace/32.clkmgr_regwen/latest

Test location	/workspace/coverage/default/32.clkmgr_smoke.3680319317
Short name	T671
Test name
Test status
Simulation time	24027470 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:24 PM PDT 24
Peak memory	201052 kb
Host	smart-5bdc3b42-fb8c-4fa6-8c25-28a04a91348a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680319317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3680319317
Directory	/workspace/32.clkmgr_smoke/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all.1637784527
Short name	T785
Test name
Test status
Simulation time	6967163662 ps
CPU time	51.76 seconds
Started	Jul 18 06:43:20 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201492 kb
Host	smart-1ac6d286-7382-4a48-adbe-af8fbbe45e32
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637784527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.1637784527
Directory	/workspace/32.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.4227460428
Short name	T778
Test name
Test status
Simulation time	31286313619 ps
CPU time	336.65 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:49:01 PM PDT 24
Peak memory	209860 kb
Host	smart-2346b7c0-e518-4149-a8a0-983c77fceede
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4227460428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.4227460428
Directory	/workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.clkmgr_trans.1725136650
Short name	T439
Test name
Test status
Simulation time	404700501 ps
CPU time	2.13 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201000 kb
Host	smart-48b7a097-f259-4e52-a127-43e09a028089
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725136650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1725136650
Directory	/workspace/32.clkmgr_trans/latest

Test location	/workspace/coverage/default/33.clkmgr_alert_test.1762822276
Short name	T625
Test name
Test status
Simulation time	14544861 ps
CPU time	0.8 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	201396 kb
Host	smart-4caa3d98-de16-4c75-9364-87a5b7e6cd27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762822276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk mgr_alert_test.1762822276
Directory	/workspace/33.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2236251966
Short name	T676
Test name
Test status
Simulation time	48973746 ps
CPU time	0.87 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201120 kb
Host	smart-b8e45fe1-33e9-480c-916c-4c16740e9bd3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236251966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.2236251966
Directory	/workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_status.4131201471
Short name	T831
Test name
Test status
Simulation time	14924678 ps
CPU time	0.71 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	200212 kb
Host	smart-c4bb3044-f016-4bd1-81e6-6a5564117203
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131201471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.4131201471
Directory	/workspace/33.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/33.clkmgr_div_intersig_mubi.780100341
Short name	T531
Test name
Test status
Simulation time	28178441 ps
CPU time	0.83 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:25 PM PDT 24
Peak memory	201104 kb
Host	smart-aeccecac-3233-41a6-be7f-fdaedc8f835f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780100341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.clkmgr_div_intersig_mubi.780100341
Directory	/workspace/33.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_extclk.2671980259
Short name	T662
Test name
Test status
Simulation time	17918074 ps
CPU time	0.78 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:27 PM PDT 24
Peak memory	201088 kb
Host	smart-29d99759-742e-4184-816a-dcd6465b9d8a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671980259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2671980259
Directory	/workspace/33.clkmgr_extclk/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency.3591103355
Short name	T392
Test name
Test status
Simulation time	442720176 ps
CPU time	3.79 seconds
Started	Jul 18 06:43:19 PM PDT 24
Finished	Jul 18 06:43:24 PM PDT 24
Peak memory	201148 kb
Host	smart-c942df59-0865-43a9-8903-aa827bc93870
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591103355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3591103355
Directory	/workspace/33.clkmgr_frequency/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency_timeout.489571149
Short name	T721
Test name
Test status
Simulation time	420420311 ps
CPU time	2.26 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:30 PM PDT 24
Peak memory	201400 kb
Host	smart-e1ccc226-66e4-44f8-b33f-f3aad3e627bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489571149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti meout.489571149
Directory	/workspace/33.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/33.clkmgr_idle_intersig_mubi.3283792890
Short name	T336
Test name
Test status
Simulation time	80115390 ps
CPU time	1.08 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:26 PM PDT 24
Peak memory	201096 kb
Host	smart-b65a7ec4-88d2-44f6-88d7-295fdc6895dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283792890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.3283792890
Directory	/workspace/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2926103715
Short name	T594
Test name
Test status
Simulation time	23995536 ps
CPU time	0.84 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:27 PM PDT 24
Peak memory	201112 kb
Host	smart-4acf89fb-5db1-4067-ad89-6f8c6282e312
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926103715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.2926103715
Directory	/workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3484627256
Short name	T660
Test name
Test status
Simulation time	124993045 ps
CPU time	1.15 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:28 PM PDT 24
Peak memory	201080 kb
Host	smart-2d4703e0-3d6f-409d-9066-249f791f5ec6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484627256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_ctrl_intersig_mubi.3484627256
Directory	/workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_peri.1712667585
Short name	T203
Test name
Test status
Simulation time	34588991 ps
CPU time	0.86 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:24 PM PDT 24
Peak memory	201024 kb
Host	smart-6d2696ae-2c9a-4ace-b925-d4d291c06b93
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712667585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1712667585
Directory	/workspace/33.clkmgr_peri/latest

Test location	/workspace/coverage/default/33.clkmgr_regwen.3003359674
Short name	T487
Test name
Test status
Simulation time	858208156 ps
CPU time	3.52 seconds
Started	Jul 18 06:49:45 PM PDT 24
Finished	Jul 18 06:49:52 PM PDT 24
Peak memory	201308 kb
Host	smart-c875a8e2-567a-4919-a748-dbce38c0d0b0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003359674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.3003359674
Directory	/workspace/33.clkmgr_regwen/latest

Test location	/workspace/coverage/default/33.clkmgr_smoke.4128185295
Short name	T760
Test name
Test status
Simulation time	114845559 ps
CPU time	1.18 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:26 PM PDT 24
Peak memory	201028 kb
Host	smart-0fad96f5-e582-45e0-9d27-61cc58d5fe09
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128185295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4128185295
Directory	/workspace/33.clkmgr_smoke/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all.87802623
Short name	T809
Test name
Test status
Simulation time	1981912016 ps
CPU time	15.13 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:44 PM PDT 24
Peak memory	201360 kb
Host	smart-1d150ea9-7893-4bb5-93db-eaf9da261a28
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87802623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.clkmgr_stress_all.87802623
Directory	/workspace/33.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.4145077487
Short name	T167
Test name
Test status
Simulation time	143747909916 ps
CPU time	765.89 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:56:10 PM PDT 24
Peak memory	217196 kb
Host	smart-38eeb5e1-a951-4a9a-bfa9-300b62287ece
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4145077487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.4145077487
Directory	/workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.clkmgr_trans.4107461980
Short name	T426
Test name
Test status
Simulation time	16500411 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:20 PM PDT 24
Finished	Jul 18 06:43:23 PM PDT 24
Peak memory	201084 kb
Host	smart-fa0b4270-cc0d-4642-8905-4af5771fc8d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107461980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.4107461980
Directory	/workspace/33.clkmgr_trans/latest

Test location	/workspace/coverage/default/34.clkmgr_alert_test.2044725560
Short name	T175
Test name
Test status
Simulation time	40328352 ps
CPU time	0.81 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:28 PM PDT 24
Peak memory	201220 kb
Host	smart-5fd82510-402e-4ce5-af24-5bd3cab412de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044725560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk mgr_alert_test.2044725560
Directory	/workspace/34.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.2192565210
Short name	T311
Test name
Test status
Simulation time	15635406 ps
CPU time	0.73 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:30 PM PDT 24
Peak memory	201124 kb
Host	smart-42e960b6-0786-46ac-9342-24b60f107bab
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192565210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.2192565210
Directory	/workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_status.293522590
Short name	T248
Test name
Test status
Simulation time	42509082 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	200940 kb
Host	smart-352b2be2-c28e-490b-bede-3d41701a555d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293522590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.293522590
Directory	/workspace/34.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/34.clkmgr_div_intersig_mubi.2610695422
Short name	T329
Test name
Test status
Simulation time	18082320 ps
CPU time	0.82 seconds
Started	Jul 18 06:43:27 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201056 kb
Host	smart-6474942e-c073-457f-8c14-d051118be26a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610695422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.2610695422
Directory	/workspace/34.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_extclk.4191443781
Short name	T510
Test name
Test status
Simulation time	48464533 ps
CPU time	0.91 seconds
Started	Jul 18 06:43:21 PM PDT 24
Finished	Jul 18 06:43:24 PM PDT 24
Peak memory	201092 kb
Host	smart-bb826701-1d3c-4a42-a09e-742662f0451d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191443781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.4191443781
Directory	/workspace/34.clkmgr_extclk/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency.3896894181
Short name	T833
Test name
Test status
Simulation time	1156152872 ps
CPU time	9.8 seconds
Started	Jul 18 06:43:23 PM PDT 24
Finished	Jul 18 06:43:38 PM PDT 24
Peak memory	201344 kb
Host	smart-28df400e-8f18-476e-b0d9-dee3464568df
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896894181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3896894181
Directory	/workspace/34.clkmgr_frequency/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency_timeout.244864098
Short name	T264
Test name
Test status
Simulation time	636857755 ps
CPU time	2.92 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201352 kb
Host	smart-d503c191-e800-4d11-ba07-df520b1a1b9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244864098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti meout.244864098
Directory	/workspace/34.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/34.clkmgr_idle_intersig_mubi.1592355797
Short name	T85
Test name
Test status
Simulation time	22573140 ps
CPU time	0.87 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:27 PM PDT 24
Peak memory	201024 kb
Host	smart-313f7942-4c61-4e76-9fff-1e4b5b038f05
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592355797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.1592355797
Directory	/workspace/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2354444496
Short name	T188
Test name
Test status
Simulation time	24634180 ps
CPU time	0.77 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:43:28 PM PDT 24
Peak memory	201100 kb
Host	smart-faa602e7-7356-4f71-b52f-1ca1c18afddf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354444496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_clk_byp_req_intersig_mubi.2354444496
Directory	/workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.737181474
Short name	T504
Test name
Test status
Simulation time	21217643 ps
CPU time	0.75 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	201108 kb
Host	smart-00d9c46e-dcc3-4fc0-b37f-fb14a31fb6df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737181474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.clkmgr_lc_ctrl_intersig_mubi.737181474
Directory	/workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_peri.1411405165
Short name	T759
Test name
Test status
Simulation time	19550548 ps
CPU time	0.72 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	200992 kb
Host	smart-cf4d0fe9-d5d9-42da-b468-c9216f35c917
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411405165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1411405165
Directory	/workspace/34.clkmgr_peri/latest

Test location	/workspace/coverage/default/34.clkmgr_regwen.62115231
Short name	T651
Test name
Test status
Simulation time	741271725 ps
CPU time	4.11 seconds
Started	Jul 18 06:43:27 PM PDT 24
Finished	Jul 18 06:43:36 PM PDT 24
Peak memory	201244 kb
Host	smart-60885959-50b2-48b0-a2c5-159bee700659
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62115231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.62115231
Directory	/workspace/34.clkmgr_regwen/latest

Test location	/workspace/coverage/default/34.clkmgr_smoke.3877135018
Short name	T719
Test name
Test status
Simulation time	24392467 ps
CPU time	0.88 seconds
Started	Jul 18 06:43:26 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201016 kb
Host	smart-c6f823f3-1cfd-4b3f-93a4-7b46fea94bcf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877135018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.3877135018
Directory	/workspace/34.clkmgr_smoke/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all.1903799260
Short name	T612
Test name
Test status
Simulation time	5134324601 ps
CPU time	20.12 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:51 PM PDT 24
Peak memory	201448 kb
Host	smart-85bdcfb6-fd11-4600-8393-e4e113370c2e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903799260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.1903799260
Directory	/workspace/34.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.1171968450
Short name	T536
Test name
Test status
Simulation time	126377635642 ps
CPU time	822.83 seconds
Started	Jul 18 06:43:22 PM PDT 24
Finished	Jul 18 06:57:08 PM PDT 24
Peak memory	209764 kb
Host	smart-89a6b09c-140d-40ec-b5cf-764a027d104c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1171968450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.1171968450
Directory	/workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.clkmgr_trans.2751406039
Short name	T803
Test name
Test status
Simulation time	27363219 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:31 PM PDT 24
Peak memory	201076 kb
Host	smart-7ad3bc63-fcbf-4d86-aec0-e3d7d763ef0c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751406039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.2751406039
Directory	/workspace/34.clkmgr_trans/latest

Test location	/workspace/coverage/default/35.clkmgr_alert_test.1409989220
Short name	T271
Test name
Test status
Simulation time	15517236 ps
CPU time	0.73 seconds
Started	Jul 18 06:43:34 PM PDT 24
Finished	Jul 18 06:43:37 PM PDT 24
Peak memory	201228 kb
Host	smart-40de8a49-c736-4cab-bff6-ac40893b9eb1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409989220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.1409989220
Directory	/workspace/35.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.1982250574
Short name	T111
Test name
Test status
Simulation time	19482147 ps
CPU time	0.8 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:44 PM PDT 24
Peak memory	201128 kb
Host	smart-23f4062a-808d-4cd5-9c4a-98308811384e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982250574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.1982250574
Directory	/workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_status.268712728
Short name	T470
Test name
Test status
Simulation time	39164511 ps
CPU time	0.75 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	200292 kb
Host	smart-2a92efc4-bdb5-4d30-af70-8953e2cf08fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268712728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.268712728
Directory	/workspace/35.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/35.clkmgr_div_intersig_mubi.3346653413
Short name	T606
Test name
Test status
Simulation time	96663305 ps
CPU time	1.05 seconds
Started	Jul 18 06:43:38 PM PDT 24
Finished	Jul 18 06:43:43 PM PDT 24
Peak memory	201124 kb
Host	smart-22b1ce9c-bb79-4344-9228-7220b7d3eb65
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346653413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.3346653413
Directory	/workspace/35.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_extclk.3967518699
Short name	T294
Test name
Test status
Simulation time	84994512 ps
CPU time	1.05 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:30 PM PDT 24
Peak memory	201080 kb
Host	smart-973c5008-bdac-4f77-9a65-dd77e7c94cf9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967518699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3967518699
Directory	/workspace/35.clkmgr_extclk/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency.90022948
Short name	T792
Test name
Test status
Simulation time	1359826620 ps
CPU time	6.6 seconds
Started	Jul 18 06:43:24 PM PDT 24
Finished	Jul 18 06:43:36 PM PDT 24
Peak memory	201148 kb
Host	smart-fde51ee9-2512-4f80-a7af-2bc0ecbc6283
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90022948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.90022948
Directory	/workspace/35.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency_timeout.2706406257
Short name	T695
Test name
Test status
Simulation time	2426166231 ps
CPU time	12.86 seconds
Started	Jul 18 06:43:25 PM PDT 24
Finished	Jul 18 06:43:43 PM PDT 24
Peak memory	201440 kb
Host	smart-ce7907c1-cd26-4b99-9eba-648db11a6b0d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706406257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t imeout.2706406257
Directory	/workspace/35.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/35.clkmgr_idle_intersig_mubi.2602775432
Short name	T254
Test name
Test status
Simulation time	71775463 ps
CPU time	1.07 seconds
Started	Jul 18 06:43:36 PM PDT 24
Finished	Jul 18 06:43:39 PM PDT 24
Peak memory	201044 kb
Host	smart-03987710-175a-470c-ac51-00cb1a6ddf28
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602775432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.2602775432
Directory	/workspace/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2380135581
Short name	T652
Test name
Test status
Simulation time	87513408 ps
CPU time	1.08 seconds
Started	Jul 18 06:43:38 PM PDT 24
Finished	Jul 18 06:43:43 PM PDT 24
Peak memory	201096 kb
Host	smart-5d8b68e4-5c8b-4c3f-8113-620a238c86b8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380135581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2380135581
Directory	/workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.768141918
Short name	T394
Test name
Test status
Simulation time	23002515 ps
CPU time	0.83 seconds
Started	Jul 18 06:43:36 PM PDT 24
Finished	Jul 18 06:43:40 PM PDT 24
Peak memory	201084 kb
Host	smart-469ed630-5395-4cc1-b274-2b3241a6deef
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768141918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.clkmgr_lc_ctrl_intersig_mubi.768141918
Directory	/workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_peri.1060075950
Short name	T386
Test name
Test status
Simulation time	50103053 ps
CPU time	0.89 seconds
Started	Jul 18 06:43:26 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201104 kb
Host	smart-04b46dc0-2173-4042-83e8-009e24ef29d1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060075950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1060075950
Directory	/workspace/35.clkmgr_peri/latest

Test location	/workspace/coverage/default/35.clkmgr_regwen.3359750065
Short name	T521
Test name
Test status
Simulation time	358383216 ps
CPU time	2.02 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	201032 kb
Host	smart-14e1a8d5-7855-41c1-9059-1ceeaa582829
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359750065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3359750065
Directory	/workspace/35.clkmgr_regwen/latest

Test location	/workspace/coverage/default/35.clkmgr_smoke.3158916993
Short name	T745
Test name
Test status
Simulation time	37240073 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:26 PM PDT 24
Finished	Jul 18 06:43:32 PM PDT 24
Peak memory	201024 kb
Host	smart-41a2886d-852c-4219-a5c1-c27d72dda7bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158916993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.3158916993
Directory	/workspace/35.clkmgr_smoke/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all.3203579710
Short name	T304
Test name
Test status
Simulation time	3542666691 ps
CPU time	15.36 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:44:03 PM PDT 24
Peak memory	201484 kb
Host	smart-40afda3a-4ac2-4c98-90c4-92db0e395584
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203579710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.3203579710
Directory	/workspace/35.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/35.clkmgr_trans.2494242078
Short name	T364
Test name
Test status
Simulation time	112376805 ps
CPU time	1.26 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:47 PM PDT 24
Peak memory	201112 kb
Host	smart-f80e4e4a-a696-4c51-82c4-bac22b4ba4de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494242078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.2494242078
Directory	/workspace/35.clkmgr_trans/latest

Test location	/workspace/coverage/default/36.clkmgr_alert_test.3349943224
Short name	T783
Test name
Test status
Simulation time	14972330 ps
CPU time	0.74 seconds
Started	Jul 18 06:43:37 PM PDT 24
Finished	Jul 18 06:43:41 PM PDT 24
Peak memory	201212 kb
Host	smart-6544944f-3a79-4f50-afa2-386ed3f9ec9c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349943224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.3349943224
Directory	/workspace/36.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.366655200
Short name	T57
Test name
Test status
Simulation time	17977361 ps
CPU time	0.84 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:47 PM PDT 24
Peak memory	201288 kb
Host	smart-ff9e3e63-6188-4962-9485-794c2411ebed
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366655200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.366655200
Directory	/workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_status.302977095
Short name	T704
Test name
Test status
Simulation time	17540314 ps
CPU time	0.72 seconds
Started	Jul 18 06:43:41 PM PDT 24
Finished	Jul 18 06:43:48 PM PDT 24
Peak memory	200292 kb
Host	smart-113ccd37-9545-44a0-beb5-f33cc03491cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302977095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.302977095
Directory	/workspace/36.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/36.clkmgr_div_intersig_mubi.4221042356
Short name	T675
Test name
Test status
Simulation time	94945315 ps
CPU time	1.09 seconds
Started	Jul 18 06:43:36 PM PDT 24
Finished	Jul 18 06:43:41 PM PDT 24
Peak memory	201100 kb
Host	smart-002c64dc-7862-4cfe-b38a-155f6a0a9b0f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221042356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.4221042356
Directory	/workspace/36.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_extclk.2391019947
Short name	T826
Test name
Test status
Simulation time	18498122 ps
CPU time	0.79 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	201088 kb
Host	smart-88f1cc47-60f7-4e98-8af8-f6cf0c1d5f2e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391019947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2391019947
Directory	/workspace/36.clkmgr_extclk/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency.4067621255
Short name	T402
Test name
Test status
Simulation time	335921033 ps
CPU time	2.02 seconds
Started	Jul 18 06:43:43 PM PDT 24
Finished	Jul 18 06:43:51 PM PDT 24
Peak memory	201172 kb
Host	smart-6fcaf9f4-cb46-4923-9c0f-c3426d116c29
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067621255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.4067621255
Directory	/workspace/36.clkmgr_frequency/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency_timeout.2477515907
Short name	T34
Test name
Test status
Simulation time	2294837640 ps
CPU time	16.76 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:44:00 PM PDT 24
Peak memory	201464 kb
Host	smart-6c106f4f-e929-45c5-bf08-db4448d0277e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477515907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t imeout.2477515907
Directory	/workspace/36.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1562438139
Short name	T710
Test name
Test status
Simulation time	371907971 ps
CPU time	2.06 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	200988 kb
Host	smart-2a7f82b3-ce59-4c80-b6cf-890910e29a4a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562438139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.1562438139
Directory	/workspace/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.259559572
Short name	T290
Test name
Test status
Simulation time	18609289 ps
CPU time	0.78 seconds
Started	Jul 18 06:43:35 PM PDT 24
Finished	Jul 18 06:43:38 PM PDT 24
Peak memory	201100 kb
Host	smart-d268e6c9-f649-4042-aa71-afa42da05325
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259559572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.clkmgr_lc_clk_byp_req_intersig_mubi.259559572
Directory	/workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1199132220
Short name	T727
Test name
Test status
Simulation time	109685453 ps
CPU time	1.1 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:45 PM PDT 24
Peak memory	201088 kb
Host	smart-2346d99f-3e08-4247-981b-c285482252a2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199132220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_ctrl_intersig_mubi.1199132220
Directory	/workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_peri.864716011
Short name	T726
Test name
Test status
Simulation time	15428013 ps
CPU time	0.73 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:49 PM PDT 24
Peak memory	201004 kb
Host	smart-0f63e229-d1e5-40c3-849e-f9df0aa3545d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864716011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.864716011
Directory	/workspace/36.clkmgr_peri/latest

Test location	/workspace/coverage/default/36.clkmgr_regwen.1409373266
Short name	T98
Test name
Test status
Simulation time	443584024 ps
CPU time	3 seconds
Started	Jul 18 06:43:36 PM PDT 24
Finished	Jul 18 06:43:43 PM PDT 24
Peak memory	201024 kb
Host	smart-487fd414-1530-45d1-ab28-97bc70323a14
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409373266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.1409373266
Directory	/workspace/36.clkmgr_regwen/latest

Test location	/workspace/coverage/default/36.clkmgr_smoke.1126064116
Short name	T168
Test name
Test status
Simulation time	24190522 ps
CPU time	0.95 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:45 PM PDT 24
Peak memory	201016 kb
Host	smart-d47e34ee-3d7b-4a44-8c10-86118818db76
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126064116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.1126064116
Directory	/workspace/36.clkmgr_smoke/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all.3050459197
Short name	T279
Test name
Test status
Simulation time	13581400422 ps
CPU time	96.68 seconds
Started	Jul 18 06:43:37 PM PDT 24
Finished	Jul 18 06:45:17 PM PDT 24
Peak memory	201456 kb
Host	smart-05f36722-7302-45e4-821b-15196d50e2b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050459197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.3050459197
Directory	/workspace/36.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.1841223104
Short name	T155
Test name
Test status
Simulation time	12559215648 ps
CPU time	191.41 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:46:57 PM PDT 24
Peak memory	217952 kb
Host	smart-69600a52-d472-4053-bded-254863309337
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1841223104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.1841223104
Directory	/workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.clkmgr_trans.1024056264
Short name	T513
Test name
Test status
Simulation time	22943190 ps
CPU time	0.84 seconds
Started	Jul 18 06:43:43 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	201100 kb
Host	smart-16dab2c7-150a-400f-b1bc-5c9f732066ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024056264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1024056264
Directory	/workspace/36.clkmgr_trans/latest

Test location	/workspace/coverage/default/37.clkmgr_alert_test.1453148912
Short name	T404
Test name
Test status
Simulation time	115944972 ps
CPU time	1.09 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:47 PM PDT 24
Peak memory	201232 kb
Host	smart-f7b45b52-4c00-4f97-8185-68ca236a6f72
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453148912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.1453148912
Directory	/workspace/37.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2282016809
Short name	T109
Test name
Test status
Simulation time	22443407 ps
CPU time	0.86 seconds
Started	Jul 18 06:43:43 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	201100 kb
Host	smart-9acc2be1-87ac-4e81-80a9-aa4c5a1a3936
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282016809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.2282016809
Directory	/workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_status.1014592376
Short name	T24
Test name
Test status
Simulation time	21151572 ps
CPU time	0.73 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:44 PM PDT 24
Peak memory	200984 kb
Host	smart-a7291b00-1e9d-4ca6-a5dc-c56643485b5d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014592376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1014592376
Directory	/workspace/37.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/37.clkmgr_div_intersig_mubi.4151724074
Short name	T571
Test name
Test status
Simulation time	50320312 ps
CPU time	0.88 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:45 PM PDT 24
Peak memory	201232 kb
Host	smart-cd888b5f-df6a-4a01-8031-0e9fb3753e2f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151724074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.4151724074
Directory	/workspace/37.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_extclk.71158066
Short name	T192
Test name
Test status
Simulation time	28152825 ps
CPU time	0.83 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	201276 kb
Host	smart-b0ef6b44-92e9-4320-af6b-3be8a4daa0bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71158066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.71158066
Directory	/workspace/37.clkmgr_extclk/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency.2452815156
Short name	T596
Test name
Test status
Simulation time	1742170769 ps
CPU time	8.07 seconds
Started	Jul 18 06:43:38 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	201156 kb
Host	smart-df0d86b8-7ea0-449b-a657-793b82d685a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452815156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2452815156
Directory	/workspace/37.clkmgr_frequency/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency_timeout.1220837299
Short name	T639
Test name
Test status
Simulation time	1224712621 ps
CPU time	6.84 seconds
Started	Jul 18 06:43:36 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	201204 kb
Host	smart-f3996cbe-c45a-485b-9725-dc2242855c40
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220837299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t imeout.1220837299
Directory	/workspace/37.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/37.clkmgr_idle_intersig_mubi.1910552766
Short name	T477
Test name
Test status
Simulation time	75066074 ps
CPU time	0.94 seconds
Started	Jul 18 06:43:34 PM PDT 24
Finished	Jul 18 06:43:38 PM PDT 24
Peak memory	201088 kb
Host	smart-ea6477fc-6970-43b9-9d45-111b3e423227
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910552766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.1910552766
Directory	/workspace/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3068306798
Short name	T129
Test name
Test status
Simulation time	58426522 ps
CPU time	0.94 seconds
Started	Jul 18 06:43:37 PM PDT 24
Finished	Jul 18 06:43:42 PM PDT 24
Peak memory	201124 kb
Host	smart-f648d619-5b85-447e-a73c-4b4d5301e2ab
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068306798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_clk_byp_req_intersig_mubi.3068306798
Directory	/workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.3128657700
Short name	T836
Test name
Test status
Simulation time	28140378 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:36 PM PDT 24
Finished	Jul 18 06:43:41 PM PDT 24
Peak memory	201116 kb
Host	smart-8da5e066-fcd3-4385-a54c-1006c540c92c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128657700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_ctrl_intersig_mubi.3128657700
Directory	/workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_peri.737018029
Short name	T630
Test name
Test status
Simulation time	28453615 ps
CPU time	0.83 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:48 PM PDT 24
Peak memory	201032 kb
Host	smart-8b4e5d04-a9c2-4978-be5a-d0a3739057fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737018029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.737018029
Directory	/workspace/37.clkmgr_peri/latest

Test location	/workspace/coverage/default/37.clkmgr_smoke.303333925
Short name	T174
Test name
Test status
Simulation time	24939404 ps
CPU time	0.85 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	201020 kb
Host	smart-c9b78ceb-5568-4e96-a5bd-3b12dc326226
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303333925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.303333925
Directory	/workspace/37.clkmgr_smoke/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all.1107241948
Short name	T469
Test name
Test status
Simulation time	73737369 ps
CPU time	1.45 seconds
Started	Jul 18 06:43:37 PM PDT 24
Finished	Jul 18 06:43:42 PM PDT 24
Peak memory	201084 kb
Host	smart-ab677e9b-ea31-42cf-b6ac-039e474e2521
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107241948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.1107241948
Directory	/workspace/37.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.366223564
Short name	T10
Test name
Test status
Simulation time	24132317622 ps
CPU time	450.26 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:51:18 PM PDT 24
Peak memory	209744 kb
Host	smart-0d26f54b-0395-48bc-8cda-6bbbd937ad9a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=366223564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.366223564
Directory	/workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.clkmgr_trans.1595566352
Short name	T479
Test name
Test status
Simulation time	83334743 ps
CPU time	1.07 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	201072 kb
Host	smart-c9261a2d-727a-4a73-9412-5192d2223cf9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595566352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.1595566352
Directory	/workspace/37.clkmgr_trans/latest

Test location	/workspace/coverage/default/38.clkmgr_alert_test.3542819849
Short name	T225
Test name
Test status
Simulation time	19051116 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:41 PM PDT 24
Finished	Jul 18 06:43:48 PM PDT 24
Peak memory	201204 kb
Host	smart-502152b1-bc20-463f-afe5-9af6afef8b14
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542819849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.3542819849
Directory	/workspace/38.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.510313858
Short name	T107
Test name
Test status
Simulation time	26516349 ps
CPU time	0.77 seconds
Started	Jul 18 06:43:37 PM PDT 24
Finished	Jul 18 06:43:42 PM PDT 24
Peak memory	201100 kb
Host	smart-9e1ad5b0-395e-4b39-9181-a709a8beb675
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510313858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.510313858
Directory	/workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_status.3759169782
Short name	T657
Test name
Test status
Simulation time	42720740 ps
CPU time	0.72 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	200288 kb
Host	smart-f0a1f5f3-8582-4574-bd7a-8494a77c9956
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759169782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3759169782
Directory	/workspace/38.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/38.clkmgr_div_intersig_mubi.1747278182
Short name	T665
Test name
Test status
Simulation time	18126074 ps
CPU time	0.78 seconds
Started	Jul 18 06:43:43 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	201104 kb
Host	smart-b713c233-44ad-458a-b32d-ed08cbed834a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747278182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.1747278182
Directory	/workspace/38.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_extclk.1947621641
Short name	T297
Test name
Test status
Simulation time	99311698 ps
CPU time	1.08 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	201088 kb
Host	smart-57a02219-c9a4-4c5f-9ec1-3bd7a24944bf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947621641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1947621641
Directory	/workspace/38.clkmgr_extclk/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency.1028905612
Short name	T807
Test name
Test status
Simulation time	1211263091 ps
CPU time	4.88 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:49 PM PDT 24
Peak memory	201320 kb
Host	smart-21801175-144f-43f2-a7e6-3ba050c9c66c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028905612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1028905612
Directory	/workspace/38.clkmgr_frequency/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency_timeout.3926873335
Short name	T309
Test name
Test status
Simulation time	1334949218 ps
CPU time	9.63 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:58 PM PDT 24
Peak memory	201104 kb
Host	smart-d793866e-7fd8-442e-a336-dcbf022879a8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926873335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t imeout.3926873335
Directory	/workspace/38.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3738879760
Short name	T714
Test name
Test status
Simulation time	13059852 ps
CPU time	0.74 seconds
Started	Jul 18 06:43:41 PM PDT 24
Finished	Jul 18 06:43:48 PM PDT 24
Peak memory	201092 kb
Host	smart-aa1e2ef1-a113-4cbe-ba2b-7a5897b60bd5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738879760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.3738879760
Directory	/workspace/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.30510015
Short name	T348
Test name
Test status
Simulation time	15361781 ps
CPU time	0.72 seconds
Started	Jul 18 06:43:36 PM PDT 24
Finished	Jul 18 06:43:40 PM PDT 24
Peak memory	201000 kb
Host	smart-ea572130-479b-4fda-aa66-46ce978a9a9f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30510015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.30510015
Directory	/workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3723272724
Short name	T698
Test name
Test status
Simulation time	19318696 ps
CPU time	0.78 seconds
Started	Jul 18 06:43:48 PM PDT 24
Finished	Jul 18 06:43:54 PM PDT 24
Peak memory	200344 kb
Host	smart-c6e7060d-53e3-4487-9b10-fce832f13e33
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723272724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_ctrl_intersig_mubi.3723272724
Directory	/workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_peri.1860429039
Short name	T210
Test name
Test status
Simulation time	20554688 ps
CPU time	0.73 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:49 PM PDT 24
Peak memory	200956 kb
Host	smart-b03c599d-cf4a-4e53-9b02-63f51473aa94
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860429039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1860429039
Directory	/workspace/38.clkmgr_peri/latest

Test location	/workspace/coverage/default/38.clkmgr_regwen.1662154104
Short name	T283
Test name
Test status
Simulation time	1408934449 ps
CPU time	4.79 seconds
Started	Jul 18 06:43:41 PM PDT 24
Finished	Jul 18 06:43:52 PM PDT 24
Peak memory	201268 kb
Host	smart-a698dd9f-94d8-4ad0-89c1-ed994a06bcab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662154104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1662154104
Directory	/workspace/38.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_smoke.931842359
Short name	T215
Test name
Test status
Simulation time	18629843 ps
CPU time	0.82 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	201056 kb
Host	smart-51a6fa11-732e-4a1b-96c7-9200b3e6c7a7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931842359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.931842359
Directory	/workspace/38.clkmgr_smoke/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all.2952641249
Short name	T447
Test name
Test status
Simulation time	7679735534 ps
CPU time	26.39 seconds
Started	Jul 18 06:43:53 PM PDT 24
Finished	Jul 18 06:44:23 PM PDT 24
Peak memory	201416 kb
Host	smart-b792d0e0-95f8-4e4c-93f7-514e62f146fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952641249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.2952641249
Directory	/workspace/38.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.3822316749
Short name	T381
Test name
Test status
Simulation time	123822576475 ps
CPU time	760.7 seconds
Started	Jul 18 06:43:51 PM PDT 24
Finished	Jul 18 06:56:36 PM PDT 24
Peak memory	213944 kb
Host	smart-20328ebc-3bdd-4a63-9cc5-19cd6f418950
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3822316749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.3822316749
Directory	/workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.clkmgr_trans.3801268762
Short name	T530
Test name
Test status
Simulation time	45171626 ps
CPU time	1 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:47 PM PDT 24
Peak memory	201108 kb
Host	smart-75afabb6-4733-42df-8b02-00058cf2b0a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801268762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3801268762
Directory	/workspace/38.clkmgr_trans/latest

Test location	/workspace/coverage/default/39.clkmgr_alert_test.1516716948
Short name	T285
Test name
Test status
Simulation time	17992908 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:44 PM PDT 24
Finished	Jul 18 06:43:51 PM PDT 24
Peak memory	201220 kb
Host	smart-0438655c-2a13-4eb1-ad15-100cd3567149
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516716948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk mgr_alert_test.1516716948
Directory	/workspace/39.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1079024699
Short name	T507
Test name
Test status
Simulation time	24848098 ps
CPU time	0.92 seconds
Started	Jul 18 06:43:44 PM PDT 24
Finished	Jul 18 06:43:51 PM PDT 24
Peak memory	201092 kb
Host	smart-533df570-4117-48c7-b522-3aac779d48dd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079024699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.1079024699
Directory	/workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_status.3152726524
Short name	T520
Test name
Test status
Simulation time	74051976 ps
CPU time	0.84 seconds
Started	Jul 18 06:43:49 PM PDT 24
Finished	Jul 18 06:43:54 PM PDT 24
Peak memory	200288 kb
Host	smart-51772180-0f7c-4b38-af86-8be582087a48
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152726524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3152726524
Directory	/workspace/39.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/39.clkmgr_div_intersig_mubi.1015392522
Short name	T579
Test name
Test status
Simulation time	19345987 ps
CPU time	0.8 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:47 PM PDT 24
Peak memory	201100 kb
Host	smart-34ad8826-94b8-4776-bdb1-a92b5a511dd4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015392522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.1015392522
Directory	/workspace/39.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_extclk.3553251212
Short name	T127
Test name
Test status
Simulation time	18072808 ps
CPU time	0.79 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:43:45 PM PDT 24
Peak memory	201100 kb
Host	smart-696ad9ca-6457-4217-8dee-0a7c031fd9ce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553251212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.3553251212
Directory	/workspace/39.clkmgr_extclk/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency.1450230565
Short name	T569
Test name
Test status
Simulation time	321406575 ps
CPU time	3.05 seconds
Started	Jul 18 06:43:41 PM PDT 24
Finished	Jul 18 06:43:50 PM PDT 24
Peak memory	201144 kb
Host	smart-0064477a-70f6-484a-bc33-5c20a309bfa1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450230565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1450230565
Directory	/workspace/39.clkmgr_frequency/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency_timeout.347277479
Short name	T263
Test name
Test status
Simulation time	138299588 ps
CPU time	1.72 seconds
Started	Jul 18 06:43:37 PM PDT 24
Finished	Jul 18 06:43:43 PM PDT 24
Peak memory	201116 kb
Host	smart-43886ac0-f169-4d58-a732-f79f0d11ed6a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347277479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_ti meout.347277479
Directory	/workspace/39.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1600675579
Short name	T559
Test name
Test status
Simulation time	29207566 ps
CPU time	0.95 seconds
Started	Jul 18 06:43:38 PM PDT 24
Finished	Jul 18 06:43:43 PM PDT 24
Peak memory	201048 kb
Host	smart-dbcfb7d9-d717-46ba-8437-41a70518bd7c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600675579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.1600675579
Directory	/workspace/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1806533415
Short name	T211
Test name
Test status
Simulation time	26150208 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:46 PM PDT 24
Peak memory	201104 kb
Host	smart-449467d0-35be-472d-ad2c-84ecd3a76497
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806533415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1806533415
Directory	/workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.2276506902
Short name	T527
Test name
Test status
Simulation time	30022531 ps
CPU time	0.75 seconds
Started	Jul 18 06:43:40 PM PDT 24
Finished	Jul 18 06:43:47 PM PDT 24
Peak memory	201128 kb
Host	smart-4f0413a0-ef6a-4bb1-9aff-3d252b3dd0ab
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276506902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_ctrl_intersig_mubi.2276506902
Directory	/workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_peri.34015869
Short name	T354
Test name
Test status
Simulation time	21840443 ps
CPU time	0.78 seconds
Started	Jul 18 06:43:38 PM PDT 24
Finished	Jul 18 06:43:43 PM PDT 24
Peak memory	201060 kb
Host	smart-929e8bbb-f813-4c18-84a4-7352ac76729a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34015869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.34015869
Directory	/workspace/39.clkmgr_peri/latest

Test location	/workspace/coverage/default/39.clkmgr_regwen.506466236
Short name	T647
Test name
Test status
Simulation time	1191332296 ps
CPU time	6.36 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:54 PM PDT 24
Peak memory	201268 kb
Host	smart-5986c7d7-5900-4523-bd12-9e4e8160e43f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506466236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.506466236
Directory	/workspace/39.clkmgr_regwen/latest

Test location	/workspace/coverage/default/39.clkmgr_smoke.3090179193
Short name	T159
Test name
Test status
Simulation time	38993533 ps
CPU time	0.89 seconds
Started	Jul 18 06:43:42 PM PDT 24
Finished	Jul 18 06:43:49 PM PDT 24
Peak memory	201056 kb
Host	smart-1a772234-936d-4491-9822-2c810fcda963
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090179193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.3090179193
Directory	/workspace/39.clkmgr_smoke/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all.2451568506
Short name	T701
Test name
Test status
Simulation time	13973972781 ps
CPU time	45.52 seconds
Started	Jul 18 06:43:45 PM PDT 24
Finished	Jul 18 06:44:37 PM PDT 24
Peak memory	201444 kb
Host	smart-2709dcb7-b6f0-4bbf-9650-341909f9a161
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451568506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.2451568506
Directory	/workspace/39.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.2527720073
Short name	T664
Test name
Test status
Simulation time	19986530085 ps
CPU time	282.33 seconds
Started	Jul 18 06:43:39 PM PDT 24
Finished	Jul 18 06:48:26 PM PDT 24
Peak memory	209780 kb
Host	smart-741affb7-10b1-4c5e-8f70-f08cc3b58e5b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2527720073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.2527720073
Directory	/workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.clkmgr_trans.1568156728
Short name	T196
Test name
Test status
Simulation time	29676156 ps
CPU time	1 seconds
Started	Jul 18 06:43:41 PM PDT 24
Finished	Jul 18 06:43:48 PM PDT 24
Peak memory	201028 kb
Host	smart-ca2518b5-e6f1-4567-911a-7167f5450e41
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568156728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1568156728
Directory	/workspace/39.clkmgr_trans/latest

Test location	/workspace/coverage/default/4.clkmgr_alert_test.3936781507
Short name	T736
Test name
Test status
Simulation time	32931208 ps
CPU time	0.82 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:16 PM PDT 24
Peak memory	201208 kb
Host	smart-8970620f-3107-4dca-8ee3-392b64ea3647
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936781507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm gr_alert_test.3936781507
Directory	/workspace/4.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.796072068
Short name	T236
Test name
Test status
Simulation time	48872511 ps
CPU time	0.88 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:14 PM PDT 24
Peak memory	201004 kb
Host	smart-0bb6811d-2851-43c4-bff6-f402feb137b2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796072068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.796072068
Directory	/workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_status.1331028897
Short name	T601
Test name
Test status
Simulation time	54416846 ps
CPU time	0.88 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:11 PM PDT 24
Peak memory	200288 kb
Host	smart-696ccb8f-a6db-4b27-979e-aea387e09045
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331028897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1331028897
Directory	/workspace/4.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/4.clkmgr_div_intersig_mubi.2660047449
Short name	T781
Test name
Test status
Simulation time	43305682 ps
CPU time	0.95 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:17 PM PDT 24
Peak memory	201084 kb
Host	smart-00ca84cb-3e3e-4f58-9933-0a2b2d6ca214
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660047449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.2660047449
Directory	/workspace/4.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_extclk.1485395755
Short name	T558
Test name
Test status
Simulation time	78827828 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:11 PM PDT 24
Peak memory	201064 kb
Host	smart-8e5305c3-cc5d-4258-8c40-35a32bbf81b6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485395755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1485395755
Directory	/workspace/4.clkmgr_extclk/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency.1396738646
Short name	T708
Test name
Test status
Simulation time	1603233658 ps
CPU time	6.14 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:24 PM PDT 24
Peak memory	201148 kb
Host	smart-086a3a51-c634-4658-84cf-9eb7dcec3e0e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396738646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1396738646
Directory	/workspace/4.clkmgr_frequency/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency_timeout.1117934087
Short name	T380
Test name
Test status
Simulation time	1565918847 ps
CPU time	6.29 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201280 kb
Host	smart-7f61e8f7-49a3-484a-aa0a-aa6acfd1c055
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117934087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti meout.1117934087
Directory	/workspace/4.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1459329704
Short name	T19
Test name
Test status
Simulation time	18542695 ps
CPU time	0.91 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201068 kb
Host	smart-20776750-42ef-497d-8346-4f88eeb4b657
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459329704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.1459329704
Directory	/workspace/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.33847325
Short name	T40
Test name
Test status
Simulation time	21123950 ps
CPU time	0.85 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:15 PM PDT 24
Peak memory	201104 kb
Host	smart-d3e8cb66-5964-4930-b827-20c71599ff79
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33847325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.33847325
Directory	/workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1311652298
Short name	T583
Test name
Test status
Simulation time	110674811 ps
CPU time	1.09 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201092 kb
Host	smart-c2da35a8-6f4b-49f5-a1b8-9912a3c1f47b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311652298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.1311652298
Directory	/workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_peri.887754390
Short name	T640
Test name
Test status
Simulation time	15000370 ps
CPU time	0.77 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:12 PM PDT 24
Peak memory	201016 kb
Host	smart-8b3a4ff1-b35d-43ed-a0fb-d668e0706d8b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887754390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.887754390
Directory	/workspace/4.clkmgr_peri/latest

Test location	/workspace/coverage/default/4.clkmgr_regwen.1363496130
Short name	T489
Test name
Test status
Simulation time	718416147 ps
CPU time	2.87 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201256 kb
Host	smart-2be11f82-de4c-4eda-a979-ff18ed0ae5cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363496130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1363496130
Directory	/workspace/4.clkmgr_regwen/latest

Test location	/workspace/coverage/default/4.clkmgr_sec_cm.304455750
Short name	T44
Test name
Test status
Simulation time	202857925 ps
CPU time	1.91 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:13 PM PDT 24
Peak memory	216272 kb
Host	smart-9e82ea49-005e-40eb-91fc-91073eca6857
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304455750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr _sec_cm.304455750
Directory	/workspace/4.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/4.clkmgr_smoke.1560433143
Short name	T51
Test name
Test status
Simulation time	77718951 ps
CPU time	1.02 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:18 PM PDT 24
Peak memory	201040 kb
Host	smart-dbb37b6c-11b5-4fac-a025-cc795a7e98a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560433143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1560433143
Directory	/workspace/4.clkmgr_smoke/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all.2502110429
Short name	T434
Test name
Test status
Simulation time	7275016971 ps
CPU time	31.46 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:42 PM PDT 24
Peak memory	201380 kb
Host	smart-fc829ed3-8464-4c0b-93c0-af6afd4c4d45
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502110429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.2502110429
Directory	/workspace/4.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.4095300051
Short name	T172
Test name
Test status
Simulation time	482142429704 ps
CPU time	1865.95 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 07:12:24 PM PDT 24
Peak memory	217160 kb
Host	smart-90195ba9-d2f1-4e0f-9f98-36bb9651e917
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4095300051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.4095300051
Directory	/workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.clkmgr_trans.3122532144
Short name	T608
Test name
Test status
Simulation time	42671405 ps
CPU time	0.9 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:11 PM PDT 24
Peak memory	201112 kb
Host	smart-87feef7e-9500-4399-b198-e2016d1d30fd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122532144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3122532144
Directory	/workspace/4.clkmgr_trans/latest

Test location	/workspace/coverage/default/40.clkmgr_alert_test.1381452746
Short name	T492
Test name
Test status
Simulation time	75188184 ps
CPU time	0.98 seconds
Started	Jul 18 06:43:50 PM PDT 24
Finished	Jul 18 06:43:55 PM PDT 24
Peak memory	201224 kb
Host	smart-1b0ed026-565c-40ac-acb9-112bd4c79044
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381452746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk mgr_alert_test.1381452746
Directory	/workspace/40.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3058391022
Short name	T41
Test name
Test status
Simulation time	19961506 ps
CPU time	0.81 seconds
Started	Jul 18 06:43:49 PM PDT 24
Finished	Jul 18 06:43:54 PM PDT 24
Peak memory	201088 kb
Host	smart-fe1b05b5-1320-4006-a218-3bfa4470cccf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058391022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.3058391022
Directory	/workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_status.1151120311
Short name	T184
Test name
Test status
Simulation time	16123165 ps
CPU time	0.7 seconds
Started	Jul 18 06:43:45 PM PDT 24
Finished	Jul 18 06:43:52 PM PDT 24
Peak memory	200268 kb
Host	smart-5abbec7c-b33d-4f45-944d-60a51ea44554
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151120311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1151120311
Directory	/workspace/40.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/40.clkmgr_div_intersig_mubi.3147073163
Short name	T235
Test name
Test status
Simulation time	48951962 ps
CPU time	0.95 seconds
Started	Jul 18 06:43:51 PM PDT 24
Finished	Jul 18 06:43:56 PM PDT 24
Peak memory	201120 kb
Host	smart-e1d0e263-be41-49b7-8e02-57641eb24673
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147073163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.3147073163
Directory	/workspace/40.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_extclk.508933280
Short name	T401
Test name
Test status
Simulation time	46353112 ps
CPU time	0.86 seconds
Started	Jul 18 06:43:46 PM PDT 24
Finished	Jul 18 06:43:53 PM PDT 24
Peak memory	201068 kb
Host	smart-2b1a186d-e91b-4f63-8b0b-e4820b28cf3b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508933280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.508933280
Directory	/workspace/40.clkmgr_extclk/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency.1143828400
Short name	T616
Test name
Test status
Simulation time	1756494237 ps
CPU time	12.93 seconds
Started	Jul 18 06:43:45 PM PDT 24
Finished	Jul 18 06:44:04 PM PDT 24
Peak memory	201308 kb
Host	smart-1fcddecd-c43c-4d22-b803-74835486ae55
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143828400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1143828400
Directory	/workspace/40.clkmgr_frequency/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency_timeout.3512564563
Short name	T376
Test name
Test status
Simulation time	1825495386 ps
CPU time	9.86 seconds
Started	Jul 18 06:43:44 PM PDT 24
Finished	Jul 18 06:44:00 PM PDT 24
Peak memory	201228 kb
Host	smart-4d8ebbab-e5f5-4150-95d1-1ac29ecbaec0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512564563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t imeout.3512564563
Directory	/workspace/40.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.3542410674
Short name	T694
Test name
Test status
Simulation time	72310213 ps
CPU time	1.01 seconds
Started	Jul 18 06:43:43 PM PDT 24
Finished	Jul 18 06:43:51 PM PDT 24
Peak memory	201084 kb
Host	smart-039a1d23-5f16-4c15-b652-18a62ab29e53
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542410674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3542410674
Directory	/workspace/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.970605781
Short name	T303
Test name
Test status
Simulation time	15081972 ps
CPU time	0.74 seconds
Started	Jul 18 06:43:49 PM PDT 24
Finished	Jul 18 06:43:54 PM PDT 24
Peak memory	201108 kb
Host	smart-afa5d5b8-fd29-4a1f-8729-11432aa85f27
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970605781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.clkmgr_lc_clk_byp_req_intersig_mubi.970605781
Directory	/workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.4046363306
Short name	T178
Test name
Test status
Simulation time	60181366 ps
CPU time	0.98 seconds
Started	Jul 18 06:43:44 PM PDT 24
Finished	Jul 18 06:43:52 PM PDT 24
Peak memory	201092 kb
Host	smart-88a8d8bf-6f45-4bab-8b2c-800433e4d1da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046363306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_ctrl_intersig_mubi.4046363306
Directory	/workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_peri.667423086
Short name	T703
Test name
Test status
Simulation time	39110062 ps
CPU time	0.85 seconds
Started	Jul 18 06:43:41 PM PDT 24
Finished	Jul 18 06:43:48 PM PDT 24
Peak memory	201040 kb
Host	smart-79417aef-c351-4314-9069-60d3049ab132
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667423086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.667423086
Directory	/workspace/40.clkmgr_peri/latest

Test location	/workspace/coverage/default/40.clkmgr_regwen.816643005
Short name	T532
Test name
Test status
Simulation time	585166088 ps
CPU time	2.55 seconds
Started	Jul 18 06:43:45 PM PDT 24
Finished	Jul 18 06:43:54 PM PDT 24
Peak memory	201096 kb
Host	smart-bb8630b7-22c0-44fc-942b-9aaa9807dc78
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816643005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.816643005
Directory	/workspace/40.clkmgr_regwen/latest

Test location	/workspace/coverage/default/40.clkmgr_smoke.1507495902
Short name	T772
Test name
Test status
Simulation time	97237259 ps
CPU time	1.04 seconds
Started	Jul 18 06:43:51 PM PDT 24
Finished	Jul 18 06:43:55 PM PDT 24
Peak memory	200968 kb
Host	smart-e03eb256-b7ba-4a07-b9af-9a4993100231
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507495902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.1507495902
Directory	/workspace/40.clkmgr_smoke/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all.3758060932
Short name	T464
Test name
Test status
Simulation time	6048585026 ps
CPU time	33.03 seconds
Started	Jul 18 06:43:49 PM PDT 24
Finished	Jul 18 06:44:26 PM PDT 24
Peak memory	201476 kb
Host	smart-f78403fc-c3c6-484f-811f-dbbe8a84efc8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758060932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.3758060932
Directory	/workspace/40.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.3874360276
Short name	T832
Test name
Test status
Simulation time	66509570735 ps
CPU time	586.99 seconds
Started	Jul 18 06:43:48 PM PDT 24
Finished	Jul 18 06:53:40 PM PDT 24
Peak memory	211220 kb
Host	smart-1e9056a9-2bcb-4483-8251-9868fce87046
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3874360276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.3874360276
Directory	/workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.clkmgr_trans.3035105581
Short name	T817
Test name
Test status
Simulation time	21465263 ps
CPU time	0.8 seconds
Started	Jul 18 06:43:46 PM PDT 24
Finished	Jul 18 06:43:53 PM PDT 24
Peak memory	201068 kb
Host	smart-a0d3da79-05d7-4897-8661-e7133ff70354
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035105581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3035105581
Directory	/workspace/40.clkmgr_trans/latest

Test location	/workspace/coverage/default/41.clkmgr_alert_test.614974391
Short name	T375
Test name
Test status
Simulation time	27271568 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:50 PM PDT 24
Finished	Jul 18 06:43:55 PM PDT 24
Peak memory	201208 kb
Host	smart-6d3c9f18-535c-4187-ac56-13e567e01fd6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614974391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkm gr_alert_test.614974391
Directory	/workspace/41.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1635705682
Short name	T195
Test name
Test status
Simulation time	15849088 ps
CPU time	0.77 seconds
Started	Jul 18 06:43:50 PM PDT 24
Finished	Jul 18 06:43:55 PM PDT 24
Peak memory	201084 kb
Host	smart-66218006-c657-4d13-b50c-4efead666ae4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635705682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.1635705682
Directory	/workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_status.1709984941
Short name	T358
Test name
Test status
Simulation time	14980626 ps
CPU time	0.7 seconds
Started	Jul 18 06:43:59 PM PDT 24
Finished	Jul 18 06:44:07 PM PDT 24
Peak memory	200648 kb
Host	smart-3d4f0062-b9e3-4e7c-9760-aaaca2ee624a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709984941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.1709984941
Directory	/workspace/41.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/41.clkmgr_div_intersig_mubi.4031408207
Short name	T573
Test name
Test status
Simulation time	52808405 ps
CPU time	0.88 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:12 PM PDT 24
Peak memory	201072 kb
Host	smart-377acaa1-ac38-4d94-9015-11dedeb06a25
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031408207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.4031408207
Directory	/workspace/41.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_extclk.4055196347
Short name	T465
Test name
Test status
Simulation time	26171105 ps
CPU time	0.89 seconds
Started	Jul 18 06:43:54 PM PDT 24
Finished	Jul 18 06:43:58 PM PDT 24
Peak memory	201084 kb
Host	smart-09121b48-cfb5-4579-9521-69e62dfe7293
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055196347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.4055196347
Directory	/workspace/41.clkmgr_extclk/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency.1356278329
Short name	T296
Test name
Test status
Simulation time	1515975735 ps
CPU time	11.57 seconds
Started	Jul 18 06:43:54 PM PDT 24
Finished	Jul 18 06:44:09 PM PDT 24
Peak memory	201176 kb
Host	smart-a3203514-37de-4023-bb76-3766a180c626
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356278329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1356278329
Directory	/workspace/41.clkmgr_frequency/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency_timeout.3070248767
Short name	T429
Test name
Test status
Simulation time	2298605175 ps
CPU time	11.77 seconds
Started	Jul 18 06:43:50 PM PDT 24
Finished	Jul 18 06:44:06 PM PDT 24
Peak memory	201512 kb
Host	smart-444c3a53-33cf-4358-b7d0-3fee453a1a63
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070248767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t imeout.3070248767
Directory	/workspace/41.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1936557781
Short name	T312
Test name
Test status
Simulation time	15729994 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:54 PM PDT 24
Finished	Jul 18 06:43:58 PM PDT 24
Peak memory	201088 kb
Host	smart-1083669b-0def-467f-be9e-d049864ba44b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936557781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.1936557781
Directory	/workspace/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3062658307
Short name	T801
Test name
Test status
Simulation time	37965208 ps
CPU time	0.89 seconds
Started	Jul 18 06:43:56 PM PDT 24
Finished	Jul 18 06:44:00 PM PDT 24
Peak memory	201100 kb
Host	smart-2cb95df2-5765-4786-a9b2-74b82fc0b1bc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062658307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3062658307
Directory	/workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3663489970
Short name	T430
Test name
Test status
Simulation time	101241020 ps
CPU time	1 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201104 kb
Host	smart-832b1462-95c2-428b-8558-0f20fa93ab4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663489970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_ctrl_intersig_mubi.3663489970
Directory	/workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_peri.3124927690
Short name	T307
Test name
Test status
Simulation time	28785470 ps
CPU time	0.75 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:03 PM PDT 24
Peak memory	201092 kb
Host	smart-0b8ac7ae-125e-4b90-b75f-57f63ccbce2d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124927690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3124927690
Directory	/workspace/41.clkmgr_peri/latest

Test location	/workspace/coverage/default/41.clkmgr_regwen.3722138651
Short name	T626
Test name
Test status
Simulation time	451405438 ps
CPU time	3.1 seconds
Started	Jul 18 06:43:54 PM PDT 24
Finished	Jul 18 06:44:01 PM PDT 24
Peak memory	201260 kb
Host	smart-a6446081-7d7e-4c09-a0f7-f030c233f2ce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722138651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3722138651
Directory	/workspace/41.clkmgr_regwen/latest

Test location	/workspace/coverage/default/41.clkmgr_smoke.3162110888
Short name	T371
Test name
Test status
Simulation time	18134400 ps
CPU time	0.86 seconds
Started	Jul 18 06:43:52 PM PDT 24
Finished	Jul 18 06:43:56 PM PDT 24
Peak memory	201016 kb
Host	smart-90473852-9bbd-4d8e-8ac4-c17a24a70eb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162110888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.3162110888
Directory	/workspace/41.clkmgr_smoke/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all.4234019608
Short name	T733
Test name
Test status
Simulation time	851825187 ps
CPU time	5.24 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:06 PM PDT 24
Peak memory	201224 kb
Host	smart-2c70e0a0-059c-4fe1-97ce-ad897ea55f39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234019608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.4234019608
Directory	/workspace/41.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.1845414105
Short name	T729
Test name
Test status
Simulation time	35576099910 ps
CPU time	538.33 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:53:00 PM PDT 24
Peak memory	217932 kb
Host	smart-2420270e-ada1-4e1e-a5bd-f0e45400a4a9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1845414105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.1845414105
Directory	/workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.clkmgr_trans.3704461832
Short name	T491
Test name
Test status
Simulation time	141933982 ps
CPU time	1.34 seconds
Started	Jul 18 06:44:01 PM PDT 24
Finished	Jul 18 06:44:11 PM PDT 24
Peak memory	201084 kb
Host	smart-3063f021-6d00-48dc-8530-56fcfc5b593f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704461832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.3704461832
Directory	/workspace/41.clkmgr_trans/latest

Test location	/workspace/coverage/default/42.clkmgr_alert_test.3251466022
Short name	T332
Test name
Test status
Simulation time	12976343 ps
CPU time	0.71 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201212 kb
Host	smart-f007378f-0a99-462a-bb27-0683ff0fce62
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251466022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.3251466022
Directory	/workspace/42.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.4106930380
Short name	T723
Test name
Test status
Simulation time	28273681 ps
CPU time	0.98 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201128 kb
Host	smart-cd4ba83e-b8d4-4b73-8dc7-18341ed36f20
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106930380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.4106930380
Directory	/workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_status.2035563193
Short name	T25
Test name
Test status
Simulation time	110612267 ps
CPU time	0.96 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:02 PM PDT 24
Peak memory	201076 kb
Host	smart-3aa855aa-816d-4ec5-8ee6-7ea69bdf4c97
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035563193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2035563193
Directory	/workspace/42.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/42.clkmgr_div_intersig_mubi.3397142123
Short name	T316
Test name
Test status
Simulation time	37704505 ps
CPU time	0.82 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201096 kb
Host	smart-c9a2d4ad-5533-4c43-897a-9d7cf488e242
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397142123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.3397142123
Directory	/workspace/42.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_extclk.1958610634
Short name	T720
Test name
Test status
Simulation time	255006258 ps
CPU time	1.57 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:02 PM PDT 24
Peak memory	201188 kb
Host	smart-67cf5596-a676-4a17-b718-819d8bee026a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958610634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1958610634
Directory	/workspace/42.clkmgr_extclk/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency.2019014217
Short name	T810
Test name
Test status
Simulation time	210148044 ps
CPU time	1.66 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201172 kb
Host	smart-5abe869f-c48a-433a-8592-19c7e9e867a7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019014217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.2019014217
Directory	/workspace/42.clkmgr_frequency/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency_timeout.2976587182
Short name	T340
Test name
Test status
Simulation time	436362353 ps
CPU time	2.15 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201300 kb
Host	smart-d67da15b-7b30-4e53-94ca-9bddd2b3d9f2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976587182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t imeout.2976587182
Directory	/workspace/42.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/42.clkmgr_idle_intersig_mubi.740245190
Short name	T849
Test name
Test status
Simulation time	44227599 ps
CPU time	1.05 seconds
Started	Jul 18 06:44:00 PM PDT 24
Finished	Jul 18 06:44:08 PM PDT 24
Peak memory	201052 kb
Host	smart-c30fd517-20c1-4e0a-a494-1735e9e9904b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740245190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.clkmgr_idle_intersig_mubi.740245190
Directory	/workspace/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.790881631
Short name	T97
Test name
Test status
Simulation time	35126855 ps
CPU time	0.93 seconds
Started	Jul 18 06:43:59 PM PDT 24
Finished	Jul 18 06:44:07 PM PDT 24
Peak memory	201108 kb
Host	smart-89188a66-4daf-4f5c-9239-f0661d95739f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790881631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.clkmgr_lc_clk_byp_req_intersig_mubi.790881631
Directory	/workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.963293391
Short name	T486
Test name
Test status
Simulation time	60634119 ps
CPU time	0.93 seconds
Started	Jul 18 06:43:59 PM PDT 24
Finished	Jul 18 06:44:07 PM PDT 24
Peak memory	200800 kb
Host	smart-648fa60d-cb36-4475-b1d9-3ef49e907a86
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963293391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.clkmgr_lc_ctrl_intersig_mubi.963293391
Directory	/workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_peri.4169187375
Short name	T328
Test name
Test status
Simulation time	13238771 ps
CPU time	0.71 seconds
Started	Jul 18 06:43:56 PM PDT 24
Finished	Jul 18 06:44:00 PM PDT 24
Peak memory	200996 kb
Host	smart-a130a1e4-bd19-41a0-8e1a-ecc75d206968
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169187375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.4169187375
Directory	/workspace/42.clkmgr_peri/latest

Test location	/workspace/coverage/default/42.clkmgr_regwen.1180220962
Short name	T165
Test name
Test status
Simulation time	750466495 ps
CPU time	4.53 seconds
Started	Jul 18 06:44:00 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201268 kb
Host	smart-1df5e5af-397d-4532-81d4-7b421d3f6a91
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180220962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1180220962
Directory	/workspace/42.clkmgr_regwen/latest

Test location	/workspace/coverage/default/42.clkmgr_smoke.1315903247
Short name	T497
Test name
Test status
Simulation time	17280976 ps
CPU time	0.82 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:02 PM PDT 24
Peak memory	201056 kb
Host	smart-9c917204-5d70-49ce-8225-c5cd40276dce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315903247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1315903247
Directory	/workspace/42.clkmgr_smoke/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all.2139096830
Short name	T823
Test name
Test status
Simulation time	2008594942 ps
CPU time	15.37 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:19 PM PDT 24
Peak memory	201360 kb
Host	smart-3da1e022-1975-4ec0-b034-66a8157435d0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139096830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.2139096830
Directory	/workspace/42.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.2996933122
Short name	T291
Test name
Test status
Simulation time	166402523658 ps
CPU time	1208.27 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 07:04:11 PM PDT 24
Peak memory	216552 kb
Host	smart-cc4c9213-c896-4556-9865-cade27900704
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2996933122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.2996933122
Directory	/workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.clkmgr_trans.1866907432
Short name	T388
Test name
Test status
Simulation time	280351043 ps
CPU time	1.75 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:06 PM PDT 24
Peak memory	201120 kb
Host	smart-2b7181fc-e790-4a02-86ed-290f6edf4ffd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866907432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1866907432
Directory	/workspace/42.clkmgr_trans/latest

Test location	/workspace/coverage/default/43.clkmgr_alert_test.4053903773
Short name	T837
Test name
Test status
Simulation time	43036858 ps
CPU time	0.82 seconds
Started	Jul 18 06:44:04 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201224 kb
Host	smart-62fc8942-94fd-45c2-80ea-db6d8472b65f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053903773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.4053903773
Directory	/workspace/43.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3935428528
Short name	T584
Test name
Test status
Simulation time	30278141 ps
CPU time	0.83 seconds
Started	Jul 18 06:44:06 PM PDT 24
Finished	Jul 18 06:44:16 PM PDT 24
Peak memory	201100 kb
Host	smart-80c4bb66-df80-4ba2-b18a-9d95ced42cf8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935428528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.3935428528
Directory	/workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_status.792263572
Short name	T308
Test name
Test status
Simulation time	14924053 ps
CPU time	0.73 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	200260 kb
Host	smart-4654304c-2096-4751-a555-df805c6cf1a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792263572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.792263572
Directory	/workspace/43.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/43.clkmgr_div_intersig_mubi.430191870
Short name	T217
Test name
Test status
Simulation time	48919200 ps
CPU time	0.98 seconds
Started	Jul 18 06:44:04 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201108 kb
Host	smart-063fab8f-7a64-4225-bacb-c4fb50e5d218
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430191870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.clkmgr_div_intersig_mubi.430191870
Directory	/workspace/43.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_extclk.2971923132
Short name	T262
Test name
Test status
Simulation time	17159176 ps
CPU time	0.77 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:04 PM PDT 24
Peak memory	201080 kb
Host	smart-9d577ddc-e4d6-4380-b088-9b5db5f4c5af
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971923132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2971923132
Directory	/workspace/43.clkmgr_extclk/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency.1772512816
Short name	T717
Test name
Test status
Simulation time	561751313 ps
CPU time	4.54 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:17 PM PDT 24
Peak memory	201148 kb
Host	smart-b4682f2a-06e8-4711-9a19-adca64fbef8b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772512816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1772512816
Directory	/workspace/43.clkmgr_frequency/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency_timeout.997642423
Short name	T407
Test name
Test status
Simulation time	2063107157 ps
CPU time	10.71 seconds
Started	Jul 18 06:44:08 PM PDT 24
Finished	Jul 18 06:44:27 PM PDT 24
Peak memory	201416 kb
Host	smart-b5494694-7f85-4c81-89bf-685e568a36a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997642423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_ti meout.997642423
Directory	/workspace/43.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/43.clkmgr_idle_intersig_mubi.3407712753
Short name	T737
Test name
Test status
Simulation time	390878214 ps
CPU time	2.07 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:06 PM PDT 24
Peak memory	201088 kb
Host	smart-40dc9574-55da-4a1f-8db4-dbbe21d78239
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407712753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.3407712753
Directory	/workspace/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.589589284
Short name	T718
Test name
Test status
Simulation time	22619277 ps
CPU time	0.86 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201100 kb
Host	smart-be149dac-a04e-4267-ae86-41ed8f6e1774
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589589284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.clkmgr_lc_clk_byp_req_intersig_mubi.589589284
Directory	/workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.1627067
Short name	T758
Test name
Test status
Simulation time	86730866 ps
CPU time	1.09 seconds
Started	Jul 18 06:44:08 PM PDT 24
Finished	Jul 18 06:44:17 PM PDT 24
Peak memory	201100 kb
Host	smart-fb6abb23-c4e4-4dcb-b49a-8f1da8e99f5d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.1627067
Directory	/workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_peri.3130505375
Short name	T754
Test name
Test status
Simulation time	17873267 ps
CPU time	0.78 seconds
Started	Jul 18 06:44:05 PM PDT 24
Finished	Jul 18 06:44:15 PM PDT 24
Peak memory	201044 kb
Host	smart-a538b272-8665-48b1-9e64-a36354bbe47f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130505375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3130505375
Directory	/workspace/43.clkmgr_peri/latest

Test location	/workspace/coverage/default/43.clkmgr_regwen.49862977
Short name	T766
Test name
Test status
Simulation time	936667742 ps
CPU time	5.68 seconds
Started	Jul 18 06:43:55 PM PDT 24
Finished	Jul 18 06:44:04 PM PDT 24
Peak memory	201288 kb
Host	smart-ad524187-daff-45b8-862a-15e501d5be01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49862977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.49862977
Directory	/workspace/43.clkmgr_regwen/latest

Test location	/workspace/coverage/default/43.clkmgr_smoke.3936096370
Short name	T232
Test name
Test status
Simulation time	30968130 ps
CPU time	0.85 seconds
Started	Jul 18 06:43:59 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201032 kb
Host	smart-02160ca0-afc5-47c0-b8da-467a4f5b0590
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936096370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3936096370
Directory	/workspace/43.clkmgr_smoke/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all.2949185470
Short name	T373
Test name
Test status
Simulation time	3270622530 ps
CPU time	24.64 seconds
Started	Jul 18 06:44:06 PM PDT 24
Finished	Jul 18 06:44:40 PM PDT 24
Peak memory	201492 kb
Host	smart-3e221980-a139-474b-9c53-0f8482015cf8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949185470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.2949185470
Directory	/workspace/43.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.1618163918
Short name	T779
Test name
Test status
Simulation time	59712852163 ps
CPU time	529.24 seconds
Started	Jul 18 06:43:55 PM PDT 24
Finished	Jul 18 06:52:48 PM PDT 24
Peak memory	209700 kb
Host	smart-9ac28542-9c3b-470b-869f-ec2359553987
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1618163918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1618163918
Directory	/workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.clkmgr_trans.2027106110
Short name	T578
Test name
Test status
Simulation time	106078458 ps
CPU time	1.1 seconds
Started	Jul 18 06:44:04 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201092 kb
Host	smart-63f654aa-8ce0-417c-af2c-498357bf736a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027106110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2027106110
Directory	/workspace/43.clkmgr_trans/latest

Test location	/workspace/coverage/default/44.clkmgr_alert_test.172036501
Short name	T325
Test name
Test status
Simulation time	19876462 ps
CPU time	0.84 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:02 PM PDT 24
Peak memory	201316 kb
Host	smart-b9467f61-c808-41d4-9844-12faef0659f6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172036501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkm gr_alert_test.172036501
Directory	/workspace/44.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2394113244
Short name	T642
Test name
Test status
Simulation time	59796902 ps
CPU time	0.9 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201100 kb
Host	smart-87b16a48-4354-4af7-9584-389fd1962dfc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394113244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.2394113244
Directory	/workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_status.3024229212
Short name	T61
Test name
Test status
Simulation time	29981883 ps
CPU time	0.74 seconds
Started	Jul 18 06:44:00 PM PDT 24
Finished	Jul 18 06:44:09 PM PDT 24
Peak memory	200312 kb
Host	smart-7fef07c3-4f20-45cc-ab83-88f025043d77
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024229212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3024229212
Directory	/workspace/44.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/44.clkmgr_div_intersig_mubi.2814041718
Short name	T302
Test name
Test status
Simulation time	53236265 ps
CPU time	0.91 seconds
Started	Jul 18 06:43:54 PM PDT 24
Finished	Jul 18 06:43:58 PM PDT 24
Peak memory	201256 kb
Host	smart-0930ffa9-c489-4776-96d8-ad431df8c6e8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814041718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.2814041718
Directory	/workspace/44.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_extclk.247961654
Short name	T534
Test name
Test status
Simulation time	23512653 ps
CPU time	0.87 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201068 kb
Host	smart-556e9675-df6d-4af2-ac4f-d042ca94697b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247961654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.247961654
Directory	/workspace/44.clkmgr_extclk/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency.3724369423
Short name	T659
Test name
Test status
Simulation time	939002376 ps
CPU time	4.6 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:06 PM PDT 24
Peak memory	201152 kb
Host	smart-12cd1a52-47de-4918-8c77-dddf9a204293
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724369423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.3724369423
Directory	/workspace/44.clkmgr_frequency/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency_timeout.1166949634
Short name	T370
Test name
Test status
Simulation time	497661763 ps
CPU time	3.93 seconds
Started	Jul 18 06:44:01 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201252 kb
Host	smart-25f413bc-3b07-4e00-88c5-6d0c5f270eca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166949634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.1166949634
Directory	/workspace/44.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.2498646450
Short name	T666
Test name
Test status
Simulation time	27971010 ps
CPU time	0.94 seconds
Started	Jul 18 06:44:04 PM PDT 24
Finished	Jul 18 06:44:14 PM PDT 24
Peak memory	201104 kb
Host	smart-767f052c-0945-4517-93b9-ed3ca3812326
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498646450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.2498646450
Directory	/workspace/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1669580419
Short name	T619
Test name
Test status
Simulation time	41975426 ps
CPU time	0.88 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:12 PM PDT 24
Peak memory	201084 kb
Host	smart-02875760-a935-4519-8a3c-3bd53c3e48a7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669580419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1669580419
Directory	/workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.979072712
Short name	T786
Test name
Test status
Simulation time	36740883 ps
CPU time	0.77 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201076 kb
Host	smart-895d578b-f30f-4fed-bf04-ef99cab7837a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979072712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.clkmgr_lc_ctrl_intersig_mubi.979072712
Directory	/workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_peri.3236297739
Short name	T337
Test name
Test status
Simulation time	218526571 ps
CPU time	1.32 seconds
Started	Jul 18 06:44:00 PM PDT 24
Finished	Jul 18 06:44:10 PM PDT 24
Peak memory	201052 kb
Host	smart-d417f1d1-9106-4246-bbf3-223535ed6bbb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236297739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3236297739
Directory	/workspace/44.clkmgr_peri/latest

Test location	/workspace/coverage/default/44.clkmgr_regwen.1074329862
Short name	T374
Test name
Test status
Simulation time	264884033 ps
CPU time	1.58 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	201040 kb
Host	smart-69bcbc22-08e8-4fa0-ab5b-f53c71926b35
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074329862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1074329862
Directory	/workspace/44.clkmgr_regwen/latest

Test location	/workspace/coverage/default/44.clkmgr_smoke.3259719173
Short name	T359
Test name
Test status
Simulation time	22842356 ps
CPU time	0.88 seconds
Started	Jul 18 06:44:08 PM PDT 24
Finished	Jul 18 06:44:17 PM PDT 24
Peak memory	201056 kb
Host	smart-7bcaf077-9153-4652-b301-de9c60888832
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259719173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3259719173
Directory	/workspace/44.clkmgr_smoke/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all.429546703
Short name	T752
Test name
Test status
Simulation time	9027660859 ps
CPU time	36.82 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:39 PM PDT 24
Peak memory	201472 kb
Host	smart-c5b131fe-6375-40bf-8367-8cb1bcd7e703
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429546703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.429546703
Directory	/workspace/44.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.3063510724
Short name	T830
Test name
Test status
Simulation time	52000495157 ps
CPU time	303.37 seconds
Started	Jul 18 06:43:56 PM PDT 24
Finished	Jul 18 06:49:04 PM PDT 24
Peak memory	209784 kb
Host	smart-dc1c2edd-c5d2-432c-8978-607167177cdc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3063510724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.3063510724
Directory	/workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.clkmgr_trans.1381864963
Short name	T255
Test name
Test status
Simulation time	126359643 ps
CPU time	1.23 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:02 PM PDT 24
Peak memory	201092 kb
Host	smart-aed32a32-4af4-4e93-a514-26a8609589d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381864963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1381864963
Directory	/workspace/44.clkmgr_trans/latest

Test location	/workspace/coverage/default/45.clkmgr_alert_test.3847731411
Short name	T476
Test name
Test status
Simulation time	23833732 ps
CPU time	0.73 seconds
Started	Jul 18 06:44:09 PM PDT 24
Finished	Jul 18 06:44:18 PM PDT 24
Peak memory	201228 kb
Host	smart-c870bab3-83cc-4a27-9414-696fa27515f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847731411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk mgr_alert_test.3847731411
Directory	/workspace/45.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.766401933
Short name	T684
Test name
Test status
Simulation time	44798636 ps
CPU time	0.99 seconds
Started	Jul 18 06:44:02 PM PDT 24
Finished	Jul 18 06:44:12 PM PDT 24
Peak memory	201068 kb
Host	smart-d87bf8a8-49e3-4dad-9215-60d111fcf22b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766401933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.766401933
Directory	/workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_status.1560256137
Short name	T707
Test name
Test status
Simulation time	15326299 ps
CPU time	0.76 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:44:04 PM PDT 24
Peak memory	200372 kb
Host	smart-edfdd56a-6a25-4758-b73b-936fd4742f04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560256137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1560256137
Directory	/workspace/45.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/45.clkmgr_div_intersig_mubi.3586978969
Short name	T349
Test name
Test status
Simulation time	28193585 ps
CPU time	0.79 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201068 kb
Host	smart-5a38f391-199e-4a01-9a95-2d4af452769f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586978969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.3586978969
Directory	/workspace/45.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_extclk.2676183163
Short name	T193
Test name
Test status
Simulation time	21631570 ps
CPU time	0.73 seconds
Started	Jul 18 06:43:56 PM PDT 24
Finished	Jul 18 06:44:01 PM PDT 24
Peak memory	201184 kb
Host	smart-83484e66-3645-46f5-aea3-e51f5da0c29c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676183163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2676183163
Directory	/workspace/45.clkmgr_extclk/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency.1478232343
Short name	T615
Test name
Test status
Simulation time	2244137825 ps
CPU time	10.1 seconds
Started	Jul 18 06:43:59 PM PDT 24
Finished	Jul 18 06:44:16 PM PDT 24
Peak memory	201452 kb
Host	smart-16d23951-8282-4f6e-8d7d-5b128399e320
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478232343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1478232343
Directory	/workspace/45.clkmgr_frequency/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency_timeout.4008499872
Short name	T523
Test name
Test status
Simulation time	744243356 ps
CPU time	4.09 seconds
Started	Jul 18 06:43:59 PM PDT 24
Finished	Jul 18 06:44:09 PM PDT 24
Peak memory	201192 kb
Host	smart-20346d21-7f09-40a5-a3f9-e84bb3fb6fdd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008499872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t imeout.4008499872
Directory	/workspace/45.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_idle_intersig_mubi.4287884445
Short name	T250
Test name
Test status
Simulation time	64999167 ps
CPU time	0.96 seconds
Started	Jul 18 06:44:01 PM PDT 24
Finished	Jul 18 06:44:11 PM PDT 24
Peak memory	201100 kb
Host	smart-639b13bf-d573-4cf3-a2d5-7a7b05c15b44
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287884445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.4287884445
Directory	/workspace/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1181630519
Short name	T265
Test name
Test status
Simulation time	41215375 ps
CPU time	0.92 seconds
Started	Jul 18 06:44:03 PM PDT 24
Finished	Jul 18 06:44:13 PM PDT 24
Peak memory	201088 kb
Host	smart-20b19d11-08f0-4b3a-b33b-1fb96bf935f2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181630519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1181630519
Directory	/workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1216676323
Short name	T482
Test name
Test status
Simulation time	27170851 ps
CPU time	0.87 seconds
Started	Jul 18 06:43:56 PM PDT 24
Finished	Jul 18 06:44:01 PM PDT 24
Peak memory	201196 kb
Host	smart-11d9d02d-05f5-4b33-adeb-18d53035cb33
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216676323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_ctrl_intersig_mubi.1216676323
Directory	/workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_peri.1871588288
Short name	T224
Test name
Test status
Simulation time	16925397 ps
CPU time	0.8 seconds
Started	Jul 18 06:44:01 PM PDT 24
Finished	Jul 18 06:44:10 PM PDT 24
Peak memory	201028 kb
Host	smart-22b6449f-2c84-4cc8-a12c-369861eaef8f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871588288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1871588288
Directory	/workspace/45.clkmgr_peri/latest

Test location	/workspace/coverage/default/45.clkmgr_regwen.187823464
Short name	T547
Test name
Test status
Simulation time	1227082146 ps
CPU time	7.11 seconds
Started	Jul 18 06:44:00 PM PDT 24
Finished	Jul 18 06:44:15 PM PDT 24
Peak memory	201292 kb
Host	smart-33fed7af-7348-47cf-b323-14cc0631eca3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187823464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.187823464
Directory	/workspace/45.clkmgr_regwen/latest

Test location	/workspace/coverage/default/45.clkmgr_smoke.3611556226
Short name	T366
Test name
Test status
Simulation time	68959814 ps
CPU time	0.98 seconds
Started	Jul 18 06:44:00 PM PDT 24
Finished	Jul 18 06:44:08 PM PDT 24
Peak memory	201056 kb
Host	smart-b75863fc-3775-451d-8dca-5f2511af28bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611556226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3611556226
Directory	/workspace/45.clkmgr_smoke/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all.4156112787
Short name	T277
Test name
Test status
Simulation time	1638168300 ps
CPU time	12.58 seconds
Started	Jul 18 06:44:10 PM PDT 24
Finished	Jul 18 06:44:30 PM PDT 24
Peak memory	201388 kb
Host	smart-8a7de227-a392-4dcb-984f-30cf2b3f21b0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156112787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.4156112787
Directory	/workspace/45.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.1900274892
Short name	T627
Test name
Test status
Simulation time	46886453221 ps
CPU time	460.85 seconds
Started	Jul 18 06:43:58 PM PDT 24
Finished	Jul 18 06:51:45 PM PDT 24
Peak memory	210192 kb
Host	smart-d3f7785f-a15d-41cf-9f8d-535240fb9a62
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1900274892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.1900274892
Directory	/workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.clkmgr_trans.2859286237
Short name	T306
Test name
Test status
Simulation time	152137738 ps
CPU time	1.26 seconds
Started	Jul 18 06:43:57 PM PDT 24
Finished	Jul 18 06:44:03 PM PDT 24
Peak memory	201172 kb
Host	smart-f517b281-9240-4a95-b6de-29db92debec8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859286237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2859286237
Directory	/workspace/45.clkmgr_trans/latest

Test location	/workspace/coverage/default/46.clkmgr_alert_test.1253392884
Short name	T450
Test name
Test status
Simulation time	21150017 ps
CPU time	0.73 seconds
Started	Jul 18 06:44:18 PM PDT 24
Finished	Jul 18 06:44:24 PM PDT 24
Peak memory	201228 kb
Host	smart-85389712-80e9-479b-b786-5db8529a952c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253392884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk mgr_alert_test.1253392884
Directory	/workspace/46.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.34231455
Short name	T575
Test name
Test status
Simulation time	57009766 ps
CPU time	0.93 seconds
Started	Jul 18 06:44:10 PM PDT 24
Finished	Jul 18 06:44:19 PM PDT 24
Peak memory	201092 kb
Host	smart-3cf1d640-bbda-428e-a036-6ffed4e5fb06
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34231455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.clkmgr_clk_handshake_intersig_mubi.34231455
Directory	/workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_status.1474772359
Short name	T699
Test name
Test status
Simulation time	18711492 ps
CPU time	0.76 seconds
Started	Jul 18 06:44:22 PM PDT 24
Finished	Jul 18 06:44:32 PM PDT 24
Peak memory	200988 kb
Host	smart-8dd45c92-e1e9-4081-b3af-9ba78e548834
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474772359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1474772359
Directory	/workspace/46.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/46.clkmgr_div_intersig_mubi.739802984
Short name	T320
Test name
Test status
Simulation time	14465383 ps
CPU time	0.77 seconds
Started	Jul 18 06:44:09 PM PDT 24
Finished	Jul 18 06:44:18 PM PDT 24
Peak memory	201284 kb
Host	smart-9383ff02-d059-4275-a3f8-5bbbf23fe048
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739802984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.clkmgr_div_intersig_mubi.739802984
Directory	/workspace/46.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_extclk.1374885794
Short name	T406
Test name
Test status
Simulation time	14806203 ps
CPU time	0.71 seconds
Started	Jul 18 06:44:09 PM PDT 24
Finished	Jul 18 06:44:18 PM PDT 24
Peak memory	200984 kb
Host	smart-80807ff0-3012-42b6-a9d6-616ea2f16296
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374885794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1374885794
Directory	/workspace/46.clkmgr_extclk/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency_timeout.120792044
Short name	T134
Test name
Test status
Simulation time	2189462753 ps
CPU time	11.01 seconds
Started	Jul 18 06:44:09 PM PDT 24
Finished	Jul 18 06:44:28 PM PDT 24
Peak memory	201464 kb
Host	smart-bd6f7af4-0447-48a9-ba48-84f440432aca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120792044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_ti meout.120792044
Directory	/workspace/46.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/46.clkmgr_idle_intersig_mubi.4281147977
Short name	T795
Test name
Test status
Simulation time	21168830 ps
CPU time	0.75 seconds
Started	Jul 18 06:44:08 PM PDT 24
Finished	Jul 18 06:44:17 PM PDT 24
Peak memory	201088 kb
Host	smart-d1090cb7-1bef-4d23-a073-dd12a0de92a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281147977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.4281147977
Directory	/workspace/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1641159573
Short name	T161
Test name
Test status
Simulation time	19286197 ps
CPU time	0.74 seconds
Started	Jul 18 06:44:11 PM PDT 24
Finished	Jul 18 06:44:19 PM PDT 24
Peak memory	201088 kb
Host	smart-7f22aa90-fd3d-4e14-af11-324cacf5f8ca
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641159573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1641159573
Directory	/workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3170413548
Short name	T852
Test name
Test status
Simulation time	77554574 ps
CPU time	1.02 seconds
Started	Jul 18 06:44:10 PM PDT 24
Finished	Jul 18 06:44:19 PM PDT 24
Peak memory	201104 kb
Host	smart-9866ed0a-2f00-4508-81b9-bcd52de254a5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170413548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_ctrl_intersig_mubi.3170413548
Directory	/workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_peri.3899325682
Short name	T526
Test name
Test status
Simulation time	41048906 ps
CPU time	0.81 seconds
Started	Jul 18 06:44:12 PM PDT 24
Finished	Jul 18 06:44:20 PM PDT 24
Peak memory	201084 kb
Host	smart-1e4ba1fb-1fcc-455c-8caf-702175caf186
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899325682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3899325682
Directory	/workspace/46.clkmgr_peri/latest

Test location	/workspace/coverage/default/46.clkmgr_regwen.1962911555
Short name	T415
Test name
Test status
Simulation time	1310717048 ps
CPU time	4.72 seconds
Started	Jul 18 06:44:22 PM PDT 24
Finished	Jul 18 06:44:36 PM PDT 24
Peak memory	201272 kb
Host	smart-91a15528-6eab-4d16-ad32-62a77026c01e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962911555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1962911555
Directory	/workspace/46.clkmgr_regwen/latest

Test location	/workspace/coverage/default/46.clkmgr_smoke.3866269013
Short name	T281
Test name
Test status
Simulation time	44549428 ps
CPU time	0.88 seconds
Started	Jul 18 06:44:12 PM PDT 24
Finished	Jul 18 06:44:20 PM PDT 24
Peak memory	201044 kb
Host	smart-ebb69500-3015-4e77-bf99-27cd0c0177ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866269013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3866269013
Directory	/workspace/46.clkmgr_smoke/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all.2945995288
Short name	T711
Test name
Test status
Simulation time	7280169817 ps
CPU time	29.28 seconds
Started	Jul 18 06:44:19 PM PDT 24
Finished	Jul 18 06:44:54 PM PDT 24
Peak memory	201444 kb
Host	smart-5f161605-fbea-4704-bed4-4e6d3c8ba40a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945995288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.2945995288
Directory	/workspace/46.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.3199544101
Short name	T822
Test name
Test status
Simulation time	441952778220 ps
CPU time	1809.37 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 07:14:38 PM PDT 24
Peak memory	217940 kb
Host	smart-bc6c3cf2-fafa-4634-9759-751ecda8c6be
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3199544101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.3199544101
Directory	/workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.clkmgr_trans.1842928219
Short name	T458
Test name
Test status
Simulation time	231767737 ps
CPU time	1.44 seconds
Started	Jul 18 06:44:08 PM PDT 24
Finished	Jul 18 06:44:18 PM PDT 24
Peak memory	201088 kb
Host	smart-de937fc0-c929-4e1a-bf6a-21238185e80f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842928219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1842928219
Directory	/workspace/46.clkmgr_trans/latest

Test location	/workspace/coverage/default/47.clkmgr_alert_test.1788285843
Short name	T800
Test name
Test status
Simulation time	78130983 ps
CPU time	0.94 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:30 PM PDT 24
Peak memory	201236 kb
Host	smart-27e1cc61-9105-4765-8236-2d3f92e165ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788285843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk mgr_alert_test.1788285843
Directory	/workspace/47.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.1009713479
Short name	T850
Test name
Test status
Simulation time	18390357 ps
CPU time	0.72 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:29 PM PDT 24
Peak memory	201096 kb
Host	smart-796fece7-9393-4c50-b7b9-dd10bf9217cc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009713479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.1009713479
Directory	/workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_status.939808968
Short name	T611
Test name
Test status
Simulation time	16977606 ps
CPU time	0.72 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:35 PM PDT 24
Peak memory	200248 kb
Host	smart-fe86a1aa-1ffd-4361-8257-58c062c2101d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939808968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.939808968
Directory	/workspace/47.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/47.clkmgr_div_intersig_mubi.2046164424
Short name	T505
Test name
Test status
Simulation time	47513878 ps
CPU time	0.83 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:28 PM PDT 24
Peak memory	201100 kb
Host	smart-5759922a-2214-41f7-8fb4-660c588574ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046164424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.2046164424
Directory	/workspace/47.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_extclk.1775533893
Short name	T177
Test name
Test status
Simulation time	26715194 ps
CPU time	0.77 seconds
Started	Jul 18 06:44:22 PM PDT 24
Finished	Jul 18 06:44:32 PM PDT 24
Peak memory	201092 kb
Host	smart-72e7f518-f6eb-403f-935d-731f7143127b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775533893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1775533893
Directory	/workspace/47.clkmgr_extclk/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency.2932693986
Short name	T478
Test name
Test status
Simulation time	1878401890 ps
CPU time	14.36 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:49 PM PDT 24
Peak memory	201312 kb
Host	smart-4b914b47-e049-4692-8766-00aa85365846
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932693986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2932693986
Directory	/workspace/47.clkmgr_frequency/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency_timeout.1669518271
Short name	T435
Test name
Test status
Simulation time	1713710607 ps
CPU time	7.26 seconds
Started	Jul 18 06:44:18 PM PDT 24
Finished	Jul 18 06:44:31 PM PDT 24
Peak memory	201208 kb
Host	smart-ec533eb5-6d02-460c-b991-c3467d91a0d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669518271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t imeout.1669518271
Directory	/workspace/47.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3088210792
Short name	T483
Test name
Test status
Simulation time	108357472 ps
CPU time	1.23 seconds
Started	Jul 18 06:44:22 PM PDT 24
Finished	Jul 18 06:44:33 PM PDT 24
Peak memory	201080 kb
Host	smart-b1f87b58-23c7-4906-b7b8-a59207a6e8dd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088210792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.3088210792
Directory	/workspace/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2142219544
Short name	T204
Test name
Test status
Simulation time	20520688 ps
CPU time	0.76 seconds
Started	Jul 18 06:44:18 PM PDT 24
Finished	Jul 18 06:44:25 PM PDT 24
Peak memory	201096 kb
Host	smart-8128bbc8-68eb-40dc-bf66-f5cc03851637
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142219544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2142219544
Directory	/workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1307730698
Short name	T209
Test name
Test status
Simulation time	19849198 ps
CPU time	0.81 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:29 PM PDT 24
Peak memory	201100 kb
Host	smart-a04caee0-9643-45a7-a3db-74957fac7461
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307730698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_ctrl_intersig_mubi.1307730698
Directory	/workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_peri.10618329
Short name	T539
Test name
Test status
Simulation time	18660539 ps
CPU time	0.77 seconds
Started	Jul 18 06:44:19 PM PDT 24
Finished	Jul 18 06:44:26 PM PDT 24
Peak memory	201068 kb
Host	smart-2f1f5577-f188-42ce-ac8a-7643d5c6f4b6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.10618329
Directory	/workspace/47.clkmgr_peri/latest

Test location	/workspace/coverage/default/47.clkmgr_regwen.666909823
Short name	T655
Test name
Test status
Simulation time	1413079294 ps
CPU time	4.96 seconds
Started	Jul 18 06:44:19 PM PDT 24
Finished	Jul 18 06:44:31 PM PDT 24
Peak memory	201244 kb
Host	smart-edee9c89-ae73-4046-a885-6dc140628b67
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666909823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.666909823
Directory	/workspace/47.clkmgr_regwen/latest

Test location	/workspace/coverage/default/47.clkmgr_smoke.1284885566
Short name	T806
Test name
Test status
Simulation time	18153511 ps
CPU time	0.82 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:29 PM PDT 24
Peak memory	200960 kb
Host	smart-7c52febe-882e-4335-8e07-2b9fadc80b90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284885566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1284885566
Directory	/workspace/47.clkmgr_smoke/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all.1572547770
Short name	T679
Test name
Test status
Simulation time	922464983 ps
CPU time	4.7 seconds
Started	Jul 18 06:44:19 PM PDT 24
Finished	Jul 18 06:44:30 PM PDT 24
Peak memory	201292 kb
Host	smart-90b5f395-7cac-44c0-9d35-a876eeee36a3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572547770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.1572547770
Directory	/workspace/47.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.2569901686
Short name	T170
Test name
Test status
Simulation time	23074193171 ps
CPU time	320.55 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:49:49 PM PDT 24
Peak memory	217980 kb
Host	smart-5c8c75a2-2ff9-4475-be9a-44f5469e6abd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2569901686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.2569901686
Directory	/workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.clkmgr_trans.3326868600
Short name	T327
Test name
Test status
Simulation time	55061583 ps
CPU time	0.9 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:29 PM PDT 24
Peak memory	201084 kb
Host	smart-b613f710-e8ab-4708-adea-32346109a9e2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326868600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3326868600
Directory	/workspace/47.clkmgr_trans/latest

Test location	/workspace/coverage/default/48.clkmgr_alert_test.3436519025
Short name	T604
Test name
Test status
Simulation time	43940317 ps
CPU time	0.85 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:35 PM PDT 24
Peak memory	201208 kb
Host	smart-41879a78-deba-4a1b-8e38-2f0404651df2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436519025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk mgr_alert_test.3436519025
Directory	/workspace/48.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.819963426
Short name	T540
Test name
Test status
Simulation time	102607239 ps
CPU time	1.1 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:35 PM PDT 24
Peak memory	201060 kb
Host	smart-43a1800c-3770-4d40-9f98-ba56091ca1e8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819963426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.819963426
Directory	/workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_status.848558896
Short name	T180
Test name
Test status
Simulation time	31773740 ps
CPU time	0.78 seconds
Started	Jul 18 06:44:22 PM PDT 24
Finished	Jul 18 06:44:32 PM PDT 24
Peak memory	200476 kb
Host	smart-0befa849-ab13-4247-afce-f0bb08583195
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848558896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.848558896
Directory	/workspace/48.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/48.clkmgr_div_intersig_mubi.775402354
Short name	T206
Test name
Test status
Simulation time	96336476 ps
CPU time	1.12 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:36 PM PDT 24
Peak memory	201104 kb
Host	smart-22c5519b-3a3d-4412-bb1e-28b565c819e9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775402354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.clkmgr_div_intersig_mubi.775402354
Directory	/workspace/48.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_extclk.2938358286
Short name	T315
Test name
Test status
Simulation time	37996445 ps
CPU time	0.97 seconds
Started	Jul 18 06:44:23 PM PDT 24
Finished	Jul 18 06:44:34 PM PDT 24
Peak memory	201076 kb
Host	smart-91573672-93c9-4877-bb0f-deab4d2f649d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938358286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2938358286
Directory	/workspace/48.clkmgr_extclk/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency.276232799
Short name	T425
Test name
Test status
Simulation time	1640178983 ps
CPU time	12.1 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:40 PM PDT 24
Peak memory	201160 kb
Host	smart-6aef96b9-0199-4432-ba4f-cc5d9f25957d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276232799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.276232799
Directory	/workspace/48.clkmgr_frequency/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency_timeout.1820496622
Short name	T202
Test name
Test status
Simulation time	412430287 ps
CPU time	2.12 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:28 PM PDT 24
Peak memory	201224 kb
Host	smart-32ee29b2-d7ec-4a35-bdad-3806d6a073f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820496622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.1820496622
Directory	/workspace/48.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1531061776
Short name	T382
Test name
Test status
Simulation time	95827784 ps
CPU time	1.12 seconds
Started	Jul 18 06:44:19 PM PDT 24
Finished	Jul 18 06:44:27 PM PDT 24
Peak memory	201096 kb
Host	smart-1375ff32-70e2-4920-ae10-5309f31fc333
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531061776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.1531061776
Directory	/workspace/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3909180827
Short name	T728
Test name
Test status
Simulation time	16423785 ps
CPU time	0.81 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:35 PM PDT 24
Peak memory	201088 kb
Host	smart-844c7d56-e3bb-42fe-970a-73fed3f3d62c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909180827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3909180827
Directory	/workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2722369679
Short name	T712
Test name
Test status
Simulation time	26062047 ps
CPU time	0.93 seconds
Started	Jul 18 06:44:19 PM PDT 24
Finished	Jul 18 06:44:27 PM PDT 24
Peak memory	201096 kb
Host	smart-60c3345e-4f66-4751-ad40-106d7c18138c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722369679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_ctrl_intersig_mubi.2722369679
Directory	/workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_peri.2703782999
Short name	T207
Test name
Test status
Simulation time	16265915 ps
CPU time	0.75 seconds
Started	Jul 18 06:44:21 PM PDT 24
Finished	Jul 18 06:44:32 PM PDT 24
Peak memory	201016 kb
Host	smart-ff5156e5-ff2e-4559-bc77-1dcb772eb2c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703782999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2703782999
Directory	/workspace/48.clkmgr_peri/latest

Test location	/workspace/coverage/default/48.clkmgr_regwen.2526261173
Short name	T339
Test name
Test status
Simulation time	1153177368 ps
CPU time	4.46 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:39 PM PDT 24
Peak memory	201264 kb
Host	smart-954332dd-3e28-4578-9579-e2652ab195c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526261173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2526261173
Directory	/workspace/48.clkmgr_regwen/latest

Test location	/workspace/coverage/default/48.clkmgr_smoke.3271884652
Short name	T632
Test name
Test status
Simulation time	311668466 ps
CPU time	1.7 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:30 PM PDT 24
Peak memory	201056 kb
Host	smart-8ed940c0-0f22-4b9f-b38c-2b59b33f2b97
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271884652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.3271884652
Directory	/workspace/48.clkmgr_smoke/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all.74830834
Short name	T151
Test name
Test status
Simulation time	6488376299 ps
CPU time	26.27 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:45:01 PM PDT 24
Peak memory	201440 kb
Host	smart-01522664-bc6e-47fa-8987-15d518125a90
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74830834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.clkmgr_stress_all.74830834
Directory	/workspace/48.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.2154193845
Short name	T59
Test name
Test status
Simulation time	19261427227 ps
CPU time	374.08 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:50:42 PM PDT 24
Peak memory	209800 kb
Host	smart-89c73c60-bbac-44b3-ad67-0a554d8978ad
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2154193845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2154193845
Directory	/workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.clkmgr_trans.1629069803
Short name	T734
Test name
Test status
Simulation time	68710896 ps
CPU time	0.91 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:36 PM PDT 24
Peak memory	201068 kb
Host	smart-386bea8f-a467-4075-8391-551c2436a970
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629069803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1629069803
Directory	/workspace/48.clkmgr_trans/latest

Test location	/workspace/coverage/default/49.clkmgr_alert_test.2002695104
Short name	T33
Test name
Test status
Simulation time	18279441 ps
CPU time	0.76 seconds
Started	Jul 18 06:44:27 PM PDT 24
Finished	Jul 18 06:44:38 PM PDT 24
Peak memory	201224 kb
Host	smart-7d597050-1055-46b3-884e-29b5bcb6e4a1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002695104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk mgr_alert_test.2002695104
Directory	/workspace/49.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.536099387
Short name	T400
Test name
Test status
Simulation time	24903381 ps
CPU time	0.91 seconds
Started	Jul 18 06:44:23 PM PDT 24
Finished	Jul 18 06:44:34 PM PDT 24
Peak memory	201096 kb
Host	smart-0f677153-430a-427c-adc8-784c701fc5b9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536099387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.536099387
Directory	/workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_status.3685083957
Short name	T216
Test name
Test status
Simulation time	47187660 ps
CPU time	0.79 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:35 PM PDT 24
Peak memory	200184 kb
Host	smart-0fa56a87-a2f3-4d89-bf5f-850b97467d69
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685083957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.3685083957
Directory	/workspace/49.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_div_intersig_mubi.853403455
Short name	T715
Test name
Test status
Simulation time	254811779 ps
CPU time	1.48 seconds
Started	Jul 18 06:44:23 PM PDT 24
Finished	Jul 18 06:44:35 PM PDT 24
Peak memory	201036 kb
Host	smart-84346f7e-978c-4818-af4c-504b8e301ae7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853403455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.clkmgr_div_intersig_mubi.853403455
Directory	/workspace/49.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_extclk.758983433
Short name	T480
Test name
Test status
Simulation time	66830519 ps
CPU time	0.94 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:29 PM PDT 24
Peak memory	201076 kb
Host	smart-916bc00f-7276-4301-a93a-0c8bcaa9d185
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758983433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.758983433
Directory	/workspace/49.clkmgr_extclk/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency.1151179559
Short name	T239
Test name
Test status
Simulation time	2359732627 ps
CPU time	10.13 seconds
Started	Jul 18 06:44:17 PM PDT 24
Finished	Jul 18 06:44:33 PM PDT 24
Peak memory	201424 kb
Host	smart-c8f1438a-4c00-4e4e-bb7e-1d6ed35957f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151179559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.1151179559
Directory	/workspace/49.clkmgr_frequency/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency_timeout.1166086328
Short name	T820
Test name
Test status
Simulation time	262260140 ps
CPU time	1.8 seconds
Started	Jul 18 06:44:18 PM PDT 24
Finished	Jul 18 06:44:25 PM PDT 24
Peak memory	201236 kb
Host	smart-2f5f6fb5-bf9f-4a24-876c-85908cb1f985
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166086328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t imeout.1166086328
Directory	/workspace/49.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.3234534717
Short name	T241
Test name
Test status
Simulation time	31531165 ps
CPU time	0.84 seconds
Started	Jul 18 06:44:26 PM PDT 24
Finished	Jul 18 06:44:38 PM PDT 24
Peak memory	201092 kb
Host	smart-89b10fdd-4f13-4586-84af-199d3d6eb56b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234534717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.3234534717
Directory	/workspace/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.867786795
Short name	T658
Test name
Test status
Simulation time	18314300 ps
CPU time	0.78 seconds
Started	Jul 18 06:44:26 PM PDT 24
Finished	Jul 18 06:44:37 PM PDT 24
Peak memory	201116 kb
Host	smart-dc6cdc51-d1f8-4d65-a4f9-9ea88f01b920
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867786795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.clkmgr_lc_clk_byp_req_intersig_mubi.867786795
Directory	/workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2900516216
Short name	T399
Test name
Test status
Simulation time	45509598 ps
CPU time	0.94 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:30 PM PDT 24
Peak memory	201116 kb
Host	smart-5f1b1a14-534a-48d3-8d8c-995489137ef5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900516216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_ctrl_intersig_mubi.2900516216
Directory	/workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_peri.2404002432
Short name	T334
Test name
Test status
Simulation time	14853660 ps
CPU time	0.71 seconds
Started	Jul 18 06:44:24 PM PDT 24
Finished	Jul 18 06:44:35 PM PDT 24
Peak memory	201012 kb
Host	smart-b8f01d39-6ab4-4762-9bff-41ae3fd1a207
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404002432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.2404002432
Directory	/workspace/49.clkmgr_peri/latest

Test location	/workspace/coverage/default/49.clkmgr_regwen.3273969096
Short name	T29
Test name
Test status
Simulation time	888307152 ps
CPU time	3.54 seconds
Started	Jul 18 06:44:21 PM PDT 24
Finished	Jul 18 06:44:34 PM PDT 24
Peak memory	201272 kb
Host	smart-c8e0acc5-274e-414b-9dbc-ceab7be213d1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273969096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3273969096
Directory	/workspace/49.clkmgr_regwen/latest

Test location	/workspace/coverage/default/49.clkmgr_smoke.1069059739
Short name	T461
Test name
Test status
Simulation time	17533351 ps
CPU time	0.79 seconds
Started	Jul 18 06:44:18 PM PDT 24
Finished	Jul 18 06:44:25 PM PDT 24
Peak memory	201048 kb
Host	smart-765847b9-402d-4630-8489-fecccbdd183c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069059739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.1069059739
Directory	/workspace/49.clkmgr_smoke/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all.4169559172
Short name	T825
Test name
Test status
Simulation time	5423111699 ps
CPU time	39.52 seconds
Started	Jul 18 06:44:21 PM PDT 24
Finished	Jul 18 06:45:11 PM PDT 24
Peak memory	201468 kb
Host	smart-b686d7d1-5448-415d-ab4f-0fe38811090f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169559172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.4169559172
Directory	/workspace/49.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.3696490421
Short name	T739
Test name
Test status
Simulation time	1391177722 ps
CPU time	24.52 seconds
Started	Jul 18 06:44:23 PM PDT 24
Finished	Jul 18 06:44:56 PM PDT 24
Peak memory	217872 kb
Host	smart-313477e0-aaf8-467c-88fa-9ffacb2079a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3696490421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.3696490421
Directory	/workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_trans.3434507751
Short name	T387
Test name
Test status
Simulation time	16358534 ps
CPU time	0.77 seconds
Started	Jul 18 06:44:20 PM PDT 24
Finished	Jul 18 06:44:27 PM PDT 24
Peak memory	201088 kb
Host	smart-3ff26d8a-c074-4a7f-b798-01ac58a9fef6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434507751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3434507751
Directory	/workspace/49.clkmgr_trans/latest

Test location	/workspace/coverage/default/5.clkmgr_alert_test.997372074
Short name	T775
Test name
Test status
Simulation time	19617707 ps
CPU time	0.8 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201180 kb
Host	smart-80dc20fd-08be-4f9f-9bd9-20c35b2c0d6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997372074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmg r_alert_test.997372074
Directory	/workspace/5.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3193972003
Short name	T607
Test name
Test status
Simulation time	59147093 ps
CPU time	0.95 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:20 PM PDT 24
Peak memory	201080 kb
Host	smart-e20bcd9e-3908-4b57-8de2-c767d563fd16
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193972003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.3193972003
Directory	/workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_status.1898342577
Short name	T26
Test name
Test status
Simulation time	36998524 ps
CPU time	0.77 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:13 PM PDT 24
Peak memory	200972 kb
Host	smart-7c4c267d-fddb-4d10-b270-cd8c9e5eac31
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898342577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1898342577
Directory	/workspace/5.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/5.clkmgr_div_intersig_mubi.255825105
Short name	T403
Test name
Test status
Simulation time	48926961 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:13 PM PDT 24
Peak memory	201280 kb
Host	smart-ecbcad5a-f1d9-4b7d-bd33-18d261757d99
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255825105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .clkmgr_div_intersig_mubi.255825105
Directory	/workspace/5.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_extclk.262598603
Short name	T814
Test name
Test status
Simulation time	35260365 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:18 PM PDT 24
Peak memory	201080 kb
Host	smart-96d79350-3897-45e5-99c4-46e90debee01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262598603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.262598603
Directory	/workspace/5.clkmgr_extclk/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency.188097314
Short name	T323
Test name
Test status
Simulation time	1900788416 ps
CPU time	8.38 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:23 PM PDT 24
Peak memory	201360 kb
Host	smart-73589423-4e57-42f0-a481-863c37f98d63
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188097314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.188097314
Directory	/workspace/5.clkmgr_frequency/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency_timeout.1594100406
Short name	T686
Test name
Test status
Simulation time	385198313 ps
CPU time	2.33 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:20 PM PDT 24
Peak memory	201232 kb
Host	smart-4e3c5982-abcd-4993-a8c1-ad7c6b53f7f0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594100406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti meout.1594100406
Directory	/workspace/5.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.2339515994
Short name	T702
Test name
Test status
Simulation time	28934016 ps
CPU time	0.95 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201100 kb
Host	smart-75fc32dc-b2f6-49f5-a24b-bd2e5c5a6151
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339515994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.2339515994
Directory	/workspace/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2596065475
Short name	T343
Test name
Test status
Simulation time	15045470 ps
CPU time	0.81 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201100 kb
Host	smart-c3c2c105-c4e3-455b-9340-f20dd3cd08dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596065475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_clk_byp_req_intersig_mubi.2596065475
Directory	/workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2186350078
Short name	T372
Test name
Test status
Simulation time	23321655 ps
CPU time	0.84 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:15 PM PDT 24
Peak memory	201192 kb
Host	smart-679d2955-89c1-4fff-a7ea-6c345f7f49a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186350078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_ctrl_intersig_mubi.2186350078
Directory	/workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_peri.3074496060
Short name	T330
Test name
Test status
Simulation time	59130308 ps
CPU time	0.84 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:17 PM PDT 24
Peak memory	201016 kb
Host	smart-1f85e8ab-1a00-4d76-ac24-de54af9be14f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074496060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3074496060
Directory	/workspace/5.clkmgr_peri/latest

Test location	/workspace/coverage/default/5.clkmgr_regwen.1676172596
Short name	T842
Test name
Test status
Simulation time	355794032 ps
CPU time	1.86 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:15 PM PDT 24
Peak memory	201152 kb
Host	smart-0ad63312-31a4-4ee6-8ba5-6c3acd26343f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676172596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1676172596
Directory	/workspace/5.clkmgr_regwen/latest

Test location	/workspace/coverage/default/5.clkmgr_smoke.1173528469
Short name	T267
Test name
Test status
Simulation time	47577781 ps
CPU time	0.89 seconds
Started	Jul 18 06:41:10 PM PDT 24
Finished	Jul 18 06:41:15 PM PDT 24
Peak memory	201056 kb
Host	smart-7f6fb653-f73b-42be-8b66-7a1db5203015
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173528469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.1173528469
Directory	/workspace/5.clkmgr_smoke/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all.3226969353
Short name	T618
Test name
Test status
Simulation time	301532327 ps
CPU time	2.13 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201060 kb
Host	smart-6253c1b8-0329-43ab-8280-9fd28d96d401
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226969353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.3226969353
Directory	/workspace/5.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/5.clkmgr_trans.2907775972
Short name	T459
Test name
Test status
Simulation time	61459564 ps
CPU time	0.92 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:20 PM PDT 24
Peak memory	201036 kb
Host	smart-a1627e86-f5d4-4ed7-85b7-3c1b57b377ad
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907775972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2907775972
Directory	/workspace/5.clkmgr_trans/latest

Test location	/workspace/coverage/default/6.clkmgr_alert_test.150991187
Short name	T490
Test name
Test status
Simulation time	13701808 ps
CPU time	0.74 seconds
Started	Jul 18 06:41:14 PM PDT 24
Finished	Jul 18 06:41:22 PM PDT 24
Peak memory	201224 kb
Host	smart-c128990d-33be-424a-a639-655c8e4ee673
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150991187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg r_alert_test.150991187
Directory	/workspace/6.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3700309705
Short name	T755
Test name
Test status
Simulation time	27736163 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:09 PM PDT 24
Finished	Jul 18 06:41:12 PM PDT 24
Peak memory	201108 kb
Host	smart-37f521f7-6bdb-492c-9d9c-63d92030a5fc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700309705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.3700309705
Directory	/workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_status.1784766204
Short name	T157
Test name
Test status
Simulation time	24725144 ps
CPU time	0.74 seconds
Started	Jul 18 06:41:23 PM PDT 24
Finished	Jul 18 06:41:25 PM PDT 24
Peak memory	200288 kb
Host	smart-905e5425-83cb-48d3-9522-326ed0d1249a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784766204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.1784766204
Directory	/workspace/6.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/6.clkmgr_div_intersig_mubi.264553776
Short name	T670
Test name
Test status
Simulation time	115268606 ps
CPU time	1.1 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:20 PM PDT 24
Peak memory	200588 kb
Host	smart-c77a41d4-e6ec-4ef5-bcf3-cad7b7714e56
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264553776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .clkmgr_div_intersig_mubi.264553776
Directory	/workspace/6.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_extclk.2343522015
Short name	T473
Test name
Test status
Simulation time	23894850 ps
CPU time	0.84 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201084 kb
Host	smart-d99ebf1c-3dec-4a6b-bf75-181ce071da83
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343522015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2343522015
Directory	/workspace/6.clkmgr_extclk/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency.1565484714
Short name	T11
Test name
Test status
Simulation time	1991477140 ps
CPU time	8.3 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:25 PM PDT 24
Peak memory	201384 kb
Host	smart-efd1b595-a73f-4ea8-ba86-75f7269e5491
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565484714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.1565484714
Directory	/workspace/6.clkmgr_frequency/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency_timeout.3205779809
Short name	T624
Test name
Test status
Simulation time	2180144705 ps
CPU time	11.2 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:31 PM PDT 24
Peak memory	201500 kb
Host	smart-e2a1ca33-abc4-421c-89f5-aeec2d99e1ce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205779809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti meout.3205779809
Directory	/workspace/6.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1708943856
Short name	T592
Test name
Test status
Simulation time	27776326 ps
CPU time	0.96 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201044 kb
Host	smart-bad66bfd-3a12-44ce-9d6a-3927c61f5d23
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708943856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.1708943856
Directory	/workspace/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3419233082
Short name	T431
Test name
Test status
Simulation time	22973512 ps
CPU time	0.86 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:20 PM PDT 24
Peak memory	201096 kb
Host	smart-42e1c88f-a9ae-460a-8e69-3ec48d1852a5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419233082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_clk_byp_req_intersig_mubi.3419233082
Directory	/workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2813650724
Short name	T369
Test name
Test status
Simulation time	17741178 ps
CPU time	0.8 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201076 kb
Host	smart-d1d2fcfd-b8ae-47bf-a316-6909c78a5d88
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813650724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_ctrl_intersig_mubi.2813650724
Directory	/workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_peri.2980635775
Short name	T637
Test name
Test status
Simulation time	41983720 ps
CPU time	0.8 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201024 kb
Host	smart-2cfc7a4c-efba-4571-9f72-55239319823b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980635775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2980635775
Directory	/workspace/6.clkmgr_peri/latest

Test location	/workspace/coverage/default/6.clkmgr_regwen.3157666955
Short name	T587
Test name
Test status
Simulation time	508462538 ps
CPU time	2.27 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:18 PM PDT 24
Peak memory	201088 kb
Host	smart-c9851125-d79a-45d7-a707-392e813338f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157666955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3157666955
Directory	/workspace/6.clkmgr_regwen/latest

Test location	/workspace/coverage/default/6.clkmgr_smoke.3170980137
Short name	T42
Test name
Test status
Simulation time	101037487 ps
CPU time	1.13 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201060 kb
Host	smart-211f5c5f-6fcc-4d8b-9043-14077b13b7ba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170980137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3170980137
Directory	/workspace/6.clkmgr_smoke/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all.1554667962
Short name	T677
Test name
Test status
Simulation time	5443895196 ps
CPU time	39.88 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:59 PM PDT 24
Peak memory	200968 kb
Host	smart-6495f81e-1b7c-4ded-a84b-bde8261936a8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554667962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.1554667962
Directory	/workspace/6.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.12613864
Short name	T78
Test name
Test status
Simulation time	128153597193 ps
CPU time	825.99 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:55:06 PM PDT 24
Peak memory	217916 kb
Host	smart-014a5d66-19ff-4f28-ab5f-06d39fc22895
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=12613864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.12613864
Directory	/workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.clkmgr_trans.822098628
Short name	T342
Test name
Test status
Simulation time	28094538 ps
CPU time	0.94 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201104 kb
Host	smart-8d41443b-a238-4041-b862-e4f2ccf1e0e7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822098628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.822098628
Directory	/workspace/6.clkmgr_trans/latest

Test location	/workspace/coverage/default/7.clkmgr_alert_test.114408701
Short name	T449
Test name
Test status
Simulation time	46463789 ps
CPU time	0.88 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201212 kb
Host	smart-e7c4d8ce-9d12-4077-8902-2e637261cb1b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114408701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg r_alert_test.114408701
Directory	/workspace/7.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1086893780
Short name	T96
Test name
Test status
Simulation time	75725376 ps
CPU time	1.03 seconds
Started	Jul 18 06:41:14 PM PDT 24
Finished	Jul 18 06:41:22 PM PDT 24
Peak memory	201000 kb
Host	smart-edc91408-72c2-418b-a786-2f302dec53f0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086893780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.1086893780
Directory	/workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_status.3072747357
Short name	T444
Test name
Test status
Simulation time	40812672 ps
CPU time	0.76 seconds
Started	Jul 18 06:41:12 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	200284 kb
Host	smart-f2eb3137-e25f-4fd3-8490-384af5f4005e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072747357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.3072747357
Directory	/workspace/7.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/7.clkmgr_div_intersig_mubi.3607481556
Short name	T350
Test name
Test status
Simulation time	83342517 ps
CPU time	1.03 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:17 PM PDT 24
Peak memory	201100 kb
Host	smart-b02a9e93-da75-4849-8c70-fad223eba41c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607481556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.3607481556
Directory	/workspace/7.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_extclk.2823881310
Short name	T101
Test name
Test status
Simulation time	37191683 ps
CPU time	0.9 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201080 kb
Host	smart-07ad20e7-9c77-492a-bf32-ad7e6b085aeb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823881310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.2823881310
Directory	/workspace/7.clkmgr_extclk/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency.2981881497
Short name	T519
Test name
Test status
Simulation time	2494355313 ps
CPU time	13.03 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:33 PM PDT 24
Peak memory	201380 kb
Host	smart-51289071-a360-4840-8a35-c724d28d38c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981881497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.2981881497
Directory	/workspace/7.clkmgr_frequency/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency_timeout.2525883012
Short name	T423
Test name
Test status
Simulation time	1116860095 ps
CPU time	4.8 seconds
Started	Jul 18 06:41:14 PM PDT 24
Finished	Jul 18 06:41:26 PM PDT 24
Peak memory	201060 kb
Host	smart-fafe9ad0-2b30-4a2a-94db-7fd9374cdd04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525883012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti meout.2525883012
Directory	/workspace/7.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/7.clkmgr_idle_intersig_mubi.4103142281
Short name	T213
Test name
Test status
Simulation time	331203659 ps
CPU time	1.87 seconds
Started	Jul 18 06:41:14 PM PDT 24
Finished	Jul 18 06:41:23 PM PDT 24
Peak memory	201048 kb
Host	smart-8347b27f-5048-4992-b359-7bbe98e3d552
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103142281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.4103142281
Directory	/workspace/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3846835299
Short name	T493
Test name
Test status
Simulation time	23434095 ps
CPU time	0.81 seconds
Started	Jul 18 06:41:14 PM PDT 24
Finished	Jul 18 06:41:22 PM PDT 24
Peak memory	201080 kb
Host	smart-4d241de4-8442-4a2c-9cdb-de1b1981bb5d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846835299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3846835299
Directory	/workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3962864781
Short name	T396
Test name
Test status
Simulation time	115217350 ps
CPU time	1.11 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201100 kb
Host	smart-e43b910d-1fa4-422e-abeb-164b508a532a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962864781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_ctrl_intersig_mubi.3962864781
Directory	/workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_peri.3403120698
Short name	T64
Test name
Test status
Simulation time	49614863 ps
CPU time	0.82 seconds
Started	Jul 18 06:41:15 PM PDT 24
Finished	Jul 18 06:41:23 PM PDT 24
Peak memory	201028 kb
Host	smart-48e59102-d353-45f9-965a-a240c16a21af
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403120698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3403120698
Directory	/workspace/7.clkmgr_peri/latest

Test location	/workspace/coverage/default/7.clkmgr_regwen.1653410550
Short name	T82
Test name
Test status
Simulation time	440859501 ps
CPU time	2.99 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:19 PM PDT 24
Peak memory	201084 kb
Host	smart-94322d38-84ea-49f9-817f-d0b24d3ec020
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653410550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1653410550
Directory	/workspace/7.clkmgr_regwen/latest

Test location	/workspace/coverage/default/7.clkmgr_smoke.3012862684
Short name	T448
Test name
Test status
Simulation time	24315079 ps
CPU time	0.89 seconds
Started	Jul 18 06:41:11 PM PDT 24
Finished	Jul 18 06:41:17 PM PDT 24
Peak memory	201060 kb
Host	smart-52499549-0611-43de-af84-63dfb1533065
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012862684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3012862684
Directory	/workspace/7.clkmgr_smoke/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all.4276822501
Short name	T617
Test name
Test status
Simulation time	9192985271 ps
CPU time	29.97 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:50 PM PDT 24
Peak memory	201456 kb
Host	smart-30f16eeb-963d-4edb-87aa-768669f82621
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276822501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.4276822501
Directory	/workspace/7.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.1103088820
Short name	T427
Test name
Test status
Simulation time	10212457606 ps
CPU time	165.5 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:44:05 PM PDT 24
Peak memory	209852 kb
Host	smart-9f28a72e-d71f-43ef-bb8e-068dcb4841df
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1103088820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.1103088820
Directory	/workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.clkmgr_trans.2325163659
Short name	T83
Test name
Test status
Simulation time	78729559 ps
CPU time	1.01 seconds
Started	Jul 18 06:41:15 PM PDT 24
Finished	Jul 18 06:41:23 PM PDT 24
Peak memory	201036 kb
Host	smart-4b769192-1f8f-40cc-8efb-f35e8d5ccb51
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325163659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2325163659
Directory	/workspace/7.clkmgr_trans/latest

Test location	/workspace/coverage/default/8.clkmgr_alert_test.4266887061
Short name	T99
Test name
Test status
Simulation time	27936336 ps
CPU time	0.78 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:35 PM PDT 24
Peak memory	201220 kb
Host	smart-8a02b752-e8b5-4a18-8415-35e980e15a4d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266887061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm gr_alert_test.4266887061
Directory	/workspace/8.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1506773383
Short name	T108
Test name
Test status
Simulation time	92236410 ps
CPU time	1.11 seconds
Started	Jul 18 06:41:34 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	201096 kb
Host	smart-a56ae193-b119-4864-bb72-3451930a6477
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506773383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.1506773383
Directory	/workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_status.3958281650
Short name	T183
Test name
Test status
Simulation time	56616846 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:35 PM PDT 24
Finished	Jul 18 06:41:41 PM PDT 24
Peak memory	200980 kb
Host	smart-10419ef8-72e0-4d03-89ab-951a58866514
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958281650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.3958281650
Directory	/workspace/8.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/8.clkmgr_div_intersig_mubi.1602000158
Short name	T189
Test name
Test status
Simulation time	126117521 ps
CPU time	1.09 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:36 PM PDT 24
Peak memory	201068 kb
Host	smart-12c8b7ca-2b1c-4606-8776-66c6e2119ead
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602000158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.1602000158
Directory	/workspace/8.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_extclk.1038175381
Short name	T383
Test name
Test status
Simulation time	45726267 ps
CPU time	0.88 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201160 kb
Host	smart-195b4b8b-2a6f-4322-98ab-f34b90c75533
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038175381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1038175381
Directory	/workspace/8.clkmgr_extclk/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency.4240724330
Short name	T844
Test name
Test status
Simulation time	2237025091 ps
CPU time	16.74 seconds
Started	Jul 18 06:41:13 PM PDT 24
Finished	Jul 18 06:41:37 PM PDT 24
Peak memory	201396 kb
Host	smart-ccbd3d54-94fe-42b3-af28-ef336703d020
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240724330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.4240724330
Directory	/workspace/8.clkmgr_frequency/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency_timeout.4262979775
Short name	T345
Test name
Test status
Simulation time	495754499 ps
CPU time	3.96 seconds
Started	Jul 18 06:41:15 PM PDT 24
Finished	Jul 18 06:41:25 PM PDT 24
Peak memory	201232 kb
Host	smart-64d24442-d0c6-4e45-bc91-09b9f849a8f0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262979775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti meout.4262979775
Directory	/workspace/8.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/8.clkmgr_idle_intersig_mubi.70769529
Short name	T176
Test name
Test status
Simulation time	38595136 ps
CPU time	1.03 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:32 PM PDT 24
Peak memory	201044 kb
Host	smart-91b5e9a7-74c7-4b17-8164-f0d846d0f543
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70769529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. clkmgr_idle_intersig_mubi.70769529
Directory	/workspace/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2321249355
Short name	T789
Test name
Test status
Simulation time	22070459 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:35 PM PDT 24
Peak memory	201092 kb
Host	smart-ec0deba1-0925-4380-81a8-2f5cef06d982
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321249355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_clk_byp_req_intersig_mubi.2321249355
Directory	/workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.978379107
Short name	T514
Test name
Test status
Simulation time	37269917 ps
CPU time	0.78 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	201080 kb
Host	smart-a02ff7a8-8efa-4a81-af5a-a685c9457005
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978379107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.clkmgr_lc_ctrl_intersig_mubi.978379107
Directory	/workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_peri.3846529880
Short name	T555
Test name
Test status
Simulation time	24714702 ps
CPU time	0.77 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:34 PM PDT 24
Peak memory	201000 kb
Host	smart-67a7f1ab-39eb-4ea1-b220-c2fbb4ba7c0b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846529880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3846529880
Directory	/workspace/8.clkmgr_peri/latest

Test location	/workspace/coverage/default/8.clkmgr_regwen.206008728
Short name	T166
Test name
Test status
Simulation time	303597060 ps
CPU time	2.07 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	201036 kb
Host	smart-a79d96a3-a9fe-4016-98b6-f9b51e921d4b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206008728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.206008728
Directory	/workspace/8.clkmgr_regwen/latest

Test location	/workspace/coverage/default/8.clkmgr_smoke.4005111746
Short name	T782
Test name
Test status
Simulation time	20589127 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:14 PM PDT 24
Finished	Jul 18 06:41:21 PM PDT 24
Peak memory	201052 kb
Host	smart-bba14ed8-8d8f-477e-9dfa-395037b8ae55
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005111746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.4005111746
Directory	/workspace/8.clkmgr_smoke/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all.3660684959
Short name	T278
Test name
Test status
Simulation time	2581605782 ps
CPU time	11.98 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:47 PM PDT 24
Peak memory	201480 kb
Host	smart-a4e0b82d-b7d2-47e5-b4c2-50f1e3c62d17
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660684959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.3660684959
Directory	/workspace/8.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.4135219320
Short name	T245
Test name
Test status
Simulation time	30711676953 ps
CPU time	481.92 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:49:34 PM PDT 24
Peak memory	209924 kb
Host	smart-3d21f6ec-873d-48fb-89bd-c6cbe48ad7c4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4135219320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.4135219320
Directory	/workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.clkmgr_trans.3623354502
Short name	T685
Test name
Test status
Simulation time	31677190 ps
CPU time	0.96 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:34 PM PDT 24
Peak memory	201112 kb
Host	smart-cbee578f-a1ed-4e5d-856d-8ddb5cdf43fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623354502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3623354502
Directory	/workspace/8.clkmgr_trans/latest

Test location	/workspace/coverage/default/9.clkmgr_alert_test.3542162498
Short name	T835
Test name
Test status
Simulation time	15127358 ps
CPU time	0.73 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:33 PM PDT 24
Peak memory	201208 kb
Host	smart-86d15257-d538-4f11-8b06-2f3de584ccb8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542162498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.3542162498
Directory	/workspace/9.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.553559732
Short name	T104
Test name
Test status
Simulation time	33482161 ps
CPU time	0.93 seconds
Started	Jul 18 06:41:27 PM PDT 24
Finished	Jul 18 06:41:28 PM PDT 24
Peak memory	201084 kb
Host	smart-f9a5a574-7f34-4e3f-83a9-14df6957935b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553559732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.553559732
Directory	/workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_status.4280931673
Short name	T181
Test name
Test status
Simulation time	16362749 ps
CPU time	0.73 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	200972 kb
Host	smart-37988c29-020d-466a-a68e-cf16199e5cf5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280931673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.4280931673
Directory	/workspace/9.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/9.clkmgr_div_intersig_mubi.175103519
Short name	T362
Test name
Test status
Simulation time	29162137 ps
CPU time	0.87 seconds
Started	Jul 18 06:41:32 PM PDT 24
Finished	Jul 18 06:41:38 PM PDT 24
Peak memory	201096 kb
Host	smart-44641b4f-dcec-4f4e-bc38-4d7f8745037f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175103519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .clkmgr_div_intersig_mubi.175103519
Directory	/workspace/9.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_extclk.4076126796
Short name	T385
Test name
Test status
Simulation time	24195976 ps
CPU time	0.83 seconds
Started	Jul 18 06:41:28 PM PDT 24
Finished	Jul 18 06:41:30 PM PDT 24
Peak memory	201068 kb
Host	smart-3d84f6d2-34e4-4536-a686-299065baa9ce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076126796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.4076126796
Directory	/workspace/9.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency.13670061
Short name	T586
Test name
Test status
Simulation time	1650309336 ps
CPU time	8.97 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:45 PM PDT 24
Peak memory	201348 kb
Host	smart-57382b19-823e-4e40-b76e-2362ac9d9195
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13670061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.13670061
Directory	/workspace/9.clkmgr_frequency/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency_timeout.3261993706
Short name	T455
Test name
Test status
Simulation time	1469122964 ps
CPU time	6.8 seconds
Started	Jul 18 06:41:33 PM PDT 24
Finished	Jul 18 06:41:45 PM PDT 24
Peak memory	201220 kb
Host	smart-fd3aed1a-13e3-4440-af2f-822a6323140a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261993706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti meout.3261993706
Directory	/workspace/9.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/9.clkmgr_idle_intersig_mubi.177242033
Short name	T787
Test name
Test status
Simulation time	54010513 ps
CPU time	1.06 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:36 PM PDT 24
Peak memory	201088 kb
Host	smart-3405f8d3-7e6e-4a2b-8e6f-93963fb75f93
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177242033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .clkmgr_idle_intersig_mubi.177242033
Directory	/workspace/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1593469300
Short name	T472
Test name
Test status
Simulation time	24314341 ps
CPU time	0.88 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:32 PM PDT 24
Peak memory	201112 kb
Host	smart-b7134c1a-37b5-4338-82a7-a633164ff1fa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593469300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1593469300
Directory	/workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1973469276
Short name	T648
Test name
Test status
Simulation time	16851796 ps
CPU time	0.8 seconds
Started	Jul 18 06:41:31 PM PDT 24
Finished	Jul 18 06:41:36 PM PDT 24
Peak memory	201084 kb
Host	smart-efdb3081-0aba-4ebe-8cc4-faa80199b60e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973469276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_ctrl_intersig_mubi.1973469276
Directory	/workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_peri.2069481026
Short name	T535
Test name
Test status
Simulation time	30927597 ps
CPU time	0.77 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:34 PM PDT 24
Peak memory	201028 kb
Host	smart-21451ac4-0cbc-4d43-a2ec-a3c7ccd3eeb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069481026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2069481026
Directory	/workspace/9.clkmgr_peri/latest

Test location	/workspace/coverage/default/9.clkmgr_regwen.2537820436
Short name	T17
Test name
Test status
Simulation time	1215474715 ps
CPU time	4.33 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:34 PM PDT 24
Peak memory	201256 kb
Host	smart-1a391a99-b9a0-48d7-9fb8-03a40178deb2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537820436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.2537820436
Directory	/workspace/9.clkmgr_regwen/latest

Test location	/workspace/coverage/default/9.clkmgr_smoke.2261641014
Short name	T622
Test name
Test status
Simulation time	35396950 ps
CPU time	0.91 seconds
Started	Jul 18 06:41:29 PM PDT 24
Finished	Jul 18 06:41:32 PM PDT 24
Peak memory	201000 kb
Host	smart-c60e0d61-8eff-4d4b-873d-350fe709dd47
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261641014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.2261641014
Directory	/workspace/9.clkmgr_smoke/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all.2321536298
Short name	T620
Test name
Test status
Simulation time	3392896685 ps
CPU time	14.32 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:48 PM PDT 24
Peak memory	201464 kb
Host	smart-d437ace9-f96a-407f-8103-36210efedcd7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321536298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.2321536298
Directory	/workspace/9.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1162193016
Short name	T36
Test name
Test status
Simulation time	80216602737 ps
CPU time	526.07 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:50:19 PM PDT 24
Peak memory	217944 kb
Host	smart-7978e7a9-549d-4b41-8703-d18ac4124160
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1162193016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.1162193016
Directory	/workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.clkmgr_trans.747200564
Short name	T466
Test name
Test status
Simulation time	19358500 ps
CPU time	0.81 seconds
Started	Jul 18 06:41:30 PM PDT 24
Finished	Jul 18 06:41:33 PM PDT 24
Peak memory	201080 kb
Host	smart-5709c76e-c511-4532-90d6-4e546f45cfc7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747200564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.747200564
Directory	/workspace/9.clkmgr_trans/latest

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%