Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 340371492 1 T4 1110 T5 1758 T1 726652
auto[1] 396888 1 T1 1520 T16 630 T17 62


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 340364290 1 T4 1110 T5 1758 T1 726701
auto[1] 404090 1 T1 1030 T16 466 T17 142


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 340288488 1 T4 1110 T5 1758 T1 726690
auto[1] 479892 1 T1 1140 T16 576 T17 182


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 318028054 1 T4 1110 T5 1758 T1 632272
auto[1] 22740326 1 T1 945328 T16 3000 T17 3054


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 195919502 1 T4 1066 T5 64 T1 265262
auto[1] 144848878 1 T4 44 T5 1694 T1 461542


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 179127374 1 T4 1066 T5 64 T1 170698
auto[0] auto[0] auto[0] auto[0] auto[1] 138566380 1 T4 44 T5 1694 T1 461475
auto[0] auto[0] auto[0] auto[1] auto[0] 27822 1 T1 236 T16 64 T20 12
auto[0] auto[0] auto[0] auto[1] auto[1] 7482 1 T1 6 T9 238 T72 88
auto[0] auto[0] auto[1] auto[0] auto[0] 16225008 1 T1 944236 T16 2286 T17 2640
auto[0] auto[0] auto[1] auto[0] auto[1] 6169840 1 T1 286 T16 50 T17 236
auto[0] auto[0] auto[1] auto[1] auto[0] 47572 1 T1 106 T16 78 T17 8
auto[0] auto[0] auto[1] auto[1] auto[1] 12432 1 T1 10 T16 28 T30 90
auto[0] auto[1] auto[0] auto[0] auto[0] 51354 1 T1 24 T20 2 T21 2
auto[0] auto[1] auto[0] auto[0] auto[1] 1228 1 T1 10 T9 24 T11 6
auto[0] auto[1] auto[0] auto[1] auto[0] 12044 1 T1 92 T20 48 T21 40
auto[0] auto[1] auto[0] auto[1] auto[1] 3078 1 T1 36 T9 116 T11 42
auto[0] auto[1] auto[1] auto[0] auto[0] 9638 1 T1 40 T16 18 T17 8
auto[0] auto[1] auto[1] auto[0] auto[1] 2978 1 T9 70 T11 34 T12 22
auto[0] auto[1] auto[1] auto[1] auto[0] 19486 1 T1 84 T16 44 T9 178
auto[0] auto[1] auto[1] auto[1] auto[1] 4772 1 T9 120 T11 126 T14 66
auto[1] auto[0] auto[0] auto[0] auto[0] 35756 1 T1 14 T17 20 T19 14
auto[1] auto[0] auto[0] auto[0] auto[1] 4292 1 T1 12 T9 132 T11 18
auto[1] auto[0] auto[0] auto[1] auto[0] 31074 1 T1 54 T30 52 T9 226
auto[1] auto[0] auto[0] auto[1] auto[1] 8218 1 T1 114 T9 266 T12 44
auto[1] auto[0] auto[1] auto[0] auto[0] 26776 1 T1 32 T16 64 T17 16
auto[1] auto[0] auto[1] auto[0] auto[1] 6626 1 T1 12 T17 12 T19 20
auto[1] auto[0] auto[1] auto[1] auto[0] 52720 1 T1 64 T16 108 T19 46
auto[1] auto[0] auto[1] auto[1] auto[1] 14918 1 T1 94 T9 382 T120 58
auto[1] auto[1] auto[0] auto[0] auto[0] 89186 1 T1 36 T16 18 T21 2
auto[1] auto[1] auto[0] auto[0] auto[1] 5704 1 T1 24 T29 18 T30 4
auto[1] auto[1] auto[0] auto[1] auto[0] 45888 1 T1 266 T16 62 T21 50
auto[1] auto[1] auto[0] auto[1] auto[1] 11174 1 T1 54 T30 64 T9 198
auto[1] auto[1] auto[1] auto[0] auto[0] 39436 1 T1 52 T16 76 T17 64
auto[1] auto[1] auto[1] auto[0] auto[1] 9916 1 T1 8 T16 2 T17 16
auto[1] auto[1] auto[1] auto[1] auto[0] 78368 1 T1 304 T16 202 T17 54
auto[1] auto[1] auto[1] auto[1] auto[1] 19840 1 T16 44 T9 282 T11 162

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%