Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 296410290 1 T1 856637 T4 3112 T5 3768
auto[1] 410390 1 T1 7316 T4 1100 T5 1182


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 296394342 1 T1 856839 T4 3350 T5 4120
auto[1] 426338 1 T1 5292 T4 862 T5 830


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 296314802 1 T1 856776 T4 3234 T5 3776
auto[1] 505878 1 T1 5930 T4 978 T5 1174


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 270343912 1 T1 697021 T4 1014 T5 2960
auto[1] 26476768 1 T1 160348 T4 3198 T5 1990


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 169296962 1 T1 304670 T4 3148 T5 2918
auto[1] 127523718 1 T1 552699 T4 1064 T5 2032


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 145510076 1 T1 302243 T4 278 T5 458
auto[0] auto[0] auto[0] auto[0] auto[1] 124485080 1 T1 394464 T4 276 T5 1922
auto[0] auto[0] auto[0] auto[1] auto[0] 28444 1 T1 306 T4 38 T5 76
auto[0] auto[0] auto[0] auto[1] auto[1] 7346 1 T1 204 T4 16 T5 26
auto[0] auto[0] auto[1] auto[0] auto[0] 23180886 1 T1 17684 T4 2010 T5 926
auto[0] auto[0] auto[1] auto[0] auto[1] 2925082 1 T1 158017 T4 304 T17 168
auto[0] auto[0] auto[1] auto[1] auto[0] 52266 1 T1 826 T4 130 T5 132
auto[0] auto[0] auto[1] auto[1] auto[1] 12840 1 T1 170 T4 48 T17 52
auto[0] auto[1] auto[0] auto[0] auto[0] 54090 1 T1 72 T17 2 T3 120
auto[0] auto[1] auto[0] auto[0] auto[1] 1598 1 T1 4 T3 94 T71 20
auto[0] auto[1] auto[0] auto[1] auto[0] 11510 1 T1 344 T17 38 T3 96
auto[0] auto[1] auto[0] auto[1] auto[1] 3650 1 T1 106 T3 186 T71 56
auto[0] auto[1] auto[1] auto[0] auto[0] 12116 1 T1 110 T4 14 T5 60
auto[0] auto[1] auto[1] auto[0] auto[1] 3174 1 T1 44 T4 18 T9 28
auto[0] auto[1] auto[1] auto[1] auto[0] 22066 1 T1 526 T4 40 T5 176
auto[0] auto[1] auto[1] auto[1] auto[1] 4578 1 T1 110 T4 62 T9 36
auto[1] auto[0] auto[0] auto[0] auto[0] 47432 1 T1 134 T5 116 T3 404
auto[1] auto[0] auto[0] auto[0] auto[1] 4294 1 T1 38 T4 28 T5 12
auto[1] auto[0] auto[0] auto[1] auto[0] 31000 1 T1 370 T5 86 T3 358
auto[1] auto[0] auto[0] auto[1] auto[1] 7560 1 T1 252 T4 56 T5 72
auto[1] auto[0] auto[1] auto[0] auto[0] 31622 1 T1 266 T4 28 T5 46
auto[1] auto[0] auto[1] auto[0] auto[1] 6400 1 T1 82 T4 10 T3 70
auto[1] auto[0] auto[1] auto[1] auto[0] 52960 1 T1 592 T4 70 T5 248
auto[1] auto[0] auto[1] auto[1] auto[1] 11054 1 T1 220 T4 58 T3 88
auto[1] auto[1] auto[0] auto[0] auto[0] 85376 1 T1 178 T4 48 T5 32
auto[1] auto[1] auto[0] auto[0] auto[1] 6400 1 T1 78 T4 20 T17 8
auto[1] auto[1] auto[0] auto[1] auto[0] 47834 1 T1 582 T4 204 T5 160
auto[1] auto[1] auto[0] auto[1] auto[1] 12222 1 T1 462 T4 50 T3 122
auto[1] auto[1] auto[1] auto[0] auto[0] 45518 1 T1 300 T4 58 T5 196
auto[1] auto[1] auto[1] auto[0] auto[1] 11146 1 T1 130 T4 20 T17 8
auto[1] auto[1] auto[1] auto[1] auto[0] 83766 1 T1 1978 T4 230 T5 206
auto[1] auto[1] auto[1] auto[1] auto[1] 21294 1 T1 268 T4 98 T17 54

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