Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265647466

1

T4

5160

T1

228292

T5

4074

auto[1]

360672

1

T2

2874

T18

48

T3

3608

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265640936

1

T4

5160

T1

228292

T5

4074

auto[1]

367202

1

T2

2090

T18

48

T3

2462

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265580956

1

T4

5160

T1

228292

T5

4074

auto[1]

427182

1

T2

2326

T18

48

T3

2898

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

247804092

1

T4

5160

T1

228292

T5

4074

auto[1]

18204046

1

T2

4902

T18

1880

T3

368096

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159500448

1

T4

1454

T1

228292

T5

492

auto[1]

106507690

1

T4

3706

T5

3582

T16

1532

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

143433408

1

T4

1454

T1

228292

T5

492

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

104054998

1

T4

3706

T5

3582

T16

1532

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

28194

1

T2

498

T3

214

T21

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5962

1

T2

16

T3

28

T21

24

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

15534666

1

T2

2038

T18

1830

T3

364976

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2353228

1

T2

166

T3

570

T9

322

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43504

1

T2

422

T18

2

T3

260

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10890

1

T2

58

T3

104

T9

78

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

67090

1

T2

76

T3

4

T21

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1322

1

T9

2

T10

36

T161

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10780

1

T2

94

T3

86

T10

42

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2194

1

T9

64

T10

66

T161

78

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

9886

1

T2

394

T3

100

T10

44

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2480

1

T2

18

T3

38

T10

16

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17864

1

T2

206

T3

498

T10

66

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4490

1

T2

84

T3

102

T14

62

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

46708

1

T2

94

T3

62

T21

48

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3930

1

T3

22

T21

14

T10

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29962

1

T2

266

T3

472

T21

158

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6572

1

T3

116

T21

86

T10

46

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25044

1

T2

322

T3

92

T9

18

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6324

1

T2

32

T3

20

T9

16

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45562

1

T2

272

T3

380

T9

228

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11984

1

T2

122

T3

100

T10

234

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57826

1

T2

72

T3

132

T21

80

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5068

1

T2

32

T3

32

T21

14

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

39854

1

T2

262

T3

516

T21

138

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10224

1

T2

84

T3

98

T21

50

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

35914

1

T2

278

T18

2

T3

202

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9574

1

T3

20

T9

20

T10

58

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

74186

1

T2

490

T18

46

T3

594

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18450

1

T3

40

T9

60

T10

208