Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 313698218 1 T5 101422 T1 886935 T6 4930
auto[1] 419132 1 T5 1094 T1 13870 T2 1962


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 313716332 1 T5 101914 T1 887228 T6 4554
auto[1] 401018 1 T5 602 T1 10940 T6 376


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 313619470 1 T5 101712 T1 886800 T6 4396
auto[1] 497880 1 T5 804 T1 15218 T6 534


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 296938222 1 T5 99518 T1 884745 T6 3716
auto[1] 17179128 1 T5 2998 T1 35774 T6 1214


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 170412060 1 T5 17740 T1 491779 T6 4344
auto[1] 143705290 1 T5 84776 T1 396543 T6 586


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 159411500 1 T5 14794 T1 488327 T6 2938
auto[0] auto[0] auto[0] auto[0] auto[1] 137202344 1 T5 84428 T1 395719 T6 422
auto[0] auto[0] auto[0] auto[1] auto[0] 32974 1 T5 114 T1 1086 T2 124
auto[0] auto[0] auto[0] auto[1] auto[1] 7078 1 T1 150 T2 14 T3 54
auto[0] auto[0] auto[1] auto[0] auto[0] 10422542 1 T5 1770 T1 18188 T6 936
auto[0] auto[0] auto[1] auto[0] auto[1] 6390790 1 T5 132 T1 4054 T2 456
auto[0] auto[0] auto[1] auto[1] auto[0] 51644 1 T5 208 T1 1538 T2 174
auto[0] auto[0] auto[1] auto[1] auto[1] 12606 1 T5 36 T1 636 T2 60
auto[0] auto[1] auto[0] auto[0] auto[0] 32380 1 T1 188 T6 56 T2 16
auto[0] auto[1] auto[0] auto[0] auto[1] 852 1 T1 12 T2 8 T3 20
auto[0] auto[1] auto[0] auto[1] auto[0] 13850 1 T1 272 T3 230 T9 172
auto[0] auto[1] auto[0] auto[1] auto[1] 2534 1 T1 80 T3 48 T8 84
auto[0] auto[1] auto[1] auto[0] auto[0] 10826 1 T5 48 T1 212 T6 44
auto[0] auto[1] auto[1] auto[0] auto[1] 2964 1 T1 158 T2 2 T3 62
auto[0] auto[1] auto[1] auto[1] auto[0] 19754 1 T5 182 T1 440 T2 212
auto[0] auto[1] auto[1] auto[1] auto[1] 4832 1 T1 528 T2 38 T3 226
auto[1] auto[0] auto[0] auto[0] auto[0] 38598 1 T5 58 T1 758 T6 98
auto[1] auto[0] auto[0] auto[0] auto[1] 3398 1 T1 30 T6 66 T3 10
auto[1] auto[0] auto[0] auto[1] auto[0] 30926 1 T5 74 T1 1250 T2 58
auto[1] auto[0] auto[0] auto[1] auto[1] 7590 1 T3 56 T7 178 T9 204
auto[1] auto[0] auto[1] auto[0] auto[0] 27304 1 T5 40 T1 1466 T6 94
auto[1] auto[0] auto[1] auto[0] auto[1] 7180 1 T5 20 T1 310 T2 22
auto[1] auto[0] auto[1] auto[1] auto[0] 56766 1 T5 170 T1 1816 T2 454
auto[1] auto[0] auto[1] auto[1] auto[1] 13092 1 T5 70 T1 538 T2 214
auto[1] auto[1] auto[0] auto[0] auto[0] 86082 1 T5 50 T1 1202 T6 38
auto[1] auto[1] auto[0] auto[0] auto[1] 5974 1 T1 172 T6 98 T2 2
auto[1] auto[1] auto[0] auto[1] auto[0] 49656 1 T1 1168 T2 268 T3 520
auto[1] auto[1] auto[0] auto[1] auto[1] 12486 1 T1 618 T2 46 T3 56
auto[1] auto[1] auto[1] auto[0] auto[0] 43982 1 T5 76 T1 1770 T6 140
auto[1] auto[1] auto[1] auto[0] auto[1] 11502 1 T5 6 T1 370 T2 8
auto[1] auto[1] auto[1] auto[1] auto[0] 83276 1 T5 156 T1 3162 T2 300
auto[1] auto[1] auto[1] auto[1] auto[1] 20068 1 T5 84 T1 588 T3 346

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