Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 145024084 1 T6 6434 T7 2258 T8 2350
auto[1] 244672 1 T8 346 T19 218 T23 728


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 144981026 1 T6 6434 T7 2258 T8 2314
auto[1] 287730 1 T8 382 T25 12 T19 378


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 144931782 1 T6 6434 T7 2258 T8 2412
auto[1] 336974 1 T8 284 T25 12 T19 318


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 134687210 1 T6 6434 T7 2258 T8 580
auto[1] 10581546 1 T8 2116 T25 1692 T19 3244


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 93674480 1 T6 4860 T7 2238 T8 2382
auto[1] 51594276 1 T6 1574 T7 20 T8 314


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 85300554 1 T6 4860 T7 2238 T8 140
auto[0] auto[0] auto[0] auto[0] auto[1] 49107402 1 T6 1574 T7 20 T8 120
auto[0] auto[0] auto[0] auto[1] auto[0] 18960 1 T8 60 T23 48 T34 18
auto[0] auto[0] auto[0] auto[1] auto[1] 4492 1 T8 16 T23 12 T12 36
auto[0] auto[0] auto[1] auto[0] auto[0] 7951472 1 T8 1882 T25 1680 T19 928
auto[0] auto[0] auto[1] auto[0] auto[1] 2419340 1 T8 68 T19 1868 T21 196
auto[0] auto[0] auto[1] auto[1] auto[0] 28736 1 T8 28 T19 82 T23 120
auto[0] auto[0] auto[1] auto[1] auto[1] 7974 1 T19 14 T23 6 T12 212
auto[0] auto[1] auto[0] auto[0] auto[0] 58514 1 T8 12 T19 34 T23 82
auto[0] auto[1] auto[0] auto[0] auto[1] 1168 1 T12 44 T122 6 T124 28
auto[0] auto[1] auto[0] auto[1] auto[0] 8100 1 T8 56 T34 50 T12 298
auto[0] auto[1] auto[0] auto[1] auto[1] 2556 1 T12 138 T122 60 T192 60
auto[0] auto[1] auto[1] auto[0] auto[0] 6056 1 T8 30 T19 86 T34 2
auto[0] auto[1] auto[1] auto[0] auto[1] 1448 1 T34 26 T12 28 T193 2
auto[0] auto[1] auto[1] auto[1] auto[0] 12230 1 T19 58 T34 56 T12 174
auto[0] auto[1] auto[1] auto[1] auto[1] 2780 1 T12 56 T193 46 T16 152
auto[1] auto[0] auto[0] auto[0] auto[0] 58968 1 T19 40 T21 40 T4 8084
auto[1] auto[0] auto[0] auto[0] auto[1] 2118 1 T166 8 T162 8 T15 44
auto[1] auto[0] auto[0] auto[1] auto[0] 19486 1 T34 56 T12 108 T73 94
auto[1] auto[0] auto[0] auto[1] auto[1] 4732 1 T166 68 T15 138 T16 152
auto[1] auto[0] auto[1] auto[0] auto[0] 15088 1 T21 50 T23 36 T12 180
auto[1] auto[0] auto[1] auto[0] auto[1] 4608 1 T19 14 T21 90 T23 22
auto[1] auto[0] auto[1] auto[1] auto[0] 29552 1 T23 108 T12 302 T122 68
auto[1] auto[0] auto[1] auto[1] auto[1] 7544 1 T19 64 T12 222 T125 56
auto[1] auto[1] auto[0] auto[0] auto[0] 60108 1 T8 18 T19 70 T23 30
auto[1] auto[1] auto[0] auto[0] auto[1] 3912 1 T8 10 T23 4 T12 42
auto[1] auto[1] auto[0] auto[1] auto[0] 30166 1 T8 78 T23 200 T34 50
auto[1] auto[1] auto[0] auto[1] auto[1] 5974 1 T8 70 T23 60 T73 134
auto[1] auto[1] auto[1] auto[0] auto[0] 27032 1 T8 40 T25 12 T19 130
auto[1] auto[1] auto[1] auto[0] auto[1] 6296 1 T8 30 T23 54 T12 142
auto[1] auto[1] auto[1] auto[1] auto[0] 49458 1 T8 38 T23 126 T12 682
auto[1] auto[1] auto[1] auto[1] auto[1] 11932 1 T23 48 T12 132 T165 158

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