Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 979
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T47 /workspace/coverage/default/4.clkmgr_sec_cm.1968759792 Jul 23 06:44:25 PM PDT 24 Jul 23 06:44:33 PM PDT 24 179249363 ps
T803 /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.178990101 Jul 23 06:46:47 PM PDT 24 Jul 23 06:46:54 PM PDT 24 25857410 ps
T804 /workspace/coverage/default/24.clkmgr_alert_test.2753589331 Jul 23 06:46:09 PM PDT 24 Jul 23 06:46:15 PM PDT 24 14915114 ps
T805 /workspace/coverage/default/38.clkmgr_stress_all.2109133345 Jul 23 06:47:18 PM PDT 24 Jul 23 06:47:47 PM PDT 24 6218443023 ps
T806 /workspace/coverage/default/19.clkmgr_trans.2358054786 Jul 23 06:45:44 PM PDT 24 Jul 23 06:45:50 PM PDT 24 161641560 ps
T807 /workspace/coverage/default/30.clkmgr_frequency_timeout.3487322545 Jul 23 06:46:39 PM PDT 24 Jul 23 06:46:51 PM PDT 24 1407664718 ps
T808 /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2480112283 Jul 23 06:45:40 PM PDT 24 Jul 23 06:45:46 PM PDT 24 23695627 ps
T809 /workspace/coverage/default/43.clkmgr_stress_all.527239005 Jul 23 06:47:42 PM PDT 24 Jul 23 06:47:50 PM PDT 24 106368589 ps
T810 /workspace/coverage/default/46.clkmgr_stress_all.4002014865 Jul 23 06:47:52 PM PDT 24 Jul 23 06:48:01 PM PDT 24 720309546 ps
T811 /workspace/coverage/default/25.clkmgr_div_intersig_mubi.4255980948 Jul 23 06:46:27 PM PDT 24 Jul 23 06:46:32 PM PDT 24 15446233 ps
T812 /workspace/coverage/default/35.clkmgr_stress_all.1541917559 Jul 23 06:47:20 PM PDT 24 Jul 23 06:48:15 PM PDT 24 7339242643 ps
T813 /workspace/coverage/default/49.clkmgr_smoke.474561702 Jul 23 06:48:11 PM PDT 24 Jul 23 06:48:14 PM PDT 24 15403713 ps
T814 /workspace/coverage/default/37.clkmgr_stress_all.3022210170 Jul 23 06:47:22 PM PDT 24 Jul 23 06:47:47 PM PDT 24 2303146010 ps
T815 /workspace/coverage/default/42.clkmgr_extclk.604451068 Jul 23 06:47:50 PM PDT 24 Jul 23 06:47:55 PM PDT 24 65108034 ps
T816 /workspace/coverage/default/49.clkmgr_peri.3914474973 Jul 23 06:48:09 PM PDT 24 Jul 23 06:48:12 PM PDT 24 14007291 ps
T817 /workspace/coverage/default/13.clkmgr_trans.1312988438 Jul 23 06:45:03 PM PDT 24 Jul 23 06:45:10 PM PDT 24 23132024 ps
T818 /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1757856291 Jul 23 06:47:22 PM PDT 24 Jul 23 06:47:30 PM PDT 24 17800954 ps
T819 /workspace/coverage/default/30.clkmgr_peri.85965396 Jul 23 06:46:37 PM PDT 24 Jul 23 06:46:44 PM PDT 24 39332090 ps
T820 /workspace/coverage/default/34.clkmgr_stress_all.2044236812 Jul 23 06:47:00 PM PDT 24 Jul 23 06:47:29 PM PDT 24 6407546623 ps
T821 /workspace/coverage/default/3.clkmgr_peri.3979551927 Jul 23 06:44:08 PM PDT 24 Jul 23 06:44:12 PM PDT 24 15587547 ps
T822 /workspace/coverage/default/23.clkmgr_extclk.3637021936 Jul 23 06:45:56 PM PDT 24 Jul 23 06:46:05 PM PDT 24 87931153 ps
T823 /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.3911504565 Jul 23 06:44:47 PM PDT 24 Jul 23 06:44:54 PM PDT 24 122322057 ps
T824 /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.775320127 Jul 23 06:46:11 PM PDT 24 Jul 23 06:46:15 PM PDT 24 22715600 ps
T825 /workspace/coverage/default/23.clkmgr_frequency_timeout.2805836957 Jul 23 06:46:09 PM PDT 24 Jul 23 06:46:15 PM PDT 24 293505132 ps
T58 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.221673895 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:11 PM PDT 24 112744441 ps
T826 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1100841358 Jul 23 06:31:19 PM PDT 24 Jul 23 06:31:36 PM PDT 24 211432345 ps
T827 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2514749605 Jul 23 06:31:34 PM PDT 24 Jul 23 06:31:47 PM PDT 24 44682354 ps
T80 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3967805029 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:26 PM PDT 24 35178833 ps
T59 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.270834644 Jul 23 06:31:20 PM PDT 24 Jul 23 06:31:38 PM PDT 24 256250630 ps
T110 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2500245491 Jul 23 06:31:25 PM PDT 24 Jul 23 06:31:40 PM PDT 24 17183996 ps
T828 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.116791799 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:23 PM PDT 24 298187854 ps
T151 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2895110133 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:31 PM PDT 24 152056591 ps
T61 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.256969529 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:26 PM PDT 24 115607592 ps
T829 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1576637774 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:25 PM PDT 24 27461048 ps
T60 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.272618494 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:33 PM PDT 24 176357459 ps
T830 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3723933943 Jul 23 06:31:21 PM PDT 24 Jul 23 06:31:37 PM PDT 24 100200526 ps
T175 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3658277010 Jul 23 06:31:19 PM PDT 24 Jul 23 06:31:35 PM PDT 24 35497390 ps
T831 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2319931678 Jul 23 06:31:24 PM PDT 24 Jul 23 06:31:40 PM PDT 24 22230078 ps
T832 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.68463666 Jul 23 06:31:28 PM PDT 24 Jul 23 06:31:43 PM PDT 24 26719889 ps
T833 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2263836131 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:26 PM PDT 24 153832576 ps
T834 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1685285971 Jul 23 06:31:27 PM PDT 24 Jul 23 06:31:42 PM PDT 24 13047145 ps
T835 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.600319339 Jul 23 06:31:36 PM PDT 24 Jul 23 06:31:49 PM PDT 24 52123869 ps
T836 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.2137135871 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:44 PM PDT 24 15439401 ps
T81 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2781389543 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:27 PM PDT 24 68573337 ps
T837 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.282359852 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:12 PM PDT 24 16365850 ps
T82 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.118346735 Jul 23 06:31:26 PM PDT 24 Jul 23 06:31:41 PM PDT 24 57201236 ps
T104 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.432294268 Jul 23 06:31:14 PM PDT 24 Jul 23 06:31:32 PM PDT 24 1265971494 ps
T838 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.606075565 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:44 PM PDT 24 78812750 ps
T83 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2006729608 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 43072922 ps
T62 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.4019213837 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:39 PM PDT 24 215809011 ps
T105 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2706604305 Jul 23 06:31:21 PM PDT 24 Jul 23 06:31:39 PM PDT 24 68401213 ps
T839 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3513893274 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:43 PM PDT 24 18113294 ps
T63 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.993327642 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:16 PM PDT 24 131986492 ps
T840 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.646281222 Jul 23 06:31:21 PM PDT 24 Jul 23 06:31:40 PM PDT 24 112051346 ps
T841 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2194809183 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:27 PM PDT 24 42853155 ps
T842 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.647449146 Jul 23 06:31:33 PM PDT 24 Jul 23 06:31:47 PM PDT 24 13142526 ps
T84 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.77695213 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:25 PM PDT 24 52766999 ps
T106 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3160223473 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:14 PM PDT 24 112270936 ps
T85 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1175438216 Jul 23 06:31:17 PM PDT 24 Jul 23 06:31:33 PM PDT 24 61067536 ps
T843 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2805728539 Jul 23 06:31:33 PM PDT 24 Jul 23 06:31:46 PM PDT 24 16138700 ps
T844 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3054950933 Jul 23 06:31:32 PM PDT 24 Jul 23 06:31:46 PM PDT 24 12709388 ps
T845 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.3377553419 Jul 23 06:31:30 PM PDT 24 Jul 23 06:31:44 PM PDT 24 48590363 ps
T111 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1722783621 Jul 23 06:31:20 PM PDT 24 Jul 23 06:31:39 PM PDT 24 386349201 ps
T846 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2510843474 Jul 23 06:31:07 PM PDT 24 Jul 23 06:31:16 PM PDT 24 32330861 ps
T847 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2345677034 Jul 23 06:31:35 PM PDT 24 Jul 23 06:31:48 PM PDT 24 12968343 ps
T86 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4221680709 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:22 PM PDT 24 47138732 ps
T191 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3460303244 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:31 PM PDT 24 69516257 ps
T848 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2991232067 Jul 23 06:31:37 PM PDT 24 Jul 23 06:31:49 PM PDT 24 12657482 ps
T849 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.668701035 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:43 PM PDT 24 13115378 ps
T850 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2212346188 Jul 23 06:31:32 PM PDT 24 Jul 23 06:31:46 PM PDT 24 12221711 ps
T64 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3106494937 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:33 PM PDT 24 142501660 ps
T133 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3634039053 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:45 PM PDT 24 195538819 ps
T851 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3026654663 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 37362984 ps
T87 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1178723763 Jul 23 06:31:14 PM PDT 24 Jul 23 06:31:28 PM PDT 24 261730838 ps
T107 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.623624368 Jul 23 06:31:27 PM PDT 24 Jul 23 06:31:44 PM PDT 24 252853837 ps
T852 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.564597262 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:38 PM PDT 24 84755746 ps
T65 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1334663856 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:24 PM PDT 24 111001610 ps
T853 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3157638453 Jul 23 06:31:18 PM PDT 24 Jul 23 06:31:35 PM PDT 24 102565715 ps
T112 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.441706283 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:31 PM PDT 24 122976270 ps
T854 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.322112889 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:19 PM PDT 24 55033313 ps
T855 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3921682866 Jul 23 06:31:09 PM PDT 24 Jul 23 06:31:18 PM PDT 24 52048503 ps
T139 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.921996482 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:25 PM PDT 24 90604388 ps
T856 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.969572570 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:23 PM PDT 24 48335226 ps
T857 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1696446765 Jul 23 06:31:28 PM PDT 24 Jul 23 06:31:43 PM PDT 24 42204175 ps
T858 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.249545483 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:27 PM PDT 24 141429428 ps
T859 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2022782135 Jul 23 06:31:19 PM PDT 24 Jul 23 06:31:35 PM PDT 24 17735848 ps
T860 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.978739844 Jul 23 06:31:20 PM PDT 24 Jul 23 06:31:36 PM PDT 24 13617918 ps
T861 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3847237773 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:13 PM PDT 24 58324429 ps
T862 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3485510116 Jul 23 06:31:07 PM PDT 24 Jul 23 06:31:18 PM PDT 24 467197683 ps
T134 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3395477577 Jul 23 06:31:09 PM PDT 24 Jul 23 06:31:19 PM PDT 24 189211632 ps
T863 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2018455760 Jul 23 06:31:04 PM PDT 24 Jul 23 06:31:11 PM PDT 24 17856805 ps
T864 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3093996877 Jul 23 06:31:08 PM PDT 24 Jul 23 06:31:17 PM PDT 24 69182123 ps
T865 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2055633750 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:23 PM PDT 24 628649148 ps
T866 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.537244572 Jul 23 06:31:34 PM PDT 24 Jul 23 06:31:47 PM PDT 24 12493179 ps
T115 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1445862389 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:46 PM PDT 24 229112454 ps
T138 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2052278617 Jul 23 06:31:25 PM PDT 24 Jul 23 06:31:41 PM PDT 24 296747560 ps
T147 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.777640776 Jul 23 06:31:24 PM PDT 24 Jul 23 06:31:40 PM PDT 24 77758005 ps
T867 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3973537744 Jul 23 06:31:28 PM PDT 24 Jul 23 06:31:43 PM PDT 24 32630658 ps
T868 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2833904338 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:19 PM PDT 24 53233089 ps
T869 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3932566756 Jul 23 06:31:25 PM PDT 24 Jul 23 06:31:42 PM PDT 24 170151533 ps
T870 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1598279449 Jul 23 06:31:08 PM PDT 24 Jul 23 06:31:18 PM PDT 24 20251691 ps
T871 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.805690027 Jul 23 06:31:20 PM PDT 24 Jul 23 06:31:35 PM PDT 24 39937350 ps
T135 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2603634248 Jul 23 06:31:26 PM PDT 24 Jul 23 06:31:43 PM PDT 24 191908961 ps
T872 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.360208313 Jul 23 06:31:23 PM PDT 24 Jul 23 06:31:39 PM PDT 24 15453578 ps
T873 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3269157887 Jul 23 06:31:09 PM PDT 24 Jul 23 06:31:23 PM PDT 24 879138197 ps
T874 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1655735877 Jul 23 06:31:27 PM PDT 24 Jul 23 06:31:42 PM PDT 24 23427764 ps
T875 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.124056468 Jul 23 06:31:33 PM PDT 24 Jul 23 06:31:47 PM PDT 24 13747914 ps
T876 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.25224442 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:27 PM PDT 24 176095009 ps
T113 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1336764434 Jul 23 06:31:08 PM PDT 24 Jul 23 06:31:19 PM PDT 24 96770326 ps
T877 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3610028126 Jul 23 06:31:32 PM PDT 24 Jul 23 06:31:46 PM PDT 24 11922893 ps
T878 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3221321254 Jul 23 06:31:17 PM PDT 24 Jul 23 06:31:34 PM PDT 24 49635502 ps
T140 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1352843243 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:33 PM PDT 24 244654345 ps
T879 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1288299789 Jul 23 06:31:21 PM PDT 24 Jul 23 06:31:37 PM PDT 24 88418810 ps
T880 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.24123401 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:28 PM PDT 24 11323260 ps
T143 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2394821991 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 293881775 ps
T881 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.162965831 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:25 PM PDT 24 227165341 ps
T882 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.956820957 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:27 PM PDT 24 455505207 ps
T883 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.355969361 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:31 PM PDT 24 17998711 ps
T884 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2279734670 Jul 23 06:31:25 PM PDT 24 Jul 23 06:31:41 PM PDT 24 184195230 ps
T149 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1593296464 Jul 23 06:31:04 PM PDT 24 Jul 23 06:31:12 PM PDT 24 51104158 ps
T885 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1345434622 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:09 PM PDT 24 13503970 ps
T886 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3905742345 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:12 PM PDT 24 30071401 ps
T887 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3078765730 Jul 23 06:31:30 PM PDT 24 Jul 23 06:31:47 PM PDT 24 265070515 ps
T888 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3305714056 Jul 23 06:31:20 PM PDT 24 Jul 23 06:31:37 PM PDT 24 295148162 ps
T889 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.93073293 Jul 23 06:31:09 PM PDT 24 Jul 23 06:31:18 PM PDT 24 127191748 ps
T890 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3017834793 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:31 PM PDT 24 2458587367 ps
T891 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4129107030 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 50927110 ps
T892 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4081666827 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:27 PM PDT 24 16526364 ps
T893 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.329411703 Jul 23 06:31:09 PM PDT 24 Jul 23 06:31:20 PM PDT 24 153274411 ps
T894 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.4070655215 Jul 23 06:31:35 PM PDT 24 Jul 23 06:31:49 PM PDT 24 142116207 ps
T895 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2381362731 Jul 23 06:31:09 PM PDT 24 Jul 23 06:31:18 PM PDT 24 14550460 ps
T136 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3879462954 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 123783015 ps
T150 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2591950466 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:22 PM PDT 24 89195187 ps
T896 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1858019764 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:21 PM PDT 24 42850200 ps
T897 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2769812294 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:38 PM PDT 24 13542460 ps
T898 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1707079175 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:22 PM PDT 24 39388383 ps
T137 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.352665190 Jul 23 06:31:14 PM PDT 24 Jul 23 06:31:29 PM PDT 24 185262693 ps
T899 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2947714509 Jul 23 06:31:17 PM PDT 24 Jul 23 06:31:34 PM PDT 24 42589079 ps
T900 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3962061177 Jul 23 06:31:35 PM PDT 24 Jul 23 06:31:48 PM PDT 24 14271666 ps
T901 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2292600586 Jul 23 06:31:26 PM PDT 24 Jul 23 06:31:41 PM PDT 24 14752497 ps
T902 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2957337607 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:25 PM PDT 24 197150492 ps
T903 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3231157970 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:21 PM PDT 24 48797594 ps
T904 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3598960449 Jul 23 06:31:04 PM PDT 24 Jul 23 06:31:12 PM PDT 24 200979663 ps
T905 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.215751934 Jul 23 06:31:07 PM PDT 24 Jul 23 06:31:15 PM PDT 24 17384530 ps
T906 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2189305978 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:31 PM PDT 24 13393882 ps
T907 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1156095138 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:30 PM PDT 24 45403801 ps
T145 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2852050193 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:24 PM PDT 24 133190081 ps
T908 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3006592110 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:10 PM PDT 24 22946155 ps
T909 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.933478215 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:43 PM PDT 24 40185494 ps
T910 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1086771764 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:25 PM PDT 24 759914339 ps
T911 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2682594579 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:12 PM PDT 24 49979386 ps
T912 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.80824480 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:28 PM PDT 24 264519076 ps
T913 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2070713345 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:22 PM PDT 24 40710888 ps
T141 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.657900382 Jul 23 06:31:21 PM PDT 24 Jul 23 06:31:39 PM PDT 24 135119361 ps
T914 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1826384808 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:30 PM PDT 24 23341361 ps
T915 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1543674180 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:27 PM PDT 24 28097768 ps
T916 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.988420412 Jul 23 06:31:24 PM PDT 24 Jul 23 06:31:40 PM PDT 24 62681321 ps
T917 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.542977405 Jul 23 06:31:23 PM PDT 24 Jul 23 06:31:39 PM PDT 24 29383089 ps
T918 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2218033598 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:29 PM PDT 24 13354133 ps
T919 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1707125857 Jul 23 06:31:35 PM PDT 24 Jul 23 06:31:48 PM PDT 24 11942939 ps
T920 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2090874724 Jul 23 06:31:13 PM PDT 24 Jul 23 06:31:28 PM PDT 24 269662920 ps
T921 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1766430467 Jul 23 06:31:24 PM PDT 24 Jul 23 06:31:40 PM PDT 24 62407489 ps
T922 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1517546494 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 305921201 ps
T116 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.729351557 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:32 PM PDT 24 203087982 ps
T923 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3698374105 Jul 23 06:31:32 PM PDT 24 Jul 23 06:31:47 PM PDT 24 34756356 ps
T924 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3667265846 Jul 23 06:31:31 PM PDT 24 Jul 23 06:31:45 PM PDT 24 171972440 ps
T925 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.4101300847 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 37729607 ps
T926 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3983731344 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:29 PM PDT 24 100005527 ps
T927 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.58244600 Jul 23 06:31:33 PM PDT 24 Jul 23 06:31:47 PM PDT 24 33591577 ps
T928 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.871749787 Jul 23 06:31:26 PM PDT 24 Jul 23 06:31:42 PM PDT 24 229643411 ps
T929 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3988564950 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:39 PM PDT 24 171649431 ps
T930 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2562017878 Jul 23 06:31:30 PM PDT 24 Jul 23 06:31:44 PM PDT 24 30537303 ps
T931 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3402998493 Jul 23 06:31:31 PM PDT 24 Jul 23 06:31:45 PM PDT 24 125453905 ps
T114 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.432664710 Jul 23 06:31:14 PM PDT 24 Jul 23 06:31:30 PM PDT 24 126325182 ps
T932 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.642541607 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:31 PM PDT 24 27764759 ps
T142 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2021055027 Jul 23 06:31:19 PM PDT 24 Jul 23 06:31:36 PM PDT 24 71638150 ps
T933 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3444151827 Jul 23 06:31:31 PM PDT 24 Jul 23 06:31:44 PM PDT 24 14482594 ps
T934 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3345686003 Jul 23 06:31:14 PM PDT 24 Jul 23 06:31:29 PM PDT 24 108785664 ps
T148 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3071540199 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:31 PM PDT 24 49439929 ps
T117 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1330729589 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:21 PM PDT 24 180228979 ps
T144 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.543402739 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 190092741 ps
T935 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2167675302 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:44 PM PDT 24 23302005 ps
T936 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.901143494 Jul 23 06:31:28 PM PDT 24 Jul 23 06:31:45 PM PDT 24 76077632 ps
T937 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2076733157 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:38 PM PDT 24 43018305 ps
T938 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1622939394 Jul 23 06:31:37 PM PDT 24 Jul 23 06:31:49 PM PDT 24 16456403 ps
T939 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2397269643 Jul 23 06:31:09 PM PDT 24 Jul 23 06:31:19 PM PDT 24 71510747 ps
T940 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.516648472 Jul 23 06:31:20 PM PDT 24 Jul 23 06:31:36 PM PDT 24 18616772 ps
T941 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2773275341 Jul 23 06:31:08 PM PDT 24 Jul 23 06:31:17 PM PDT 24 16110459 ps
T942 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4109758585 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:23 PM PDT 24 29655939 ps
T943 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2296724941 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:24 PM PDT 24 197600737 ps
T944 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.643786264 Jul 23 06:31:20 PM PDT 24 Jul 23 06:31:38 PM PDT 24 411920540 ps
T945 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1193352326 Jul 23 06:31:23 PM PDT 24 Jul 23 06:31:39 PM PDT 24 207742986 ps
T946 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3429419594 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:25 PM PDT 24 74898045 ps
T947 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1499080725 Jul 23 06:31:23 PM PDT 24 Jul 23 06:31:39 PM PDT 24 63982582 ps
T948 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3517668861 Jul 23 06:31:02 PM PDT 24 Jul 23 06:31:14 PM PDT 24 989429774 ps
T949 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.132957511 Jul 23 06:31:30 PM PDT 24 Jul 23 06:31:44 PM PDT 24 13265503 ps
T950 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3557935778 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:40 PM PDT 24 78858821 ps
T951 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1526566014 Jul 23 06:31:35 PM PDT 24 Jul 23 06:31:48 PM PDT 24 15974998 ps
T952 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3391637789 Jul 23 06:31:19 PM PDT 24 Jul 23 06:31:36 PM PDT 24 323530817 ps
T953 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.88490823 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:31 PM PDT 24 130927392 ps
T954 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3590455438 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:21 PM PDT 24 65896769 ps
T108 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3218588932 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:26 PM PDT 24 236537930 ps
T955 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1000226826 Jul 23 06:31:24 PM PDT 24 Jul 23 06:31:41 PM PDT 24 245216429 ps
T956 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.2765207717 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 56136052 ps
T957 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.808951798 Jul 23 06:31:35 PM PDT 24 Jul 23 06:31:48 PM PDT 24 35010278 ps
T958 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2107267967 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:31 PM PDT 24 43183039 ps
T959 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1648065829 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:19 PM PDT 24 75259311 ps
T960 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1347657878 Jul 23 06:31:37 PM PDT 24 Jul 23 06:31:49 PM PDT 24 36033949 ps
T961 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3457380355 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:23 PM PDT 24 338037322 ps
T962 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2212158790 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:30 PM PDT 24 18831966 ps
T963 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2584530317 Jul 23 06:31:35 PM PDT 24 Jul 23 06:31:48 PM PDT 24 13362003 ps
T964 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3800456131 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:29 PM PDT 24 46814710 ps
T965 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.785496931 Jul 23 06:31:19 PM PDT 24 Jul 23 06:31:37 PM PDT 24 88846829 ps
T966 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2806967228 Jul 23 06:31:19 PM PDT 24 Jul 23 06:31:36 PM PDT 24 88063480 ps
T967 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.541492876 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:39 PM PDT 24 70629252 ps
T968 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.668767479 Jul 23 06:31:29 PM PDT 24 Jul 23 06:31:44 PM PDT 24 64475555 ps
T146 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3486939254 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:40 PM PDT 24 355363823 ps
T118 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2550404525 Jul 23 06:31:15 PM PDT 24 Jul 23 06:31:30 PM PDT 24 216601568 ps
T969 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2852317519 Jul 23 06:31:31 PM PDT 24 Jul 23 06:31:45 PM PDT 24 12556474 ps
T970 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1153806271 Jul 23 06:31:11 PM PDT 24 Jul 23 06:31:22 PM PDT 24 23299503 ps
T971 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4088548797 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:13 PM PDT 24 218116614 ps
T972 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2327287476 Jul 23 06:31:12 PM PDT 24 Jul 23 06:31:26 PM PDT 24 257169019 ps
T973 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3672222384 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 40908615 ps
T974 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2005017733 Jul 23 06:31:22 PM PDT 24 Jul 23 06:31:38 PM PDT 24 24070978 ps
T975 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2305621935 Jul 23 06:31:17 PM PDT 24 Jul 23 06:31:34 PM PDT 24 81909146 ps
T976 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1899397091 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:15 PM PDT 24 491043875 ps
T977 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1259888759 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 38546395 ps
T978 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1056617274 Jul 23 06:31:08 PM PDT 24 Jul 23 06:31:17 PM PDT 24 40170053 ps
T979 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.4032290306 Jul 23 06:31:16 PM PDT 24 Jul 23 06:31:32 PM PDT 24 95595036 ps

Test location /workspace/coverage/default/29.clkmgr_frequency.3466635576
Short name T1
Test name
Test status
Simulation time 1396390910 ps
CPU time 9.16 seconds
Started Jul 23 06:46:37 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 200492 kb
Host smart-aad211d7-9510-4d4a-8f0f-43ab0c3ef3e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466635576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3466635576
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.3110878957
Short name T12
Test name
Test status
Simulation time 132374126916 ps
CPU time 636.69 seconds
Started Jul 23 06:45:29 PM PDT 24
Finished Jul 23 06:56:09 PM PDT 24
Peak memory 217248 kb
Host smart-91ae70aa-dfc1-4ede-b98b-987897a2313a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3110878957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3110878957
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3213785414
Short name T6
Test name
Test status
Simulation time 136623488 ps
CPU time 1.31 seconds
Started Jul 23 06:45:39 PM PDT 24
Finished Jul 23 06:45:47 PM PDT 24
Peak memory 200448 kb
Host smart-c8abce1a-c51d-44dc-9b8e-a912536acdff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213785414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.3213785414
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3634039053
Short name T133
Test name
Test status
Simulation time 195538819 ps
CPU time 2.14 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:45 PM PDT 24
Peak memory 209240 kb
Host smart-e867c6fc-efff-439e-909e-7d831a057e31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634039053 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.3634039053
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.2489621295
Short name T39
Test name
Test status
Simulation time 969542799 ps
CPU time 3.7 seconds
Started Jul 23 06:44:56 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 200632 kb
Host smart-8cd2a057-5f25-48c5-97a1-fb1bbbd51901
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489621295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2489621295
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.181694840
Short name T22
Test name
Test status
Simulation time 50710053 ps
CPU time 0.85 seconds
Started Jul 23 06:45:16 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 200380 kb
Host smart-a5f65e8c-aeb5-4645-889d-7bf41ee9f360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181694840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.181694840
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.446043987
Short name T46
Test name
Test status
Simulation time 152403154 ps
CPU time 2.03 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 215696 kb
Host smart-d69c6f64-9c3b-4649-b1b3-be5d87a9a2d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446043987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_sec_cm.446043987
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.301322922
Short name T23
Test name
Test status
Simulation time 60050021 ps
CPU time 0.99 seconds
Started Jul 23 06:45:18 PM PDT 24
Finished Jul 23 06:45:21 PM PDT 24
Peak memory 200452 kb
Host smart-157342ed-44b6-40b3-a7c8-3895ba1c18d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301322922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.clkmgr_div_intersig_mubi.301322922
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.4112017747
Short name T217
Test name
Test status
Simulation time 78258109 ps
CPU time 0.98 seconds
Started Jul 23 06:44:56 PM PDT 24
Finished Jul 23 06:45:02 PM PDT 24
Peak memory 200516 kb
Host smart-20b92006-574f-44e0-92c5-03d24af43652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112017747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.4112017747
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.432294268
Short name T104
Test name
Test status
Simulation time 1265971494 ps
CPU time 5.61 seconds
Started Jul 23 06:31:14 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 200860 kb
Host smart-e0530470-881b-4ddc-a666-083e991d2fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432294268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.clkmgr_tl_intg_err.432294268
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.2478214480
Short name T127
Test name
Test status
Simulation time 25540253 ps
CPU time 0.92 seconds
Started Jul 23 06:44:02 PM PDT 24
Finished Jul 23 06:44:06 PM PDT 24
Peak memory 200436 kb
Host smart-3326bb04-27bd-4020-ab06-6c89826a7a69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478214480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2478214480
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.1767001885
Short name T15
Test name
Test status
Simulation time 146246457727 ps
CPU time 883.67 seconds
Started Jul 23 06:46:26 PM PDT 24
Finished Jul 23 07:01:13 PM PDT 24
Peak memory 217288 kb
Host smart-9df3067c-b69d-4dd9-9edb-1500e98cb966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1767001885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.1767001885
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.270834644
Short name T59
Test name
Test status
Simulation time 256250630 ps
CPU time 3.06 seconds
Started Jul 23 06:31:20 PM PDT 24
Finished Jul 23 06:31:38 PM PDT 24
Peak memory 209344 kb
Host smart-8f73a61c-b0f7-47b1-8300-f2ed6a6e8d5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270834644 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.270834644
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.221673895
Short name T58
Test name
Test status
Simulation time 112744441 ps
CPU time 1.92 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:11 PM PDT 24
Peak memory 209156 kb
Host smart-1ef03382-1ea0-4a2e-8534-b7433a9d3597
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221673895 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.clkmgr_shadow_reg_errors.221673895
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.526619605
Short name T9
Test name
Test status
Simulation time 1095921903 ps
CPU time 6.19 seconds
Started Jul 23 06:47:27 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 200492 kb
Host smart-b44243d3-8f51-473d-adce-b3262dea493d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526619605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.526619605
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.1164613636
Short name T34
Test name
Test status
Simulation time 51716694 ps
CPU time 0.88 seconds
Started Jul 23 06:45:29 PM PDT 24
Finished Jul 23 06:45:33 PM PDT 24
Peak memory 200456 kb
Host smart-deee16f9-efd7-48e4-9b35-e0abbad63261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164613636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1164613636
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1336764434
Short name T113
Test name
Test status
Simulation time 96770326 ps
CPU time 2.45 seconds
Started Jul 23 06:31:08 PM PDT 24
Finished Jul 23 06:31:19 PM PDT 24
Peak memory 200864 kb
Host smart-09e177b1-bdf6-4208-9616-75b329c10a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336764434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1336764434
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.349331078
Short name T3
Test name
Test status
Simulation time 565810556 ps
CPU time 2.7 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:44:00 PM PDT 24
Peak memory 200372 kb
Host smart-eb4cb9ad-0e5b-4c6d-b8d7-c4b641fba15c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349331078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.349331078
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.325947573
Short name T254
Test name
Test status
Simulation time 920779508 ps
CPU time 3.56 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:02 PM PDT 24
Peak memory 200624 kb
Host smart-1fc3e8a6-743e-4553-bc97-01d79d2b099f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325947573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.325947573
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.3312315872
Short name T307
Test name
Test status
Simulation time 49577475 ps
CPU time 1.01 seconds
Started Jul 23 06:45:48 PM PDT 24
Finished Jul 23 06:45:55 PM PDT 24
Peak memory 200464 kb
Host smart-3eb1bf7e-b074-448e-a54d-5ae1b482a61a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312315872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.3312315872
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2852050193
Short name T145
Test name
Test status
Simulation time 133190081 ps
CPU time 1.85 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:24 PM PDT 24
Peak memory 209304 kb
Host smart-f03ca60b-597b-4fb4-a4d1-a847667a28fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852050193 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.2852050193
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.4286934540
Short name T102
Test name
Test status
Simulation time 219942771 ps
CPU time 1.41 seconds
Started Jul 23 06:44:57 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 200456 kb
Host smart-c634dc31-3bb9-48a6-bb52-eb6bdd0da7dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286934540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.4286934540
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3160223473
Short name T106
Test name
Test status
Simulation time 112270936 ps
CPU time 1.79 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 200900 kb
Host smart-a98f8658-2ce8-45e5-b4a3-83b331e99bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160223473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.3160223473
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.441706283
Short name T112
Test name
Test status
Simulation time 122976270 ps
CPU time 1.98 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200720 kb
Host smart-9447badb-b1d2-4e0d-bcec-62b6b5a9f24a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441706283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_tl_intg_err.441706283
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1330729589
Short name T117
Test name
Test status
Simulation time 180228979 ps
CPU time 2.05 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:21 PM PDT 24
Peak memory 200828 kb
Host smart-27c4c001-55b8-4406-abc6-ad5692eabd7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330729589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.1330729589
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3847237773
Short name T861
Test name
Test status
Simulation time 58324429 ps
CPU time 1.76 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:13 PM PDT 24
Peak memory 200728 kb
Host smart-63b9ed25-cde5-4569-84a6-30c2107faf17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847237773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.3847237773
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1086771764
Short name T910
Test name
Test status
Simulation time 759914339 ps
CPU time 4.91 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:25 PM PDT 24
Peak memory 200860 kb
Host smart-f1fb51a9-69f0-4daf-8852-7f89cf99db82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086771764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.1086771764
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2018455760
Short name T863
Test name
Test status
Simulation time 17856805 ps
CPU time 0.79 seconds
Started Jul 23 06:31:04 PM PDT 24
Finished Jul 23 06:31:11 PM PDT 24
Peak memory 200720 kb
Host smart-b23caf84-8775-4107-a13f-567fb550d0e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018455760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.2018455760
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3921682866
Short name T855
Test name
Test status
Simulation time 52048503 ps
CPU time 0.92 seconds
Started Jul 23 06:31:09 PM PDT 24
Finished Jul 23 06:31:18 PM PDT 24
Peak memory 200852 kb
Host smart-53bda9a0-24e7-4a08-887b-35ac6439faa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921682866 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.3921682866
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2682594579
Short name T911
Test name
Test status
Simulation time 49979386 ps
CPU time 0.93 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 200592 kb
Host smart-4ed67020-3873-45ed-a70f-f62faebde40e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682594579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.2682594579
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1345434622
Short name T885
Test name
Test status
Simulation time 13503970 ps
CPU time 0.66 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 199348 kb
Host smart-8ae68f94-f026-4f64-8a6e-af0ae6f84ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345434622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1345434622
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.2765207717
Short name T956
Test name
Test status
Simulation time 56136052 ps
CPU time 1.04 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 200768 kb
Host smart-c0868815-139f-4e84-a374-59dba00723ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765207717 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.2765207717
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4088548797
Short name T971
Test name
Test status
Simulation time 218116614 ps
CPU time 2.15 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:13 PM PDT 24
Peak memory 209376 kb
Host smart-8fa78572-a950-4c49-a186-8860b265e440
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088548797 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.4088548797
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4129107030
Short name T891
Test name
Test status
Simulation time 50927110 ps
CPU time 1.54 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 200900 kb
Host smart-6dcbceee-23ec-4c06-9eb5-1e2968a4fa69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129107030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.4129107030
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3517668861
Short name T948
Test name
Test status
Simulation time 989429774 ps
CPU time 4.97 seconds
Started Jul 23 06:31:02 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 200812 kb
Host smart-80207164-a5b3-4a40-a69a-57014c17d3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517668861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.3517668861
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3598960449
Short name T904
Test name
Test status
Simulation time 200979663 ps
CPU time 1.58 seconds
Started Jul 23 06:31:04 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 200748 kb
Host smart-629cac4c-98f2-4542-9272-a7a74c4ad38b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598960449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.3598960449
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.162965831
Short name T881
Test name
Test status
Simulation time 227165341 ps
CPU time 4.42 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:25 PM PDT 24
Peak memory 200880 kb
Host smart-bd2beaca-cf2a-4c29-9779-5a867d90ede8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162965831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_bit_bash.162965831
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3026654663
Short name T851
Test name
Test status
Simulation time 37362984 ps
CPU time 0.83 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 200740 kb
Host smart-cb7cb54c-3c5c-4bca-b2b9-93a761f525a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026654663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.3026654663
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3006592110
Short name T908
Test name
Test status
Simulation time 22946155 ps
CPU time 1.23 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:10 PM PDT 24
Peak memory 200720 kb
Host smart-de3be803-9335-42fa-a96f-f8c364e5dd2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006592110 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.3006592110
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.322112889
Short name T854
Test name
Test status
Simulation time 55033313 ps
CPU time 0.89 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:19 PM PDT 24
Peak memory 200788 kb
Host smart-0ffddfec-a90b-4454-b9a3-01bb910e1c5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322112889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.c
lkmgr_csr_rw.322112889
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3905742345
Short name T886
Test name
Test status
Simulation time 30071401 ps
CPU time 0.68 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 199236 kb
Host smart-2a1b0987-afb9-4d56-a312-6ea0e4ec7295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905742345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.3905742345
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2006729608
Short name T83
Test name
Test status
Simulation time 43072922 ps
CPU time 0.96 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 200780 kb
Host smart-8db60846-404f-4672-94b5-d67d0a43f1c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006729608 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.2006729608
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.993327642
Short name T63
Test name
Test status
Simulation time 131986492 ps
CPU time 2.29 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:16 PM PDT 24
Peak memory 209316 kb
Host smart-39693f5c-37bf-4237-a537-5788d91e0a2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993327642 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.clkmgr_shadow_reg_errors.993327642
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1899397091
Short name T976
Test name
Test status
Simulation time 491043875 ps
CPU time 3.59 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:15 PM PDT 24
Peak memory 210360 kb
Host smart-c5eab943-a46f-4f89-8b84-a5461af65313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899397091 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.1899397091
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3485510116
Short name T862
Test name
Test status
Simulation time 467197683 ps
CPU time 3.91 seconds
Started Jul 23 06:31:07 PM PDT 24
Finished Jul 23 06:31:18 PM PDT 24
Peak memory 200844 kb
Host smart-e3409831-ef20-4632-a6f1-2385f50eb1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485510116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.3485510116
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3672222384
Short name T973
Test name
Test status
Simulation time 40908615 ps
CPU time 0.99 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 200740 kb
Host smart-df9e0fd4-5b0d-4b14-994b-4e7c2369068e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672222384 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.3672222384
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3800456131
Short name T964
Test name
Test status
Simulation time 46814710 ps
CPU time 0.83 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:29 PM PDT 24
Peak memory 200584 kb
Host smart-b2fd5ff7-5de0-41c8-8cec-2f502527976e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800456131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3800456131
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2218033598
Short name T918
Test name
Test status
Simulation time 13354133 ps
CPU time 0.69 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:29 PM PDT 24
Peak memory 199308 kb
Host smart-30143653-5371-40e8-8456-7026125c5a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218033598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.2218033598
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.642541607
Short name T932
Test name
Test status
Simulation time 27764759 ps
CPU time 0.91 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200768 kb
Host smart-6fe40a55-2d0c-48b1-8cd3-4083d559f5f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642541607 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.642541607
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2021055027
Short name T142
Test name
Test status
Simulation time 71638150 ps
CPU time 1.31 seconds
Started Jul 23 06:31:19 PM PDT 24
Finished Jul 23 06:31:36 PM PDT 24
Peak memory 201016 kb
Host smart-a83ff73a-e3a8-443f-bf8e-edd4c570285f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021055027 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.2021055027
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1352843243
Short name T140
Test name
Test status
Simulation time 244654345 ps
CPU time 2.75 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:33 PM PDT 24
Peak memory 201424 kb
Host smart-7c0cf5af-fb31-492f-9657-d1436ee8af80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352843243 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.1352843243
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2090874724
Short name T920
Test name
Test status
Simulation time 269662920 ps
CPU time 3.62 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:28 PM PDT 24
Peak memory 200844 kb
Host smart-59b95a2e-f10f-4540-9b99-a1248e40c8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090874724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.2090874724
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2305621935
Short name T975
Test name
Test status
Simulation time 81909146 ps
CPU time 1.7 seconds
Started Jul 23 06:31:17 PM PDT 24
Finished Jul 23 06:31:34 PM PDT 24
Peak memory 200876 kb
Host smart-3d9a40b9-f170-4fb0-b1ea-12d31465a976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305621935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.2305621935
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2895110133
Short name T151
Test name
Test status
Simulation time 152056591 ps
CPU time 1.62 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200868 kb
Host smart-5e968925-f1b8-40e7-a778-fd1a87c76a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895110133 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.2895110133
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1175438216
Short name T85
Test name
Test status
Simulation time 61067536 ps
CPU time 0.95 seconds
Started Jul 23 06:31:17 PM PDT 24
Finished Jul 23 06:31:33 PM PDT 24
Peak memory 200740 kb
Host smart-458d2601-70af-418e-b68d-26c948fb0396
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175438216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.1175438216
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.805690027
Short name T871
Test name
Test status
Simulation time 39937350 ps
CPU time 0.71 seconds
Started Jul 23 06:31:20 PM PDT 24
Finished Jul 23 06:31:35 PM PDT 24
Peak memory 199268 kb
Host smart-fda61ddf-bc9c-46fb-a89c-e19c6767a0ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805690027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk
mgr_intr_test.805690027
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1517546494
Short name T922
Test name
Test status
Simulation time 305921201 ps
CPU time 2.01 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 200880 kb
Host smart-171e2724-936b-48b3-baee-731dc409a1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517546494 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.1517546494
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.88490823
Short name T953
Test name
Test status
Simulation time 130927392 ps
CPU time 2.19 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 209308 kb
Host smart-9177af4c-5947-4032-a72f-99614cb6ccae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88490823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.clkmgr_shadow_reg_errors.88490823
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3879462954
Short name T136
Test name
Test status
Simulation time 123783015 ps
CPU time 1.87 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 217320 kb
Host smart-abeebf29-0d88-4b26-a097-387a28ae57d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879462954 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3879462954
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2947714509
Short name T899
Test name
Test status
Simulation time 42589079 ps
CPU time 1.52 seconds
Started Jul 23 06:31:17 PM PDT 24
Finished Jul 23 06:31:34 PM PDT 24
Peak memory 200756 kb
Host smart-516c7fd8-bf6d-469d-9eee-902b587a6e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947714509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.2947714509
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.4032290306
Short name T979
Test name
Test status
Simulation time 95595036 ps
CPU time 1.43 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 200880 kb
Host smart-c87928e8-ca47-41cb-9a86-c04e3d221084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032290306 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.4032290306
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2189305978
Short name T906
Test name
Test status
Simulation time 13393882 ps
CPU time 0.81 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200732 kb
Host smart-5cf0bc69-c883-4f78-be7f-16162c424425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189305978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.2189305978
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2022782135
Short name T859
Test name
Test status
Simulation time 17735848 ps
CPU time 0.68 seconds
Started Jul 23 06:31:19 PM PDT 24
Finished Jul 23 06:31:35 PM PDT 24
Peak memory 199268 kb
Host smart-794abb29-5842-45d2-a03e-184caf9d7d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022782135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.2022782135
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.4101300847
Short name T925
Test name
Test status
Simulation time 37729607 ps
CPU time 1.31 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 200888 kb
Host smart-f17c6d74-87db-4f80-89d5-2d3d0e8c2ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101300847 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.4101300847
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3106494937
Short name T64
Test name
Test status
Simulation time 142501660 ps
CPU time 2.44 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:33 PM PDT 24
Peak memory 201160 kb
Host smart-ed8d5401-5553-45e5-945c-d0861ba6d0df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106494937 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.3106494937
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.785496931
Short name T965
Test name
Test status
Simulation time 88846829 ps
CPU time 2.42 seconds
Started Jul 23 06:31:19 PM PDT 24
Finished Jul 23 06:31:37 PM PDT 24
Peak memory 200860 kb
Host smart-a0d16fbd-b2a6-4990-ac0d-04c691ba7e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785496931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_tl_errors.785496931
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2806967228
Short name T966
Test name
Test status
Simulation time 88063480 ps
CPU time 1.11 seconds
Started Jul 23 06:31:19 PM PDT 24
Finished Jul 23 06:31:36 PM PDT 24
Peak memory 200748 kb
Host smart-d40c756f-09ee-4845-9beb-df0955edc300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806967228 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.2806967228
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2500245491
Short name T110
Test name
Test status
Simulation time 17183996 ps
CPU time 0.76 seconds
Started Jul 23 06:31:25 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 200768 kb
Host smart-1f51e460-8edb-462c-90a8-c6f7b0beb397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500245491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.2500245491
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2319931678
Short name T831
Test name
Test status
Simulation time 22230078 ps
CPU time 0.7 seconds
Started Jul 23 06:31:24 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 199364 kb
Host smart-ac043d31-531f-4fb2-842a-869065b70f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319931678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.2319931678
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3157638453
Short name T853
Test name
Test status
Simulation time 102565715 ps
CPU time 1.18 seconds
Started Jul 23 06:31:18 PM PDT 24
Finished Jul 23 06:31:35 PM PDT 24
Peak memory 200768 kb
Host smart-8cd13d6c-da35-4936-91e2-c9568aa33343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157638453 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.3157638453
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3391637789
Short name T952
Test name
Test status
Simulation time 323530817 ps
CPU time 2.29 seconds
Started Jul 23 06:31:19 PM PDT 24
Finished Jul 23 06:31:36 PM PDT 24
Peak memory 216892 kb
Host smart-e164246b-8a41-4fb2-83cf-9c397bba008c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391637789 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.3391637789
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2394821991
Short name T143
Test name
Test status
Simulation time 293881775 ps
CPU time 2.29 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 209232 kb
Host smart-ad1b592d-1bbb-40ca-9d48-666cfc278ad5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394821991 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.2394821991
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3988564950
Short name T929
Test name
Test status
Simulation time 171649431 ps
CPU time 1.89 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200860 kb
Host smart-1675d789-917d-483c-804d-930965d74593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988564950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.3988564950
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1000226826
Short name T955
Test name
Test status
Simulation time 245216429 ps
CPU time 2.16 seconds
Started Jul 23 06:31:24 PM PDT 24
Finished Jul 23 06:31:41 PM PDT 24
Peak memory 200888 kb
Host smart-314cc0d5-9265-4c13-8a84-5b8ccd9860c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000226826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.1000226826
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1696446765
Short name T857
Test name
Test status
Simulation time 42204175 ps
CPU time 0.92 seconds
Started Jul 23 06:31:28 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 201024 kb
Host smart-f407a36c-4ecd-492f-8db5-65a593d10fa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696446765 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.1696446765
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.978739844
Short name T860
Test name
Test status
Simulation time 13617918 ps
CPU time 0.75 seconds
Started Jul 23 06:31:20 PM PDT 24
Finished Jul 23 06:31:36 PM PDT 24
Peak memory 200632 kb
Host smart-bd95b71d-b38e-40c1-8370-e8e0d355126e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978739844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
clkmgr_csr_rw.978739844
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.516648472
Short name T940
Test name
Test status
Simulation time 18616772 ps
CPU time 0.71 seconds
Started Jul 23 06:31:20 PM PDT 24
Finished Jul 23 06:31:36 PM PDT 24
Peak memory 199284 kb
Host smart-48d0b745-4b3b-411d-b698-16b7a1c6b112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516648472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_intr_test.516648472
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1499080725
Short name T947
Test name
Test status
Simulation time 63982582 ps
CPU time 1.32 seconds
Started Jul 23 06:31:23 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200752 kb
Host smart-348e7dd6-9344-4dae-b539-515ad52ee621
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499080725 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.1499080725
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.272618494
Short name T60
Test name
Test status
Simulation time 176357459 ps
CPU time 2.05 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:33 PM PDT 24
Peak memory 201208 kb
Host smart-96c7be41-52c8-49bc-93ae-9c0e407517f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272618494 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.clkmgr_shadow_reg_errors.272618494
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.543402739
Short name T144
Test name
Test status
Simulation time 190092741 ps
CPU time 2 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 209224 kb
Host smart-5980ab4c-3579-449b-aee2-834b4f46f176
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543402739 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.543402739
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1826384808
Short name T914
Test name
Test status
Simulation time 23341361 ps
CPU time 1.41 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:30 PM PDT 24
Peak memory 200804 kb
Host smart-8e746c19-49ed-4709-9cc2-299084577204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826384808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.1826384808
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3460303244
Short name T191
Test name
Test status
Simulation time 69516257 ps
CPU time 1.7 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200916 kb
Host smart-36ac901f-b446-4b6e-ba9b-e6a77a5a5e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460303244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.3460303244
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3723933943
Short name T830
Test name
Test status
Simulation time 100200526 ps
CPU time 1.32 seconds
Started Jul 23 06:31:21 PM PDT 24
Finished Jul 23 06:31:37 PM PDT 24
Peak memory 200712 kb
Host smart-31f769ae-6171-44c0-98c9-05d2fe8f4d87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723933943 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.3723933943
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2005017733
Short name T974
Test name
Test status
Simulation time 24070978 ps
CPU time 0.78 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:38 PM PDT 24
Peak memory 200780 kb
Host smart-34c47e32-f12f-4e9c-a653-ca9e1bfefc51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005017733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.2005017733
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2769812294
Short name T897
Test name
Test status
Simulation time 13542460 ps
CPU time 0.69 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:38 PM PDT 24
Peak memory 199264 kb
Host smart-8dd55ad8-3a3e-42ce-ae02-63f9d3fa6951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769812294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2769812294
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1193352326
Short name T945
Test name
Test status
Simulation time 207742986 ps
CPU time 1.76 seconds
Started Jul 23 06:31:23 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200808 kb
Host smart-377bdb7f-e3bf-445f-93fa-38f6cb7d1f30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193352326 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.1193352326
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.657900382
Short name T141
Test name
Test status
Simulation time 135119361 ps
CPU time 2.09 seconds
Started Jul 23 06:31:21 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 201128 kb
Host smart-47f389cb-7ccb-4e4d-ae6b-f9d65d53cf12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657900382 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.clkmgr_shadow_reg_errors.657900382
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.871749787
Short name T928
Test name
Test status
Simulation time 229643411 ps
CPU time 2.13 seconds
Started Jul 23 06:31:26 PM PDT 24
Finished Jul 23 06:31:42 PM PDT 24
Peak memory 217444 kb
Host smart-ebe1c9bc-f94e-4118-9c75-038770db52c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871749787 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.871749787
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3932566756
Short name T869
Test name
Test status
Simulation time 170151533 ps
CPU time 2.96 seconds
Started Jul 23 06:31:25 PM PDT 24
Finished Jul 23 06:31:42 PM PDT 24
Peak memory 200860 kb
Host smart-88e22dde-43f1-4ee0-a12f-d08acea7bef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932566756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.3932566756
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1722783621
Short name T111
Test name
Test status
Simulation time 386349201 ps
CPU time 3.64 seconds
Started Jul 23 06:31:20 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200872 kb
Host smart-0248b8c0-d3ce-4140-aaa2-358c8fc5e8d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722783621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.1722783621
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.542977405
Short name T917
Test name
Test status
Simulation time 29383089 ps
CPU time 1.09 seconds
Started Jul 23 06:31:23 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200868 kb
Host smart-29bc3040-6bb1-4eee-a37a-59af65fcb5a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542977405 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.542977405
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.360208313
Short name T872
Test name
Test status
Simulation time 15453578 ps
CPU time 0.86 seconds
Started Jul 23 06:31:23 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200748 kb
Host smart-a6159341-dda1-4ce9-91ab-c98cb6d2f0cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360208313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
clkmgr_csr_rw.360208313
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2076733157
Short name T937
Test name
Test status
Simulation time 43018305 ps
CPU time 0.77 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:38 PM PDT 24
Peak memory 199348 kb
Host smart-b3e4aabb-85f1-4ab9-8d68-f78837a221b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076733157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2076733157
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2279734670
Short name T884
Test name
Test status
Simulation time 184195230 ps
CPU time 1.44 seconds
Started Jul 23 06:31:25 PM PDT 24
Finished Jul 23 06:31:41 PM PDT 24
Peak memory 200756 kb
Host smart-d7d5a207-f280-4b74-a03e-64bbbaef5d7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279734670 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.2279734670
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2052278617
Short name T138
Test name
Test status
Simulation time 296747560 ps
CPU time 2.21 seconds
Started Jul 23 06:31:25 PM PDT 24
Finished Jul 23 06:31:41 PM PDT 24
Peak memory 201240 kb
Host smart-1d148af9-ecdc-4f13-8dc7-2184bbe539ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052278617 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.2052278617
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3305714056
Short name T888
Test name
Test status
Simulation time 295148162 ps
CPU time 2.46 seconds
Started Jul 23 06:31:20 PM PDT 24
Finished Jul 23 06:31:37 PM PDT 24
Peak memory 201140 kb
Host smart-5475ced1-0964-4bb5-b5ca-00cfe54b0d36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305714056 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.3305714056
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.646281222
Short name T840
Test name
Test status
Simulation time 112051346 ps
CPU time 2.82 seconds
Started Jul 23 06:31:21 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 200844 kb
Host smart-67e5a706-b5b7-4356-af48-95176ef6d548
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646281222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk
mgr_tl_errors.646281222
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.623624368
Short name T107
Test name
Test status
Simulation time 252853837 ps
CPU time 3.11 seconds
Started Jul 23 06:31:27 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 201048 kb
Host smart-b94ab45d-2f16-472f-b84c-224bc23f42c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623624368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_tl_intg_err.623624368
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.541492876
Short name T967
Test name
Test status
Simulation time 70629252 ps
CPU time 1.74 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 209084 kb
Host smart-0cb4c6ab-3d5b-470b-8525-fffe3fcf6ccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541492876 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.541492876
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.118346735
Short name T82
Test name
Test status
Simulation time 57201236 ps
CPU time 0.96 seconds
Started Jul 23 06:31:26 PM PDT 24
Finished Jul 23 06:31:41 PM PDT 24
Peak memory 200732 kb
Host smart-a1941e94-1718-4362-bc16-c16e955620a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118346735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
clkmgr_csr_rw.118346735
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2292600586
Short name T901
Test name
Test status
Simulation time 14752497 ps
CPU time 0.71 seconds
Started Jul 23 06:31:26 PM PDT 24
Finished Jul 23 06:31:41 PM PDT 24
Peak memory 199112 kb
Host smart-9ae9ceb1-0ddb-4a53-ab70-955edf8a1116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292600586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2292600586
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.564597262
Short name T852
Test name
Test status
Simulation time 84755746 ps
CPU time 1.41 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:38 PM PDT 24
Peak memory 200808 kb
Host smart-90a51a38-09b8-404b-a1c2-cc313f167451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564597262 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 17.clkmgr_same_csr_outstanding.564597262
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.4019213837
Short name T62
Test name
Test status
Simulation time 215809011 ps
CPU time 1.81 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200960 kb
Host smart-ba75a70a-444c-4913-9ef1-b32f699b753d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019213837 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.4019213837
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1288299789
Short name T879
Test name
Test status
Simulation time 88418810 ps
CPU time 1.43 seconds
Started Jul 23 06:31:21 PM PDT 24
Finished Jul 23 06:31:37 PM PDT 24
Peak memory 200820 kb
Host smart-e1f90b26-75ab-41b3-bd70-0c4690f0ad59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288299789 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1288299789
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3557935778
Short name T950
Test name
Test status
Simulation time 78858821 ps
CPU time 2.38 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 200808 kb
Host smart-2444ad3b-bf3c-4699-951c-1398389e6b78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557935778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3557935778
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2706604305
Short name T105
Test name
Test status
Simulation time 68401213 ps
CPU time 1.87 seconds
Started Jul 23 06:31:21 PM PDT 24
Finished Jul 23 06:31:39 PM PDT 24
Peak memory 200864 kb
Host smart-0bf7b29c-17b7-48d9-adb8-aa30c0b96733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706604305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.2706604305
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3402998493
Short name T931
Test name
Test status
Simulation time 125453905 ps
CPU time 1.37 seconds
Started Jul 23 06:31:31 PM PDT 24
Finished Jul 23 06:31:45 PM PDT 24
Peak memory 200796 kb
Host smart-f0bd2f4b-743f-4b64-ae08-734e9c0cffa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402998493 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3402998493
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3973537744
Short name T867
Test name
Test status
Simulation time 32630658 ps
CPU time 0.79 seconds
Started Jul 23 06:31:28 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 200616 kb
Host smart-663a2bea-07e2-4248-9bc1-4099cfc04e92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973537744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.3973537744
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3698374105
Short name T923
Test name
Test status
Simulation time 34756356 ps
CPU time 0.73 seconds
Started Jul 23 06:31:32 PM PDT 24
Finished Jul 23 06:31:47 PM PDT 24
Peak memory 199308 kb
Host smart-29da7488-d343-45a5-8de0-54452196e077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698374105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.3698374105
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1655735877
Short name T874
Test name
Test status
Simulation time 23427764 ps
CPU time 1.04 seconds
Started Jul 23 06:31:27 PM PDT 24
Finished Jul 23 06:31:42 PM PDT 24
Peak memory 200708 kb
Host smart-43fa538d-8c4e-4aa3-a360-514f5417d58c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655735877 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1655735877
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.988420412
Short name T916
Test name
Test status
Simulation time 62681321 ps
CPU time 1.39 seconds
Started Jul 23 06:31:24 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 201056 kb
Host smart-1f06523c-decc-46f5-b17d-7376bee7bf36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988420412 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.clkmgr_shadow_reg_errors.988420412
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.777640776
Short name T147
Test name
Test status
Simulation time 77758005 ps
CPU time 1.63 seconds
Started Jul 23 06:31:24 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 201184 kb
Host smart-8f39a424-930b-4fd6-b7ff-55356bd828c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777640776 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.777640776
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3078765730
Short name T887
Test name
Test status
Simulation time 265070515 ps
CPU time 3.57 seconds
Started Jul 23 06:31:30 PM PDT 24
Finished Jul 23 06:31:47 PM PDT 24
Peak memory 200872 kb
Host smart-874b00b1-353e-4fc5-a63d-fb0de84ae6d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078765730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.3078765730
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1445862389
Short name T115
Test name
Test status
Simulation time 229112454 ps
CPU time 2.8 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:46 PM PDT 24
Peak memory 200928 kb
Host smart-e7207dc2-3d6c-49d5-8667-36a9d20c9bde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445862389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.1445862389
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2167675302
Short name T935
Test name
Test status
Simulation time 23302005 ps
CPU time 0.94 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 200880 kb
Host smart-e589920a-e353-4c61-a9cb-897871313315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167675302 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.2167675302
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.2137135871
Short name T836
Test name
Test status
Simulation time 15439401 ps
CPU time 0.76 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 200668 kb
Host smart-153d20ec-e667-4b9a-a05a-13455300bae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137135871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.2137135871
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3444151827
Short name T933
Test name
Test status
Simulation time 14482594 ps
CPU time 0.71 seconds
Started Jul 23 06:31:31 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 199288 kb
Host smart-fca95f96-b720-4fa9-9c25-55d13e4841ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444151827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.3444151827
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3667265846
Short name T924
Test name
Test status
Simulation time 171972440 ps
CPU time 1.63 seconds
Started Jul 23 06:31:31 PM PDT 24
Finished Jul 23 06:31:45 PM PDT 24
Peak memory 200836 kb
Host smart-526524bf-5db5-4857-abea-d83b0872ef1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667265846 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.3667265846
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2603634248
Short name T135
Test name
Test status
Simulation time 191908961 ps
CPU time 1.8 seconds
Started Jul 23 06:31:26 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 209332 kb
Host smart-357ce612-49b2-4b13-ada2-24e28f0c079d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603634248 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2603634248
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.901143494
Short name T936
Test name
Test status
Simulation time 76077632 ps
CPU time 2.62 seconds
Started Jul 23 06:31:28 PM PDT 24
Finished Jul 23 06:31:45 PM PDT 24
Peak memory 200876 kb
Host smart-013497e5-3a30-4e8d-a3e0-e98062b1d97f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901143494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_tl_errors.901143494
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.668767479
Short name T968
Test name
Test status
Simulation time 64475555 ps
CPU time 1.66 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 200912 kb
Host smart-086ea754-25b9-4f4b-8a00-248775400197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668767479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_tl_intg_err.668767479
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3429419594
Short name T946
Test name
Test status
Simulation time 74898045 ps
CPU time 1.59 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:25 PM PDT 24
Peak memory 200692 kb
Host smart-9d101193-da7a-452d-8f3f-bfd64df17643
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429419594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.3429419594
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3269157887
Short name T873
Test name
Test status
Simulation time 879138197 ps
CPU time 5.96 seconds
Started Jul 23 06:31:09 PM PDT 24
Finished Jul 23 06:31:23 PM PDT 24
Peak memory 200888 kb
Host smart-b78232bc-df54-4790-bde0-ab7df549392d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269157887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.3269157887
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.215751934
Short name T905
Test name
Test status
Simulation time 17384530 ps
CPU time 0.81 seconds
Started Jul 23 06:31:07 PM PDT 24
Finished Jul 23 06:31:15 PM PDT 24
Peak memory 200724 kb
Host smart-604a24f2-fba7-4a84-887e-c45577badea2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215751934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_hw_reset.215751934
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.969572570
Short name T856
Test name
Test status
Simulation time 48335226 ps
CPU time 1.03 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:23 PM PDT 24
Peak memory 200864 kb
Host smart-a22e2c67-6cb2-41cd-90b5-63690ba4de92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969572570 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.969572570
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2773275341
Short name T941
Test name
Test status
Simulation time 16110459 ps
CPU time 0.77 seconds
Started Jul 23 06:31:08 PM PDT 24
Finished Jul 23 06:31:17 PM PDT 24
Peak memory 200656 kb
Host smart-d64f45d1-33c7-4fbc-ab94-c4d7381e2902
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773275341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.2773275341
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.282359852
Short name T837
Test name
Test status
Simulation time 16365850 ps
CPU time 0.72 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 199232 kb
Host smart-4a496707-80a6-4398-93b2-3199ea7b8cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282359852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.282359852
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2833904338
Short name T868
Test name
Test status
Simulation time 53233089 ps
CPU time 1.28 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:19 PM PDT 24
Peak memory 200772 kb
Host smart-80ea9e1d-1abb-4e52-9225-756aa5023e50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833904338 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.2833904338
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1593296464
Short name T149
Test name
Test status
Simulation time 51104158 ps
CPU time 1.28 seconds
Started Jul 23 06:31:04 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 201000 kb
Host smart-994c3c62-7efe-40cc-8466-73bae2d095e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593296464 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.1593296464
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4221680709
Short name T86
Test name
Test status
Simulation time 47138732 ps
CPU time 1.48 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:22 PM PDT 24
Peak memory 201236 kb
Host smart-37f39456-1ed0-45b4-bef6-de2372fff6a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221680709 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.4221680709
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.116791799
Short name T828
Test name
Test status
Simulation time 298187854 ps
CPU time 2.72 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:23 PM PDT 24
Peak memory 200880 kb
Host smart-dcc816b2-45c7-4a0d-ae07-800831bd1609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116791799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.116791799
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3457380355
Short name T961
Test name
Test status
Simulation time 338037322 ps
CPU time 3.02 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:23 PM PDT 24
Peak memory 200912 kb
Host smart-775e38b2-ac6e-4274-8a5f-c8bce1269e37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457380355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3457380355
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.606075565
Short name T838
Test name
Test status
Simulation time 78812750 ps
CPU time 0.79 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 199296 kb
Host smart-d1e4a294-9cbb-486f-aaf5-f27c7e956fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606075565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clk
mgr_intr_test.606075565
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.668701035
Short name T849
Test name
Test status
Simulation time 13115378 ps
CPU time 0.72 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 199288 kb
Host smart-db0d759d-2d0e-47ae-9152-3f8d3a0fd270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668701035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clk
mgr_intr_test.668701035
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.132957511
Short name T949
Test name
Test status
Simulation time 13265503 ps
CPU time 0.69 seconds
Started Jul 23 06:31:30 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 199328 kb
Host smart-2fdbb215-7967-4e6c-859f-a0a31af50746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132957511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clk
mgr_intr_test.132957511
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.933478215
Short name T909
Test name
Test status
Simulation time 40185494 ps
CPU time 0.72 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 199264 kb
Host smart-caf19ccb-5c2b-46ea-a7fc-0cbc31ff69fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933478215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clk
mgr_intr_test.933478215
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2852317519
Short name T969
Test name
Test status
Simulation time 12556474 ps
CPU time 0.72 seconds
Started Jul 23 06:31:31 PM PDT 24
Finished Jul 23 06:31:45 PM PDT 24
Peak memory 199532 kb
Host smart-22128fa6-bdf6-4317-ae03-bbda5905fe6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852317519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.2852317519
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2562017878
Short name T930
Test name
Test status
Simulation time 30537303 ps
CPU time 0.71 seconds
Started Jul 23 06:31:30 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 199256 kb
Host smart-86d5742c-98b9-4ebf-b2c1-d3d94f2115ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562017878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2562017878
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1685285971
Short name T834
Test name
Test status
Simulation time 13047145 ps
CPU time 0.68 seconds
Started Jul 23 06:31:27 PM PDT 24
Finished Jul 23 06:31:42 PM PDT 24
Peak memory 199360 kb
Host smart-8cb4ee7a-776a-4e24-8e32-2f077ceef4da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685285971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.1685285971
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3513893274
Short name T839
Test name
Test status
Simulation time 18113294 ps
CPU time 0.67 seconds
Started Jul 23 06:31:29 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 199272 kb
Host smart-7be7220a-551c-4b4f-99bc-c9898fb9751a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513893274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.3513893274
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.3377553419
Short name T845
Test name
Test status
Simulation time 48590363 ps
CPU time 0.77 seconds
Started Jul 23 06:31:30 PM PDT 24
Finished Jul 23 06:31:44 PM PDT 24
Peak memory 199268 kb
Host smart-8d05243a-7816-43c1-a78a-0658173f0777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377553419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.3377553419
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3610028126
Short name T877
Test name
Test status
Simulation time 11922893 ps
CPU time 0.71 seconds
Started Jul 23 06:31:32 PM PDT 24
Finished Jul 23 06:31:46 PM PDT 24
Peak memory 199380 kb
Host smart-024127c9-edaf-41b3-8dc1-405d27c37561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610028126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.3610028126
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2055633750
Short name T865
Test name
Test status
Simulation time 628649148 ps
CPU time 3.03 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:23 PM PDT 24
Peak memory 200880 kb
Host smart-6adc35c0-039d-4cf4-b0e8-9ac2847218d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055633750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.2055633750
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3017834793
Short name T890
Test name
Test status
Simulation time 2458587367 ps
CPU time 9.82 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200924 kb
Host smart-3028d1ba-01d4-4de5-b0b4-f195e869d9c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017834793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.3017834793
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2510843474
Short name T846
Test name
Test status
Simulation time 32330861 ps
CPU time 0.83 seconds
Started Jul 23 06:31:07 PM PDT 24
Finished Jul 23 06:31:16 PM PDT 24
Peak memory 200704 kb
Host smart-c8fdac14-5aee-461d-bd4d-c35511f08224
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510843474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.2510843474
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1648065829
Short name T959
Test name
Test status
Simulation time 75259311 ps
CPU time 1.07 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:19 PM PDT 24
Peak memory 200868 kb
Host smart-e1163063-ec44-404d-b490-d934203a913e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648065829 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.1648065829
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2381362731
Short name T895
Test name
Test status
Simulation time 14550460 ps
CPU time 0.79 seconds
Started Jul 23 06:31:09 PM PDT 24
Finished Jul 23 06:31:18 PM PDT 24
Peak memory 200748 kb
Host smart-0a704139-c484-4267-9631-709f79e9ac8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381362731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.2381362731
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.24123401
Short name T880
Test name
Test status
Simulation time 11323260 ps
CPU time 0.66 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:28 PM PDT 24
Peak memory 199244 kb
Host smart-1afa3cff-9748-4339-b68c-eeb63d60da6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24123401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmg
r_intr_test.24123401
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1707079175
Short name T898
Test name
Test status
Simulation time 39388383 ps
CPU time 1.21 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:22 PM PDT 24
Peak memory 200884 kb
Host smart-fa2ace61-9830-41a4-be2c-7bcb13b6ce82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707079175 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.1707079175
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.352665190
Short name T137
Test name
Test status
Simulation time 185262693 ps
CPU time 2.21 seconds
Started Jul 23 06:31:14 PM PDT 24
Finished Jul 23 06:31:29 PM PDT 24
Peak memory 201148 kb
Host smart-8d7ba25b-76ba-49e5-9f94-20826c23d267
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352665190 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.clkmgr_shadow_reg_errors.352665190
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.921996482
Short name T139
Test name
Test status
Simulation time 90604388 ps
CPU time 2.03 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:25 PM PDT 24
Peak memory 209288 kb
Host smart-f24f7670-78a4-4df1-9866-dd65bbdef2a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921996482 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.921996482
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2327287476
Short name T972
Test name
Test status
Simulation time 257169019 ps
CPU time 2.48 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:26 PM PDT 24
Peak memory 201068 kb
Host smart-aa603f8d-5a56-4cd7-b5ff-ae878c5b4e29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327287476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2327287476
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3218588932
Short name T108
Test name
Test status
Simulation time 236537930 ps
CPU time 2.68 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:26 PM PDT 24
Peak memory 200840 kb
Host smart-141f9fc7-f757-4870-b575-3a3214679c40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218588932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.3218588932
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.68463666
Short name T832
Test name
Test status
Simulation time 26719889 ps
CPU time 0.73 seconds
Started Jul 23 06:31:28 PM PDT 24
Finished Jul 23 06:31:43 PM PDT 24
Peak memory 199292 kb
Host smart-4c69baa2-7055-4649-ab93-392b483102df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68463666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkm
gr_intr_test.68463666
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.58244600
Short name T927
Test name
Test status
Simulation time 33591577 ps
CPU time 0.7 seconds
Started Jul 23 06:31:33 PM PDT 24
Finished Jul 23 06:31:47 PM PDT 24
Peak memory 199252 kb
Host smart-dd9c5a96-cb19-4b81-b762-1627e93bcce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58244600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkm
gr_intr_test.58244600
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.124056468
Short name T875
Test name
Test status
Simulation time 13747914 ps
CPU time 0.68 seconds
Started Jul 23 06:31:33 PM PDT 24
Finished Jul 23 06:31:47 PM PDT 24
Peak memory 199300 kb
Host smart-9e6b30f2-2c3d-4b46-ab8f-775f1e863001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124056468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk
mgr_intr_test.124056468
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.537244572
Short name T866
Test name
Test status
Simulation time 12493179 ps
CPU time 0.68 seconds
Started Jul 23 06:31:34 PM PDT 24
Finished Jul 23 06:31:47 PM PDT 24
Peak memory 199344 kb
Host smart-bd0f1e8f-af03-4c86-90f2-075f47473048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537244572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clk
mgr_intr_test.537244572
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1707125857
Short name T919
Test name
Test status
Simulation time 11942939 ps
CPU time 0.67 seconds
Started Jul 23 06:31:35 PM PDT 24
Finished Jul 23 06:31:48 PM PDT 24
Peak memory 199344 kb
Host smart-a0889b26-c69c-42eb-ab34-d241a6473b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707125857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.1707125857
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3962061177
Short name T900
Test name
Test status
Simulation time 14271666 ps
CPU time 0.67 seconds
Started Jul 23 06:31:35 PM PDT 24
Finished Jul 23 06:31:48 PM PDT 24
Peak memory 199240 kb
Host smart-b0bd2653-dbfe-45c6-8545-8d9e769abacc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962061177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.3962061177
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.600319339
Short name T835
Test name
Test status
Simulation time 52123869 ps
CPU time 0.76 seconds
Started Jul 23 06:31:36 PM PDT 24
Finished Jul 23 06:31:49 PM PDT 24
Peak memory 199332 kb
Host smart-347b8cf3-ec7b-40f6-ae06-a81179f41335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600319339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clk
mgr_intr_test.600319339
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.808951798
Short name T957
Test name
Test status
Simulation time 35010278 ps
CPU time 0.72 seconds
Started Jul 23 06:31:35 PM PDT 24
Finished Jul 23 06:31:48 PM PDT 24
Peak memory 199244 kb
Host smart-16e80823-8adf-4334-a169-c91be5a18356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808951798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk
mgr_intr_test.808951798
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2805728539
Short name T843
Test name
Test status
Simulation time 16138700 ps
CPU time 0.66 seconds
Started Jul 23 06:31:33 PM PDT 24
Finished Jul 23 06:31:46 PM PDT 24
Peak memory 199356 kb
Host smart-253a318c-353c-403f-8547-f7cce2613ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805728539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2805728539
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2991232067
Short name T848
Test name
Test status
Simulation time 12657482 ps
CPU time 0.69 seconds
Started Jul 23 06:31:37 PM PDT 24
Finished Jul 23 06:31:49 PM PDT 24
Peak memory 199288 kb
Host smart-1ae57f62-98ef-4d59-b805-7db5f094dcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991232067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.2991232067
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2194809183
Short name T841
Test name
Test status
Simulation time 42853155 ps
CPU time 1.26 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:27 PM PDT 24
Peak memory 200768 kb
Host smart-83ec0559-9230-4c60-8c54-5deefc8dc3b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194809183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.2194809183
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.80824480
Short name T912
Test name
Test status
Simulation time 264519076 ps
CPU time 7.09 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:28 PM PDT 24
Peak memory 200920 kb
Host smart-e35d97ed-178e-4bf8-a2f7-979f04558dbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80824480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_csr_bit_bash.80824480
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3231157970
Short name T903
Test name
Test status
Simulation time 48797594 ps
CPU time 0.86 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:21 PM PDT 24
Peak memory 200728 kb
Host smart-19e05e50-682a-49da-bfaf-3ad8dc74bbd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231157970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.3231157970
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1056617274
Short name T978
Test name
Test status
Simulation time 40170053 ps
CPU time 1.28 seconds
Started Jul 23 06:31:08 PM PDT 24
Finished Jul 23 06:31:17 PM PDT 24
Peak memory 200740 kb
Host smart-fb4e4c3c-16b7-4af2-8f68-0dee6e6ed481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056617274 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.1056617274
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3967805029
Short name T80
Test name
Test status
Simulation time 35178833 ps
CPU time 0.87 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:26 PM PDT 24
Peak memory 200744 kb
Host smart-9db7de30-0768-4d5e-9737-2cc8cfc32bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967805029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3967805029
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2070713345
Short name T913
Test name
Test status
Simulation time 40710888 ps
CPU time 0.73 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:22 PM PDT 24
Peak memory 199284 kb
Host smart-9d073120-815a-42de-b87f-baf8700b664e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070713345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.2070713345
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3093996877
Short name T864
Test name
Test status
Simulation time 69182123 ps
CPU time 1.66 seconds
Started Jul 23 06:31:08 PM PDT 24
Finished Jul 23 06:31:17 PM PDT 24
Peak memory 200836 kb
Host smart-004032f7-4637-433d-a2c1-3c085e6f0843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093996877 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.3093996877
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3395477577
Short name T134
Test name
Test status
Simulation time 189211632 ps
CPU time 1.9 seconds
Started Jul 23 06:31:09 PM PDT 24
Finished Jul 23 06:31:19 PM PDT 24
Peak memory 217164 kb
Host smart-8bcaee6a-330c-4b0a-843c-e02c0ccb7c6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395477577 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.3395477577
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.956820957
Short name T882
Test name
Test status
Simulation time 455505207 ps
CPU time 3.78 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:27 PM PDT 24
Peak memory 209332 kb
Host smart-e05b2c03-77c2-443f-8333-2e278ae2ef82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956820957 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.956820957
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2263836131
Short name T833
Test name
Test status
Simulation time 153832576 ps
CPU time 2.98 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:26 PM PDT 24
Peak memory 200780 kb
Host smart-0ac9efcc-5608-474c-b1ab-dcdeef645e28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263836131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.2263836131
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.647449146
Short name T842
Test name
Test status
Simulation time 13142526 ps
CPU time 0.66 seconds
Started Jul 23 06:31:33 PM PDT 24
Finished Jul 23 06:31:47 PM PDT 24
Peak memory 199268 kb
Host smart-101a2d7a-43d0-414a-be48-1de5960d25ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647449146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk
mgr_intr_test.647449146
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2584530317
Short name T963
Test name
Test status
Simulation time 13362003 ps
CPU time 0.67 seconds
Started Jul 23 06:31:35 PM PDT 24
Finished Jul 23 06:31:48 PM PDT 24
Peak memory 199284 kb
Host smart-414e59b5-9a01-4480-b4dc-6a77965ba67b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584530317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2584530317
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2212346188
Short name T850
Test name
Test status
Simulation time 12221711 ps
CPU time 0.72 seconds
Started Jul 23 06:31:32 PM PDT 24
Finished Jul 23 06:31:46 PM PDT 24
Peak memory 199300 kb
Host smart-41ca51ba-716d-4729-b38b-46fde903749e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212346188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.2212346188
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1526566014
Short name T951
Test name
Test status
Simulation time 15974998 ps
CPU time 0.72 seconds
Started Jul 23 06:31:35 PM PDT 24
Finished Jul 23 06:31:48 PM PDT 24
Peak memory 199280 kb
Host smart-ee30bd02-0f6f-4edc-80be-38eaa391c928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526566014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1526566014
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.4070655215
Short name T894
Test name
Test status
Simulation time 142116207 ps
CPU time 0.99 seconds
Started Jul 23 06:31:35 PM PDT 24
Finished Jul 23 06:31:49 PM PDT 24
Peak memory 199316 kb
Host smart-5b39f454-4691-4a3f-8952-4c2e66a91f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070655215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.4070655215
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1347657878
Short name T960
Test name
Test status
Simulation time 36033949 ps
CPU time 0.71 seconds
Started Jul 23 06:31:37 PM PDT 24
Finished Jul 23 06:31:49 PM PDT 24
Peak memory 199260 kb
Host smart-af857aad-9f86-4105-a28f-cec193f7b131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347657878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.1347657878
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2514749605
Short name T827
Test name
Test status
Simulation time 44682354 ps
CPU time 0.73 seconds
Started Jul 23 06:31:34 PM PDT 24
Finished Jul 23 06:31:47 PM PDT 24
Peak memory 199252 kb
Host smart-a5cdb9cb-e3b6-4888-a0c3-355ab4acb685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514749605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.2514749605
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3054950933
Short name T844
Test name
Test status
Simulation time 12709388 ps
CPU time 0.7 seconds
Started Jul 23 06:31:32 PM PDT 24
Finished Jul 23 06:31:46 PM PDT 24
Peak memory 199236 kb
Host smart-7ffe0894-0e33-4c72-96da-2751b34d8168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054950933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.3054950933
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2345677034
Short name T847
Test name
Test status
Simulation time 12968343 ps
CPU time 0.68 seconds
Started Jul 23 06:31:35 PM PDT 24
Finished Jul 23 06:31:48 PM PDT 24
Peak memory 199308 kb
Host smart-46dead79-b343-4f2c-8210-47a3918fa515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345677034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.2345677034
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1622939394
Short name T938
Test name
Test status
Simulation time 16456403 ps
CPU time 0.7 seconds
Started Jul 23 06:31:37 PM PDT 24
Finished Jul 23 06:31:49 PM PDT 24
Peak memory 199324 kb
Host smart-592effad-be0c-427f-ae7e-d018d39e43d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622939394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.1622939394
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.93073293
Short name T889
Test name
Test status
Simulation time 127191748 ps
CPU time 1.31 seconds
Started Jul 23 06:31:09 PM PDT 24
Finished Jul 23 06:31:18 PM PDT 24
Peak memory 200836 kb
Host smart-ea359e60-4d71-4606-bd8b-9bd699fd1b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93073293 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.93073293
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2107267967
Short name T958
Test name
Test status
Simulation time 43183039 ps
CPU time 0.85 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200648 kb
Host smart-74c5d26e-4d65-4ddb-a5b8-99a2b05579a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107267967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.2107267967
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1858019764
Short name T896
Test name
Test status
Simulation time 42850200 ps
CPU time 0.77 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:21 PM PDT 24
Peak memory 199280 kb
Host smart-245de0d7-9972-450e-bb72-ccd7a85116eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858019764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.1858019764
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2296724941
Short name T943
Test name
Test status
Simulation time 197600737 ps
CPU time 1.76 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:24 PM PDT 24
Peak memory 200820 kb
Host smart-82f37224-11dc-4fb2-bb32-0cb150ca9275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296724941 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.2296724941
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1334663856
Short name T65
Test name
Test status
Simulation time 111001610 ps
CPU time 1.4 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:24 PM PDT 24
Peak memory 201064 kb
Host smart-949cc030-f037-4508-8659-f0b1c4e95b46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334663856 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1334663856
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2591950466
Short name T150
Test name
Test status
Simulation time 89195187 ps
CPU time 1.79 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:22 PM PDT 24
Peak memory 209300 kb
Host smart-2d36a73c-975f-487e-8997-da32dbfdf5aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591950466 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2591950466
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2957337607
Short name T902
Test name
Test status
Simulation time 197150492 ps
CPU time 2.18 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:25 PM PDT 24
Peak memory 200836 kb
Host smart-86d7ed1c-f5d9-4770-974a-effe8060ff9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957337607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.2957337607
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.432664710
Short name T114
Test name
Test status
Simulation time 126325182 ps
CPU time 2.64 seconds
Started Jul 23 06:31:14 PM PDT 24
Finished Jul 23 06:31:30 PM PDT 24
Peak memory 200968 kb
Host smart-235c0a3e-9bcc-44ae-8fd7-0f91f67e8cff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432664710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_tl_intg_err.432664710
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.25224442
Short name T876
Test name
Test status
Simulation time 176095009 ps
CPU time 1.68 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:27 PM PDT 24
Peak memory 200868 kb
Host smart-539ffee2-3dd1-41ea-9b1c-1cfa15f9374e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224442 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.25224442
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1598279449
Short name T870
Test name
Test status
Simulation time 20251691 ps
CPU time 0.85 seconds
Started Jul 23 06:31:08 PM PDT 24
Finished Jul 23 06:31:18 PM PDT 24
Peak memory 200764 kb
Host smart-69ff4ae9-1171-427b-9c7c-4aac2db61cd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598279449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.1598279449
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.355969361
Short name T883
Test name
Test status
Simulation time 17998711 ps
CPU time 0.71 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 199232 kb
Host smart-97f68b51-fa64-4c52-975b-0f1997f1c8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355969361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm
gr_intr_test.355969361
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.77695213
Short name T84
Test name
Test status
Simulation time 52766999 ps
CPU time 1.25 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:25 PM PDT 24
Peak memory 200936 kb
Host smart-eb14b7de-d8d3-4a8d-a084-a779d3fb62ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77695213 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.clkmgr_same_csr_outstanding.77695213
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2397269643
Short name T939
Test name
Test status
Simulation time 71510747 ps
CPU time 1.28 seconds
Started Jul 23 06:31:09 PM PDT 24
Finished Jul 23 06:31:19 PM PDT 24
Peak memory 201048 kb
Host smart-3bb5537e-c5a9-4cbc-bf3f-96de520a8d7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397269643 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.2397269643
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1156095138
Short name T907
Test name
Test status
Simulation time 45403801 ps
CPU time 1.52 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:30 PM PDT 24
Peak memory 217472 kb
Host smart-5e548580-77e7-419e-b0ee-b617ba80df01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156095138 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1156095138
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4109758585
Short name T942
Test name
Test status
Simulation time 29655939 ps
CPU time 1.69 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:23 PM PDT 24
Peak memory 200868 kb
Host smart-e5534452-8616-4c5c-8702-4bd6cc6798d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109758585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.4109758585
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.329411703
Short name T893
Test name
Test status
Simulation time 153274411 ps
CPU time 2.73 seconds
Started Jul 23 06:31:09 PM PDT 24
Finished Jul 23 06:31:20 PM PDT 24
Peak memory 200872 kb
Host smart-86deef1c-2279-407f-9d3b-451ba6663dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329411703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_tl_intg_err.329411703
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1543674180
Short name T915
Test name
Test status
Simulation time 28097768 ps
CPU time 1.07 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:27 PM PDT 24
Peak memory 200824 kb
Host smart-246d85e1-f99f-4ddd-9283-58cdc4926f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543674180 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1543674180
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3590455438
Short name T954
Test name
Test status
Simulation time 65896769 ps
CPU time 0.92 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:21 PM PDT 24
Peak memory 200644 kb
Host smart-16e51d31-6143-479c-9811-a820d55ca714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590455438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.3590455438
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1153806271
Short name T970
Test name
Test status
Simulation time 23299503 ps
CPU time 0.69 seconds
Started Jul 23 06:31:11 PM PDT 24
Finished Jul 23 06:31:22 PM PDT 24
Peak memory 199364 kb
Host smart-b919d174-261a-4b91-8fd0-6034d1cf4554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153806271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.1153806271
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2781389543
Short name T81
Test name
Test status
Simulation time 68573337 ps
CPU time 1.07 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:27 PM PDT 24
Peak memory 200728 kb
Host smart-65882a92-ed50-4fdc-af3f-47f87bd8b037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781389543 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.2781389543
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.256969529
Short name T61
Test name
Test status
Simulation time 115607592 ps
CPU time 1.69 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:26 PM PDT 24
Peak memory 201252 kb
Host smart-5a66389c-f2ad-42c5-b371-46e6a4177ac6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256969529 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.256969529
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1766430467
Short name T921
Test name
Test status
Simulation time 62407489 ps
CPU time 1.87 seconds
Started Jul 23 06:31:24 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 200852 kb
Host smart-6279e5c0-fb7e-4ea9-983c-c697913fdd90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766430467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.1766430467
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1259888759
Short name T977
Test name
Test status
Simulation time 38546395 ps
CPU time 1.07 seconds
Started Jul 23 06:31:16 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 200768 kb
Host smart-209d6e33-5258-418b-bcc2-f3678e68c76c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259888759 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.1259888759
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4081666827
Short name T892
Test name
Test status
Simulation time 16526364 ps
CPU time 0.85 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:27 PM PDT 24
Peak memory 200720 kb
Host smart-a8a5cd3a-f175-4e79-9294-0eacca421c29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081666827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.4081666827
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1576637774
Short name T829
Test name
Test status
Simulation time 27461048 ps
CPU time 0.69 seconds
Started Jul 23 06:31:13 PM PDT 24
Finished Jul 23 06:31:25 PM PDT 24
Peak memory 199280 kb
Host smart-e4ee6edf-d7cd-4513-9ea9-9bde43d5835e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576637774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.1576637774
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3345686003
Short name T934
Test name
Test status
Simulation time 108785664 ps
CPU time 1.28 seconds
Started Jul 23 06:31:14 PM PDT 24
Finished Jul 23 06:31:29 PM PDT 24
Peak memory 200716 kb
Host smart-abedb2af-69d6-4338-9a4c-821011ca2f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345686003 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.3345686003
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3486939254
Short name T146
Test name
Test status
Simulation time 355363823 ps
CPU time 2.66 seconds
Started Jul 23 06:31:22 PM PDT 24
Finished Jul 23 06:31:40 PM PDT 24
Peak memory 217500 kb
Host smart-f2d3b3b6-b4c4-4626-8a10-db303c016f02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486939254 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.3486939254
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1178723763
Short name T87
Test name
Test status
Simulation time 261730838 ps
CPU time 2.22 seconds
Started Jul 23 06:31:14 PM PDT 24
Finished Jul 23 06:31:28 PM PDT 24
Peak memory 201260 kb
Host smart-355328f7-4777-4060-bedb-90ade1a5bbe4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178723763 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.1178723763
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.249545483
Short name T858
Test name
Test status
Simulation time 141429428 ps
CPU time 2.65 seconds
Started Jul 23 06:31:12 PM PDT 24
Finished Jul 23 06:31:27 PM PDT 24
Peak memory 200832 kb
Host smart-fcadd07e-c2c0-4e12-890a-147ab240c998
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249545483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.249545483
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.729351557
Short name T116
Test name
Test status
Simulation time 203087982 ps
CPU time 2.67 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:32 PM PDT 24
Peak memory 200848 kb
Host smart-83f5bacc-535e-4f34-9b17-5bda9c551722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729351557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_tl_intg_err.729351557
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3658277010
Short name T175
Test name
Test status
Simulation time 35497390 ps
CPU time 1.19 seconds
Started Jul 23 06:31:19 PM PDT 24
Finished Jul 23 06:31:35 PM PDT 24
Peak memory 200844 kb
Host smart-fa9cf95a-3f6b-4371-b231-7d9512200fb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658277010 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.3658277010
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3221321254
Short name T878
Test name
Test status
Simulation time 49635502 ps
CPU time 0.89 seconds
Started Jul 23 06:31:17 PM PDT 24
Finished Jul 23 06:31:34 PM PDT 24
Peak memory 200760 kb
Host smart-7e1b523a-45c9-43a5-9ed6-5002742e66c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221321254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3221321254
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2212158790
Short name T962
Test name
Test status
Simulation time 18831966 ps
CPU time 0.71 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:30 PM PDT 24
Peak memory 199272 kb
Host smart-12242fd5-b377-4d23-b64e-0767abf15a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212158790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.2212158790
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3983731344
Short name T926
Test name
Test status
Simulation time 100005527 ps
CPU time 1.45 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:29 PM PDT 24
Peak memory 200820 kb
Host smart-ab76aaab-bff7-4d9d-8b1c-de6d8779c807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983731344 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.3983731344
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3071540199
Short name T148
Test name
Test status
Simulation time 49439929 ps
CPU time 1.32 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:31 PM PDT 24
Peak memory 200996 kb
Host smart-ab747e6d-50a4-495b-ae79-72b867bbcf1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071540199 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.3071540199
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.643786264
Short name T944
Test name
Test status
Simulation time 411920540 ps
CPU time 3.52 seconds
Started Jul 23 06:31:20 PM PDT 24
Finished Jul 23 06:31:38 PM PDT 24
Peak memory 217508 kb
Host smart-50aa8b63-63f3-4383-9110-a249bd7448e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643786264 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.643786264
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1100841358
Short name T826
Test name
Test status
Simulation time 211432345 ps
CPU time 2.07 seconds
Started Jul 23 06:31:19 PM PDT 24
Finished Jul 23 06:31:36 PM PDT 24
Peak memory 200844 kb
Host smart-84afdb35-cff2-450b-81ba-78a29b7730ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100841358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.1100841358
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2550404525
Short name T118
Test name
Test status
Simulation time 216601568 ps
CPU time 2 seconds
Started Jul 23 06:31:15 PM PDT 24
Finished Jul 23 06:31:30 PM PDT 24
Peak memory 200848 kb
Host smart-1ec3ade8-8f95-43a1-81bd-d0e494088823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550404525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2550404525
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.3540972248
Short name T442
Test name
Test status
Simulation time 12961804 ps
CPU time 0.74 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 200552 kb
Host smart-6ebfc20c-bf7d-4b39-8c98-6649e93d6e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540972248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.3540972248
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1766654159
Short name T639
Test name
Test status
Simulation time 50064700 ps
CPU time 0.92 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:00 PM PDT 24
Peak memory 200376 kb
Host smart-d569200a-2fc2-4780-b4b6-d584c880de9e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766654159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.1766654159
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2680240775
Short name T651
Test name
Test status
Simulation time 41003315 ps
CPU time 0.81 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 199664 kb
Host smart-332610c7-48cb-4871-9981-722150538924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680240775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2680240775
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.851917970
Short name T378
Test name
Test status
Simulation time 41205953 ps
CPU time 0.84 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:00 PM PDT 24
Peak memory 200456 kb
Host smart-72637561-9e22-449c-a029-5eb9c2c387d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851917970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_div_intersig_mubi.851917970
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.1074664546
Short name T724
Test name
Test status
Simulation time 74010380 ps
CPU time 1.01 seconds
Started Jul 23 06:43:43 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 200352 kb
Host smart-0f5a1e8e-ead3-40cd-9496-605974f45b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074664546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.1074664546
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.4021393526
Short name T573
Test name
Test status
Simulation time 1473127888 ps
CPU time 6.49 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:44:02 PM PDT 24
Peak memory 200492 kb
Host smart-c29a7742-6b9b-4a56-95a7-3e72ccc985a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021393526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.4021393526
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.222561180
Short name T690
Test name
Test status
Simulation time 197910680 ps
CPU time 1.51 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:53 PM PDT 24
Peak memory 200456 kb
Host smart-cc5e3aba-2f4e-4175-b0bf-b30d46d3bb90
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222561180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.222561180
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.3822827600
Short name T284
Test name
Test status
Simulation time 59090152 ps
CPU time 0.95 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:02 PM PDT 24
Peak memory 200480 kb
Host smart-7c89e40f-2d1b-4d00-bc78-11c7e397ce72
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822827600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.3822827600
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.3345953434
Short name T530
Test name
Test status
Simulation time 41203779 ps
CPU time 0.91 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 200468 kb
Host smart-3ab801fe-d6bb-4f8a-8209-9aaab2014b45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345953434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.3345953434
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.1540522676
Short name T203
Test name
Test status
Simulation time 38027186 ps
CPU time 0.82 seconds
Started Jul 23 06:43:42 PM PDT 24
Finished Jul 23 06:43:49 PM PDT 24
Peak memory 200428 kb
Host smart-662a3de5-785b-4c7f-b30e-9174aaa03543
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540522676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.1540522676
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.1584852819
Short name T479
Test name
Test status
Simulation time 38484130 ps
CPU time 0.97 seconds
Started Jul 23 06:43:44 PM PDT 24
Finished Jul 23 06:43:52 PM PDT 24
Peak memory 200392 kb
Host smart-1334738f-619c-4795-aaf6-1daab363e4d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584852819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.1584852819
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.3326033014
Short name T293
Test name
Test status
Simulation time 2306991478 ps
CPU time 10.25 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:44:07 PM PDT 24
Peak memory 200700 kb
Host smart-78796e31-7184-44b2-8742-bbaf00b60ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326033014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.3326033014
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.603844371
Short name T756
Test name
Test status
Simulation time 62417822 ps
CPU time 1.08 seconds
Started Jul 23 06:43:51 PM PDT 24
Finished Jul 23 06:43:56 PM PDT 24
Peak memory 200468 kb
Host smart-3c75dde1-2e2a-4b61-9159-a756af5112b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603844371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.603844371
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.1271920277
Short name T49
Test name
Test status
Simulation time 25390962 ps
CPU time 0.78 seconds
Started Jul 23 06:43:59 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 200540 kb
Host smart-c746acc8-95c2-4cd0-bf1c-2c8fda339726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271920277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.1271920277
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3708702340
Short name T491
Test name
Test status
Simulation time 59290820 ps
CPU time 0.94 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 200460 kb
Host smart-f3ccf706-9808-4347-accd-7659b8bcb1b0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708702340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.3708702340
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.648553929
Short name T258
Test name
Test status
Simulation time 24221255 ps
CPU time 0.8 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 199564 kb
Host smart-df1bda89-8864-4cda-a0e3-bbe16b22e2c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648553929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.648553929
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3589037711
Short name T385
Test name
Test status
Simulation time 25430149 ps
CPU time 0.87 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 200484 kb
Host smart-982b82e3-4697-46f8-90d5-6b299aed312f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589037711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3589037711
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.97892862
Short name T297
Test name
Test status
Simulation time 36892479 ps
CPU time 0.96 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:02 PM PDT 24
Peak memory 200476 kb
Host smart-06e1d968-5df8-4138-b426-da171ef917bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97892862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.97892862
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.3669908802
Short name T467
Test name
Test status
Simulation time 211771381 ps
CPU time 1.82 seconds
Started Jul 23 06:43:53 PM PDT 24
Finished Jul 23 06:43:58 PM PDT 24
Peak memory 200452 kb
Host smart-4bfff180-ff2e-432a-a0cd-79605e395a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669908802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3669908802
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.1268623810
Short name T582
Test name
Test status
Simulation time 627800012 ps
CPU time 4.04 seconds
Started Jul 23 06:43:52 PM PDT 24
Finished Jul 23 06:44:00 PM PDT 24
Peak memory 200380 kb
Host smart-04c6cb38-f50d-44cf-9047-d9e552565ede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268623810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.1268623810
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.399874076
Short name T772
Test name
Test status
Simulation time 27764501 ps
CPU time 0.94 seconds
Started Jul 23 06:43:58 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 200464 kb
Host smart-477990e2-3af3-4c8d-aae4-e50c905dd989
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399874076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.clkmgr_idle_intersig_mubi.399874076
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.4217599822
Short name T171
Test name
Test status
Simulation time 23077707 ps
CPU time 0.88 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:01 PM PDT 24
Peak memory 200488 kb
Host smart-64eec552-8464-4043-bc33-c9c6845a98cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217599822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.4217599822
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3538034289
Short name T508
Test name
Test status
Simulation time 48337791 ps
CPU time 0.9 seconds
Started Jul 23 06:43:58 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 200452 kb
Host smart-3ae63162-0597-4c5e-becb-414257b96b02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538034289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.3538034289
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2766603205
Short name T726
Test name
Test status
Simulation time 37946289 ps
CPU time 0.81 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:00 PM PDT 24
Peak memory 200404 kb
Host smart-d2a85684-8633-47e9-ac00-d6f0fd3595ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766603205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2766603205
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.3364442422
Short name T445
Test name
Test status
Simulation time 961454106 ps
CPU time 3.88 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 200604 kb
Host smart-5c78b094-6215-45c5-a618-91c64c16f22a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364442422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3364442422
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.1845254548
Short name T44
Test name
Test status
Simulation time 390980395 ps
CPU time 3.42 seconds
Started Jul 23 06:43:55 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 221120 kb
Host smart-d740c2d0-2a61-4823-844f-ad1f4c5ad1dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845254548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.1845254548
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.2141872045
Short name T301
Test name
Test status
Simulation time 15296664 ps
CPU time 0.82 seconds
Started Jul 23 06:43:54 PM PDT 24
Finished Jul 23 06:43:59 PM PDT 24
Peak memory 200396 kb
Host smart-b97c1b51-4188-41e9-a4d1-d9903083ecf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141872045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2141872045
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.586094143
Short name T370
Test name
Test status
Simulation time 3101635645 ps
CPU time 23.4 seconds
Started Jul 23 06:43:56 PM PDT 24
Finished Jul 23 06:44:24 PM PDT 24
Peak memory 200728 kb
Host smart-918af636-d8fd-49e9-a72d-04eb1ed2623d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586094143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.586094143
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.3409419140
Short name T548
Test name
Test status
Simulation time 29159235 ps
CPU time 0.95 seconds
Started Jul 23 06:43:57 PM PDT 24
Finished Jul 23 06:44:03 PM PDT 24
Peak memory 200480 kb
Host smart-5a972932-3ffd-40ea-8b60-6e7d3dc7c0aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409419140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3409419140
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.2146186789
Short name T250
Test name
Test status
Simulation time 14723706 ps
CPU time 0.73 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 199656 kb
Host smart-3332195e-17e0-4641-88c8-ab4a059e3b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146186789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2146186789
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.2782841879
Short name T211
Test name
Test status
Simulation time 42245811 ps
CPU time 0.94 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 200464 kb
Host smart-7e142292-6db3-4af2-8151-bf27e6b0afc7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782841879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.2782841879
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.1268487581
Short name T272
Test name
Test status
Simulation time 24852783 ps
CPU time 0.81 seconds
Started Jul 23 06:44:55 PM PDT 24
Finished Jul 23 06:45:02 PM PDT 24
Peak memory 200328 kb
Host smart-eef97465-5dc3-44b2-a432-7399725c2bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268487581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1268487581
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.440691616
Short name T676
Test name
Test status
Simulation time 451810201 ps
CPU time 3.2 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:02 PM PDT 24
Peak memory 200468 kb
Host smart-f523f5e4-9557-411b-ac47-cf267bd214e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440691616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.440691616
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.3083812791
Short name T766
Test name
Test status
Simulation time 974426069 ps
CPU time 8.1 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 200516 kb
Host smart-28a88ae9-7cbc-4631-8491-9ad06c430018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083812791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.3083812791
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.2071421710
Short name T363
Test name
Test status
Simulation time 17352317 ps
CPU time 0.77 seconds
Started Jul 23 06:44:56 PM PDT 24
Finished Jul 23 06:45:02 PM PDT 24
Peak memory 200444 kb
Host smart-a95b3fe4-83ed-49ba-b8a4-c62f3ccf2b60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071421710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.2071421710
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2979995609
Short name T218
Test name
Test status
Simulation time 18114386 ps
CPU time 0.79 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 200476 kb
Host smart-3d6b9ebb-b40c-4b64-b780-63447bcf97e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979995609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.2979995609
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.689251717
Short name T343
Test name
Test status
Simulation time 132470058 ps
CPU time 1.32 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 200408 kb
Host smart-b0e76ea9-9c2f-4167-a1ba-49f6350e78dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689251717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.689251717
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.416695509
Short name T411
Test name
Test status
Simulation time 25542355 ps
CPU time 0.79 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 200460 kb
Host smart-65521889-e6db-4809-a5d8-50ea91d93d62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416695509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.416695509
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.4195177903
Short name T700
Test name
Test status
Simulation time 16147902 ps
CPU time 0.82 seconds
Started Jul 23 06:44:49 PM PDT 24
Finished Jul 23 06:44:56 PM PDT 24
Peak memory 200440 kb
Host smart-2e0f6a47-837a-4181-8694-b55863ca9b1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195177903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.4195177903
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.2878404640
Short name T342
Test name
Test status
Simulation time 13876935723 ps
CPU time 47.09 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:47 PM PDT 24
Peak memory 200728 kb
Host smart-20b0f764-5b09-47f6-8f17-e01fc8cdf251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878404640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.2878404640
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.2305671520
Short name T734
Test name
Test status
Simulation time 26355131 ps
CPU time 1 seconds
Started Jul 23 06:44:53 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 200480 kb
Host smart-e4d228ac-7cf7-4d7f-b129-902d458837c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305671520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2305671520
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.3079634586
Short name T433
Test name
Test status
Simulation time 15729708 ps
CPU time 0.77 seconds
Started Jul 23 06:45:00 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 200528 kb
Host smart-495711dc-7b9e-4b3c-a068-c7dd33e8f949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079634586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.3079634586
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3223841887
Short name T76
Test name
Test status
Simulation time 110916326 ps
CPU time 1.14 seconds
Started Jul 23 06:45:01 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 200444 kb
Host smart-03a7464c-7d29-4fae-a80b-57a6fd282254
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223841887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.3223841887
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.508942285
Short name T623
Test name
Test status
Simulation time 37846956 ps
CPU time 0.78 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 199624 kb
Host smart-73a02cfc-235a-4380-ab56-a6ba8f547b2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508942285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.508942285
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.773006021
Short name T290
Test name
Test status
Simulation time 33386791 ps
CPU time 1 seconds
Started Jul 23 06:44:57 PM PDT 24
Finished Jul 23 06:45:03 PM PDT 24
Peak memory 200444 kb
Host smart-87661d72-85e1-4862-8ca8-0391df049666
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773006021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.clkmgr_div_intersig_mubi.773006021
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.4023520006
Short name T350
Test name
Test status
Simulation time 23589282 ps
CPU time 0.81 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 200696 kb
Host smart-7b612b40-1e14-4fe2-9449-66947ccbeeec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023520006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.4023520006
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.2783206469
Short name T665
Test name
Test status
Simulation time 1294134668 ps
CPU time 5.95 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:06 PM PDT 24
Peak memory 200456 kb
Host smart-0514ca75-6762-482d-8a2f-b5313fba531e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783206469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.2783206469
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.2314416125
Short name T36
Test name
Test status
Simulation time 1582112469 ps
CPU time 5.28 seconds
Started Jul 23 06:44:54 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 200416 kb
Host smart-fd6fc5d2-6f40-4f05-8db4-49e9801a640d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314416125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.2314416125
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.4028826615
Short name T438
Test name
Test status
Simulation time 30345792 ps
CPU time 0.79 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:12 PM PDT 24
Peak memory 200452 kb
Host smart-711472d2-6be3-4958-ac3a-7756e190710d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028826615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.4028826615
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.2568228079
Short name T560
Test name
Test status
Simulation time 29302266 ps
CPU time 0.9 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 200460 kb
Host smart-2111691e-8a3a-4343-8c33-d6a48d995f4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568228079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.2568228079
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1712881710
Short name T595
Test name
Test status
Simulation time 24204380 ps
CPU time 0.8 seconds
Started Jul 23 06:45:01 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 200424 kb
Host smart-0e306e16-4abb-43d5-a4e4-74f0a1fe2c5d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712881710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.1712881710
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.3789078529
Short name T482
Test name
Test status
Simulation time 20296671 ps
CPU time 0.85 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 200428 kb
Host smart-a5323935-f42b-457f-b898-7ece71c9543f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789078529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.3789078529
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.2014172848
Short name T168
Test name
Test status
Simulation time 1249073755 ps
CPU time 5.76 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:09 PM PDT 24
Peak memory 200612 kb
Host smart-47085532-15d4-42b7-aa58-9097eb77378c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014172848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2014172848
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.3898669872
Short name T475
Test name
Test status
Simulation time 191444372 ps
CPU time 1.35 seconds
Started Jul 23 06:44:52 PM PDT 24
Finished Jul 23 06:44:59 PM PDT 24
Peak memory 200340 kb
Host smart-a59ef2c5-b309-4bee-8317-469fe3096d43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898669872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.3898669872
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.1703535862
Short name T715
Test name
Test status
Simulation time 11836985742 ps
CPU time 49.6 seconds
Started Jul 23 06:45:01 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 200760 kb
Host smart-7e6084e4-f4ed-46ba-bc5f-9c2f38eb9c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703535862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.1703535862
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.1850065525
Short name T265
Test name
Test status
Simulation time 53375305 ps
CPU time 1.03 seconds
Started Jul 23 06:45:00 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 200412 kb
Host smart-fe3136b9-12d9-4cea-860a-96028f4eb093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850065525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1850065525
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.1457971256
Short name T7
Test name
Test status
Simulation time 12825423 ps
CPU time 0.74 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 200492 kb
Host smart-b21ee16e-678f-4d04-b830-9ec125188023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457971256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.1457971256
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3664889223
Short name T796
Test name
Test status
Simulation time 19550321 ps
CPU time 0.85 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 200440 kb
Host smart-3cead183-ee63-4058-a5d8-c5c135895bb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664889223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3664889223
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.130163661
Short name T285
Test name
Test status
Simulation time 16500086 ps
CPU time 0.72 seconds
Started Jul 23 06:45:04 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 200376 kb
Host smart-71dc79cd-59a1-470a-ba83-78c6be96c82e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130163661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.130163661
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.562129292
Short name T238
Test name
Test status
Simulation time 20149110 ps
CPU time 0.81 seconds
Started Jul 23 06:45:10 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 200432 kb
Host smart-b9cd4352-b649-4c52-a0d5-285da57534c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562129292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.clkmgr_div_intersig_mubi.562129292
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.1531605152
Short name T670
Test name
Test status
Simulation time 24099399 ps
CPU time 0.83 seconds
Started Jul 23 06:44:59 PM PDT 24
Finished Jul 23 06:45:05 PM PDT 24
Peak memory 200352 kb
Host smart-790305aa-0639-4261-acf0-b0e7af156809
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531605152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1531605152
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.301450967
Short name T661
Test name
Test status
Simulation time 3078600986 ps
CPU time 10.75 seconds
Started Jul 23 06:44:58 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 200640 kb
Host smart-54795dc9-b32f-4162-bf6a-d2d05f9b84a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301450967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.301450967
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.713190868
Short name T195
Test name
Test status
Simulation time 1465742190 ps
CPU time 7.89 seconds
Started Jul 23 06:45:00 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 200484 kb
Host smart-a12196a4-3e85-4a2d-ae40-fa117657702b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713190868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_ti
meout.713190868
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.3714217347
Short name T50
Test name
Test status
Simulation time 96773708 ps
CPU time 1.16 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 200456 kb
Host smart-0b42df6d-796d-41fd-8250-1b406dd9c03f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714217347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.3714217347
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3299356934
Short name T632
Test name
Test status
Simulation time 158805255 ps
CPU time 1.25 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 200348 kb
Host smart-ae4f2d55-43d5-41a7-9d22-b159ebe53855
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299356934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.3299356934
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2927638246
Short name T680
Test name
Test status
Simulation time 15536194 ps
CPU time 0.71 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:09 PM PDT 24
Peak memory 200300 kb
Host smart-74e8e2b0-60ed-4512-b453-fdc0e4c01b05
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927638246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.2927638246
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.3948515801
Short name T225
Test name
Test status
Simulation time 14565167 ps
CPU time 0.73 seconds
Started Jul 23 06:45:01 PM PDT 24
Finished Jul 23 06:45:07 PM PDT 24
Peak memory 200432 kb
Host smart-7e1ff28a-9b96-45d2-954b-6eb2def6b313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948515801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3948515801
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.238105813
Short name T580
Test name
Test status
Simulation time 227907355 ps
CPU time 1.32 seconds
Started Jul 23 06:45:02 PM PDT 24
Finished Jul 23 06:45:09 PM PDT 24
Peak memory 200396 kb
Host smart-d3f01d97-43e3-43cc-a359-287869381ddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238105813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.238105813
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.2552343885
Short name T256
Test name
Test status
Simulation time 35391713 ps
CPU time 0.84 seconds
Started Jul 23 06:45:04 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 200404 kb
Host smart-0f1486c7-8565-49bf-89bd-d0f2d28272d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552343885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2552343885
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.3272919887
Short name T495
Test name
Test status
Simulation time 3453063015 ps
CPU time 16.12 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:26 PM PDT 24
Peak memory 200724 kb
Host smart-93c542f5-dd49-45fb-986e-4113055106bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272919887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.3272919887
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.1639159608
Short name T474
Test name
Test status
Simulation time 59977897 ps
CPU time 1.02 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:11 PM PDT 24
Peak memory 200432 kb
Host smart-676e7fb4-798f-4d72-af36-78849736ece9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639159608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1639159608
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.3981836992
Short name T439
Test name
Test status
Simulation time 32436248 ps
CPU time 0.75 seconds
Started Jul 23 06:45:10 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 200536 kb
Host smart-f61ad0cb-7db6-47f9-83ee-8c9c1538d054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981836992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.3981836992
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1822721664
Short name T585
Test name
Test status
Simulation time 52271667 ps
CPU time 0.85 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 200472 kb
Host smart-e66f3b36-e0f1-4e2a-bb14-36af63d1ce8f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822721664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.1822721664
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.2443707549
Short name T517
Test name
Test status
Simulation time 46062260 ps
CPU time 0.82 seconds
Started Jul 23 06:45:13 PM PDT 24
Finished Jul 23 06:45:17 PM PDT 24
Peak memory 199660 kb
Host smart-302237d7-59c0-4dc8-a2f1-2cc6f3741386
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443707549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2443707549
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.3666029421
Short name T207
Test name
Test status
Simulation time 51970844 ps
CPU time 0.87 seconds
Started Jul 23 06:45:10 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 200344 kb
Host smart-beec408c-7a5a-42a4-b76d-ac7da724209e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666029421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.3666029421
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.2841864324
Short name T193
Test name
Test status
Simulation time 237045350 ps
CPU time 1.56 seconds
Started Jul 23 06:45:06 PM PDT 24
Finished Jul 23 06:45:13 PM PDT 24
Peak memory 200460 kb
Host smart-97cb50cb-bccd-459c-a059-6f057b9cdb20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841864324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2841864324
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3421124329
Short name T504
Test name
Test status
Simulation time 958768978 ps
CPU time 4.56 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 200304 kb
Host smart-603b74ce-2061-4899-9060-56c52938b885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421124329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3421124329
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.2009272422
Short name T771
Test name
Test status
Simulation time 1816684159 ps
CPU time 13.11 seconds
Started Jul 23 06:45:05 PM PDT 24
Finished Jul 23 06:45:24 PM PDT 24
Peak memory 200484 kb
Host smart-fddbac1a-06a5-4bb2-b5df-1ef19c2002ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009272422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.2009272422
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.4244403311
Short name T274
Test name
Test status
Simulation time 51391749 ps
CPU time 0.96 seconds
Started Jul 23 06:45:06 PM PDT 24
Finished Jul 23 06:45:13 PM PDT 24
Peak memory 200192 kb
Host smart-78a7caf9-5392-4fbd-a01e-db74bd251e4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244403311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.4244403311
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.324816960
Short name T209
Test name
Test status
Simulation time 34036184 ps
CPU time 0.83 seconds
Started Jul 23 06:45:12 PM PDT 24
Finished Jul 23 06:45:17 PM PDT 24
Peak memory 200400 kb
Host smart-33190a69-6444-40dc-8c2d-930355c895ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324816960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_clk_byp_req_intersig_mubi.324816960
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.979235096
Short name T158
Test name
Test status
Simulation time 34758315 ps
CPU time 0.9 seconds
Started Jul 23 06:45:08 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 200480 kb
Host smart-501ed670-30ff-4256-a0f8-e87d579fddd4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979235096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_ctrl_intersig_mubi.979235096
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.3759196172
Short name T526
Test name
Test status
Simulation time 18190265 ps
CPU time 0.83 seconds
Started Jul 23 06:45:07 PM PDT 24
Finished Jul 23 06:45:13 PM PDT 24
Peak memory 200380 kb
Host smart-e157e3b6-ebd8-40bd-8d6d-856a5c5d7b3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759196172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.3759196172
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.1299710946
Short name T523
Test name
Test status
Simulation time 335501287 ps
CPU time 1.84 seconds
Started Jul 23 06:45:07 PM PDT 24
Finished Jul 23 06:45:14 PM PDT 24
Peak memory 200476 kb
Host smart-35c3d318-0dd6-41db-88c2-fefb4fa46710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299710946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1299710946
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.2155448326
Short name T570
Test name
Test status
Simulation time 85157342 ps
CPU time 1.03 seconds
Started Jul 23 06:45:07 PM PDT 24
Finished Jul 23 06:45:13 PM PDT 24
Peak memory 200152 kb
Host smart-77a9e499-0dba-407c-8afa-dc621c88eb04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155448326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2155448326
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.2713675598
Short name T677
Test name
Test status
Simulation time 5336525373 ps
CPU time 40.92 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 200812 kb
Host smart-848ca561-2943-4c26-baa4-7d33857be3e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713675598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.2713675598
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.1312988438
Short name T817
Test name
Test status
Simulation time 23132024 ps
CPU time 0.83 seconds
Started Jul 23 06:45:03 PM PDT 24
Finished Jul 23 06:45:10 PM PDT 24
Peak memory 200308 kb
Host smart-7dcfc2b9-c7bc-49a3-a480-9e60337869ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312988438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.1312988438
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.336750836
Short name T679
Test name
Test status
Simulation time 12212070 ps
CPU time 0.74 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 200516 kb
Host smart-217481f8-dbbb-4df6-adef-de1d0739996b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336750836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkm
gr_alert_test.336750836
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2968341230
Short name T763
Test name
Test status
Simulation time 19378797 ps
CPU time 0.83 seconds
Started Jul 23 06:45:16 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 200448 kb
Host smart-9ffb6bf0-d80b-46f3-a8c5-6600458a8d53
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968341230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.2968341230
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.1672016292
Short name T732
Test name
Test status
Simulation time 49625652 ps
CPU time 0.9 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 200452 kb
Host smart-d107abc8-650d-4d5b-8a6e-753f64fa0585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672016292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.1672016292
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.2120662951
Short name T604
Test name
Test status
Simulation time 2139535612 ps
CPU time 8.89 seconds
Started Jul 23 06:45:10 PM PDT 24
Finished Jul 23 06:45:24 PM PDT 24
Peak memory 200552 kb
Host smart-c23a383c-b7a3-4117-9b4a-068ceed095ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120662951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2120662951
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.353563071
Short name T544
Test name
Test status
Simulation time 1462412856 ps
CPU time 10.68 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:26 PM PDT 24
Peak memory 200532 kb
Host smart-753f1668-745c-46aa-9f57-f531689635e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353563071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti
meout.353563071
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1640797060
Short name T412
Test name
Test status
Simulation time 85564485 ps
CPU time 1.17 seconds
Started Jul 23 06:45:19 PM PDT 24
Finished Jul 23 06:45:22 PM PDT 24
Peak memory 200460 kb
Host smart-713c8fd6-429f-4519-99c8-e873c5bdee48
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640797060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.1640797060
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.2889620869
Short name T529
Test name
Test status
Simulation time 165878469 ps
CPU time 1.38 seconds
Started Jul 23 06:45:16 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 200448 kb
Host smart-d41d25f0-aba3-4e75-b843-d804f9b5636d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889620869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.2889620869
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.2386233137
Short name T90
Test name
Test status
Simulation time 29387360 ps
CPU time 0.81 seconds
Started Jul 23 06:45:24 PM PDT 24
Finished Jul 23 06:45:28 PM PDT 24
Peak memory 200424 kb
Host smart-b36d3d33-6735-4276-88fb-5fc25456b5ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386233137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.2386233137
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.521623011
Short name T234
Test name
Test status
Simulation time 16673905 ps
CPU time 0.8 seconds
Started Jul 23 06:45:09 PM PDT 24
Finished Jul 23 06:45:15 PM PDT 24
Peak memory 200440 kb
Host smart-c6258c43-f1ae-444a-9c72-6282dca3cc18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521623011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.521623011
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.3139027388
Short name T547
Test name
Test status
Simulation time 954361049 ps
CPU time 5.72 seconds
Started Jul 23 06:45:18 PM PDT 24
Finished Jul 23 06:45:27 PM PDT 24
Peak memory 200656 kb
Host smart-2f46224f-1146-4643-a436-29549852899f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139027388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3139027388
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.2708929393
Short name T710
Test name
Test status
Simulation time 44210949 ps
CPU time 0.88 seconds
Started Jul 23 06:45:11 PM PDT 24
Finished Jul 23 06:45:16 PM PDT 24
Peak memory 200428 kb
Host smart-bc061e57-62c5-4644-8c2b-20d37cd4643e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708929393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2708929393
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.1997668686
Short name T317
Test name
Test status
Simulation time 720715489 ps
CPU time 4.67 seconds
Started Jul 23 06:45:19 PM PDT 24
Finished Jul 23 06:45:26 PM PDT 24
Peak memory 200720 kb
Host smart-a95c8314-afd1-4264-a6d5-3680ec12bbd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997668686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.1997668686
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.634079419
Short name T488
Test name
Test status
Simulation time 101416730 ps
CPU time 1.23 seconds
Started Jul 23 06:45:21 PM PDT 24
Finished Jul 23 06:45:24 PM PDT 24
Peak memory 200448 kb
Host smart-074bdaba-1850-4dae-9a5f-c7f0bed0dca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634079419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.634079419
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1571580687
Short name T33
Test name
Test status
Simulation time 225826378 ps
CPU time 1.42 seconds
Started Jul 23 06:45:29 PM PDT 24
Finished Jul 23 06:45:34 PM PDT 24
Peak memory 200524 kb
Host smart-e8adf134-0572-46d4-903a-ba6adb45c4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571580687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1571580687
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2158576062
Short name T304
Test name
Test status
Simulation time 104667823 ps
CPU time 1.15 seconds
Started Jul 23 06:45:28 PM PDT 24
Finished Jul 23 06:45:32 PM PDT 24
Peak memory 200692 kb
Host smart-f6c99a4d-e23d-49d9-9bfe-24ed8a037103
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158576062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.2158576062
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.1418234234
Short name T706
Test name
Test status
Simulation time 14126550 ps
CPU time 0.76 seconds
Started Jul 23 06:45:25 PM PDT 24
Finished Jul 23 06:45:28 PM PDT 24
Peak memory 200348 kb
Host smart-1623022a-400a-440d-9277-058a311f793d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418234234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1418234234
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.1038146628
Short name T25
Test name
Test status
Simulation time 40062017 ps
CPU time 0.8 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:26 PM PDT 24
Peak memory 200456 kb
Host smart-871b59c9-4f82-4ad5-a6b9-5893ed9b179a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038146628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.1038146628
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.3312194310
Short name T688
Test name
Test status
Simulation time 41443088 ps
CPU time 0.89 seconds
Started Jul 23 06:45:16 PM PDT 24
Finished Jul 23 06:45:19 PM PDT 24
Peak memory 200472 kb
Host smart-0921153e-b135-4dc6-b6ae-e80f4aab609c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312194310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3312194310
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.452744921
Short name T410
Test name
Test status
Simulation time 1037079606 ps
CPU time 8.71 seconds
Started Jul 23 06:45:27 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 200460 kb
Host smart-6d88be80-44a7-4424-8f41-c0fce2818cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452744921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.452744921
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.4245498294
Short name T450
Test name
Test status
Simulation time 1274765538 ps
CPU time 5.71 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:31 PM PDT 24
Peak memory 200500 kb
Host smart-c5e5e58e-9fa6-4887-9838-5eee12e4c1bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245498294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.4245498294
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.3144377752
Short name T499
Test name
Test status
Simulation time 49772004 ps
CPU time 0.86 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:26 PM PDT 24
Peak memory 200448 kb
Host smart-dc2573d0-176b-4956-abbc-6c1521a2e9fa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144377752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.3144377752
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.642752868
Short name T591
Test name
Test status
Simulation time 18823144 ps
CPU time 0.9 seconds
Started Jul 23 06:45:24 PM PDT 24
Finished Jul 23 06:45:28 PM PDT 24
Peak memory 200444 kb
Host smart-d6f885b4-3a2b-4eb9-9b97-40fcbe96eb3d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642752868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.clkmgr_lc_clk_byp_req_intersig_mubi.642752868
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3553830223
Short name T260
Test name
Test status
Simulation time 68304736 ps
CPU time 0.97 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 200340 kb
Host smart-d959ed37-acd4-4d12-87fb-88d7f992eb23
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553830223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.3553830223
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.786797356
Short name T409
Test name
Test status
Simulation time 17821468 ps
CPU time 0.78 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 200376 kb
Host smart-549e7615-08ee-4897-8350-e8caf86a1e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786797356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.786797356
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.1998842876
Short name T91
Test name
Test status
Simulation time 1048072843 ps
CPU time 5.7 seconds
Started Jul 23 06:45:30 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 200636 kb
Host smart-278458a7-564a-42ab-8c19-b4e7f57c3816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998842876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1998842876
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.3465349473
Short name T471
Test name
Test status
Simulation time 167462382 ps
CPU time 1.29 seconds
Started Jul 23 06:45:17 PM PDT 24
Finished Jul 23 06:45:20 PM PDT 24
Peak memory 200420 kb
Host smart-14197828-c609-43a9-adf9-7741a4fd398e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465349473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.3465349473
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.4212591535
Short name T686
Test name
Test status
Simulation time 8883078089 ps
CPU time 48.83 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 200636 kb
Host smart-597bf816-15a3-4c77-bc39-b4756fbb60ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212591535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.4212591535
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.245950175
Short name T128
Test name
Test status
Simulation time 187217210 ps
CPU time 1.34 seconds
Started Jul 23 06:45:25 PM PDT 24
Finished Jul 23 06:45:29 PM PDT 24
Peak memory 200492 kb
Host smart-e7391b18-3e7d-41e8-a27a-98b00017d727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245950175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.245950175
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.1085931281
Short name T620
Test name
Test status
Simulation time 14540463 ps
CPU time 0.8 seconds
Started Jul 23 06:45:35 PM PDT 24
Finished Jul 23 06:45:41 PM PDT 24
Peak memory 200524 kb
Host smart-f6841add-3903-47e0-a2ae-1c98affeb113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085931281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.1085931281
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3485113819
Short name T642
Test name
Test status
Simulation time 82365208 ps
CPU time 0.99 seconds
Started Jul 23 06:45:33 PM PDT 24
Finished Jul 23 06:45:38 PM PDT 24
Peak memory 200464 kb
Host smart-c823301f-60af-4940-9e5f-ebe610056137
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485113819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.3485113819
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.4137609470
Short name T735
Test name
Test status
Simulation time 72645751 ps
CPU time 0.83 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 199652 kb
Host smart-4c1f73ab-3797-41e7-8505-44967d98a2d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137609470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.4137609470
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.316404248
Short name T391
Test name
Test status
Simulation time 122987647 ps
CPU time 1.1 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:35 PM PDT 24
Peak memory 200404 kb
Host smart-e78c3ba0-6dde-4702-bbc4-ed8a41155347
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316404248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.clkmgr_div_intersig_mubi.316404248
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.3028480599
Short name T89
Test name
Test status
Simulation time 17878810 ps
CPU time 0.81 seconds
Started Jul 23 06:45:25 PM PDT 24
Finished Jul 23 06:45:29 PM PDT 24
Peak memory 200476 kb
Host smart-811e51d1-a5a7-4182-9b13-ea979e61b068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028480599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.3028480599
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.107555983
Short name T131
Test name
Test status
Simulation time 1516624820 ps
CPU time 12.02 seconds
Started Jul 23 06:45:25 PM PDT 24
Finished Jul 23 06:45:40 PM PDT 24
Peak memory 200452 kb
Host smart-00dc2b22-b2ce-41ba-88b7-9f0f44eb3521
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107555983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.107555983
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.1336898798
Short name T542
Test name
Test status
Simulation time 2054741101 ps
CPU time 15.24 seconds
Started Jul 23 06:45:31 PM PDT 24
Finished Jul 23 06:45:49 PM PDT 24
Peak memory 200708 kb
Host smart-cab437fe-8d68-4362-b36d-05dbed26f1a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336898798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.1336898798
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.1270734478
Short name T691
Test name
Test status
Simulation time 156233955 ps
CPU time 1.49 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:27 PM PDT 24
Peak memory 200460 kb
Host smart-82bf4390-dd15-4bee-a7d1-c3f769b0256c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270734478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.1270734478
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.4284592777
Short name T578
Test name
Test status
Simulation time 14849832 ps
CPU time 0.76 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:36 PM PDT 24
Peak memory 200452 kb
Host smart-ff368834-6d5d-40ae-9a77-66554dd42261
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284592777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.4284592777
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.45434454
Short name T51
Test name
Test status
Simulation time 39376287 ps
CPU time 0.78 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:36 PM PDT 24
Peak memory 200436 kb
Host smart-d33c1f24-b3cf-4c38-84d6-1db5d1a753fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45434454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_lc_ctrl_intersig_mubi.45434454
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.1649152844
Short name T190
Test name
Test status
Simulation time 16835104 ps
CPU time 0.8 seconds
Started Jul 23 06:45:23 PM PDT 24
Finished Jul 23 06:45:27 PM PDT 24
Peak memory 200380 kb
Host smart-c003426d-7a8b-44b8-87bb-3709ccf3fa22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649152844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1649152844
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.3928432948
Short name T702
Test name
Test status
Simulation time 506137138 ps
CPU time 2.38 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:38 PM PDT 24
Peak memory 200444 kb
Host smart-330a3700-ee94-42d3-a27e-3683576c95e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928432948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3928432948
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.283105179
Short name T628
Test name
Test status
Simulation time 67860386 ps
CPU time 1.09 seconds
Started Jul 23 06:45:28 PM PDT 24
Finished Jul 23 06:45:32 PM PDT 24
Peak memory 200440 kb
Host smart-3a9ee52f-7a06-4e5a-97b7-59e5a0f9b457
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283105179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.283105179
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.4053685811
Short name T622
Test name
Test status
Simulation time 13493100014 ps
CPU time 71.62 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 200776 kb
Host smart-89b07fa9-574b-4be9-8b6b-89084adbdf93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053685811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.4053685811
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3209393910
Short name T484
Test name
Test status
Simulation time 64175296 ps
CPU time 0.92 seconds
Started Jul 23 06:45:26 PM PDT 24
Finished Jul 23 06:45:29 PM PDT 24
Peak memory 200492 kb
Host smart-867e84d6-6ff8-46bc-b864-fc1af7bd1a80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209393910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3209393910
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.208569397
Short name T56
Test name
Test status
Simulation time 27293463 ps
CPU time 0.8 seconds
Started Jul 23 06:45:39 PM PDT 24
Finished Jul 23 06:45:47 PM PDT 24
Peak memory 200524 kb
Host smart-8d283e2f-ce4b-44fb-bf58-76bbd48cfcbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208569397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkm
gr_alert_test.208569397
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1613818933
Short name T224
Test name
Test status
Simulation time 60688301 ps
CPU time 0.92 seconds
Started Jul 23 06:45:36 PM PDT 24
Finished Jul 23 06:45:43 PM PDT 24
Peak memory 200416 kb
Host smart-c21e7665-2871-41fe-9ef0-0617252f50b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613818933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.1613818933
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1506254884
Short name T283
Test name
Test status
Simulation time 22421994 ps
CPU time 0.74 seconds
Started Jul 23 06:45:36 PM PDT 24
Finished Jul 23 06:45:42 PM PDT 24
Peak memory 199652 kb
Host smart-815738a8-171b-4331-bb81-088880153ba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506254884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1506254884
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.3816414020
Short name T643
Test name
Test status
Simulation time 80611135 ps
CPU time 1.08 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 200440 kb
Host smart-2ffbb590-1bab-4da3-9cc6-7fd98b82feb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816414020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.3816414020
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1135680462
Short name T389
Test name
Test status
Simulation time 1997389085 ps
CPU time 15.59 seconds
Started Jul 23 06:45:35 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 200688 kb
Host smart-f8ddf8ae-98e5-46ba-a249-b873442d32d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135680462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1135680462
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.1587621396
Short name T288
Test name
Test status
Simulation time 2056214063 ps
CPU time 14.7 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 200724 kb
Host smart-7e0b5996-4c11-44a6-84eb-525006dcac2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587621396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.1587621396
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.576334580
Short name T432
Test name
Test status
Simulation time 13190744 ps
CPU time 0.75 seconds
Started Jul 23 06:45:34 PM PDT 24
Finished Jul 23 06:45:39 PM PDT 24
Peak memory 200468 kb
Host smart-216055e1-b1ac-4d09-8aab-468fda62a5c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576334580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_clk_byp_req_intersig_mubi.576334580
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2480112283
Short name T808
Test name
Test status
Simulation time 23695627 ps
CPU time 0.77 seconds
Started Jul 23 06:45:40 PM PDT 24
Finished Jul 23 06:45:46 PM PDT 24
Peak memory 200452 kb
Host smart-803b728e-2f3f-4b71-888b-8a1f1a07c99c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480112283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.2480112283
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.2553562742
Short name T316
Test name
Test status
Simulation time 19335765 ps
CPU time 0.73 seconds
Started Jul 23 06:45:30 PM PDT 24
Finished Jul 23 06:45:34 PM PDT 24
Peak memory 200360 kb
Host smart-9005873a-3d09-4d76-83ad-8c4aa3320ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553562742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2553562742
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.2252655537
Short name T496
Test name
Test status
Simulation time 1359666086 ps
CPU time 5.32 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:48 PM PDT 24
Peak memory 200652 kb
Host smart-48db46d3-8bdc-427e-aa32-a77ec6b7ae58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252655537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2252655537
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.2476588162
Short name T446
Test name
Test status
Simulation time 16626672 ps
CPU time 0.84 seconds
Started Jul 23 06:45:33 PM PDT 24
Finished Jul 23 06:45:38 PM PDT 24
Peak memory 200424 kb
Host smart-03417c09-8812-4cc6-bad5-69ed0bb24e8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476588162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2476588162
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.3999090186
Short name T572
Test name
Test status
Simulation time 49161890 ps
CPU time 1.15 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:52 PM PDT 24
Peak memory 200424 kb
Host smart-96cefb34-0847-40f7-8f37-15857d8c8ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999090186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.3999090186
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.1309254045
Short name T583
Test name
Test status
Simulation time 22746410 ps
CPU time 0.78 seconds
Started Jul 23 06:45:32 PM PDT 24
Finished Jul 23 06:45:36 PM PDT 24
Peak memory 200460 kb
Host smart-62baa3ed-e12e-455f-af3f-5499f4aac36b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309254045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.1309254045
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.1024780763
Short name T454
Test name
Test status
Simulation time 144112412 ps
CPU time 1.17 seconds
Started Jul 23 06:45:43 PM PDT 24
Finished Jul 23 06:45:50 PM PDT 24
Peak memory 200548 kb
Host smart-f0136ef3-63ed-4edd-b4c7-abfceb003394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024780763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.1024780763
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3181882014
Short name T167
Test name
Test status
Simulation time 17002990 ps
CPU time 0.8 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 200480 kb
Host smart-fad9b18e-e92c-48ec-ab09-a2c427c29fde
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181882014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.3181882014
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.3130212462
Short name T243
Test name
Test status
Simulation time 46330829 ps
CPU time 0.79 seconds
Started Jul 23 06:45:37 PM PDT 24
Finished Jul 23 06:45:44 PM PDT 24
Peak memory 199616 kb
Host smart-321ffb44-1a1c-4161-9140-f565bd96b3ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130212462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3130212462
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.3720416309
Short name T648
Test name
Test status
Simulation time 21278330 ps
CPU time 0.83 seconds
Started Jul 23 06:45:46 PM PDT 24
Finished Jul 23 06:45:52 PM PDT 24
Peak memory 200464 kb
Host smart-d9116b96-10de-4710-8d35-3abe56ea4028
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720416309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.3720416309
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.1016100902
Short name T705
Test name
Test status
Simulation time 15104207 ps
CPU time 0.78 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:45:46 PM PDT 24
Peak memory 200444 kb
Host smart-2b415462-d865-4a66-8187-864590b14938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016100902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.1016100902
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.4104231087
Short name T130
Test name
Test status
Simulation time 1997292377 ps
CPU time 15.63 seconds
Started Jul 23 06:45:42 PM PDT 24
Finished Jul 23 06:46:03 PM PDT 24
Peak memory 200640 kb
Host smart-49521a78-9561-4844-9f43-2f5458dca6a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104231087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.4104231087
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.595645139
Short name T663
Test name
Test status
Simulation time 1235286988 ps
CPU time 5.34 seconds
Started Jul 23 06:45:39 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 200484 kb
Host smart-e8c6c411-1288-46a3-b389-fcc0861597a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595645139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_ti
meout.595645139
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.925058281
Short name T534
Test name
Test status
Simulation time 360820336 ps
CPU time 1.89 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:45:46 PM PDT 24
Peak memory 200460 kb
Host smart-fa6dac9f-651b-4f69-aace-d4510bc962ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925058281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.clkmgr_idle_intersig_mubi.925058281
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.1367008912
Short name T457
Test name
Test status
Simulation time 140147800 ps
CPU time 1.18 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:50 PM PDT 24
Peak memory 200392 kb
Host smart-34388b26-a8f2-4952-9bc8-82cef42683da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367008912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.1367008912
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.4193827073
Short name T693
Test name
Test status
Simulation time 53258008 ps
CPU time 0.89 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 200396 kb
Host smart-86d4f525-e38b-435d-b3d6-84aebb06a6d7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193827073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.4193827073
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.1717853872
Short name T481
Test name
Test status
Simulation time 11555599 ps
CPU time 0.73 seconds
Started Jul 23 06:45:42 PM PDT 24
Finished Jul 23 06:45:48 PM PDT 24
Peak memory 200452 kb
Host smart-b90c503a-b674-4db7-bb06-9ac63f0502c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717853872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1717853872
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.2494737013
Short name T444
Test name
Test status
Simulation time 1150680608 ps
CPU time 5.15 seconds
Started Jul 23 06:45:48 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 200600 kb
Host smart-908ab7e4-77eb-4548-bddc-ef45e3f81735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494737013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2494737013
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.3224243733
Short name T375
Test name
Test status
Simulation time 16647606 ps
CPU time 0.82 seconds
Started Jul 23 06:45:38 PM PDT 24
Finished Jul 23 06:45:45 PM PDT 24
Peak memory 200428 kb
Host smart-6626afe0-6b3f-4ec6-a3d5-4eabcebb419a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224243733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3224243733
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.3282829701
Short name T42
Test name
Test status
Simulation time 11832345902 ps
CPU time 49.32 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 200776 kb
Host smart-b10b67ec-0758-49c1-8dff-232948688e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282829701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.3282829701
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.4183402053
Short name T608
Test name
Test status
Simulation time 14094884 ps
CPU time 0.76 seconds
Started Jul 23 06:45:39 PM PDT 24
Finished Jul 23 06:45:46 PM PDT 24
Peak memory 200460 kb
Host smart-1015bd5f-8d12-4a31-aaf7-b1019d0cf678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183402053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.4183402053
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.9859158
Short name T384
Test name
Test status
Simulation time 43342197 ps
CPU time 0.8 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 200500 kb
Host smart-3fd23867-cbf7-4b77-81b4-ab6d876fdcab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9859158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr
_alert_test.9859158
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2010726107
Short name T95
Test name
Test status
Simulation time 72171904 ps
CPU time 1.03 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 200692 kb
Host smart-594f31da-bc5e-4ccc-a90d-91f949932a9e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010726107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.2010726107
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.2879333318
Short name T780
Test name
Test status
Simulation time 19510399 ps
CPU time 0.68 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 200368 kb
Host smart-f3a2ccb0-bfeb-4998-8608-ee8d7c35d757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879333318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.2879333318
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.2810468706
Short name T758
Test name
Test status
Simulation time 15971607 ps
CPU time 0.78 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 200444 kb
Host smart-211f92c5-3f32-4ead-8aff-fef358042ce4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810468706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.2810468706
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.233596717
Short name T401
Test name
Test status
Simulation time 20133383 ps
CPU time 0.82 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 200336 kb
Host smart-df2d6952-ccbc-4502-8e3e-c11d29689e8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233596717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.233596717
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.3446228258
Short name T178
Test name
Test status
Simulation time 2479770249 ps
CPU time 10.99 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:46:09 PM PDT 24
Peak memory 200716 kb
Host smart-068b234a-c259-4bcc-a058-3a4265f17bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446228258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3446228258
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.3938244856
Short name T660
Test name
Test status
Simulation time 988178367 ps
CPU time 5.52 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:56 PM PDT 24
Peak memory 200472 kb
Host smart-7b64061f-8b7c-448a-a044-504934721eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938244856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.3938244856
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.3196013194
Short name T759
Test name
Test status
Simulation time 22176486 ps
CPU time 0.89 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:50 PM PDT 24
Peak memory 200488 kb
Host smart-ffcb9974-6faa-4e9d-8b88-2c8e8c27b8e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196013194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.3196013194
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2934761524
Short name T716
Test name
Test status
Simulation time 22142827 ps
CPU time 0.84 seconds
Started Jul 23 06:45:42 PM PDT 24
Finished Jul 23 06:45:49 PM PDT 24
Peak memory 200368 kb
Host smart-8d1dd559-a92a-42cc-be8c-418c58cc83ed
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934761524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.2934761524
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.2411672895
Short name T349
Test name
Test status
Simulation time 16014051 ps
CPU time 0.83 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:49 PM PDT 24
Peak memory 200416 kb
Host smart-bf9c4f6b-b386-4e74-a9f8-b7eb8faa4f5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411672895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.2411672895
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.1443768973
Short name T311
Test name
Test status
Simulation time 1215634384 ps
CPU time 4.06 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:53 PM PDT 24
Peak memory 200620 kb
Host smart-cced6e71-7e1b-44fb-b488-cba7f023a206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443768973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1443768973
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.1587798437
Short name T427
Test name
Test status
Simulation time 68423562 ps
CPU time 1.01 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 200420 kb
Host smart-be294d72-9dba-4e30-ad5f-91145afe887a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587798437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.1587798437
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.1660378948
Short name T299
Test name
Test status
Simulation time 2194237741 ps
CPU time 11.12 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 201004 kb
Host smart-2352d028-6fa3-403d-bc07-9a5d9ce1779d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660378948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.1660378948
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.2762665275
Short name T71
Test name
Test status
Simulation time 79193158546 ps
CPU time 539.79 seconds
Started Jul 23 06:45:46 PM PDT 24
Finished Jul 23 06:54:52 PM PDT 24
Peak memory 217208 kb
Host smart-a22a5c66-520e-4323-808f-952665384d8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2762665275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.2762665275
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.2358054786
Short name T806
Test name
Test status
Simulation time 161641560 ps
CPU time 1.35 seconds
Started Jul 23 06:45:44 PM PDT 24
Finished Jul 23 06:45:50 PM PDT 24
Peak memory 200480 kb
Host smart-63f49fbd-956c-4878-b18e-b643dc4a274c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358054786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2358054786
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.13140363
Short name T246
Test name
Test status
Simulation time 14778267 ps
CPU time 0.78 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 200532 kb
Host smart-2b3d95e8-f433-4a12-b4c4-77b0827df366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13140363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr
_alert_test.13140363
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1910494313
Short name T101
Test name
Test status
Simulation time 27323209 ps
CPU time 0.96 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 200416 kb
Host smart-70da6ecc-9373-4968-ba5b-63ef4cbbdb6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910494313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1910494313
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.4205616092
Short name T189
Test name
Test status
Simulation time 18041028 ps
CPU time 0.73 seconds
Started Jul 23 06:44:02 PM PDT 24
Finished Jul 23 06:44:06 PM PDT 24
Peak memory 199644 kb
Host smart-d8068400-a1b0-4feb-b950-9e8404323dbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205616092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.4205616092
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.2328874653
Short name T324
Test name
Test status
Simulation time 83798444 ps
CPU time 1.13 seconds
Started Jul 23 06:44:07 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 200464 kb
Host smart-18ca5ad2-3d7f-4247-ae3e-4668e4b6c658
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328874653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.2328874653
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.2982670648
Short name T125
Test name
Test status
Simulation time 20494930 ps
CPU time 0.8 seconds
Started Jul 23 06:43:59 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 200460 kb
Host smart-4322648e-8516-4a93-b7e0-9ac5723fa6cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982670648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2982670648
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.2904910611
Short name T769
Test name
Test status
Simulation time 435350592 ps
CPU time 3.98 seconds
Started Jul 23 06:44:02 PM PDT 24
Finished Jul 23 06:44:09 PM PDT 24
Peak memory 200432 kb
Host smart-de2254fa-3a95-44f9-ac24-a7acfccf1e01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904910611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2904910611
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.3380321931
Short name T746
Test name
Test status
Simulation time 1150789095 ps
CPU time 4.27 seconds
Started Jul 23 06:44:02 PM PDT 24
Finished Jul 23 06:44:09 PM PDT 24
Peak memory 200528 kb
Host smart-85d594cf-8419-44a0-891b-e0c7f9b1dfd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380321931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.3380321931
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1058647821
Short name T327
Test name
Test status
Simulation time 54458430 ps
CPU time 0.9 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:10 PM PDT 24
Peak memory 200408 kb
Host smart-b3b8e6d8-1c47-44b1-b453-be1113e54464
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058647821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.1058647821
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1637163950
Short name T75
Test name
Test status
Simulation time 28139070 ps
CPU time 0.78 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 200484 kb
Host smart-edbd8281-1590-43b7-a5a8-0c9d120ee302
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637163950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.1637163950
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.2033081671
Short name T194
Test name
Test status
Simulation time 37342148 ps
CPU time 0.89 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:10 PM PDT 24
Peak memory 200496 kb
Host smart-2d597bc5-d10c-476f-bab6-10813df153e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033081671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.2033081671
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2583154710
Short name T476
Test name
Test status
Simulation time 37802066 ps
CPU time 0.81 seconds
Started Jul 23 06:44:00 PM PDT 24
Finished Jul 23 06:44:05 PM PDT 24
Peak memory 200420 kb
Host smart-db13d500-fb55-4eb2-91cd-dd7104936a89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583154710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2583154710
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.383396116
Short name T420
Test name
Test status
Simulation time 1249905077 ps
CPU time 5.75 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:16 PM PDT 24
Peak memory 200632 kb
Host smart-6381f11c-012b-474c-a45b-553f2af239df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383396116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.383396116
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.2237368346
Short name T45
Test name
Test status
Simulation time 392181518 ps
CPU time 2.5 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:11 PM PDT 24
Peak memory 215748 kb
Host smart-d8cba761-2ada-4b24-8ebc-4b52841e975a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237368346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.2237368346
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.3846777017
Short name T30
Test name
Test status
Simulation time 2293168540 ps
CPU time 18.51 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 200736 kb
Host smart-d0784bb4-806b-4601-8f90-362898235f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846777017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.3846777017
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.1525485456
Short name T310
Test name
Test status
Simulation time 42874598 ps
CPU time 0.83 seconds
Started Jul 23 06:43:59 PM PDT 24
Finished Jul 23 06:44:04 PM PDT 24
Peak memory 200456 kb
Host smart-ca75b2bd-337e-4857-a514-8d8c7b83a1ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525485456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1525485456
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.1448180671
Short name T655
Test name
Test status
Simulation time 145261753 ps
CPU time 1.1 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 200536 kb
Host smart-3c9c82ab-e674-4c27-bbe8-86096116c0a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448180671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.1448180671
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2801068786
Short name T358
Test name
Test status
Simulation time 12710370 ps
CPU time 0.76 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:00 PM PDT 24
Peak memory 200448 kb
Host smart-a4e526f3-b8b6-4992-8110-2826d56b3903
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801068786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.2801068786
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.2288965095
Short name T215
Test name
Test status
Simulation time 18114553 ps
CPU time 0.75 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:57 PM PDT 24
Peak memory 200368 kb
Host smart-25a16777-e917-4786-bdb3-62a1e31c2a53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288965095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.2288965095
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.587074599
Short name T408
Test name
Test status
Simulation time 24219020 ps
CPU time 0.82 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 200456 kb
Host smart-be851a38-e819-40fc-ba58-658b3a25b054
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587074599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.587074599
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.3979513957
Short name T255
Test name
Test status
Simulation time 61579918 ps
CPU time 0.88 seconds
Started Jul 23 06:45:48 PM PDT 24
Finished Jul 23 06:45:55 PM PDT 24
Peak memory 200696 kb
Host smart-3f8b5aec-1e4e-4c16-8a7f-bfa2c83fb20a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979513957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3979513957
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.2828724054
Short name T17
Test name
Test status
Simulation time 1279310877 ps
CPU time 10.63 seconds
Started Jul 23 06:45:47 PM PDT 24
Finished Jul 23 06:46:03 PM PDT 24
Peak memory 200440 kb
Host smart-47a63fdf-7646-41a0-ba20-202265fede6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828724054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2828724054
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.1950353601
Short name T379
Test name
Test status
Simulation time 1661338477 ps
CPU time 7.13 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:46:02 PM PDT 24
Peak memory 200508 kb
Host smart-3ec7bc63-11c5-4ce1-8637-ee9c103df7c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950353601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.1950353601
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3124869759
Short name T635
Test name
Test status
Simulation time 15207616 ps
CPU time 0.76 seconds
Started Jul 23 06:45:53 PM PDT 24
Finished Jul 23 06:46:01 PM PDT 24
Peak memory 200432 kb
Host smart-7292ac14-3cd7-4813-9358-e3f69c20ecb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124869759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.3124869759
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.258502409
Short name T400
Test name
Test status
Simulation time 51675626 ps
CPU time 0.88 seconds
Started Jul 23 06:45:54 PM PDT 24
Finished Jul 23 06:46:03 PM PDT 24
Peak memory 200484 kb
Host smart-0766f2a4-0765-4403-858a-65415f916bb3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258502409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_clk_byp_req_intersig_mubi.258502409
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.766554456
Short name T473
Test name
Test status
Simulation time 43010293 ps
CPU time 0.95 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 200464 kb
Host smart-ba49fd00-9b6f-47b8-a85c-6362c9ebb8a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766554456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_ctrl_intersig_mubi.766554456
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.2792658926
Short name T647
Test name
Test status
Simulation time 53994692 ps
CPU time 0.88 seconds
Started Jul 23 06:45:45 PM PDT 24
Finished Jul 23 06:45:51 PM PDT 24
Peak memory 200440 kb
Host smart-9efe2193-bea5-4386-b80c-e3e6ea9faa8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792658926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.2792658926
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.4026601496
Short name T268
Test name
Test status
Simulation time 1437917566 ps
CPU time 5.34 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 200632 kb
Host smart-00a3282e-5fdb-4ff5-9237-132842ffed11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026601496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.4026601496
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.1205536681
Short name T603
Test name
Test status
Simulation time 75753176 ps
CPU time 1.03 seconds
Started Jul 23 06:45:47 PM PDT 24
Finished Jul 23 06:45:54 PM PDT 24
Peak memory 200392 kb
Host smart-68560f6a-1e9c-407a-ac2e-7efe552b9a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205536681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.1205536681
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.25080917
Short name T335
Test name
Test status
Simulation time 3033423263 ps
CPU time 13.84 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 200724 kb
Host smart-ae8d6f57-1464-4b04-993b-f1fd31e6300d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25080917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_stress_all.25080917
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.2566972826
Short name T371
Test name
Test status
Simulation time 12975757 ps
CPU time 0.75 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 200456 kb
Host smart-cf4cf972-f7f4-4ee7-bf6c-02b2d06650c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566972826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2566972826
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.3791159506
Short name T545
Test name
Test status
Simulation time 61847980 ps
CPU time 0.89 seconds
Started Jul 23 06:45:55 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 200512 kb
Host smart-6b4b5a2f-7ebb-442e-9f4d-1c60a4b5f782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791159506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.3791159506
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2302039663
Short name T98
Test name
Test status
Simulation time 22877801 ps
CPU time 0.86 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:00 PM PDT 24
Peak memory 200500 kb
Host smart-3c063846-714d-44fe-895f-744aedf0b5de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302039663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.2302039663
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.414680075
Short name T160
Test name
Test status
Simulation time 35162172 ps
CPU time 0.79 seconds
Started Jul 23 06:45:59 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 199656 kb
Host smart-9dd95208-fdea-4413-885d-ffaee2e877a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414680075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.414680075
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.3798780642
Short name T372
Test name
Test status
Simulation time 59130663 ps
CPU time 0.96 seconds
Started Jul 23 06:45:52 PM PDT 24
Finished Jul 23 06:46:01 PM PDT 24
Peak memory 200464 kb
Host smart-b27c7037-f20a-41c0-a161-c709d4a12aa7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798780642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.3798780642
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.345913860
Short name T671
Test name
Test status
Simulation time 52980183 ps
CPU time 1.02 seconds
Started Jul 23 06:45:48 PM PDT 24
Finished Jul 23 06:46:02 PM PDT 24
Peak memory 200356 kb
Host smart-c9533957-aa73-495e-9fc1-4eaa8fdc40b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345913860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.345913860
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.2332453138
Short name T79
Test name
Test status
Simulation time 2016214663 ps
CPU time 9.51 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 200636 kb
Host smart-f3e23ae1-b544-466a-ae7b-05dbe97ebe01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332453138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2332453138
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.381930824
Short name T197
Test name
Test status
Simulation time 2067845847 ps
CPU time 10.97 seconds
Started Jul 23 06:45:49 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 200720 kb
Host smart-a4dd508a-aae3-4fb3-994f-b63c1931ac25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381930824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_ti
meout.381930824
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1904324027
Short name T788
Test name
Test status
Simulation time 61703492 ps
CPU time 1.1 seconds
Started Jul 23 06:45:54 PM PDT 24
Finished Jul 23 06:46:04 PM PDT 24
Peak memory 200464 kb
Host smart-7cc80016-7227-41b8-aa36-931dc1762879
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904324027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.1904324027
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.885946186
Short name T662
Test name
Test status
Simulation time 120725956 ps
CPU time 1.17 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 200384 kb
Host smart-73ceee3b-4f75-429c-97a2-a3054ee84d08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885946186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_clk_byp_req_intersig_mubi.885946186
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2231283161
Short name T747
Test name
Test status
Simulation time 16693873 ps
CPU time 0.82 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 200456 kb
Host smart-1fd4b84c-7da8-447d-8afd-4b534c3a0745
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231283161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.2231283161
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.3821135806
Short name T543
Test name
Test status
Simulation time 31938598 ps
CPU time 0.78 seconds
Started Jul 23 06:45:54 PM PDT 24
Finished Jul 23 06:46:03 PM PDT 24
Peak memory 200456 kb
Host smart-4b7c11c4-edc0-4d8b-b46d-53214008f263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821135806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3821135806
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.2173015180
Short name T765
Test name
Test status
Simulation time 1375002515 ps
CPU time 6.22 seconds
Started Jul 23 06:45:54 PM PDT 24
Finished Jul 23 06:46:09 PM PDT 24
Peak memory 200660 kb
Host smart-f6e31344-cd08-4a98-9e9d-36140f350387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173015180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.2173015180
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.1160094226
Short name T652
Test name
Test status
Simulation time 47334134 ps
CPU time 0.92 seconds
Started Jul 23 06:45:51 PM PDT 24
Finished Jul 23 06:45:59 PM PDT 24
Peak memory 200380 kb
Host smart-ea1779cd-bb42-47a9-b35c-d6b90812af3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160094226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1160094226
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.3531673802
Short name T460
Test name
Test status
Simulation time 15436790757 ps
CPU time 82.98 seconds
Started Jul 23 06:45:55 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 200684 kb
Host smart-d662b434-7477-46be-a344-012725d12862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531673802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.3531673802
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.2385913389
Short name T554
Test name
Test status
Simulation time 59178277 ps
CPU time 0.92 seconds
Started Jul 23 06:45:50 PM PDT 24
Finished Jul 23 06:45:58 PM PDT 24
Peak memory 200448 kb
Host smart-d863b28d-d450-47ab-9db4-082351f3da89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385913389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2385913389
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.196765105
Short name T219
Test name
Test status
Simulation time 62676481 ps
CPU time 0.9 seconds
Started Jul 23 06:46:06 PM PDT 24
Finished Jul 23 06:46:13 PM PDT 24
Peak memory 200520 kb
Host smart-2981fa23-8292-4084-985e-b09de9998a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196765105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkm
gr_alert_test.196765105
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1031623983
Short name T192
Test name
Test status
Simulation time 22634316 ps
CPU time 0.87 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 200468 kb
Host smart-9d239f12-ff94-4ec9-a8b6-4420f3a87fa7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031623983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.1031623983
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.2182728180
Short name T465
Test name
Test status
Simulation time 37283270 ps
CPU time 0.75 seconds
Started Jul 23 06:45:59 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 199652 kb
Host smart-8b6b9b29-094f-4f33-a4e9-14c98b31207e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182728180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2182728180
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.3056039525
Short name T708
Test name
Test status
Simulation time 21305681 ps
CPU time 0.85 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:06 PM PDT 24
Peak memory 200472 kb
Host smart-c4276de9-88b7-428f-87af-c63c2432855d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056039525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.3056039525
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.1863120751
Short name T55
Test name
Test status
Simulation time 107148394 ps
CPU time 1.16 seconds
Started Jul 23 06:45:56 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 200328 kb
Host smart-9e4fe4fc-de2b-438b-bc13-4a20ef828dd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863120751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.1863120751
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.2204903095
Short name T636
Test name
Test status
Simulation time 2369003187 ps
CPU time 10.48 seconds
Started Jul 23 06:45:57 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 200704 kb
Host smart-cbb80254-b34d-460e-b35d-d0b0875b4e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204903095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.2204903095
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.3554464142
Short name T35
Test name
Test status
Simulation time 1940333626 ps
CPU time 15.21 seconds
Started Jul 23 06:45:56 PM PDT 24
Finished Jul 23 06:46:19 PM PDT 24
Peak memory 200556 kb
Host smart-89f99d9a-96f7-42e1-ba4a-04b491ed103d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554464142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.3554464142
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.124203482
Short name T519
Test name
Test status
Simulation time 77123725 ps
CPU time 1.04 seconds
Started Jul 23 06:46:01 PM PDT 24
Finished Jul 23 06:46:09 PM PDT 24
Peak memory 200440 kb
Host smart-a063ae14-3122-4b99-baec-5476636c7452
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124203482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_idle_intersig_mubi.124203482
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2230819118
Short name T355
Test name
Test status
Simulation time 19402434 ps
CPU time 0.8 seconds
Started Jul 23 06:45:59 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 200448 kb
Host smart-199a2390-1f8e-4da9-9647-797be3e23c47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230819118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2230819118
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.526881905
Short name T588
Test name
Test status
Simulation time 56526380 ps
CPU time 0.93 seconds
Started Jul 23 06:45:59 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 200440 kb
Host smart-4b5f376e-35cd-48c4-8a4d-6ea9e5de885e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526881905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_ctrl_intersig_mubi.526881905
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.573122860
Short name T461
Test name
Test status
Simulation time 97283983 ps
CPU time 1.01 seconds
Started Jul 23 06:45:56 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 200432 kb
Host smart-eb89470d-2399-4e1e-99ff-b9923e355bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573122860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.573122860
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2580733926
Short name T520
Test name
Test status
Simulation time 1415021930 ps
CPU time 5.45 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 200672 kb
Host smart-00439e59-c0c3-466d-bace-cc48351b7f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580733926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2580733926
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.943940019
Short name T184
Test name
Test status
Simulation time 18714212 ps
CPU time 0.89 seconds
Started Jul 23 06:45:59 PM PDT 24
Finished Jul 23 06:46:07 PM PDT 24
Peak memory 200440 kb
Host smart-ecac4fa1-ed91-4f4f-9a2b-2d1a5549127f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943940019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.943940019
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.529792827
Short name T536
Test name
Test status
Simulation time 2243004424 ps
CPU time 17.16 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:27 PM PDT 24
Peak memory 200744 kb
Host smart-8eee56a6-9d36-477c-b6b0-17c020490a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529792827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.529792827
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.2149110692
Short name T725
Test name
Test status
Simulation time 131230939 ps
CPU time 1.39 seconds
Started Jul 23 06:45:55 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 200500 kb
Host smart-a23d14e4-f8fa-4aab-8a1c-1b03c9c8638a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149110692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2149110692
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.4159820975
Short name T575
Test name
Test status
Simulation time 24541920 ps
CPU time 0.78 seconds
Started Jul 23 06:46:01 PM PDT 24
Finished Jul 23 06:46:08 PM PDT 24
Peak memory 200512 kb
Host smart-fe28633c-3cb4-4052-b3c7-a52f29704030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159820975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.4159820975
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2747294906
Short name T415
Test name
Test status
Simulation time 108549428 ps
CPU time 1.16 seconds
Started Jul 23 06:46:08 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 200436 kb
Host smart-c08a2253-778c-481f-9a7b-74eccd8e8362
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747294906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.2747294906
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.4017658542
Short name T736
Test name
Test status
Simulation time 104103694 ps
CPU time 0.93 seconds
Started Jul 23 06:46:21 PM PDT 24
Finished Jul 23 06:46:23 PM PDT 24
Peak memory 199648 kb
Host smart-193905ae-e212-4f09-9c98-2173ecba8ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017658542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.4017658542
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2584847537
Short name T528
Test name
Test status
Simulation time 31575283 ps
CPU time 0.83 seconds
Started Jul 23 06:46:02 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 200492 kb
Host smart-cd9b523e-505c-4561-8bbb-35e3464c78a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584847537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2584847537
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.3637021936
Short name T822
Test name
Test status
Simulation time 87931153 ps
CPU time 1.09 seconds
Started Jul 23 06:45:56 PM PDT 24
Finished Jul 23 06:46:05 PM PDT 24
Peak memory 200460 kb
Host smart-766d69e8-704b-439c-8f7c-a0aee17e3345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637021936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3637021936
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.1501666414
Short name T500
Test name
Test status
Simulation time 267485591 ps
CPU time 1.62 seconds
Started Jul 23 06:46:11 PM PDT 24
Finished Jul 23 06:46:17 PM PDT 24
Peak memory 200356 kb
Host smart-1733ba70-cc60-49b5-8402-8738f97fe95f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501666414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1501666414
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.2805836957
Short name T825
Test name
Test status
Simulation time 293505132 ps
CPU time 1.75 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 200528 kb
Host smart-854bacde-bc65-42fe-9b97-36fd242da0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805836957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.2805836957
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.4062045154
Short name T777
Test name
Test status
Simulation time 30403502 ps
CPU time 0.98 seconds
Started Jul 23 06:46:08 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 200400 kb
Host smart-c29b6e34-4922-4baa-8e1e-c99791416ea9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062045154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.4062045154
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.539839099
Short name T640
Test name
Test status
Simulation time 14833961 ps
CPU time 0.75 seconds
Started Jul 23 06:46:20 PM PDT 24
Finished Jul 23 06:46:22 PM PDT 24
Peak memory 200468 kb
Host smart-9a9b3534-855e-463d-af40-2c08413ecc5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539839099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.clkmgr_lc_clk_byp_req_intersig_mubi.539839099
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2216330584
Short name T244
Test name
Test status
Simulation time 217920967 ps
CPU time 1.44 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 200484 kb
Host smart-c75e2b56-2f98-4f67-b872-235c7097b54f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216330584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.2216330584
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.3219266831
Short name T94
Test name
Test status
Simulation time 13791486 ps
CPU time 0.76 seconds
Started Jul 23 06:46:04 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 200432 kb
Host smart-19ea4dd4-f6de-4fb6-90d9-721f3144b382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219266831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3219266831
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.3600867932
Short name T613
Test name
Test status
Simulation time 613277728 ps
CPU time 3.8 seconds
Started Jul 23 06:46:05 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 200620 kb
Host smart-4c04a972-d08f-4bc5-83b4-b5b343566bc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600867932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3600867932
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.2985940892
Short name T241
Test name
Test status
Simulation time 50316904 ps
CPU time 0.88 seconds
Started Jul 23 06:46:02 PM PDT 24
Finished Jul 23 06:46:10 PM PDT 24
Peak memory 200380 kb
Host smart-21b84a71-d4a6-4c8d-b135-280dab089c4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985940892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2985940892
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.818309008
Short name T346
Test name
Test status
Simulation time 46329438 ps
CPU time 1.08 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 200428 kb
Host smart-ddf17309-445b-4b44-9b30-e4cd902ed1e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818309008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.818309008
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2526598358
Short name T300
Test name
Test status
Simulation time 186200339 ps
CPU time 1.44 seconds
Started Jul 23 06:46:03 PM PDT 24
Finished Jul 23 06:46:11 PM PDT 24
Peak memory 200476 kb
Host smart-f693647a-8aca-4a34-88a9-deb40101dd53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526598358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2526598358
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.2753589331
Short name T804
Test name
Test status
Simulation time 14915114 ps
CPU time 0.74 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 200532 kb
Host smart-a410d10a-1659-4563-ba92-0f7a90d846b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753589331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.2753589331
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3995279142
Short name T352
Test name
Test status
Simulation time 33971942 ps
CPU time 0.96 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:35 PM PDT 24
Peak memory 200336 kb
Host smart-611a4072-a401-498f-aee5-23ac07073612
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995279142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3995279142
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.2520558462
Short name T717
Test name
Test status
Simulation time 146208526 ps
CPU time 1.14 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 199648 kb
Host smart-9adb4d58-9021-45fd-974b-1c1f44e592e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520558462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2520558462
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.2453894833
Short name T239
Test name
Test status
Simulation time 97022754 ps
CPU time 1.18 seconds
Started Jul 23 06:46:23 PM PDT 24
Finished Jul 23 06:46:26 PM PDT 24
Peak memory 200448 kb
Host smart-f7af5d84-8a04-41c8-978c-f90f9d282bb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453894833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.2453894833
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2464256548
Short name T165
Test name
Test status
Simulation time 25846766 ps
CPU time 0.89 seconds
Started Jul 23 06:46:02 PM PDT 24
Finished Jul 23 06:46:09 PM PDT 24
Peak memory 200472 kb
Host smart-fe6bfd04-77de-4a86-9012-8b19488795f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464256548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2464256548
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.1248579806
Short name T801
Test name
Test status
Simulation time 2013943387 ps
CPU time 9.33 seconds
Started Jul 23 06:46:08 PM PDT 24
Finished Jul 23 06:46:23 PM PDT 24
Peak memory 200688 kb
Host smart-4bbf3e9f-4f48-465c-8732-e9f063b2d7ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248579806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1248579806
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.2750992731
Short name T525
Test name
Test status
Simulation time 692512827 ps
CPU time 2.67 seconds
Started Jul 23 06:46:13 PM PDT 24
Finished Jul 23 06:46:19 PM PDT 24
Peak memory 200512 kb
Host smart-60fc1467-f280-40b4-9ea8-aa8776ddd09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750992731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.2750992731
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3068552435
Short name T452
Test name
Test status
Simulation time 52778999 ps
CPU time 0.89 seconds
Started Jul 23 06:46:09 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 200440 kb
Host smart-db92826d-2e45-4a7e-bca7-d49a3e802d8f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068552435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3068552435
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1846717222
Short name T571
Test name
Test status
Simulation time 52577119 ps
CPU time 0.88 seconds
Started Jul 23 06:46:11 PM PDT 24
Finished Jul 23 06:46:16 PM PDT 24
Peak memory 200492 kb
Host smart-94d25757-8ae1-42c2-84e6-2b4d4ca4fefc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846717222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1846717222
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.775320127
Short name T824
Test name
Test status
Simulation time 22715600 ps
CPU time 0.86 seconds
Started Jul 23 06:46:11 PM PDT 24
Finished Jul 23 06:46:15 PM PDT 24
Peak memory 200456 kb
Host smart-97affccf-2f4c-46ee-9349-2d9fdebeedd1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775320127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_ctrl_intersig_mubi.775320127
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.2381750152
Short name T477
Test name
Test status
Simulation time 15788671 ps
CPU time 0.76 seconds
Started Jul 23 06:46:14 PM PDT 24
Finished Jul 23 06:46:17 PM PDT 24
Peak memory 200456 kb
Host smart-dc8fbe48-a971-430e-a490-794438296827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381750152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.2381750152
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.977199645
Short name T524
Test name
Test status
Simulation time 1114689316 ps
CPU time 5.93 seconds
Started Jul 23 06:46:21 PM PDT 24
Finished Jul 23 06:46:29 PM PDT 24
Peak memory 200560 kb
Host smart-fd1120fc-5894-4e70-a023-0db3ab54d23f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977199645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.977199645
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.442383870
Short name T555
Test name
Test status
Simulation time 25191272 ps
CPU time 0.91 seconds
Started Jul 23 06:46:07 PM PDT 24
Finished Jul 23 06:46:14 PM PDT 24
Peak memory 200400 kb
Host smart-d8d11416-93b8-43ab-a1a5-0f5a3d117e28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442383870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.442383870
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.4141398684
Short name T41
Test name
Test status
Simulation time 2518699736 ps
CPU time 12.4 seconds
Started Jul 23 06:46:26 PM PDT 24
Finished Jul 23 06:46:42 PM PDT 24
Peak memory 200756 kb
Host smart-9bbf8d9f-fa6d-4c87-b1df-9678bc1fec6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141398684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.4141398684
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.4121228448
Short name T16
Test name
Test status
Simulation time 112893084363 ps
CPU time 772.93 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:59:28 PM PDT 24
Peak memory 216648 kb
Host smart-41155f87-55ff-4bd5-8d60-e1e559dd2a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4121228448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.4121228448
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.clkmgr_trans.168616879
Short name T469
Test name
Test status
Simulation time 106540329 ps
CPU time 1.11 seconds
Started Jul 23 06:46:24 PM PDT 24
Finished Jul 23 06:46:27 PM PDT 24
Peak memory 200448 kb
Host smart-a126619f-32ec-4b38-9dad-7286e25c95e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168616879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.168616879
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.2542667760
Short name T201
Test name
Test status
Simulation time 69658039 ps
CPU time 0.91 seconds
Started Jul 23 06:46:19 PM PDT 24
Finished Jul 23 06:46:22 PM PDT 24
Peak memory 200508 kb
Host smart-bcaa4d01-36a9-4f93-8ccb-95a5dffbd656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542667760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.2542667760
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2313149680
Short name T741
Test name
Test status
Simulation time 18706124 ps
CPU time 0.86 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:35 PM PDT 24
Peak memory 200484 kb
Host smart-dbe3ffc6-0732-48eb-acfd-d54cb897b082
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313149680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.2313149680
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.4171852216
Short name T418
Test name
Test status
Simulation time 35883608 ps
CPU time 0.79 seconds
Started Jul 23 06:46:26 PM PDT 24
Finished Jul 23 06:46:30 PM PDT 24
Peak memory 199644 kb
Host smart-99499848-515c-4d70-ab5a-6bf9ff95c0db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171852216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.4171852216
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.4255980948
Short name T811
Test name
Test status
Simulation time 15446233 ps
CPU time 0.74 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:32 PM PDT 24
Peak memory 200436 kb
Host smart-215a1a86-8322-43dd-8e84-3e2c36885d29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255980948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.4255980948
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.1709416251
Short name T313
Test name
Test status
Simulation time 19227152 ps
CPU time 0.8 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:32 PM PDT 24
Peak memory 200404 kb
Host smart-b5e0a651-a751-4f2b-a8ec-ec34a702c1f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709416251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.1709416251
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.3845956799
Short name T637
Test name
Test status
Simulation time 714249284 ps
CPU time 3.53 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 200692 kb
Host smart-ec61e1ff-274e-4080-968c-f464f53c7a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845956799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3845956799
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.578468685
Short name T565
Test name
Test status
Simulation time 2421984997 ps
CPU time 16.33 seconds
Started Jul 23 06:46:16 PM PDT 24
Finished Jul 23 06:46:34 PM PDT 24
Peak memory 200760 kb
Host smart-1abb0c6a-f057-48bd-8e5a-a0659c5e6140
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578468685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_ti
meout.578468685
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3001957054
Short name T478
Test name
Test status
Simulation time 55681423 ps
CPU time 0.94 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 200444 kb
Host smart-476cd676-d171-4e28-9077-aa6c8104645f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001957054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3001957054
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2907383476
Short name T124
Test name
Test status
Simulation time 80987026 ps
CPU time 1.1 seconds
Started Jul 23 06:46:17 PM PDT 24
Finished Jul 23 06:46:19 PM PDT 24
Peak memory 200488 kb
Host smart-c835956d-5aca-4ad1-a301-f53e61710730
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907383476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.2907383476
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.106957610
Short name T749
Test name
Test status
Simulation time 27543077 ps
CPU time 0.94 seconds
Started Jul 23 06:46:18 PM PDT 24
Finished Jul 23 06:46:20 PM PDT 24
Peak memory 200472 kb
Host smart-e3d4d4a4-bff7-44ee-a373-b513001d5c4e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106957610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_ctrl_intersig_mubi.106957610
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.846505768
Short name T428
Test name
Test status
Simulation time 18599063 ps
CPU time 0.75 seconds
Started Jul 23 06:46:16 PM PDT 24
Finished Jul 23 06:46:18 PM PDT 24
Peak memory 200456 kb
Host smart-9180f867-cc13-4f7e-a6aa-d755b3482f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846505768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.846505768
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.2665089161
Short name T742
Test name
Test status
Simulation time 98147578 ps
CPU time 1.13 seconds
Started Jul 23 06:46:17 PM PDT 24
Finished Jul 23 06:46:20 PM PDT 24
Peak memory 200464 kb
Host smart-008949fc-d3e3-4766-9636-00c092b43dd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665089161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.2665089161
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.3581792345
Short name T402
Test name
Test status
Simulation time 76490172 ps
CPU time 0.99 seconds
Started Jul 23 06:46:20 PM PDT 24
Finished Jul 23 06:46:23 PM PDT 24
Peak memory 200400 kb
Host smart-920f5442-125c-4faf-9be0-5a710a7b533d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581792345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3581792345
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.3849179649
Short name T416
Test name
Test status
Simulation time 7261494410 ps
CPU time 30.22 seconds
Started Jul 23 06:46:19 PM PDT 24
Finished Jul 23 06:46:50 PM PDT 24
Peak memory 200744 kb
Host smart-06d621b9-1444-41ae-b927-59e184bd1acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849179649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.3849179649
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.1424249084
Short name T425
Test name
Test status
Simulation time 94586684 ps
CPU time 1.11 seconds
Started Jul 23 06:46:16 PM PDT 24
Finished Jul 23 06:46:18 PM PDT 24
Peak memory 200392 kb
Host smart-8aceb72d-c639-47ee-a905-cd309f0cf669
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424249084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1424249084
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.633621432
Short name T539
Test name
Test status
Simulation time 22774455 ps
CPU time 0.78 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:36 PM PDT 24
Peak memory 200492 kb
Host smart-ebea5ede-e31b-4c0d-9875-4d6aa2a7c359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633621432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkm
gr_alert_test.633621432
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3445690643
Short name T767
Test name
Test status
Simulation time 26511426 ps
CPU time 0.97 seconds
Started Jul 23 06:46:22 PM PDT 24
Finished Jul 23 06:46:24 PM PDT 24
Peak memory 200472 kb
Host smart-4d7d08ce-aa76-4515-a73c-fd241b8ceb26
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445690643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.3445690643
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.2888566314
Short name T480
Test name
Test status
Simulation time 55231434 ps
CPU time 0.87 seconds
Started Jul 23 06:46:22 PM PDT 24
Finished Jul 23 06:46:24 PM PDT 24
Peak memory 199652 kb
Host smart-a0a339c1-07e0-4d4a-b22d-f39d9f7c964a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888566314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2888566314
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.2431992158
Short name T553
Test name
Test status
Simulation time 38816902 ps
CPU time 0.85 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:29 PM PDT 24
Peak memory 200460 kb
Host smart-151f63de-9af6-4f09-a5ec-26d94c86736d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431992158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.2431992158
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.178327577
Short name T459
Test name
Test status
Simulation time 35737109 ps
CPU time 0.82 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 200448 kb
Host smart-b9664f38-d93a-4b93-95d6-42cf406a20a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178327577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.178327577
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.1211776480
Short name T270
Test name
Test status
Simulation time 1636680038 ps
CPU time 12.98 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:40 PM PDT 24
Peak memory 200472 kb
Host smart-99851bcd-f627-4729-bac6-679f6a7a3e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211776480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.1211776480
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.4016316347
Short name T210
Test name
Test status
Simulation time 1913399796 ps
CPU time 7.63 seconds
Started Jul 23 06:46:21 PM PDT 24
Finished Jul 23 06:46:30 PM PDT 24
Peak memory 200524 kb
Host smart-d1a9228c-3355-43cb-a7cf-04f2d1a38984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016316347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.4016316347
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2001510640
Short name T624
Test name
Test status
Simulation time 47272257 ps
CPU time 1.12 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 200388 kb
Host smart-b29b4f78-a805-4f94-8fe7-8c63f17cb06d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001510640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.2001510640
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.919333890
Short name T333
Test name
Test status
Simulation time 17967495 ps
CPU time 0.71 seconds
Started Jul 23 06:46:33 PM PDT 24
Finished Jul 23 06:46:40 PM PDT 24
Peak memory 200464 kb
Host smart-97cfa3cf-7166-4c29-ab21-5ac7fb031479
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919333890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.clkmgr_lc_clk_byp_req_intersig_mubi.919333890
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.3316539183
Short name T257
Test name
Test status
Simulation time 21094177 ps
CPU time 0.83 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 200452 kb
Host smart-902cddd0-9ae3-4130-97fc-1b77b7458155
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316539183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.3316539183
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.2902483960
Short name T493
Test name
Test status
Simulation time 20432258 ps
CPU time 0.8 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 200420 kb
Host smart-e5fcf137-ad23-4475-81fb-377db8953c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902483960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2902483960
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.3617043834
Short name T382
Test name
Test status
Simulation time 1204545009 ps
CPU time 4.8 seconds
Started Jul 23 06:46:20 PM PDT 24
Finished Jul 23 06:46:26 PM PDT 24
Peak memory 200652 kb
Host smart-25be5745-f7c1-4e88-a94c-7a1f35a14948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617043834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3617043834
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.608715615
Short name T440
Test name
Test status
Simulation time 71904642 ps
CPU time 1 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:29 PM PDT 24
Peak memory 200684 kb
Host smart-ce457fb9-0ddb-4c4d-9a31-d6bfd2da1116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608715615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.608715615
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.917767327
Short name T559
Test name
Test status
Simulation time 5408839142 ps
CPU time 25.16 seconds
Started Jul 23 06:46:39 PM PDT 24
Finished Jul 23 06:47:11 PM PDT 24
Peak memory 200748 kb
Host smart-155caf8d-a61a-4663-a3e3-73f338525598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917767327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.917767327
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.2891782108
Short name T638
Test name
Test status
Simulation time 59922777 ps
CPU time 1 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 200460 kb
Host smart-e51c71b8-19cb-4956-be58-61d49578fb39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891782108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.2891782108
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.2251613946
Short name T505
Test name
Test status
Simulation time 41288945 ps
CPU time 0.9 seconds
Started Jul 23 06:46:30 PM PDT 24
Finished Jul 23 06:46:38 PM PDT 24
Peak memory 200476 kb
Host smart-dac1c3ae-8849-4013-9d2a-48474b8c65d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251613946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.2251613946
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3527597143
Short name T541
Test name
Test status
Simulation time 30920655 ps
CPU time 1.01 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:33 PM PDT 24
Peak memory 200444 kb
Host smart-1f433a41-bfe1-4d57-afee-fe7f50b6e616
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527597143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.3527597143
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.943264657
Short name T252
Test name
Test status
Simulation time 15482682 ps
CPU time 0.74 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:33 PM PDT 24
Peak memory 199616 kb
Host smart-0146fb5b-4508-4e03-8025-8426f1e27981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943264657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.943264657
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.4015387566
Short name T336
Test name
Test status
Simulation time 21539675 ps
CPU time 0.73 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:36 PM PDT 24
Peak memory 200460 kb
Host smart-76574dc9-e364-4ffb-983b-878f411b98a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015387566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.4015387566
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.2568756981
Short name T701
Test name
Test status
Simulation time 27066816 ps
CPU time 0.96 seconds
Started Jul 23 06:46:21 PM PDT 24
Finished Jul 23 06:46:24 PM PDT 24
Peak memory 200444 kb
Host smart-9bcdc29d-38cc-4527-b42c-56a480b068e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568756981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2568756981
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.3585206361
Short name T443
Test name
Test status
Simulation time 1787307707 ps
CPU time 7.82 seconds
Started Jul 23 06:46:22 PM PDT 24
Finished Jul 23 06:46:31 PM PDT 24
Peak memory 200604 kb
Host smart-a9dddafc-6adc-42bb-9367-9d97adeadcf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585206361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.3585206361
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.324331277
Short name T5
Test name
Test status
Simulation time 1112656730 ps
CPU time 5.06 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 200496 kb
Host smart-b76381c0-d1df-483b-aee4-a082a72fbd5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324331277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_ti
meout.324331277
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3126715642
Short name T392
Test name
Test status
Simulation time 177957187 ps
CPU time 1.29 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 200456 kb
Host smart-d39b414c-2559-46ac-88d2-862dce74ebff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126715642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.3126715642
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3544266569
Short name T795
Test name
Test status
Simulation time 60813970 ps
CPU time 0.95 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:37 PM PDT 24
Peak memory 200480 kb
Host smart-0d3d75f4-81d9-4643-83a2-d8940038ccab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544266569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3544266569
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1206426484
Short name T800
Test name
Test status
Simulation time 18885178 ps
CPU time 0.8 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:32 PM PDT 24
Peak memory 200392 kb
Host smart-e223d971-5dfd-4182-9307-2b34bbb22efc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206426484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.1206426484
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.3497030129
Short name T345
Test name
Test status
Simulation time 17268379 ps
CPU time 0.76 seconds
Started Jul 23 06:46:25 PM PDT 24
Finished Jul 23 06:46:28 PM PDT 24
Peak memory 200448 kb
Host smart-9c55d1e7-272e-4b2c-8026-b168b3752d7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497030129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.3497030129
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.2713127127
Short name T514
Test name
Test status
Simulation time 366097740 ps
CPU time 2.55 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:46:36 PM PDT 24
Peak memory 200336 kb
Host smart-8b7e3f12-c308-42bb-b113-5114b6d97db9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713127127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.2713127127
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.3092710050
Short name T731
Test name
Test status
Simulation time 110869082 ps
CPU time 1.04 seconds
Started Jul 23 06:46:35 PM PDT 24
Finished Jul 23 06:46:43 PM PDT 24
Peak memory 200308 kb
Host smart-13c06c5f-ed79-4194-b8b5-c29bd188cfa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092710050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3092710050
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.3695634248
Short name T302
Test name
Test status
Simulation time 8218704433 ps
CPU time 31.3 seconds
Started Jul 23 06:46:28 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 200772 kb
Host smart-7166cf16-aca8-4908-96c1-d89f23603940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695634248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.3695634248
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.3330543096
Short name T646
Test name
Test status
Simulation time 67394389 ps
CPU time 1.1 seconds
Started Jul 23 06:46:31 PM PDT 24
Finished Jul 23 06:46:39 PM PDT 24
Peak memory 200444 kb
Host smart-40520d64-786a-478c-8b22-9d96daed22ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330543096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3330543096
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.1179030820
Short name T279
Test name
Test status
Simulation time 191570044 ps
CPU time 1.22 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 200508 kb
Host smart-8c5f3513-c332-4f5e-8835-f63cb3a453ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179030820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.1179030820
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1288395955
Short name T97
Test name
Test status
Simulation time 100612067 ps
CPU time 1.1 seconds
Started Jul 23 06:46:41 PM PDT 24
Finished Jul 23 06:46:49 PM PDT 24
Peak memory 200476 kb
Host smart-383d5187-0aef-4f9d-8e53-5d4b033768da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288395955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.1288395955
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3427176479
Short name T344
Test name
Test status
Simulation time 14714796 ps
CPU time 0.74 seconds
Started Jul 23 06:46:37 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 199616 kb
Host smart-30068393-c1f3-44ca-8061-92b1677d287f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427176479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3427176479
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.4254002064
Short name T266
Test name
Test status
Simulation time 67378928 ps
CPU time 0.95 seconds
Started Jul 23 06:46:44 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 200432 kb
Host smart-c97a2f06-8b1d-42b9-a76c-1107a335357f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254002064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.4254002064
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.2121353670
Short name T365
Test name
Test status
Simulation time 86964822 ps
CPU time 1.01 seconds
Started Jul 23 06:46:29 PM PDT 24
Finished Jul 23 06:46:35 PM PDT 24
Peak memory 200460 kb
Host smart-dc0d3c92-71bb-4527-8b5f-b6af9b8b16da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121353670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.2121353670
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.118169836
Short name T179
Test name
Test status
Simulation time 2362618843 ps
CPU time 17.94 seconds
Started Jul 23 06:46:33 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 200700 kb
Host smart-bd7530ff-baac-47ef-bfee-2df56b8e27bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118169836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.118169836
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.2819634121
Short name T515
Test name
Test status
Simulation time 748962276 ps
CPU time 4.08 seconds
Started Jul 23 06:46:33 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 200416 kb
Host smart-2c677862-603f-4643-b8ef-b722a7ae95ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819634121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.2819634121
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1249929950
Short name T360
Test name
Test status
Simulation time 30498268 ps
CPU time 1.03 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:40 PM PDT 24
Peak memory 200460 kb
Host smart-5a5dfc30-7cda-4117-bcdd-f31e469d7ac5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249929950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.1249929950
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.401521299
Short name T486
Test name
Test status
Simulation time 20925262 ps
CPU time 0.86 seconds
Started Jul 23 06:46:33 PM PDT 24
Finished Jul 23 06:46:41 PM PDT 24
Peak memory 200460 kb
Host smart-716bac8e-ef1e-4ced-8edb-12bb36cec728
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401521299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.clkmgr_lc_clk_byp_req_intersig_mubi.401521299
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3971274911
Short name T73
Test name
Test status
Simulation time 28754659 ps
CPU time 0.91 seconds
Started Jul 23 06:46:36 PM PDT 24
Finished Jul 23 06:46:43 PM PDT 24
Peak memory 200488 kb
Host smart-39ad6742-21c1-4467-94d4-9019a00e5992
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971274911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.3971274911
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.1892089277
Short name T497
Test name
Test status
Simulation time 19393285 ps
CPU time 0.79 seconds
Started Jul 23 06:46:34 PM PDT 24
Finished Jul 23 06:46:42 PM PDT 24
Peak memory 200464 kb
Host smart-fa5ff9a1-89d6-4784-8f29-dc2591b0c27c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892089277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.1892089277
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.1873652714
Short name T11
Test name
Test status
Simulation time 1084714005 ps
CPU time 5.13 seconds
Started Jul 23 06:46:35 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 200624 kb
Host smart-cb6ca028-07b8-4819-9d4f-4c6968379a1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873652714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1873652714
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.4124821042
Short name T326
Test name
Test status
Simulation time 162408736 ps
CPU time 1.27 seconds
Started Jul 23 06:46:27 PM PDT 24
Finished Jul 23 06:46:34 PM PDT 24
Peak memory 200308 kb
Host smart-7ba1ca45-cd73-499b-941a-b039e2474939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124821042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.4124821042
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.3275232741
Short name T318
Test name
Test status
Simulation time 1843411946 ps
CPU time 6.69 seconds
Started Jul 23 06:46:34 PM PDT 24
Finished Jul 23 06:46:48 PM PDT 24
Peak memory 200508 kb
Host smart-edcb8ae5-4646-4255-85f2-58e2be3aea84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275232741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.3275232741
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.3641080540
Short name T70
Test name
Test status
Simulation time 34644731699 ps
CPU time 320.45 seconds
Started Jul 23 06:46:36 PM PDT 24
Finished Jul 23 06:52:03 PM PDT 24
Peak memory 209108 kb
Host smart-7b40a7c6-274c-40a1-a7ad-f65e40f81bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3641080540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3641080540
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3114382795
Short name T617
Test name
Test status
Simulation time 125722674 ps
CPU time 1.27 seconds
Started Jul 23 06:46:43 PM PDT 24
Finished Jul 23 06:46:51 PM PDT 24
Peak memory 200416 kb
Host smart-4dfc506c-e6af-46c2-8a35-b2272b437b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114382795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3114382795
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.1923327931
Short name T271
Test name
Test status
Simulation time 11779836 ps
CPU time 0.7 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 200496 kb
Host smart-a239e592-1f76-4dbe-8e16-91982c25d515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923327931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.1923327931
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.1228654172
Short name T634
Test name
Test status
Simulation time 27065494 ps
CPU time 0.88 seconds
Started Jul 23 06:46:39 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 200484 kb
Host smart-9ce1b9e8-95d5-4109-9cd8-7204d65bbdaf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228654172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.1228654172
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.2026639456
Short name T431
Test name
Test status
Simulation time 122832563 ps
CPU time 0.96 seconds
Started Jul 23 06:46:42 PM PDT 24
Finished Jul 23 06:46:50 PM PDT 24
Peak memory 199636 kb
Host smart-b412351f-5913-4e05-a27e-6b1991065595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026639456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2026639456
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.2408774388
Short name T242
Test name
Test status
Simulation time 21561491 ps
CPU time 0.84 seconds
Started Jul 23 06:46:40 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 200460 kb
Host smart-d0f3f4b8-9ebd-43e0-bcb0-7b9e24d32f8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408774388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.2408774388
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1262625578
Short name T221
Test name
Test status
Simulation time 20779274 ps
CPU time 0.86 seconds
Started Jul 23 06:46:32 PM PDT 24
Finished Jul 23 06:46:40 PM PDT 24
Peak memory 200440 kb
Host smart-cd6b4a00-1f26-455b-99b4-d2e6a891d498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262625578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1262625578
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.589686568
Short name T303
Test name
Test status
Simulation time 1829582426 ps
CPU time 9.01 seconds
Started Jul 23 06:46:43 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 200528 kb
Host smart-1a7326ba-36a3-4c6d-9f97-1e1f26079df0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589686568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_ti
meout.589686568
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.25903565
Short name T52
Test name
Test status
Simulation time 26247964 ps
CPU time 0.91 seconds
Started Jul 23 06:46:34 PM PDT 24
Finished Jul 23 06:46:42 PM PDT 24
Peak memory 200472 kb
Host smart-6735fe1a-e861-4e51-82d4-42e4362ed042
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25903565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.clkmgr_idle_intersig_mubi.25903565
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2772217397
Short name T683
Test name
Test status
Simulation time 70277125 ps
CPU time 0.99 seconds
Started Jul 23 06:46:36 PM PDT 24
Finished Jul 23 06:46:43 PM PDT 24
Peak memory 200492 kb
Host smart-73364fc0-e0d9-4b08-a404-0c46ece4462a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772217397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2772217397
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2287990816
Short name T286
Test name
Test status
Simulation time 59649290 ps
CPU time 0.89 seconds
Started Jul 23 06:46:42 PM PDT 24
Finished Jul 23 06:46:50 PM PDT 24
Peak memory 200308 kb
Host smart-b941c842-c3d2-49e4-b258-27069920ded2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287990816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.2287990816
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.3622008898
Short name T566
Test name
Test status
Simulation time 18871421 ps
CPU time 0.82 seconds
Started Jul 23 06:46:38 PM PDT 24
Finished Jul 23 06:46:45 PM PDT 24
Peak memory 200408 kb
Host smart-d7141021-5075-4489-9fd0-1b1058128908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622008898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3622008898
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.478473426
Short name T4
Test name
Test status
Simulation time 1513767665 ps
CPU time 5.56 seconds
Started Jul 23 06:46:42 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 200636 kb
Host smart-2f9928cc-3f31-4357-baff-a907fcfb65cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478473426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.478473426
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.2594631914
Short name T129
Test name
Test status
Simulation time 19234415 ps
CPU time 0.82 seconds
Started Jul 23 06:46:36 PM PDT 24
Finished Jul 23 06:46:48 PM PDT 24
Peak memory 200392 kb
Host smart-07dc2c79-9bcd-4e76-a835-5046b9ca6fc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594631914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.2594631914
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.1607429774
Short name T659
Test name
Test status
Simulation time 3554442206 ps
CPU time 12.73 seconds
Started Jul 23 06:46:44 PM PDT 24
Finished Jul 23 06:47:04 PM PDT 24
Peak memory 200756 kb
Host smart-b737abd1-6a4a-4a36-a273-4e6aa5481760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607429774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.1607429774
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.1884659482
Short name T739
Test name
Test status
Simulation time 11060385424 ps
CPU time 200.4 seconds
Started Jul 23 06:46:40 PM PDT 24
Finished Jul 23 06:50:06 PM PDT 24
Peak memory 209056 kb
Host smart-83e01ecc-8322-4de1-857e-27f7c4643831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1884659482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.1884659482
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.160037301
Short name T278
Test name
Test status
Simulation time 134436965 ps
CPU time 1.33 seconds
Started Jul 23 06:46:39 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 200480 kb
Host smart-0792ef48-c34b-4de7-876b-489dacd09432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160037301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.160037301
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.2144651373
Short name T627
Test name
Test status
Simulation time 54221514 ps
CPU time 0.92 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 200536 kb
Host smart-16f4a5d3-a2d4-4bb8-8155-ec7cb9efa1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144651373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.2144651373
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.958445357
Short name T561
Test name
Test status
Simulation time 39037450 ps
CPU time 0.93 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 200452 kb
Host smart-0640088d-b2f6-4570-9d71-ea23dcfcd215
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958445357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.958445357
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2712647533
Short name T213
Test name
Test status
Simulation time 47675626 ps
CPU time 0.81 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:24 PM PDT 24
Peak memory 199572 kb
Host smart-e03ae9fa-6ae1-465c-9d9a-28958e2767ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712647533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2712647533
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.3667326336
Short name T406
Test name
Test status
Simulation time 14814184 ps
CPU time 0.73 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:22 PM PDT 24
Peak memory 200460 kb
Host smart-e482a854-a4b8-4901-a9d4-e1c5b54bb4cf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667326336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.3667326336
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.3011183787
Short name T166
Test name
Test status
Simulation time 19482679 ps
CPU time 0.83 seconds
Started Jul 23 06:44:06 PM PDT 24
Finished Jul 23 06:44:09 PM PDT 24
Peak memory 200428 kb
Host smart-c650cef6-648b-46ec-8ed9-ddcf8a744a0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011183787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.3011183787
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.4060900853
Short name T291
Test name
Test status
Simulation time 1275683726 ps
CPU time 9.72 seconds
Started Jul 23 06:44:07 PM PDT 24
Finished Jul 23 06:44:19 PM PDT 24
Peak memory 200452 kb
Host smart-831c1cf8-dd3e-402a-8fb1-2bb13337541f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060900853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.4060900853
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.341198956
Short name T38
Test name
Test status
Simulation time 2061589864 ps
CPU time 15 seconds
Started Jul 23 06:44:10 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 200720 kb
Host smart-dfd7ef45-1141-4361-b987-0a53e03482fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341198956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_tim
eout.341198956
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.2999171373
Short name T462
Test name
Test status
Simulation time 30307407 ps
CPU time 0.97 seconds
Started Jul 23 06:44:22 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 200356 kb
Host smart-5073646b-964f-4a3d-80a2-9f5d37d84d9e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999171373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.2999171373
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.2255724253
Short name T606
Test name
Test status
Simulation time 71486754 ps
CPU time 0.94 seconds
Started Jul 23 06:44:20 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 200672 kb
Host smart-414fda9a-a1df-4aac-bf3f-cdb85088e97e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255724253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.2255724253
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.2169534331
Short name T727
Test name
Test status
Simulation time 16603173 ps
CPU time 0.83 seconds
Started Jul 23 06:44:15 PM PDT 24
Finished Jul 23 06:44:17 PM PDT 24
Peak memory 200456 kb
Host smart-ce69dbd9-d5b1-4667-b663-aea73570498a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169534331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.2169534331
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.3979551927
Short name T821
Test name
Test status
Simulation time 15587547 ps
CPU time 0.76 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:12 PM PDT 24
Peak memory 200668 kb
Host smart-8069e8a2-42a7-4382-8e98-75e1e70d396b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979551927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3979551927
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.3259565977
Short name T404
Test name
Test status
Simulation time 672071276 ps
CPU time 2.88 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 200668 kb
Host smart-33444136-7e6d-48a6-b40e-c9dff45f3a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259565977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3259565977
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.3449656178
Short name T57
Test name
Test status
Simulation time 582187894 ps
CPU time 3.71 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 217168 kb
Host smart-8f5bb259-3cd8-430d-ab39-3daada8481c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449656178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.3449656178
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.1657428256
Short name T714
Test name
Test status
Simulation time 24030350 ps
CPU time 0.89 seconds
Started Jul 23 06:44:08 PM PDT 24
Finished Jul 23 06:44:12 PM PDT 24
Peak memory 200352 kb
Host smart-c937d43a-d1c3-48ec-b9bf-af455f321606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657428256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1657428256
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.3035349559
Short name T31
Test name
Test status
Simulation time 8927589831 ps
CPU time 67.21 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:45:31 PM PDT 24
Peak memory 200756 kb
Host smart-e58ba1f6-8e3b-4d5d-83c5-332ed6df11ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035349559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.3035349559
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.1463993949
Short name T180
Test name
Test status
Simulation time 16859238 ps
CPU time 0.79 seconds
Started Jul 23 06:44:07 PM PDT 24
Finished Jul 23 06:44:10 PM PDT 24
Peak memory 200392 kb
Host smart-582682dd-7f24-44f9-a6ab-2e4e3fbea800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463993949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1463993949
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.3190996063
Short name T518
Test name
Test status
Simulation time 40863667 ps
CPU time 0.93 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 200532 kb
Host smart-4a91a70b-8f8c-43d1-8a77-68ca5e57c769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190996063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.3190996063
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.178990101
Short name T803
Test name
Test status
Simulation time 25857410 ps
CPU time 0.9 seconds
Started Jul 23 06:46:47 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 200404 kb
Host smart-2f450479-b80b-4a64-a949-60bea1691e33
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178990101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.178990101
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.777002004
Short name T159
Test name
Test status
Simulation time 41407997 ps
CPU time 0.79 seconds
Started Jul 23 06:46:40 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 199652 kb
Host smart-4f5f26c0-5189-461c-b165-709c77d70731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777002004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.777002004
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.2609887080
Short name T513
Test name
Test status
Simulation time 27452729 ps
CPU time 0.79 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 200472 kb
Host smart-96b7554d-6f52-4de1-8e49-183de24124e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609887080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.2609887080
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.607769151
Short name T322
Test name
Test status
Simulation time 62583635 ps
CPU time 0.94 seconds
Started Jul 23 06:46:44 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 200452 kb
Host smart-843f293d-8d33-40d6-a55a-28fa02bcda94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607769151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.607769151
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.656613805
Short name T334
Test name
Test status
Simulation time 567808490 ps
CPU time 4.32 seconds
Started Jul 23 06:46:37 PM PDT 24
Finished Jul 23 06:46:47 PM PDT 24
Peak memory 200380 kb
Host smart-25834b1a-ab54-4388-b069-ba15dbe689b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656613805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.656613805
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.3487322545
Short name T807
Test name
Test status
Simulation time 1407664718 ps
CPU time 5.68 seconds
Started Jul 23 06:46:39 PM PDT 24
Finished Jul 23 06:46:51 PM PDT 24
Peak memory 200528 kb
Host smart-4eae4d2f-ec79-4e2f-a03b-7a803230a59b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487322545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.3487322545
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.556589048
Short name T396
Test name
Test status
Simulation time 56902179 ps
CPU time 0.84 seconds
Started Jul 23 06:46:39 PM PDT 24
Finished Jul 23 06:46:46 PM PDT 24
Peak memory 200468 kb
Host smart-db2afb31-9140-4fac-8470-543fec4bb9a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556589048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_idle_intersig_mubi.556589048
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.37608025
Short name T208
Test name
Test status
Simulation time 13057243 ps
CPU time 0.73 seconds
Started Jul 23 06:46:47 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 200452 kb
Host smart-e90ce84f-e9c6-4fe4-8f88-07ef5a6ab807
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37608025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_lc_clk_byp_req_intersig_mubi.37608025
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.4212900574
Short name T351
Test name
Test status
Simulation time 13502753 ps
CPU time 0.75 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:52 PM PDT 24
Peak memory 200476 kb
Host smart-504e4da3-35a3-4cfb-a5a6-101ddbde9107
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212900574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.4212900574
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.85965396
Short name T819
Test name
Test status
Simulation time 39332090 ps
CPU time 0.81 seconds
Started Jul 23 06:46:37 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 200480 kb
Host smart-d81c3163-f784-49b8-ac42-a7e8168e5b67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85965396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.85965396
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.3104824748
Short name T563
Test name
Test status
Simulation time 312083129 ps
CPU time 2.25 seconds
Started Jul 23 06:46:49 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 200404 kb
Host smart-8b3f98fe-3bec-487c-88d2-ed30e7613127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104824748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3104824748
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.3112462301
Short name T320
Test name
Test status
Simulation time 46512537 ps
CPU time 0.9 seconds
Started Jul 23 06:46:42 PM PDT 24
Finished Jul 23 06:46:49 PM PDT 24
Peak memory 200328 kb
Host smart-9ff9273c-3b81-42ae-8605-4d7b3c1cc226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112462301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3112462301
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.3017016984
Short name T29
Test name
Test status
Simulation time 1518054110 ps
CPU time 7.22 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 200688 kb
Host smart-50b52423-b786-4c2e-8afb-f403bfa7ab33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017016984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.3017016984
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.1254372344
Short name T799
Test name
Test status
Simulation time 17733672741 ps
CPU time 329.88 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:52:24 PM PDT 24
Peak memory 217188 kb
Host smart-21375def-8293-4f53-8d47-db41db0a0d0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1254372344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.1254372344
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.1396675341
Short name T598
Test name
Test status
Simulation time 101927325 ps
CPU time 1.11 seconds
Started Jul 23 06:46:37 PM PDT 24
Finished Jul 23 06:46:44 PM PDT 24
Peak memory 200436 kb
Host smart-51d1fff4-fa8a-4c3c-af06-14e63d8c0440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396675341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1396675341
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.3932581758
Short name T744
Test name
Test status
Simulation time 119111339 ps
CPU time 1.11 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 200548 kb
Host smart-8800744e-8e06-40a4-bf26-2ba60639cedb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932581758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.3932581758
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1597220360
Short name T245
Test name
Test status
Simulation time 84850854 ps
CPU time 1.11 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 200444 kb
Host smart-d4169710-6917-4095-8de2-2ba96dd265e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597220360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.1597220360
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.3191652207
Short name T20
Test name
Test status
Simulation time 18204658 ps
CPU time 0.69 seconds
Started Jul 23 06:46:47 PM PDT 24
Finished Jul 23 06:46:53 PM PDT 24
Peak memory 199624 kb
Host smart-9c43e108-38c9-408a-8345-8f2d0492328a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191652207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3191652207
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.3148320279
Short name T359
Test name
Test status
Simulation time 186130912 ps
CPU time 1.34 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:46:56 PM PDT 24
Peak memory 200472 kb
Host smart-80880708-62ca-4b70-b4e3-f205f00c6cd5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148320279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.3148320279
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.235686976
Short name T785
Test name
Test status
Simulation time 26450692 ps
CPU time 0.87 seconds
Started Jul 23 06:46:51 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 200444 kb
Host smart-e3a18d12-e883-441d-8f75-49e4c3697c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235686976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.235686976
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1050224968
Short name T711
Test name
Test status
Simulation time 2127622638 ps
CPU time 11.45 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:47:03 PM PDT 24
Peak memory 200660 kb
Host smart-bfe38bea-d4cb-4daf-bcb7-3507be31d223
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050224968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1050224968
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.3160466123
Short name T607
Test name
Test status
Simulation time 1600877222 ps
CPU time 5.85 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:47:00 PM PDT 24
Peak memory 200548 kb
Host smart-2c2cd54f-20d6-4f66-b827-9879072a6b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160466123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.3160466123
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1753811947
Short name T199
Test name
Test status
Simulation time 31595534 ps
CPU time 0.96 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:53 PM PDT 24
Peak memory 200464 kb
Host smart-b8096b0f-7ea1-4cfe-a457-29c995876bcc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753811947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1753811947
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2508409904
Short name T753
Test name
Test status
Simulation time 125309149 ps
CPU time 1.29 seconds
Started Jul 23 06:46:46 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 200476 kb
Host smart-7d55d4fc-18da-42de-8229-669c5af1814d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508409904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.2508409904
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.3846031972
Short name T249
Test name
Test status
Simulation time 158838658 ps
CPU time 1.23 seconds
Started Jul 23 06:46:47 PM PDT 24
Finished Jul 23 06:46:54 PM PDT 24
Peak memory 200488 kb
Host smart-c9617b54-1c5c-433b-9fe5-9237b7f9d217
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846031972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.3846031972
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.2895438813
Short name T494
Test name
Test status
Simulation time 38055144 ps
CPU time 0.79 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:46:55 PM PDT 24
Peak memory 200484 kb
Host smart-8aa2c70a-0fff-4c8f-be18-751d2a1a0eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895438813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.2895438813
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.3111029323
Short name T357
Test name
Test status
Simulation time 523690871 ps
CPU time 2.53 seconds
Started Jul 23 06:46:58 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 200444 kb
Host smart-42ab27d6-f44c-4102-a5c8-77d3c8feafbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111029323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3111029323
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.1736692984
Short name T156
Test name
Test status
Simulation time 55966683 ps
CPU time 1.02 seconds
Started Jul 23 06:46:45 PM PDT 24
Finished Jul 23 06:46:53 PM PDT 24
Peak memory 200392 kb
Host smart-610a9f28-45bb-49a6-b6d1-b1730f78e0cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736692984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.1736692984
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.2973104103
Short name T768
Test name
Test status
Simulation time 9193869393 ps
CPU time 40.66 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:47:35 PM PDT 24
Peak memory 200804 kb
Host smart-3cde5df6-01b6-4f94-997d-748bf4c6b840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973104103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.2973104103
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.3756868242
Short name T66
Test name
Test status
Simulation time 178847690743 ps
CPU time 1108.91 seconds
Started Jul 23 06:46:44 PM PDT 24
Finished Jul 23 07:05:20 PM PDT 24
Peak memory 209076 kb
Host smart-cbc02f23-3244-47d5-8ed8-0f7e4ddd1ec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3756868242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3756868242
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.3721195343
Short name T611
Test name
Test status
Simulation time 18656272 ps
CPU time 0.77 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 200484 kb
Host smart-a6b8b1c5-0862-4d7d-93dd-039ede3d3567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721195343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3721195343
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.2168663096
Short name T276
Test name
Test status
Simulation time 15388279 ps
CPU time 0.76 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 200524 kb
Host smart-5663b18f-c131-4bcf-9540-2b7ae94c15b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168663096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.2168663096
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.2282525728
Short name T435
Test name
Test status
Simulation time 82605492 ps
CPU time 1.11 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 200476 kb
Host smart-55811783-fb85-4fc9-8387-fdb45b620ea8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282525728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.2282525728
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.1915729794
Short name T216
Test name
Test status
Simulation time 15501501 ps
CPU time 0.73 seconds
Started Jul 23 06:47:13 PM PDT 24
Finished Jul 23 06:47:16 PM PDT 24
Peak memory 199636 kb
Host smart-933c2f6a-f22e-40f5-aadf-e45125c33fe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915729794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1915729794
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2460965527
Short name T678
Test name
Test status
Simulation time 14234454 ps
CPU time 0.72 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 200468 kb
Host smart-3fb79fdf-2678-45c3-a008-3b6e7cdea6df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460965527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2460965527
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.652846866
Short name T712
Test name
Test status
Simulation time 22751361 ps
CPU time 0.83 seconds
Started Jul 23 06:47:10 PM PDT 24
Finished Jul 23 06:47:13 PM PDT 24
Peak memory 200484 kb
Host smart-0bda37a4-c99f-4a5c-a24c-a4cd005e2d07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652846866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.652846866
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.2307080435
Short name T441
Test name
Test status
Simulation time 1641685493 ps
CPU time 12.22 seconds
Started Jul 23 06:46:47 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 200472 kb
Host smart-9ccce54a-3438-43ef-a4f8-1df9cba62893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307080435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.2307080435
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.730971676
Short name T684
Test name
Test status
Simulation time 2055529478 ps
CPU time 16.04 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 200688 kb
Host smart-749bbed5-cfbc-4618-b1b3-3321953b07f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730971676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti
meout.730971676
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.1430243295
Short name T600
Test name
Test status
Simulation time 27594150 ps
CPU time 0.91 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 200460 kb
Host smart-2a18abc7-7a3a-4d53-a460-991753774da5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430243295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.1430243295
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.2705440242
Short name T451
Test name
Test status
Simulation time 21976424 ps
CPU time 0.83 seconds
Started Jul 23 06:46:55 PM PDT 24
Finished Jul 23 06:47:00 PM PDT 24
Peak memory 200452 kb
Host smart-cc7a4deb-3a93-481c-b16d-9a91f560bfdf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705440242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.2705440242
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.819260329
Short name T774
Test name
Test status
Simulation time 42542952 ps
CPU time 0.81 seconds
Started Jul 23 06:46:56 PM PDT 24
Finished Jul 23 06:47:01 PM PDT 24
Peak memory 200484 kb
Host smart-0586aef8-3523-4c15-8ee3-d9bbbc6766f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819260329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_ctrl_intersig_mubi.819260329
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.1249171358
Short name T782
Test name
Test status
Simulation time 41473258 ps
CPU time 0.86 seconds
Started Jul 23 06:46:48 PM PDT 24
Finished Jul 23 06:46:55 PM PDT 24
Peak memory 200456 kb
Host smart-3cde9905-e130-4f1f-9fb5-6b1b98c91250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249171358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1249171358
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.1088780510
Short name T421
Test name
Test status
Simulation time 1044250005 ps
CPU time 4.02 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 200652 kb
Host smart-4a2cabf2-3a4d-45ce-b4e8-bb943405686a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088780510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1088780510
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.941126902
Short name T269
Test name
Test status
Simulation time 89689186 ps
CPU time 1.02 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 200408 kb
Host smart-9e48d9dd-c0be-4b7d-8530-227b4169a307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941126902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.941126902
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.1529502379
Short name T155
Test name
Test status
Simulation time 1567777853 ps
CPU time 12.39 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:47:10 PM PDT 24
Peak memory 200688 kb
Host smart-ac2dfb5d-6f25-4adf-a56e-d820dca487d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529502379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.1529502379
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.3008203264
Short name T67
Test name
Test status
Simulation time 18342238620 ps
CPU time 284.38 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:51:42 PM PDT 24
Peak memory 217272 kb
Host smart-a25b5d56-f6a7-496e-98bc-885239072ff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3008203264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3008203264
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.311139611
Short name T492
Test name
Test status
Simulation time 29526176 ps
CPU time 0.76 seconds
Started Jul 23 06:46:54 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 200484 kb
Host smart-5ed69559-9eb4-40fd-9a57-477fade7b90f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311139611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.311139611
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.2663368916
Short name T792
Test name
Test status
Simulation time 42237727 ps
CPU time 0.86 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 200516 kb
Host smart-658678cf-ad6e-4f33-9f40-cba988b56ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663368916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.2663368916
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.1179898926
Short name T103
Test name
Test status
Simulation time 87282261 ps
CPU time 1.12 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 200476 kb
Host smart-1fe86bf2-5e91-40a3-9cfa-7dc0229b799a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179898926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.1179898926
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.3299405084
Short name T631
Test name
Test status
Simulation time 16208181 ps
CPU time 0.76 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 200384 kb
Host smart-fc512f34-a34c-43d3-a118-3b8e48048b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299405084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.3299405084
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.4160077253
Short name T248
Test name
Test status
Simulation time 24540498 ps
CPU time 0.78 seconds
Started Jul 23 06:46:50 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 200460 kb
Host smart-d8ff8ec0-67de-4cdd-b776-e97aeb2bd45b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160077253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.4160077253
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.1881223158
Short name T361
Test name
Test status
Simulation time 48016774 ps
CPU time 0.94 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:04 PM PDT 24
Peak memory 200356 kb
Host smart-b841af27-6c87-4988-a765-b1ecc72f67de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881223158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1881223158
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.4155622769
Short name T770
Test name
Test status
Simulation time 1282174834 ps
CPU time 9.86 seconds
Started Jul 23 06:46:51 PM PDT 24
Finished Jul 23 06:47:06 PM PDT 24
Peak memory 200480 kb
Host smart-a2d5ab55-7700-41da-839d-90a0880d4a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155622769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.4155622769
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.2068214268
Short name T610
Test name
Test status
Simulation time 1290482347 ps
CPU time 5.7 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:07 PM PDT 24
Peak memory 200520 kb
Host smart-b0c30ed6-0c42-48b6-805e-27b129229b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068214268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.2068214268
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.763991987
Short name T601
Test name
Test status
Simulation time 28169901 ps
CPU time 0.92 seconds
Started Jul 23 06:47:07 PM PDT 24
Finished Jul 23 06:47:11 PM PDT 24
Peak memory 200424 kb
Host smart-46374266-347d-47fe-8e56-b5aa82b3c24b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763991987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_idle_intersig_mubi.763991987
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.551948338
Short name T312
Test name
Test status
Simulation time 16716290 ps
CPU time 0.8 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 200492 kb
Host smart-130e00fd-8995-4a9d-9a99-de2984182302
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551948338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.clkmgr_lc_clk_byp_req_intersig_mubi.551948338
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.47994270
Short name T656
Test name
Test status
Simulation time 33572683 ps
CPU time 0.85 seconds
Started Jul 23 06:46:53 PM PDT 24
Finished Jul 23 06:46:59 PM PDT 24
Peak memory 200452 kb
Host smart-e4611ecc-293d-4325-903e-ffc8cf694e55
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47994270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_lc_ctrl_intersig_mubi.47994270
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.3684410086
Short name T54
Test name
Test status
Simulation time 17162783 ps
CPU time 0.73 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 200416 kb
Host smart-d3f7dba5-6da5-4e66-a206-e92197d23c43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684410086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.3684410086
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.1021771459
Short name T170
Test name
Test status
Simulation time 1388816496 ps
CPU time 4.98 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:47:03 PM PDT 24
Peak memory 200652 kb
Host smart-1ba880dd-3734-4d81-8d43-4ecffc3cff2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021771459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1021771459
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.2716159997
Short name T485
Test name
Test status
Simulation time 46776107 ps
CPU time 0.92 seconds
Started Jul 23 06:47:02 PM PDT 24
Finished Jul 23 06:47:07 PM PDT 24
Peak memory 200408 kb
Host smart-4a045c2a-76b7-492e-8cd2-85e26c2a8583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716159997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.2716159997
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.130304066
Short name T388
Test name
Test status
Simulation time 16391679224 ps
CPU time 53.06 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 200664 kb
Host smart-a531cdc5-cf4b-4bee-ba93-6ac70cfd39a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130304066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.130304066
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.235264311
Short name T681
Test name
Test status
Simulation time 133437997 ps
CPU time 1.08 seconds
Started Jul 23 06:46:50 PM PDT 24
Finished Jul 23 06:46:57 PM PDT 24
Peak memory 200496 kb
Host smart-cc430836-4525-4302-a3a2-aba686c9e63a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235264311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.235264311
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.4008058464
Short name T240
Test name
Test status
Simulation time 25859209 ps
CPU time 0.84 seconds
Started Jul 23 06:47:04 PM PDT 24
Finished Jul 23 06:47:08 PM PDT 24
Peak memory 200488 kb
Host smart-bc290f0b-4d31-412d-b6d4-40f523e46197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008058464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.4008058464
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3584816831
Short name T99
Test name
Test status
Simulation time 31872846 ps
CPU time 0.88 seconds
Started Jul 23 06:47:11 PM PDT 24
Finished Jul 23 06:47:13 PM PDT 24
Peak memory 200408 kb
Host smart-9cc72d21-0656-4125-8085-96b80173ccce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584816831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.3584816831
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.3218663943
Short name T186
Test name
Test status
Simulation time 29528623 ps
CPU time 0.78 seconds
Started Jul 23 06:47:01 PM PDT 24
Finished Jul 23 06:47:06 PM PDT 24
Peak memory 200348 kb
Host smart-543f6f71-66e7-4fd3-a2b8-42f4ba2f25bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218663943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.3218663943
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.3013589469
Short name T556
Test name
Test status
Simulation time 53559615 ps
CPU time 0.94 seconds
Started Jul 23 06:47:06 PM PDT 24
Finished Jul 23 06:47:10 PM PDT 24
Peak memory 200428 kb
Host smart-fed340e8-f62a-49bc-9c48-dd38d49e3771
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013589469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.3013589469
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.2983479996
Short name T674
Test name
Test status
Simulation time 15771918 ps
CPU time 0.77 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:46:58 PM PDT 24
Peak memory 200456 kb
Host smart-2f81d46c-468e-4612-bcbb-0c6ba6f53f74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983479996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.2983479996
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.3600643889
Short name T675
Test name
Test status
Simulation time 699034104 ps
CPU time 3.61 seconds
Started Jul 23 06:46:52 PM PDT 24
Finished Jul 23 06:47:01 PM PDT 24
Peak memory 200444 kb
Host smart-250e48b2-5554-4831-baac-d870b9f62937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600643889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3600643889
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.1416959993
Short name T282
Test name
Test status
Simulation time 2304649228 ps
CPU time 11.87 seconds
Started Jul 23 06:46:57 PM PDT 24
Finished Jul 23 06:47:13 PM PDT 24
Peak memory 200728 kb
Host smart-b3dc47fc-af50-4d5d-a978-2b7f00314a0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416959993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.1416959993
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.4004831374
Short name T694
Test name
Test status
Simulation time 68788307 ps
CPU time 1 seconds
Started Jul 23 06:47:06 PM PDT 24
Finished Jul 23 06:47:10 PM PDT 24
Peak memory 200456 kb
Host smart-ac09ff0a-0747-4515-a2d1-268d2854e8c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004831374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.4004831374
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.647560713
Short name T784
Test name
Test status
Simulation time 75125889 ps
CPU time 1.07 seconds
Started Jul 23 06:46:58 PM PDT 24
Finished Jul 23 06:47:03 PM PDT 24
Peak memory 200436 kb
Host smart-3e3d711b-a63e-4953-bfb4-c14458d2aa31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647560713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_clk_byp_req_intersig_mubi.647560713
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1738081592
Short name T776
Test name
Test status
Simulation time 68402426 ps
CPU time 0.96 seconds
Started Jul 23 06:47:10 PM PDT 24
Finished Jul 23 06:47:13 PM PDT 24
Peak memory 200692 kb
Host smart-db8f1eab-b19c-4244-9046-a780e5cd94c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738081592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.1738081592
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.18297961
Short name T464
Test name
Test status
Simulation time 42249181 ps
CPU time 0.82 seconds
Started Jul 23 06:47:01 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 200440 kb
Host smart-a7ae41c5-1895-4aaf-9775-12bc64f14fe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18297961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.18297961
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.638059887
Short name T403
Test name
Test status
Simulation time 1059018268 ps
CPU time 5.75 seconds
Started Jul 23 06:47:02 PM PDT 24
Finished Jul 23 06:47:11 PM PDT 24
Peak memory 200620 kb
Host smart-8d80db08-486b-4022-9298-137668e29cf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638059887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.638059887
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.2080629131
Short name T718
Test name
Test status
Simulation time 375889272 ps
CPU time 1.89 seconds
Started Jul 23 06:46:56 PM PDT 24
Finished Jul 23 06:47:02 PM PDT 24
Peak memory 200440 kb
Host smart-44baee89-0df9-40af-9778-a1db90ed0def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080629131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2080629131
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.2044236812
Short name T820
Test name
Test status
Simulation time 6407546623 ps
CPU time 25.58 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:29 PM PDT 24
Peak memory 200736 kb
Host smart-eb7c1ad5-368f-4157-90fe-6ea230d4989d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044236812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.2044236812
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.421218013
Short name T790
Test name
Test status
Simulation time 23973681 ps
CPU time 0.87 seconds
Started Jul 23 06:47:01 PM PDT 24
Finished Jul 23 06:47:06 PM PDT 24
Peak memory 200456 kb
Host smart-8117c616-b854-4cd2-bd89-080a046cbfa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421218013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.421218013
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.2836447141
Short name T353
Test name
Test status
Simulation time 31818302 ps
CPU time 0.75 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:25 PM PDT 24
Peak memory 200516 kb
Host smart-a4b0b16d-dd72-49b1-9e9b-476373684fca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836447141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.2836447141
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3756216776
Short name T325
Test name
Test status
Simulation time 15925503 ps
CPU time 0.76 seconds
Started Jul 23 06:47:18 PM PDT 24
Finished Jul 23 06:47:22 PM PDT 24
Peak memory 200488 kb
Host smart-db7eb86d-e59c-4e03-9dfb-c41bf5eb2cdb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756216776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.3756216776
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.3255310429
Short name T92
Test name
Test status
Simulation time 15852973 ps
CPU time 0.7 seconds
Started Jul 23 06:47:01 PM PDT 24
Finished Jul 23 06:47:05 PM PDT 24
Peak memory 199660 kb
Host smart-69d1c209-ce46-4136-93f2-f301036e09bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255310429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3255310429
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.974040067
Short name T386
Test name
Test status
Simulation time 85828002 ps
CPU time 1.08 seconds
Started Jul 23 06:47:13 PM PDT 24
Finished Jul 23 06:47:16 PM PDT 24
Peak memory 200384 kb
Host smart-66a119df-acd1-4a96-83ee-9b20725f32fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974040067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_div_intersig_mubi.974040067
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.1901809576
Short name T368
Test name
Test status
Simulation time 73035792 ps
CPU time 0.93 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:04 PM PDT 24
Peak memory 200448 kb
Host smart-ef837b52-cc90-45b9-b4d0-840651e9ce4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901809576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.1901809576
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.1785731638
Short name T666
Test name
Test status
Simulation time 1396581379 ps
CPU time 11.08 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:15 PM PDT 24
Peak memory 200692 kb
Host smart-ba9ea52b-db4d-46f2-be64-2662ed5e384d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785731638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1785731638
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.3209059949
Short name T182
Test name
Test status
Simulation time 2053703519 ps
CPU time 15.04 seconds
Started Jul 23 06:47:14 PM PDT 24
Finished Jul 23 06:47:31 PM PDT 24
Peak memory 200664 kb
Host smart-6ba23cd1-a8af-4f7b-a7e1-925f0416f966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209059949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.3209059949
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3972137458
Short name T223
Test name
Test status
Simulation time 121758058 ps
CPU time 1.33 seconds
Started Jul 23 06:47:18 PM PDT 24
Finished Jul 23 06:47:23 PM PDT 24
Peak memory 200644 kb
Host smart-e3c37312-54a2-44cf-b9a7-7d8e0af342ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972137458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3972137458
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.153913495
Short name T380
Test name
Test status
Simulation time 26000447 ps
CPU time 0.75 seconds
Started Jul 23 06:47:04 PM PDT 24
Finished Jul 23 06:47:08 PM PDT 24
Peak memory 200440 kb
Host smart-d8b0944a-1f03-41ed-a8c9-eb4de21e1350
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153913495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.clkmgr_lc_clk_byp_req_intersig_mubi.153913495
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3539482020
Short name T275
Test name
Test status
Simulation time 79478815 ps
CPU time 1.05 seconds
Started Jul 23 06:47:05 PM PDT 24
Finished Jul 23 06:47:10 PM PDT 24
Peak memory 200492 kb
Host smart-dfdc9a07-404b-4186-808f-bbc268378051
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539482020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.3539482020
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.4139381910
Short name T263
Test name
Test status
Simulation time 18723880 ps
CPU time 0.79 seconds
Started Jul 23 06:46:58 PM PDT 24
Finished Jul 23 06:47:03 PM PDT 24
Peak memory 200328 kb
Host smart-fdc8ff43-bde8-4a1c-8e64-f61c0b8e6f16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139381910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.4139381910
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.3006044887
Short name T10
Test name
Test status
Simulation time 377628003 ps
CPU time 2.49 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:30 PM PDT 24
Peak memory 200460 kb
Host smart-e50280c9-1bb0-465e-a3d0-229722169d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006044887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3006044887
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.2806871531
Short name T164
Test name
Test status
Simulation time 62482677 ps
CPU time 0.99 seconds
Started Jul 23 06:47:00 PM PDT 24
Finished Jul 23 06:47:04 PM PDT 24
Peak memory 200444 kb
Host smart-bfc0da5f-c640-48ea-bd3c-c723c036ffc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806871531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2806871531
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.1541917559
Short name T812
Test name
Test status
Simulation time 7339242643 ps
CPU time 48.66 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:48:15 PM PDT 24
Peak memory 200744 kb
Host smart-c670592b-5ef3-4c42-a354-2d0ffd5f4f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541917559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.1541917559
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.3101369096
Short name T69
Test name
Test status
Simulation time 138443486926 ps
CPU time 611.8 seconds
Started Jul 23 06:47:06 PM PDT 24
Finished Jul 23 06:57:20 PM PDT 24
Peak memory 217272 kb
Host smart-a97527c1-76aa-4ec9-9c83-28af5b5484ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3101369096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.3101369096
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1249835522
Short name T664
Test name
Test status
Simulation time 19225345 ps
CPU time 0.79 seconds
Started Jul 23 06:47:07 PM PDT 24
Finished Jul 23 06:47:11 PM PDT 24
Peak memory 200472 kb
Host smart-5b5afc28-c26a-4776-9b23-93a1c3e68d8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249835522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1249835522
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.460535798
Short name T685
Test name
Test status
Simulation time 31582924 ps
CPU time 0.88 seconds
Started Jul 23 06:47:17 PM PDT 24
Finished Jul 23 06:47:21 PM PDT 24
Peak memory 200516 kb
Host smart-7ee1ca0b-803a-4cb9-95be-1350c7553ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460535798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkm
gr_alert_test.460535798
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3769759560
Short name T549
Test name
Test status
Simulation time 34880841 ps
CPU time 0.91 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:25 PM PDT 24
Peak memory 200468 kb
Host smart-5222da71-2cb7-44f1-9563-5368a9b25abb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769759560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.3769759560
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.2030162257
Short name T709
Test name
Test status
Simulation time 12758057 ps
CPU time 0.7 seconds
Started Jul 23 06:47:06 PM PDT 24
Finished Jul 23 06:47:09 PM PDT 24
Peak memory 199676 kb
Host smart-a181cda1-c808-4a0b-8e49-70a2d16b3ba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030162257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2030162257
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2997461963
Short name T230
Test name
Test status
Simulation time 16999795 ps
CPU time 0.79 seconds
Started Jul 23 06:47:11 PM PDT 24
Finished Jul 23 06:47:14 PM PDT 24
Peak memory 200452 kb
Host smart-d36e7978-9d93-4aef-89e1-e83212d1e139
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997461963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.2997461963
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.257881690
Short name T177
Test name
Test status
Simulation time 19683670 ps
CPU time 0.84 seconds
Started Jul 23 06:47:14 PM PDT 24
Finished Jul 23 06:47:17 PM PDT 24
Peak memory 200456 kb
Host smart-f588813b-0289-47ba-9b2b-598ba33081a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257881690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.257881690
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.2908489550
Short name T687
Test name
Test status
Simulation time 2480722655 ps
CPU time 14.07 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 200724 kb
Host smart-ec17f1ff-679c-486c-95a6-351951d0bddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908489550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2908489550
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.4210172174
Short name T455
Test name
Test status
Simulation time 741217884 ps
CPU time 5.71 seconds
Started Jul 23 06:47:15 PM PDT 24
Finished Jul 23 06:47:24 PM PDT 24
Peak memory 200524 kb
Host smart-26263ec5-25d6-472a-ab90-208f361e26f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210172174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.4210172174
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.2404150592
Short name T26
Test name
Test status
Simulation time 21550389 ps
CPU time 0.9 seconds
Started Jul 23 06:47:07 PM PDT 24
Finished Jul 23 06:47:11 PM PDT 24
Peak memory 200468 kb
Host smart-bc55ad8b-6872-4809-9dc1-36d8715afccd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404150592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.2404150592
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.305407107
Short name T729
Test name
Test status
Simulation time 32614820 ps
CPU time 0.89 seconds
Started Jul 23 06:47:10 PM PDT 24
Finished Jul 23 06:47:13 PM PDT 24
Peak memory 200476 kb
Host smart-211b2bbb-3484-4f15-8e0a-4abee1c2d885
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305407107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_clk_byp_req_intersig_mubi.305407107
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.4142677398
Short name T773
Test name
Test status
Simulation time 73993292 ps
CPU time 0.95 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 200448 kb
Host smart-030cd6fa-1b4c-4fa1-89d9-e45996a09b54
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142677398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.4142677398
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.3141041669
Short name T658
Test name
Test status
Simulation time 15212904 ps
CPU time 0.7 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:24 PM PDT 24
Peak memory 200460 kb
Host smart-7e35d5ff-3ea1-469c-a210-34a6742b991e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141041669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.3141041669
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.3556767133
Short name T374
Test name
Test status
Simulation time 622303273 ps
CPU time 2.7 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 200656 kb
Host smart-a0b9ec11-798b-4264-9c77-da0b8b5d93c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556767133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.3556767133
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.3701152575
Short name T153
Test name
Test status
Simulation time 24158566 ps
CPU time 0.85 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:24 PM PDT 24
Peak memory 200404 kb
Host smart-1b4f4b3a-d20e-44e6-a886-4012de0263f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701152575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3701152575
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.613283241
Short name T376
Test name
Test status
Simulation time 5881615038 ps
CPU time 42.31 seconds
Started Jul 23 06:47:10 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 200752 kb
Host smart-136444a0-adc8-4b9a-8dc9-c4e09e41dd7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613283241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.613283241
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.3728893112
Short name T323
Test name
Test status
Simulation time 98935980 ps
CPU time 1.23 seconds
Started Jul 23 06:47:10 PM PDT 24
Finished Jul 23 06:47:13 PM PDT 24
Peak memory 200468 kb
Host smart-50a8f44e-3d03-47b3-b432-7150b869281c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728893112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.3728893112
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3876121305
Short name T672
Test name
Test status
Simulation time 17353111 ps
CPU time 0.73 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 200524 kb
Host smart-bb20b548-fae3-4bd8-b981-da763bdf52ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876121305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3876121305
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.930329526
Short name T96
Test name
Test status
Simulation time 24861875 ps
CPU time 0.89 seconds
Started Jul 23 06:47:13 PM PDT 24
Finished Jul 23 06:47:16 PM PDT 24
Peak memory 200460 kb
Host smart-393b9476-653a-4550-a230-81772cdda8a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930329526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.930329526
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2027508901
Short name T713
Test name
Test status
Simulation time 48480010 ps
CPU time 0.81 seconds
Started Jul 23 06:47:18 PM PDT 24
Finished Jul 23 06:47:23 PM PDT 24
Peak memory 200376 kb
Host smart-438b7246-b8ed-41b2-b51a-ba319dde513e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027508901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2027508901
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.4268969080
Short name T289
Test name
Test status
Simulation time 26030952 ps
CPU time 0.89 seconds
Started Jul 23 06:47:17 PM PDT 24
Finished Jul 23 06:47:21 PM PDT 24
Peak memory 200332 kb
Host smart-d7363898-bccd-40fd-b809-b7e309b0aeb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268969080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.4268969080
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.3069931445
Short name T237
Test name
Test status
Simulation time 81570105 ps
CPU time 1.1 seconds
Started Jul 23 06:47:11 PM PDT 24
Finished Jul 23 06:47:14 PM PDT 24
Peak memory 200460 kb
Host smart-0219f4b3-3d89-443a-b139-f1faacdd4171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069931445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3069931445
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.3817955439
Short name T626
Test name
Test status
Simulation time 2515846600 ps
CPU time 10.48 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:47:41 PM PDT 24
Peak memory 200688 kb
Host smart-b1474322-643f-4f7d-a11a-f1266dfde00b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817955439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.3817955439
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.212614669
Short name T78
Test name
Test status
Simulation time 875868361 ps
CPU time 3.8 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:32 PM PDT 24
Peak memory 200520 kb
Host smart-cbbce546-ac9b-4961-bc08-0b61f9e7c62b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212614669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_ti
meout.212614669
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.3204615025
Short name T653
Test name
Test status
Simulation time 48670085 ps
CPU time 0.82 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:29 PM PDT 24
Peak memory 200468 kb
Host smart-719ebcf7-722f-49c3-9957-76e350987469
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204615025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.3204615025
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.588547539
Short name T214
Test name
Test status
Simulation time 20620639 ps
CPU time 0.74 seconds
Started Jul 23 06:47:11 PM PDT 24
Finished Jul 23 06:47:14 PM PDT 24
Peak memory 200464 kb
Host smart-e0b56155-47f8-475b-9679-d3fe4313dfe5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588547539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.clkmgr_lc_clk_byp_req_intersig_mubi.588547539
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1757856291
Short name T818
Test name
Test status
Simulation time 17800954 ps
CPU time 0.79 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:47:30 PM PDT 24
Peak memory 200408 kb
Host smart-fe0e6206-f71f-423e-923b-9280418a9582
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757856291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.1757856291
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.2675329169
Short name T330
Test name
Test status
Simulation time 21602701 ps
CPU time 0.77 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:26 PM PDT 24
Peak memory 200456 kb
Host smart-f7971df3-fd11-46b6-b980-b200e5275430
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675329169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.2675329169
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.532681018
Short name T121
Test name
Test status
Simulation time 231035094 ps
CPU time 1.42 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 200424 kb
Host smart-f2b08a3a-0d3d-4071-a9d6-76492a2cb30d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532681018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.532681018
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.3527230007
Short name T612
Test name
Test status
Simulation time 56885593 ps
CPU time 0.96 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:47:30 PM PDT 24
Peak memory 200640 kb
Host smart-23fe5502-9741-4dec-90bc-b825a8f8410a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527230007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3527230007
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.3022210170
Short name T814
Test name
Test status
Simulation time 2303146010 ps
CPU time 16.4 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 06:47:47 PM PDT 24
Peak memory 200736 kb
Host smart-943ab451-6915-411e-b7d4-1dce2cb7222c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022210170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.3022210170
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.2759488040
Short name T390
Test name
Test status
Simulation time 35245828 ps
CPU time 1.01 seconds
Started Jul 23 06:47:12 PM PDT 24
Finished Jul 23 06:47:15 PM PDT 24
Peak memory 200448 kb
Host smart-599c69f4-c729-4aba-bd26-2addb529916d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759488040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2759488040
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.461708430
Short name T40
Test name
Test status
Simulation time 20379600 ps
CPU time 0.75 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 200524 kb
Host smart-48fd3f4c-80cd-4131-ae12-d96ea3959b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461708430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkm
gr_alert_test.461708430
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3956513001
Short name T596
Test name
Test status
Simulation time 31614340 ps
CPU time 0.94 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:25 PM PDT 24
Peak memory 200424 kb
Host smart-195122c0-0a90-40b8-bef8-7aa9925efb32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956513001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.3956513001
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.1421399761
Short name T232
Test name
Test status
Simulation time 49508166 ps
CPU time 0.84 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:23 PM PDT 24
Peak memory 200376 kb
Host smart-d1654f53-c955-469a-b22e-cb4f0308b803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421399761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1421399761
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.2954317702
Short name T48
Test name
Test status
Simulation time 41914240 ps
CPU time 0.88 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:36 PM PDT 24
Peak memory 200468 kb
Host smart-b3447b74-deb3-43cc-95b9-f3d36c927c0e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954317702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.2954317702
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.3814414601
Short name T340
Test name
Test status
Simulation time 24875081 ps
CPU time 0.84 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:36 PM PDT 24
Peak memory 200464 kb
Host smart-21834060-6c20-48f3-acad-d5778c2983dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814414601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.3814414601
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.742515887
Short name T354
Test name
Test status
Simulation time 324802323 ps
CPU time 2.56 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:29 PM PDT 24
Peak memory 200460 kb
Host smart-f1bcb92b-e8d1-4849-9fd5-7a3a1642aa1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742515887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.742515887
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.3913625588
Short name T703
Test name
Test status
Simulation time 629347963 ps
CPU time 3.68 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 200524 kb
Host smart-bb78ca5d-997e-4551-b7ad-c33f1184562e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913625588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.3913625588
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.2821984743
Short name T589
Test name
Test status
Simulation time 247680794 ps
CPU time 1.48 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:37 PM PDT 24
Peak memory 200456 kb
Host smart-2a37da5a-256c-4863-af73-779845f944be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821984743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.2821984743
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2925591918
Short name T220
Test name
Test status
Simulation time 21197517 ps
CPU time 0.82 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 200492 kb
Host smart-83cc9be6-d9f5-4c75-981c-297f5fbb2913
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925591918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2925591918
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.1685322947
Short name T161
Test name
Test status
Simulation time 70393278 ps
CPU time 0.97 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:24 PM PDT 24
Peak memory 200472 kb
Host smart-9c98f1cd-20f5-4a3b-8b54-488c3e4bee1b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685322947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.1685322947
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.3738633534
Short name T27
Test name
Test status
Simulation time 23787745 ps
CPU time 0.8 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 200480 kb
Host smart-57e788eb-e51c-4e2a-9897-e461d19d30dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738633534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3738633534
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.1778682915
Short name T394
Test name
Test status
Simulation time 54628381 ps
CPU time 1 seconds
Started Jul 23 06:47:19 PM PDT 24
Finished Jul 23 06:47:23 PM PDT 24
Peak memory 200436 kb
Host smart-8d300b85-e6f5-4971-a9bb-cdfc0be56160
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778682915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.1778682915
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.2109133345
Short name T805
Test name
Test status
Simulation time 6218443023 ps
CPU time 25.87 seconds
Started Jul 23 06:47:18 PM PDT 24
Finished Jul 23 06:47:47 PM PDT 24
Peak memory 200788 kb
Host smart-c1484f34-b9fe-43c9-919c-6bb9e4903b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109133345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.2109133345
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.2455608059
Short name T673
Test name
Test status
Simulation time 23980590577 ps
CPU time 351.9 seconds
Started Jul 23 06:47:18 PM PDT 24
Finished Jul 23 06:53:13 PM PDT 24
Peak memory 209132 kb
Host smart-71f00b7a-7e09-42cb-952d-343137a94c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2455608059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.2455608059
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.48964165
Short name T183
Test name
Test status
Simulation time 89001766 ps
CPU time 1.1 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 200480 kb
Host smart-4c0607ce-9456-49b2-8ca7-30fefaca2736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48964165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.48964165
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.32206042
Short name T527
Test name
Test status
Simulation time 20535412 ps
CPU time 0.81 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 200520 kb
Host smart-da453308-52f8-48e9-bb00-9836ca25d841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32206042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmg
r_alert_test.32206042
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.917338648
Short name T750
Test name
Test status
Simulation time 44888348 ps
CPU time 0.91 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:30 PM PDT 24
Peak memory 200496 kb
Host smart-efd40109-dcb4-4445-b2e4-5a514c1b9d24
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917338648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.917338648
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.2345560843
Short name T429
Test name
Test status
Simulation time 17547341 ps
CPU time 0.73 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:29 PM PDT 24
Peak memory 200376 kb
Host smart-dd9bb952-1ab5-40ba-b2de-86471e186923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345560843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2345560843
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.3177124005
Short name T314
Test name
Test status
Simulation time 35571466 ps
CPU time 0.91 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:30 PM PDT 24
Peak memory 200336 kb
Host smart-433d1de6-e57a-4ac1-8cc3-30beff5d3290
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177124005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.3177124005
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.1288247286
Short name T787
Test name
Test status
Simulation time 22672939 ps
CPU time 0.88 seconds
Started Jul 23 06:47:17 PM PDT 24
Finished Jul 23 06:47:21 PM PDT 24
Peak memory 200472 kb
Host smart-749b362a-d44e-43aa-9546-380942664418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288247286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1288247286
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.2467070015
Short name T692
Test name
Test status
Simulation time 1875295501 ps
CPU time 14.07 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:46 PM PDT 24
Peak memory 200636 kb
Host smart-33d9410c-99db-4f78-a758-bcfdb2f78ae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467070015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2467070015
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.3325588281
Short name T381
Test name
Test status
Simulation time 1717103443 ps
CPU time 7.48 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200524 kb
Host smart-cf8f8c93-8502-4028-86d4-ed789be23d45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325588281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.3325588281
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.3955759338
Short name T581
Test name
Test status
Simulation time 197579979 ps
CPU time 1.27 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:35 PM PDT 24
Peak memory 200432 kb
Host smart-0dfc4565-dff7-44c7-afeb-813339a38ff7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955759338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.3955759338
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2270774977
Short name T348
Test name
Test status
Simulation time 29817010 ps
CPU time 0.82 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 200480 kb
Host smart-9d34d11d-1085-4584-9501-b6a234187a78
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270774977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2270774977
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1046512599
Short name T470
Test name
Test status
Simulation time 28640958 ps
CPU time 0.78 seconds
Started Jul 23 06:47:17 PM PDT 24
Finished Jul 23 06:47:21 PM PDT 24
Peak memory 200480 kb
Host smart-e799f0ea-5984-4804-98a7-99ea25d536d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046512599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.1046512599
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.2758663504
Short name T616
Test name
Test status
Simulation time 17889568 ps
CPU time 0.79 seconds
Started Jul 23 06:47:15 PM PDT 24
Finished Jul 23 06:47:18 PM PDT 24
Peak memory 200452 kb
Host smart-fb2190ef-f65e-4309-a145-4ea65f4f9aeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758663504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.2758663504
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.2052968156
Short name T395
Test name
Test status
Simulation time 656718180 ps
CPU time 2.9 seconds
Started Jul 23 06:47:23 PM PDT 24
Finished Jul 23 06:47:35 PM PDT 24
Peak memory 200628 kb
Host smart-56dade7b-4551-445c-8318-8ef22eace075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052968156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.2052968156
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.2757782698
Short name T778
Test name
Test status
Simulation time 261946518 ps
CPU time 1.61 seconds
Started Jul 23 06:47:18 PM PDT 24
Finished Jul 23 06:47:23 PM PDT 24
Peak memory 200388 kb
Host smart-f08d75a8-a2bb-48f8-af0e-c917ad447054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757782698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.2757782698
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.2164953063
Short name T309
Test name
Test status
Simulation time 54549239 ps
CPU time 1.16 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 200452 kb
Host smart-18e5235d-07f7-4ce2-b607-db6bc121dc02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164953063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.2164953063
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.2118277147
Short name T173
Test name
Test status
Simulation time 9775930918 ps
CPU time 146.11 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:50:06 PM PDT 24
Peak memory 209040 kb
Host smart-4f364b93-eb9b-489a-8083-7127c767fb63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2118277147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.2118277147
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.332710318
Short name T176
Test name
Test status
Simulation time 33733714 ps
CPU time 0.96 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 200456 kb
Host smart-ad5844f5-f426-483c-bd2a-6171a31a43a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332710318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.332710318
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.2410343271
Short name T426
Test name
Test status
Simulation time 58002890 ps
CPU time 0.87 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:31 PM PDT 24
Peak memory 200524 kb
Host smart-ccb9ef7b-e67b-4aee-9a6b-bd1b33339f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410343271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.2410343271
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.4120366428
Short name T347
Test name
Test status
Simulation time 17262247 ps
CPU time 0.78 seconds
Started Jul 23 06:44:17 PM PDT 24
Finished Jul 23 06:44:20 PM PDT 24
Peak memory 200452 kb
Host smart-d7f80fb8-ab03-438a-887c-c21c99eda9b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120366428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.4120366428
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.1687919248
Short name T298
Test name
Test status
Simulation time 32256531 ps
CPU time 0.77 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 199636 kb
Host smart-97210039-73f8-416a-91a1-eb8c4a11c357
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687919248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1687919248
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1972646268
Short name T434
Test name
Test status
Simulation time 57934958 ps
CPU time 0.94 seconds
Started Jul 23 06:44:20 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 200456 kb
Host smart-0e0c296e-844e-4f4a-a229-21f8ace3a13e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972646268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1972646268
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.4174007467
Short name T122
Test name
Test status
Simulation time 39507272 ps
CPU time 0.81 seconds
Started Jul 23 06:44:22 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 200400 kb
Host smart-eae1aad0-cbd5-45d3-99a6-99fe62720dbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174007467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.4174007467
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.9207952
Short name T802
Test name
Test status
Simulation time 2001864222 ps
CPU time 15.79 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:33 PM PDT 24
Peak memory 200588 kb
Host smart-5198c567-88ea-47a8-8202-c7d2395ed440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9207952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.9207952
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.3813773745
Short name T743
Test name
Test status
Simulation time 741666316 ps
CPU time 5.85 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 200516 kb
Host smart-7d33c965-62a3-4eae-a6b9-749ef6382f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813773745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.3813773745
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.451641173
Short name T72
Test name
Test status
Simulation time 57150074 ps
CPU time 0.93 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 200448 kb
Host smart-d54ae7ac-33f1-4af5-8d01-3977162b92e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451641173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_idle_intersig_mubi.451641173
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.1062639101
Short name T762
Test name
Test status
Simulation time 106201369 ps
CPU time 1.13 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 200508 kb
Host smart-d9de18e8-a969-4348-8183-189dcda1a6e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062639101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.1062639101
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.163506340
Short name T602
Test name
Test status
Simulation time 77498667 ps
CPU time 1.03 seconds
Started Jul 23 06:44:18 PM PDT 24
Finished Jul 23 06:44:23 PM PDT 24
Peak memory 200384 kb
Host smart-ab36de9a-ac86-422f-8532-e66ab5113edc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163506340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_lc_ctrl_intersig_mubi.163506340
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.61267313
Short name T633
Test name
Test status
Simulation time 31962659 ps
CPU time 0.83 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:19 PM PDT 24
Peak memory 200428 kb
Host smart-bbbbcd6e-56c4-436c-9760-b13199bd2b3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61267313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.61267313
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.2584225834
Short name T369
Test name
Test status
Simulation time 629221300 ps
CPU time 2.65 seconds
Started Jul 23 06:44:20 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 200484 kb
Host smart-c98c3ac9-b3bb-4f24-afcf-90c422e721cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584225834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2584225834
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.1968759792
Short name T47
Test name
Test status
Simulation time 179249363 ps
CPU time 2.16 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:33 PM PDT 24
Peak memory 215692 kb
Host smart-2863e7ab-6aa7-4e0a-aff7-229ebafd6ec3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968759792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.1968759792
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.3336961162
Short name T43
Test name
Test status
Simulation time 64469156 ps
CPU time 1.01 seconds
Started Jul 23 06:44:15 PM PDT 24
Finished Jul 23 06:44:17 PM PDT 24
Peak memory 200440 kb
Host smart-a53037f7-aa6d-481b-991b-777ff23f14a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336961162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3336961162
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.3404588476
Short name T419
Test name
Test status
Simulation time 63988419 ps
CPU time 0.89 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:29 PM PDT 24
Peak memory 200332 kb
Host smart-34d3c98d-958d-4756-8223-1ea15d9c5062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404588476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.3404588476
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.944760147
Short name T18
Test name
Test status
Simulation time 179955603948 ps
CPU time 1023.23 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 07:01:34 PM PDT 24
Peak memory 217232 kb
Host smart-748b963e-08bb-41f7-b255-c00de2fa24c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=944760147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.944760147
Directory /workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.clkmgr_trans.3207773030
Short name T93
Test name
Test status
Simulation time 27498987 ps
CPU time 0.99 seconds
Started Jul 23 06:44:16 PM PDT 24
Finished Jul 23 06:44:18 PM PDT 24
Peak memory 200460 kb
Host smart-96940ec9-9b4f-41f5-b84d-042324383f0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207773030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3207773030
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.2278079613
Short name T587
Test name
Test status
Simulation time 18422206 ps
CPU time 0.82 seconds
Started Jul 23 06:47:21 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 200536 kb
Host smart-7a47caf1-ad3b-4db9-bc68-c7a96c829014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278079613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.2278079613
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.4103481581
Short name T761
Test name
Test status
Simulation time 32515428 ps
CPU time 0.85 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200484 kb
Host smart-1df8bced-da53-4594-83fd-2adae8e1361a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103481581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.4103481581
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.2277433599
Short name T551
Test name
Test status
Simulation time 31953570 ps
CPU time 0.76 seconds
Started Jul 23 06:47:23 PM PDT 24
Finished Jul 23 06:47:32 PM PDT 24
Peak memory 200292 kb
Host smart-341b27cd-763f-4959-9325-b6a214790f9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277433599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.2277433599
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.4186433149
Short name T437
Test name
Test status
Simulation time 58786846 ps
CPU time 0.94 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 200444 kb
Host smart-f8e93995-a9e0-4a5b-90bd-edba428de32b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186433149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.4186433149
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.2816941303
Short name T586
Test name
Test status
Simulation time 18145730 ps
CPU time 0.79 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:47:39 PM PDT 24
Peak memory 200440 kb
Host smart-d91de1cb-e6ef-40df-b567-1fe46cc949ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816941303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.2816941303
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.3252905881
Short name T502
Test name
Test status
Simulation time 2474759260 ps
CPU time 19.44 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:48:02 PM PDT 24
Peak memory 200660 kb
Host smart-e08f1c4d-9d54-43eb-9c10-050f83e5f358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252905881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.3252905881
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.2261724306
Short name T720
Test name
Test status
Simulation time 1230019061 ps
CPU time 5.37 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200536 kb
Host smart-f2ad21cd-d0b7-4948-b285-7c5d545e78fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261724306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.2261724306
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1045067374
Short name T126
Test name
Test status
Simulation time 25501403 ps
CPU time 0.89 seconds
Started Jul 23 06:47:23 PM PDT 24
Finished Jul 23 06:47:32 PM PDT 24
Peak memory 200360 kb
Host smart-653f419b-03d1-4697-92e6-74b7b058fd1b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045067374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1045067374
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2429979771
Short name T562
Test name
Test status
Simulation time 43926238 ps
CPU time 0.94 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 200492 kb
Host smart-f64647c4-d7bd-4474-8616-db889dd97589
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429979771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.2429979771
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3354969605
Short name T262
Test name
Test status
Simulation time 14099948 ps
CPU time 0.76 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 200476 kb
Host smart-b7581e53-8d40-4186-9660-a907c3891b3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354969605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.3354969605
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.277291337
Short name T362
Test name
Test status
Simulation time 17567548 ps
CPU time 0.84 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 200428 kb
Host smart-4d24b209-f87a-40c7-b824-b80f6bbed604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277291337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.277291337
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.2657441484
Short name T77
Test name
Test status
Simulation time 160454196 ps
CPU time 1.28 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:28 PM PDT 24
Peak memory 200432 kb
Host smart-00c1240d-d6c2-4644-bb5f-acd2e9b0876f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657441484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.2657441484
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.837196326
Short name T650
Test name
Test status
Simulation time 17832708 ps
CPU time 0.8 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 200592 kb
Host smart-52005760-d7f2-4fd6-bb01-773ecb2b0e42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837196326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.837196326
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.1299303228
Short name T590
Test name
Test status
Simulation time 5825333234 ps
CPU time 21.62 seconds
Started Jul 23 06:47:25 PM PDT 24
Finished Jul 23 06:47:57 PM PDT 24
Peak memory 200764 kb
Host smart-f7f23080-3bbd-4a44-b5e2-1a2dd1369ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299303228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.1299303228
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.4170148414
Short name T174
Test name
Test status
Simulation time 210281522706 ps
CPU time 1219.59 seconds
Started Jul 23 06:47:22 PM PDT 24
Finished Jul 23 07:07:50 PM PDT 24
Peak memory 214148 kb
Host smart-5e0056c9-4759-4181-aa9f-b2a5799adc23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4170148414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.4170148414
Directory /workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.clkmgr_trans.755073546
Short name T367
Test name
Test status
Simulation time 189247079 ps
CPU time 1.52 seconds
Started Jul 23 06:47:20 PM PDT 24
Finished Jul 23 06:47:27 PM PDT 24
Peak memory 200464 kb
Host smart-c13ab6fb-431c-4ee3-978e-156e260ce11f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755073546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.755073546
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.459263225
Short name T531
Test name
Test status
Simulation time 14396274 ps
CPU time 0.78 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200524 kb
Host smart-c464f8ea-9443-4f8c-aeec-7740f329580a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459263225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkm
gr_alert_test.459263225
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.2174290615
Short name T100
Test name
Test status
Simulation time 29248868 ps
CPU time 0.9 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:41 PM PDT 24
Peak memory 200476 kb
Host smart-f5dd51a3-6acf-417c-ab72-77116d329f28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174290615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.2174290615
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.1461681982
Short name T328
Test name
Test status
Simulation time 12203136 ps
CPU time 0.69 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 199636 kb
Host smart-e2238547-3d3f-4505-8d9f-8dfdf94ebbc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461681982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.1461681982
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.2949165018
Short name T738
Test name
Test status
Simulation time 20824750 ps
CPU time 0.83 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:41 PM PDT 24
Peak memory 200420 kb
Host smart-197e6334-99ea-4724-bfa1-3647d4390f4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949165018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.2949165018
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.4009581391
Short name T696
Test name
Test status
Simulation time 133648499 ps
CPU time 1.06 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 200460 kb
Host smart-4dbe1f37-5d50-467c-bb18-b5f3aa22670b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009581391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.4009581391
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.128403933
Short name T405
Test name
Test status
Simulation time 2249879218 ps
CPU time 12.97 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:52 PM PDT 24
Peak memory 200712 kb
Host smart-243e732a-6182-4045-8383-ee1575e32b0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128403933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.128403933
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.16795454
Short name T206
Test name
Test status
Simulation time 1239246193 ps
CPU time 5.14 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 200520 kb
Host smart-874d3716-f5b5-403d-bccc-71d90722be08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16795454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_tim
eout.16795454
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.3889032713
Short name T172
Test name
Test status
Simulation time 57182744 ps
CPU time 0.98 seconds
Started Jul 23 06:47:26 PM PDT 24
Finished Jul 23 06:47:38 PM PDT 24
Peak memory 200448 kb
Host smart-15cfb13c-6e04-4db7-8ede-714b4eba1888
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889032713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.3889032713
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3761494603
Short name T775
Test name
Test status
Simulation time 14074840 ps
CPU time 0.76 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 200448 kb
Host smart-446c0434-81f3-4625-90d4-0b1fc848738e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761494603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3761494603
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2288431525
Short name T669
Test name
Test status
Simulation time 43313137 ps
CPU time 0.95 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 200396 kb
Host smart-af7e1a0b-77db-4da3-81d6-1c198897ce8e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288431525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.2288431525
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.1794272564
Short name T74
Test name
Test status
Simulation time 43025427 ps
CPU time 0.79 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200280 kb
Host smart-c7ba4a4a-b283-4a38-b00b-f46a92f19e3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794272564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.1794272564
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.1686236615
Short name T609
Test name
Test status
Simulation time 323229075 ps
CPU time 2.33 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200424 kb
Host smart-d50b6ccd-c00e-4e77-b59e-d4f5251c24f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686236615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1686236615
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1305134282
Short name T757
Test name
Test status
Simulation time 17588651 ps
CPU time 0.82 seconds
Started Jul 23 06:47:24 PM PDT 24
Finished Jul 23 06:47:34 PM PDT 24
Peak memory 200472 kb
Host smart-475a9916-224d-4fea-a39d-5837704f7d6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305134282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1305134282
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.1927952085
Short name T719
Test name
Test status
Simulation time 3470598131 ps
CPU time 13.78 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:53 PM PDT 24
Peak memory 200760 kb
Host smart-dd5177e1-2cf8-4e3b-a89c-49e7acf5f70c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927952085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.1927952085
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.2473805431
Short name T68
Test name
Test status
Simulation time 40975801168 ps
CPU time 602.56 seconds
Started Jul 23 06:47:27 PM PDT 24
Finished Jul 23 06:57:40 PM PDT 24
Peak memory 209092 kb
Host smart-d41c5f43-8270-4d55-a2ba-49e65f344a18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2473805431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.2473805431
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.440019881
Short name T532
Test name
Test status
Simulation time 17301910 ps
CPU time 0.78 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:41 PM PDT 24
Peak memory 200480 kb
Host smart-5154c726-4f2f-4ac0-a5eb-f95c137d9a4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440019881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.440019881
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.3266677582
Short name T331
Test name
Test status
Simulation time 15454618 ps
CPU time 0.78 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 200524 kb
Host smart-5c1fdf36-46ef-4a33-856b-da4613f62d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266677582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.3266677582
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.754425708
Short name T88
Test name
Test status
Simulation time 20097146 ps
CPU time 0.82 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:40 PM PDT 24
Peak memory 200472 kb
Host smart-9193a8a2-b92c-454b-88a9-43f8ba56d2b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754425708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.754425708
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.4158777726
Short name T689
Test name
Test status
Simulation time 61178751 ps
CPU time 0.82 seconds
Started Jul 23 06:47:29 PM PDT 24
Finished Jul 23 06:47:41 PM PDT 24
Peak memory 199676 kb
Host smart-82bdb75e-1ced-466e-972f-338976ac4038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158777726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.4158777726
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.3486835652
Short name T200
Test name
Test status
Simulation time 83196127 ps
CPU time 1.02 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 200440 kb
Host smart-1ec1f0e8-4a15-491e-b4e6-6cb49743bfe2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486835652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.3486835652
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.604451068
Short name T815
Test name
Test status
Simulation time 65108034 ps
CPU time 0.96 seconds
Started Jul 23 06:47:50 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 200464 kb
Host smart-c2fe67a5-29a2-46ec-8daf-1870fd3d1371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604451068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.604451068
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.718405054
Short name T791
Test name
Test status
Simulation time 1521901247 ps
CPU time 11.62 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:47:53 PM PDT 24
Peak memory 200460 kb
Host smart-68e8d276-7533-41b2-b133-3e967a2d5665
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718405054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.718405054
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.2262294131
Short name T537
Test name
Test status
Simulation time 734570469 ps
CPU time 5.19 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:47:47 PM PDT 24
Peak memory 200412 kb
Host smart-94a7fc1b-9c5c-49f2-8969-b1a83591098a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262294131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.2262294131
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2214536239
Short name T593
Test name
Test status
Simulation time 43143621 ps
CPU time 0.84 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200456 kb
Host smart-aa4df8f0-b858-4882-8fb1-306c70ff610d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214536239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.2214536239
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3619019284
Short name T751
Test name
Test status
Simulation time 20293275 ps
CPU time 0.77 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200452 kb
Host smart-b3a12663-ec2b-490f-b804-cf641fefba32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619019284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3619019284
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1357150931
Short name T618
Test name
Test status
Simulation time 64995628 ps
CPU time 0.97 seconds
Started Jul 23 06:47:43 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 200460 kb
Host smart-3f964a33-1c2d-4991-aedd-b35237b4d0d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357150931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.1357150931
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.1324750639
Short name T383
Test name
Test status
Simulation time 13342965 ps
CPU time 0.72 seconds
Started Jul 23 06:47:27 PM PDT 24
Finished Jul 23 06:47:39 PM PDT 24
Peak memory 200428 kb
Host smart-d33fe2bb-af06-462a-87be-72d89e2e4cc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324750639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1324750639
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.1417039285
Short name T449
Test name
Test status
Simulation time 1265444256 ps
CPU time 7.04 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 200636 kb
Host smart-bed79958-0333-4c96-bd43-589129c26edb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417039285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1417039285
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.2637926329
Short name T722
Test name
Test status
Simulation time 24052878 ps
CPU time 0.82 seconds
Started Jul 23 06:47:30 PM PDT 24
Finished Jul 23 06:47:42 PM PDT 24
Peak memory 200476 kb
Host smart-76b72128-412a-4c0c-9a46-e3191607473a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637926329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2637926329
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.3635074752
Short name T154
Test name
Test status
Simulation time 5603277811 ps
CPU time 28.98 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:48:11 PM PDT 24
Peak memory 200736 kb
Host smart-11380510-6462-4131-8ecc-080a866e0ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635074752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.3635074752
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.2959680392
Short name T453
Test name
Test status
Simulation time 83907427840 ps
CPU time 564.03 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:57:08 PM PDT 24
Peak memory 217228 kb
Host smart-61f478ea-372e-4ea2-a4c2-93429b8f0775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2959680392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.2959680392
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.338438718
Short name T264
Test name
Test status
Simulation time 124382582 ps
CPU time 1.27 seconds
Started Jul 23 06:47:37 PM PDT 24
Finished Jul 23 06:47:47 PM PDT 24
Peak memory 200460 kb
Host smart-b6659c4b-eee5-4e39-9492-ebbbce520cae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338438718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.338438718
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.1241114930
Short name T730
Test name
Test status
Simulation time 24260503 ps
CPU time 0.77 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 200544 kb
Host smart-0b33d9d0-aa72-4648-9c0d-58f2ddb61009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241114930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.1241114930
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.1875606277
Short name T483
Test name
Test status
Simulation time 27886438 ps
CPU time 0.83 seconds
Started Jul 23 06:47:34 PM PDT 24
Finished Jul 23 06:47:46 PM PDT 24
Peak memory 200448 kb
Host smart-f65feaa4-6792-4dde-b920-fc47f8083882
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875606277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.1875606277
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.755116037
Short name T37
Test name
Test status
Simulation time 14325158 ps
CPU time 0.7 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:47:43 PM PDT 24
Peak memory 200276 kb
Host smart-75d20c14-af22-4416-9f14-eb9e05fcd771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755116037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.755116037
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2023390417
Short name T226
Test name
Test status
Simulation time 26302553 ps
CPU time 0.83 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:45 PM PDT 24
Peak memory 200460 kb
Host smart-6b351b82-a6a2-44f0-a96a-4b9f6fecc572
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023390417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.2023390417
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3728043099
Short name T463
Test name
Test status
Simulation time 19277732 ps
CPU time 0.83 seconds
Started Jul 23 06:47:28 PM PDT 24
Finished Jul 23 06:47:39 PM PDT 24
Peak memory 200380 kb
Host smart-0c0cb681-5deb-41bb-97d9-39265e0ffede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728043099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3728043099
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.1069485922
Short name T745
Test name
Test status
Simulation time 2236206690 ps
CPU time 16.24 seconds
Started Jul 23 06:47:34 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 200652 kb
Host smart-17d4aefb-49dc-46bf-88d9-95f0b3e604e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069485922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1069485922
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.974380235
Short name T797
Test name
Test status
Simulation time 1474150966 ps
CPU time 6.29 seconds
Started Jul 23 06:47:46 PM PDT 24
Finished Jul 23 06:47:58 PM PDT 24
Peak memory 200520 kb
Host smart-31339c9c-7e66-448b-b5c7-cc6bed7a0506
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974380235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_ti
meout.974380235
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.618099607
Short name T512
Test name
Test status
Simulation time 51280631 ps
CPU time 1.01 seconds
Started Jul 23 06:47:38 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 200432 kb
Host smart-d24794f5-1941-432d-83c8-ffe566fd2a9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618099607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.clkmgr_idle_intersig_mubi.618099607
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.861247663
Short name T21
Test name
Test status
Simulation time 100110180 ps
CPU time 1.06 seconds
Started Jul 23 06:47:34 PM PDT 24
Finished Jul 23 06:47:46 PM PDT 24
Peak memory 200460 kb
Host smart-bb51f9d8-8336-4cc1-ab7d-4688c6156762
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861247663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_clk_byp_req_intersig_mubi.861247663
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.733865731
Short name T292
Test name
Test status
Simulation time 23392375 ps
CPU time 0.86 seconds
Started Jul 23 06:47:32 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 200452 kb
Host smart-ec230eef-610c-46b4-ad81-6ce010c2080d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733865731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.733865731
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.4187099544
Short name T319
Test name
Test status
Simulation time 14759928 ps
CPU time 0.76 seconds
Started Jul 23 06:47:56 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 200428 kb
Host smart-eb53778a-e593-4273-a729-28c6f1ab1321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187099544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.4187099544
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.1047340084
Short name T533
Test name
Test status
Simulation time 693475736 ps
CPU time 3.11 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 200640 kb
Host smart-a6f9adfa-1bc7-4978-ade2-bdeb86ef0277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047340084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1047340084
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.1945204807
Short name T728
Test name
Test status
Simulation time 129578216 ps
CPU time 1.15 seconds
Started Jul 23 06:47:31 PM PDT 24
Finished Jul 23 06:47:44 PM PDT 24
Peak memory 200304 kb
Host smart-5b6deab9-e1eb-4651-a208-3ffc286b4cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945204807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.1945204807
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.527239005
Short name T809
Test name
Test status
Simulation time 106368589 ps
CPU time 1.15 seconds
Started Jul 23 06:47:42 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 200416 kb
Host smart-3345fce5-d04d-4e81-8d57-a3dd09b05290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527239005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.527239005
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.1624995524
Short name T657
Test name
Test status
Simulation time 184657270909 ps
CPU time 834.58 seconds
Started Jul 23 06:47:34 PM PDT 24
Finished Jul 23 07:01:39 PM PDT 24
Peak memory 217228 kb
Host smart-5e6b9a4a-25b7-4d45-9c7b-b8dbc913c4aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1624995524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1624995524
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.117032195
Short name T503
Test name
Test status
Simulation time 86572809 ps
CPU time 1.12 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:45 PM PDT 24
Peak memory 200480 kb
Host smart-2787fe5e-4ae7-4e64-bf04-6f189f7215a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117032195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.117032195
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.3766110893
Short name T615
Test name
Test status
Simulation time 18367105 ps
CPU time 0.79 seconds
Started Jul 23 06:47:39 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 200536 kb
Host smart-d217bb7a-2f99-4d0f-ab4b-d4fd7ad20b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766110893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.3766110893
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2086718212
Short name T577
Test name
Test status
Simulation time 80783438 ps
CPU time 1.05 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 200484 kb
Host smart-42c7227b-7844-47c7-b154-688222c5479f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086718212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.2086718212
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.1416608169
Short name T185
Test name
Test status
Simulation time 50250252 ps
CPU time 0.86 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 200380 kb
Host smart-55f1e8c7-2b8e-4c89-8208-ef1b151e6c46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416608169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.1416608169
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.640865030
Short name T568
Test name
Test status
Simulation time 26823034 ps
CPU time 0.96 seconds
Started Jul 23 06:47:41 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 200444 kb
Host smart-6817f766-acdf-48eb-b86f-accb1ea057a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640865030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_div_intersig_mubi.640865030
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.1788162933
Short name T511
Test name
Test status
Simulation time 25926181 ps
CPU time 0.8 seconds
Started Jul 23 06:47:47 PM PDT 24
Finished Jul 23 06:47:53 PM PDT 24
Peak memory 200424 kb
Host smart-a74c18c6-966d-4a9a-a6bd-3663d1e5d89f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788162933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.1788162933
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2905683420
Short name T564
Test name
Test status
Simulation time 325489535 ps
CPU time 2.45 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:48:00 PM PDT 24
Peak memory 200356 kb
Host smart-a9196dda-ca8d-4ae4-a736-fba50e9f84db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905683420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2905683420
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.2275444399
Short name T339
Test name
Test status
Simulation time 1604099857 ps
CPU time 6.68 seconds
Started Jul 23 06:47:52 PM PDT 24
Finished Jul 23 06:48:02 PM PDT 24
Peak memory 200508 kb
Host smart-10a198b2-13ac-4292-92b1-7c6bd0a9cf2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275444399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.2275444399
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.2140455781
Short name T24
Test name
Test status
Simulation time 17872260 ps
CPU time 0.83 seconds
Started Jul 23 06:47:52 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 200456 kb
Host smart-aa46ba55-9fc2-4144-bc36-e0fce6b14bd5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140455781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.2140455781
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3819855126
Short name T447
Test name
Test status
Simulation time 53426459 ps
CPU time 0.86 seconds
Started Jul 23 06:47:38 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 200472 kb
Host smart-da24f71a-dca7-4fc2-913f-2295d49156ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819855126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.3819855126
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1609494026
Short name T436
Test name
Test status
Simulation time 54102540 ps
CPU time 0.99 seconds
Started Jul 23 06:47:42 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 200488 kb
Host smart-780681f1-7bb2-4d94-b58b-5aa10c09d976
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609494026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.1609494026
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.825016053
Short name T630
Test name
Test status
Simulation time 29614350 ps
CPU time 0.76 seconds
Started Jul 23 06:47:48 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 200656 kb
Host smart-a3871004-6e89-46d6-bffd-2f9c162f4161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825016053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.825016053
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.1218978500
Short name T644
Test name
Test status
Simulation time 198731767 ps
CPU time 1.66 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 200452 kb
Host smart-b37a55ed-7f60-4084-b222-ad362c3a376c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218978500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1218978500
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.2376898362
Short name T621
Test name
Test status
Simulation time 17712111 ps
CPU time 0.79 seconds
Started Jul 23 06:47:33 PM PDT 24
Finished Jul 23 06:47:45 PM PDT 24
Peak memory 200428 kb
Host smart-ec59e6aa-244e-4cd4-bf6a-772c7c04364c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376898362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.2376898362
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3167357471
Short name T132
Test name
Test status
Simulation time 3610914945 ps
CPU time 27.92 seconds
Started Jul 23 06:47:39 PM PDT 24
Finished Jul 23 06:48:15 PM PDT 24
Peak memory 200680 kb
Host smart-c46a350f-afb8-4d42-9201-f1e799462e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167357471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3167357471
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.519495920
Short name T228
Test name
Test status
Simulation time 53627605 ps
CPU time 1 seconds
Started Jul 23 06:48:02 PM PDT 24
Finished Jul 23 06:48:05 PM PDT 24
Peak memory 200460 kb
Host smart-88febc27-ef47-438d-b7cc-f75a701b63e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519495920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.519495920
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.667973207
Short name T273
Test name
Test status
Simulation time 20567845 ps
CPU time 0.89 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 200508 kb
Host smart-4a68d76b-e62e-455b-a752-977534fd67f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667973207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkm
gr_alert_test.667973207
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.418688384
Short name T667
Test name
Test status
Simulation time 80030809 ps
CPU time 1.08 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 200452 kb
Host smart-c1111409-1bd8-4856-84e4-69f01c54b87e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418688384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.418688384
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3987090827
Short name T163
Test name
Test status
Simulation time 14697320 ps
CPU time 0.72 seconds
Started Jul 23 06:47:41 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 199640 kb
Host smart-1869e440-9923-49ae-8c2d-35bc6bb15376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987090827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3987090827
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2023410881
Short name T123
Test name
Test status
Simulation time 16796902 ps
CPU time 0.75 seconds
Started Jul 23 06:47:50 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 200356 kb
Host smart-65681108-1b87-4ae4-9225-12dcd67654a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023410881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2023410881
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.2001113091
Short name T53
Test name
Test status
Simulation time 26962177 ps
CPU time 0.91 seconds
Started Jul 23 06:47:49 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 200404 kb
Host smart-0f676696-dc32-4733-8aa1-9d3fbe41593d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001113091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2001113091
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.1038357873
Short name T305
Test name
Test status
Simulation time 1519934350 ps
CPU time 8.94 seconds
Started Jul 23 06:47:39 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 200492 kb
Host smart-64997399-45ca-48ad-bc5b-aa979001377f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038357873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1038357873
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.3694575981
Short name T377
Test name
Test status
Simulation time 2315253202 ps
CPU time 9.8 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 200764 kb
Host smart-a5002260-afb7-41fc-b06d-ab8a0e9db5b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694575981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.3694575981
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.3993483188
Short name T205
Test name
Test status
Simulation time 40385779 ps
CPU time 0.92 seconds
Started Jul 23 06:48:04 PM PDT 24
Finished Jul 23 06:48:07 PM PDT 24
Peak memory 200448 kb
Host smart-4dddc8d3-1f0a-411b-88be-34fc21212eb3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993483188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.3993483188
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.848089344
Short name T472
Test name
Test status
Simulation time 28740969 ps
CPU time 0.83 seconds
Started Jul 23 06:47:41 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 200464 kb
Host smart-7c86307f-b4b8-4d6e-8294-1ed5f7ddf242
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848089344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_clk_byp_req_intersig_mubi.848089344
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.778888791
Short name T574
Test name
Test status
Simulation time 18592159 ps
CPU time 0.8 seconds
Started Jul 23 06:47:39 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 200468 kb
Host smart-7eedcdd4-6ee5-4ac5-9285-368e8678a6f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778888791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_ctrl_intersig_mubi.778888791
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.1353297425
Short name T356
Test name
Test status
Simulation time 34024270 ps
CPU time 0.79 seconds
Started Jul 23 06:47:39 PM PDT 24
Finished Jul 23 06:47:48 PM PDT 24
Peak memory 200444 kb
Host smart-31d9467c-f354-40ae-a636-c24961f622a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353297425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1353297425
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.207015797
Short name T169
Test name
Test status
Simulation time 701520549 ps
CPU time 3.12 seconds
Started Jul 23 06:48:03 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 200632 kb
Host smart-29305f6c-0df0-4450-a2ca-c4678d2af34a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207015797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.207015797
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.2786853720
Short name T540
Test name
Test status
Simulation time 72211056 ps
CPU time 1.02 seconds
Started Jul 23 06:47:40 PM PDT 24
Finished Jul 23 06:47:49 PM PDT 24
Peak memory 200420 kb
Host smart-430303bb-3bf0-4100-a0eb-33f65b8a2292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786853720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2786853720
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.3384906215
Short name T468
Test name
Test status
Simulation time 2579146614 ps
CPU time 19.36 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:48:17 PM PDT 24
Peak memory 200612 kb
Host smart-634af781-6011-452f-8e30-9f94b3c724b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384906215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.3384906215
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.1785610506
Short name T399
Test name
Test status
Simulation time 28468313 ps
CPU time 0.99 seconds
Started Jul 23 06:47:56 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 200452 kb
Host smart-f8e16b89-2ea9-44d5-87ff-b590effa0bef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785610506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1785610506
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3394967602
Short name T236
Test name
Test status
Simulation time 16959805 ps
CPU time 0.78 seconds
Started Jul 23 06:48:00 PM PDT 24
Finished Jul 23 06:48:03 PM PDT 24
Peak memory 200524 kb
Host smart-96b081e8-224e-483b-ad8c-c269e96b1300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394967602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3394967602
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.90399927
Short name T422
Test name
Test status
Simulation time 39733206 ps
CPU time 0.81 seconds
Started Jul 23 06:47:42 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 200460 kb
Host smart-14f8755b-1ab3-4d5f-a8c6-a69f0841a817
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90399927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_clk_handshake_intersig_mubi.90399927
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1205777807
Short name T188
Test name
Test status
Simulation time 38418743 ps
CPU time 0.78 seconds
Started Jul 23 06:47:43 PM PDT 24
Finished Jul 23 06:47:51 PM PDT 24
Peak memory 200328 kb
Host smart-178af711-af67-4542-bc31-228d03cc63e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205777807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1205777807
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.3538768847
Short name T752
Test name
Test status
Simulation time 40284802 ps
CPU time 0.91 seconds
Started Jul 23 06:47:51 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 200428 kb
Host smart-33e3a7bf-ac50-488f-aee2-8ef685bd6577
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538768847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.3538768847
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.2023770734
Short name T308
Test name
Test status
Simulation time 27656193 ps
CPU time 0.8 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:47:51 PM PDT 24
Peak memory 200460 kb
Host smart-bcb410df-36df-4459-865e-f7df116d1c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023770734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.2023770734
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.1899524571
Short name T781
Test name
Test status
Simulation time 1045099791 ps
CPU time 5.95 seconds
Started Jul 23 06:47:43 PM PDT 24
Finished Jul 23 06:47:56 PM PDT 24
Peak memory 200472 kb
Host smart-6a5b8c9c-4180-4d58-8d75-cca7c18c1bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899524571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.1899524571
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.1765208383
Short name T629
Test name
Test status
Simulation time 981112207 ps
CPU time 3.89 seconds
Started Jul 23 06:47:43 PM PDT 24
Finished Jul 23 06:47:54 PM PDT 24
Peak memory 200500 kb
Host smart-ecafe2e3-7985-4b3a-aaeb-f2c15de7ca2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765208383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.1765208383
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1412603316
Short name T373
Test name
Test status
Simulation time 24263741 ps
CPU time 0.88 seconds
Started Jul 23 06:47:43 PM PDT 24
Finished Jul 23 06:47:51 PM PDT 24
Peak memory 200456 kb
Host smart-51bd0ae0-f60c-4fb9-b8ea-5c6590eb2d7c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412603316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1412603316
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1525195576
Short name T579
Test name
Test status
Simulation time 23343696 ps
CPU time 0.88 seconds
Started Jul 23 06:47:59 PM PDT 24
Finished Jul 23 06:48:02 PM PDT 24
Peak memory 200436 kb
Host smart-10870259-f27e-49cc-ab6e-5d68f2946f6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525195576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1525195576
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.1877326075
Short name T458
Test name
Test status
Simulation time 38481870 ps
CPU time 0.91 seconds
Started Jul 23 06:47:42 PM PDT 24
Finished Jul 23 06:47:50 PM PDT 24
Peak memory 200452 kb
Host smart-1a4697a1-c6b8-43a5-8d13-5c9cb2b5e17d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877326075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.1877326075
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.2394264868
Short name T619
Test name
Test status
Simulation time 17594286 ps
CPU time 0.81 seconds
Started Jul 23 06:47:58 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 200444 kb
Host smart-a2323434-7a31-424e-a1b8-65fadfb0f2d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394264868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.2394264868
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.1592334186
Short name T120
Test name
Test status
Simulation time 935474797 ps
CPU time 4.31 seconds
Started Jul 23 06:48:04 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 200624 kb
Host smart-412c3502-82d0-4926-976d-1aa2a8224361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592334186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1592334186
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.1364036611
Short name T407
Test name
Test status
Simulation time 23171853 ps
CPU time 0.85 seconds
Started Jul 23 06:47:44 PM PDT 24
Finished Jul 23 06:47:52 PM PDT 24
Peak memory 200440 kb
Host smart-2c490dd1-6434-432c-bc57-22b4cbbc993b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364036611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.1364036611
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.4002014865
Short name T810
Test name
Test status
Simulation time 720309546 ps
CPU time 6.39 seconds
Started Jul 23 06:47:52 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 200492 kb
Host smart-15e1555e-b3f8-400a-8c19-87c9809c30ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002014865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.4002014865
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.3321589262
Short name T592
Test name
Test status
Simulation time 43752745 ps
CPU time 0.81 seconds
Started Jul 23 06:47:57 PM PDT 24
Finished Jul 23 06:48:00 PM PDT 24
Peak memory 200472 kb
Host smart-b1a6d02a-52b5-4f66-b4d4-ab9158780ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321589262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3321589262
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.2714391136
Short name T641
Test name
Test status
Simulation time 34213929 ps
CPU time 0.8 seconds
Started Jul 23 06:47:54 PM PDT 24
Finished Jul 23 06:47:58 PM PDT 24
Peak memory 200496 kb
Host smart-273f5149-0dd7-4d30-9117-eefeb9db94a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714391136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.2714391136
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.4227359852
Short name T417
Test name
Test status
Simulation time 15872276 ps
CPU time 0.85 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 200416 kb
Host smart-d1c0b788-def1-4ec1-ba62-db2105c1670b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227359852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.4227359852
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.3395998630
Short name T187
Test name
Test status
Simulation time 25785098 ps
CPU time 0.75 seconds
Started Jul 23 06:47:51 PM PDT 24
Finished Jul 23 06:47:55 PM PDT 24
Peak memory 199544 kb
Host smart-93ca1563-6e9f-4e5a-8feb-62f881acea59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395998630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.3395998630
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.2680263126
Short name T387
Test name
Test status
Simulation time 17590271 ps
CPU time 0.77 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 200380 kb
Host smart-d1de51ab-1dcf-4631-83f1-0005974b3e16
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680263126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.2680263126
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.3798656315
Short name T423
Test name
Test status
Simulation time 13402565 ps
CPU time 0.74 seconds
Started Jul 23 06:48:10 PM PDT 24
Finished Jul 23 06:48:13 PM PDT 24
Peak memory 200452 kb
Host smart-96aef976-1b74-427a-a8fc-9c6a3698b6c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798656315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3798656315
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.1716867522
Short name T798
Test name
Test status
Simulation time 565716470 ps
CPU time 3.74 seconds
Started Jul 23 06:48:04 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 200440 kb
Host smart-68ecde92-d4a7-4d3a-bfb8-630eeb29630e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716867522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1716867522
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.2523478551
Short name T614
Test name
Test status
Simulation time 1829683109 ps
CPU time 9.38 seconds
Started Jul 23 06:47:51 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 200508 kb
Host smart-e4fb2663-32ac-43d0-b34b-4751eccd54eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523478551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.2523478551
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1256139376
Short name T783
Test name
Test status
Simulation time 17264186 ps
CPU time 0.77 seconds
Started Jul 23 06:47:59 PM PDT 24
Finished Jul 23 06:48:01 PM PDT 24
Peak memory 200448 kb
Host smart-dd556ebe-d547-4426-9dcd-fe4e38b94a6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256139376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.1256139376
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.4069515195
Short name T19
Test name
Test status
Simulation time 41447141 ps
CPU time 0.93 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:58 PM PDT 24
Peak memory 200452 kb
Host smart-24d9fba5-e4ee-462c-a243-747bb1e7910f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069515195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.4069515195
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1727394023
Short name T558
Test name
Test status
Simulation time 24170973 ps
CPU time 0.91 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:09 PM PDT 24
Peak memory 200448 kb
Host smart-549fd10c-2c7f-407c-a46a-0da97ef8322e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727394023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.1727394023
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.3394263532
Short name T253
Test name
Test status
Simulation time 28716692 ps
CPU time 0.85 seconds
Started Jul 23 06:48:08 PM PDT 24
Finished Jul 23 06:48:12 PM PDT 24
Peak memory 200444 kb
Host smart-b92c4e15-1291-422e-ba82-8b0516019535
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394263532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.3394263532
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.1941647490
Short name T498
Test name
Test status
Simulation time 227461220 ps
CPU time 1.54 seconds
Started Jul 23 06:47:55 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 200464 kb
Host smart-aad76d06-a18f-4988-9be4-aa6e71ad9620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941647490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.1941647490
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.123863713
Short name T251
Test name
Test status
Simulation time 29677313 ps
CPU time 0.86 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 200416 kb
Host smart-50f68acb-0be9-469f-9bfd-2b59aad4f370
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123863713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.123863713
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.445038206
Short name T364
Test name
Test status
Simulation time 3464730150 ps
CPU time 14.55 seconds
Started Jul 23 06:48:06 PM PDT 24
Finished Jul 23 06:48:23 PM PDT 24
Peak memory 200664 kb
Host smart-45c5195f-263b-4d83-bf25-e94e2ea37219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445038206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.445038206
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.665283958
Short name T567
Test name
Test status
Simulation time 23100867 ps
CPU time 0.78 seconds
Started Jul 23 06:47:56 PM PDT 24
Finished Jul 23 06:47:59 PM PDT 24
Peak memory 200492 kb
Host smart-aa7567ba-0364-4c3e-93cc-c33bf96712cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665283958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.665283958
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.1603839982
Short name T181
Test name
Test status
Simulation time 17948942 ps
CPU time 0.79 seconds
Started Jul 23 06:48:18 PM PDT 24
Finished Jul 23 06:48:23 PM PDT 24
Peak memory 200524 kb
Host smart-01a4dea9-2cda-4184-a2b9-a81f516f3282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603839982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.1603839982
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.141763639
Short name T287
Test name
Test status
Simulation time 60265020 ps
CPU time 0.94 seconds
Started Jul 23 06:48:08 PM PDT 24
Finished Jul 23 06:48:12 PM PDT 24
Peak memory 200468 kb
Host smart-709feb80-6deb-4015-8f11-707461ce3a1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141763639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.141763639
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.713913903
Short name T281
Test name
Test status
Simulation time 20032279 ps
CPU time 0.77 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:22 PM PDT 24
Peak memory 200612 kb
Host smart-aa3fd3ec-03b8-4f6c-bb43-e5fc4f17d561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713913903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.713913903
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.1019948345
Short name T649
Test name
Test status
Simulation time 34126505 ps
CPU time 0.9 seconds
Started Jul 23 06:48:04 PM PDT 24
Finished Jul 23 06:48:06 PM PDT 24
Peak memory 200460 kb
Host smart-356a9e4a-f3fd-445c-96c6-b0116e2e38bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019948345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.1019948345
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.3823744834
Short name T321
Test name
Test status
Simulation time 12229235 ps
CPU time 0.74 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:48:14 PM PDT 24
Peak memory 200692 kb
Host smart-ea5cea78-bc93-41c7-84c1-8eff8c89a244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823744834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.3823744834
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.198049669
Short name T755
Test name
Test status
Simulation time 477067090 ps
CPU time 2.77 seconds
Started Jul 23 06:47:58 PM PDT 24
Finished Jul 23 06:48:03 PM PDT 24
Peak memory 200332 kb
Host smart-94ff3f20-b01a-4646-ace5-24278f4accc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198049669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.198049669
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.1648567524
Short name T599
Test name
Test status
Simulation time 2024053429 ps
CPU time 6.61 seconds
Started Jul 23 06:48:19 PM PDT 24
Finished Jul 23 06:48:30 PM PDT 24
Peak memory 200440 kb
Host smart-1e15dba7-aaa3-44e9-a089-7a935dc6b082
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648567524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.1648567524
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.278815612
Short name T487
Test name
Test status
Simulation time 72404652 ps
CPU time 0.95 seconds
Started Jul 23 06:48:15 PM PDT 24
Finished Jul 23 06:48:19 PM PDT 24
Peak memory 200444 kb
Host smart-0492725f-9156-425c-aa36-5a991c138b9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278815612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_idle_intersig_mubi.278815612
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1161263743
Short name T721
Test name
Test status
Simulation time 41838505 ps
CPU time 0.95 seconds
Started Jul 23 06:48:00 PM PDT 24
Finished Jul 23 06:48:03 PM PDT 24
Peak memory 200480 kb
Host smart-ff72ae9c-0c79-4ea7-9b51-bc64bfc68cf2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161263743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.1161263743
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2455720053
Short name T764
Test name
Test status
Simulation time 44834018 ps
CPU time 0.88 seconds
Started Jul 23 06:48:12 PM PDT 24
Finished Jul 23 06:48:15 PM PDT 24
Peak memory 200460 kb
Host smart-8b0dbed5-845e-4a9f-9de8-fb63a9f238a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455720053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.2455720053
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.3535991385
Short name T760
Test name
Test status
Simulation time 14690902 ps
CPU time 0.74 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:17 PM PDT 24
Peak memory 200404 kb
Host smart-67473a44-57b6-4bb4-abce-c2fa3084f20b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535991385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3535991385
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.1869789462
Short name T510
Test name
Test status
Simulation time 1066779329 ps
CPU time 6.47 seconds
Started Jul 23 06:48:03 PM PDT 24
Finished Jul 23 06:48:12 PM PDT 24
Peak memory 200640 kb
Host smart-25552f18-2121-4893-aca5-d0ea2ee8865f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869789462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1869789462
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2325121180
Short name T231
Test name
Test status
Simulation time 57326744 ps
CPU time 0.94 seconds
Started Jul 23 06:48:05 PM PDT 24
Finished Jul 23 06:48:08 PM PDT 24
Peak memory 200444 kb
Host smart-d14c5dd9-bfe4-485b-9b95-e2d0b12b7fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325121180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2325121180
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.3977631311
Short name T157
Test name
Test status
Simulation time 6276616881 ps
CPU time 26.98 seconds
Started Jul 23 06:48:17 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 200728 kb
Host smart-c2582200-323a-4c15-be86-4abce4f47b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977631311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.3977631311
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.1632668226
Short name T296
Test name
Test status
Simulation time 28387409 ps
CPU time 0.9 seconds
Started Jul 23 06:48:01 PM PDT 24
Finished Jul 23 06:48:04 PM PDT 24
Peak memory 200432 kb
Host smart-106e0098-a06b-4da1-9570-4c985b39d5f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632668226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1632668226
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.180213357
Short name T546
Test name
Test status
Simulation time 18565122 ps
CPU time 0.79 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:48:27 PM PDT 24
Peak memory 200492 kb
Host smart-774ccfbb-ded7-48bd-a43c-1caf623c01fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180213357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkm
gr_alert_test.180213357
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1286036716
Short name T557
Test name
Test status
Simulation time 22333667 ps
CPU time 0.84 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 200456 kb
Host smart-0500efc8-730f-4c25-bc63-d1f28d0122ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286036716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1286036716
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.1412629819
Short name T294
Test name
Test status
Simulation time 37422502 ps
CPU time 0.75 seconds
Started Jul 23 06:48:07 PM PDT 24
Finished Jul 23 06:48:10 PM PDT 24
Peak memory 199588 kb
Host smart-3d5e1d74-44b8-4320-8b8d-e69c9b6de6ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412629819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.1412629819
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.1143211414
Short name T576
Test name
Test status
Simulation time 20076081 ps
CPU time 0.79 seconds
Started Jul 23 06:48:14 PM PDT 24
Finished Jul 23 06:48:18 PM PDT 24
Peak memory 200372 kb
Host smart-aa4fe336-e3df-4870-9dcb-3da7b7202715
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143211414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.1143211414
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.2333446571
Short name T259
Test name
Test status
Simulation time 32662532 ps
CPU time 0.82 seconds
Started Jul 23 06:48:13 PM PDT 24
Finished Jul 23 06:48:16 PM PDT 24
Peak memory 200444 kb
Host smart-0cbc4f6f-84e7-4c4f-9f0a-e989ad4ed0f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333446571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2333446571
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.579587490
Short name T2
Test name
Test status
Simulation time 2004735214 ps
CPU time 11.95 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:48:25 PM PDT 24
Peak memory 200652 kb
Host smart-b11b94ec-b786-4053-896d-ca764ecc196c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579587490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.579587490
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.405117840
Short name T699
Test name
Test status
Simulation time 2296636470 ps
CPU time 15.87 seconds
Started Jul 23 06:48:07 PM PDT 24
Finished Jul 23 06:48:26 PM PDT 24
Peak memory 200792 kb
Host smart-8017ba6f-8152-4a95-9d41-7c7cd8f77751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405117840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_ti
meout.405117840
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.875324102
Short name T212
Test name
Test status
Simulation time 128207591 ps
CPU time 1.19 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:48:14 PM PDT 24
Peak memory 200472 kb
Host smart-f0447376-3e13-4bf8-96c7-12bcf9feeb2c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875324102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_idle_intersig_mubi.875324102
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.500955541
Short name T162
Test name
Test status
Simulation time 59072194 ps
CPU time 0.89 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 200492 kb
Host smart-183320ff-48e0-411a-9d51-2159e3fa1763
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500955541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.clkmgr_lc_clk_byp_req_intersig_mubi.500955541
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.1918008507
Short name T740
Test name
Test status
Simulation time 25909150 ps
CPU time 0.77 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 200448 kb
Host smart-82585b9c-1d6e-4118-9a4a-1bc480b3c90e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918008507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.1918008507
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.3914474973
Short name T816
Test name
Test status
Simulation time 14007291 ps
CPU time 0.77 seconds
Started Jul 23 06:48:09 PM PDT 24
Finished Jul 23 06:48:12 PM PDT 24
Peak memory 200488 kb
Host smart-7c1891be-abc1-42bb-8467-48483b0b0fcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914474973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3914474973
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.329499001
Short name T119
Test name
Test status
Simulation time 898611555 ps
CPU time 3.4 seconds
Started Jul 23 06:48:21 PM PDT 24
Finished Jul 23 06:48:30 PM PDT 24
Peak memory 200636 kb
Host smart-2706f97e-854d-467f-b78f-041c0235a350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329499001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.329499001
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.474561702
Short name T813
Test name
Test status
Simulation time 15403713 ps
CPU time 0.89 seconds
Started Jul 23 06:48:11 PM PDT 24
Finished Jul 23 06:48:14 PM PDT 24
Peak memory 200428 kb
Host smart-300ed36c-63e8-4549-8a96-8c83f1046730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474561702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.474561702
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.3870437086
Short name T509
Test name
Test status
Simulation time 2463258476 ps
CPU time 9.89 seconds
Started Jul 23 06:48:16 PM PDT 24
Finished Jul 23 06:48:28 PM PDT 24
Peak memory 200712 kb
Host smart-9666dc9b-8dbd-4dc5-a679-4b260370a579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870437086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.3870437086
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.3885084161
Short name T397
Test name
Test status
Simulation time 43563855 ps
CPU time 0.8 seconds
Started Jul 23 06:48:13 PM PDT 24
Finished Jul 23 06:48:16 PM PDT 24
Peak memory 200460 kb
Host smart-50ceffbe-b69e-41ec-84d4-d636a1a8b5df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885084161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3885084161
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.2667532731
Short name T506
Test name
Test status
Simulation time 143696005 ps
CPU time 1.22 seconds
Started Jul 23 06:44:23 PM PDT 24
Finished Jul 23 06:44:29 PM PDT 24
Peak memory 200544 kb
Host smart-1876576c-9bb3-4baa-a728-02fb350e2b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667532731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.2667532731
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3486215646
Short name T341
Test name
Test status
Simulation time 149281864 ps
CPU time 1.15 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:30 PM PDT 24
Peak memory 200484 kb
Host smart-da7573e1-893f-4a00-80e9-68718c62f792
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486215646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.3486215646
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.615780892
Short name T28
Test name
Test status
Simulation time 21657954 ps
CPU time 0.7 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 200348 kb
Host smart-a49f3a79-fb63-46d5-9e59-0201fa134c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615780892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.615780892
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.3059291600
Short name T235
Test name
Test status
Simulation time 42911563 ps
CPU time 0.84 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:31 PM PDT 24
Peak memory 200440 kb
Host smart-aaa4eab0-1019-41e7-90bf-6af609cfbc04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059291600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.3059291600
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.2368931202
Short name T654
Test name
Test status
Simulation time 88420541 ps
CPU time 1 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:31 PM PDT 24
Peak memory 200448 kb
Host smart-692cbe53-563f-470f-b06e-4e1817c03f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368931202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2368931202
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.1492720084
Short name T424
Test name
Test status
Simulation time 2116315309 ps
CPU time 15.88 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:57 PM PDT 24
Peak memory 200604 kb
Host smart-d50c345e-63d3-48cf-b4c3-b3db0e32cafa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492720084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1492720084
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.842844741
Short name T32
Test name
Test status
Simulation time 2414721335 ps
CPU time 17.25 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:59 PM PDT 24
Peak memory 200700 kb
Host smart-9df3ba98-96a3-480c-b6e6-ce7bd1caddf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842844741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_tim
eout.842844741
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.2655807537
Short name T490
Test name
Test status
Simulation time 60849852 ps
CPU time 1.05 seconds
Started Jul 23 06:44:19 PM PDT 24
Finished Jul 23 06:44:26 PM PDT 24
Peak memory 200460 kb
Host smart-3f607ba8-c1c9-4366-9218-e57cbcf92f4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655807537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.2655807537
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.820280264
Short name T202
Test name
Test status
Simulation time 43026339 ps
CPU time 0.88 seconds
Started Jul 23 06:44:23 PM PDT 24
Finished Jul 23 06:44:29 PM PDT 24
Peak memory 200492 kb
Host smart-1f59b67f-5b0e-4971-a373-c233b45fcdb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820280264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_clk_byp_req_intersig_mubi.820280264
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.1493815676
Short name T789
Test name
Test status
Simulation time 30536396 ps
CPU time 0.82 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:29 PM PDT 24
Peak memory 200432 kb
Host smart-3870096e-9c29-47d8-b83f-5da6f3cc38b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493815676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.1493815676
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3202519984
Short name T594
Test name
Test status
Simulation time 30290019 ps
CPU time 0.73 seconds
Started Jul 23 06:44:34 PM PDT 24
Finished Jul 23 06:44:40 PM PDT 24
Peak memory 200400 kb
Host smart-b081451c-c7e0-4207-a932-5a524879d8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202519984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3202519984
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.2889131476
Short name T398
Test name
Test status
Simulation time 1112142773 ps
CPU time 5.34 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:34 PM PDT 24
Peak memory 200632 kb
Host smart-4bae4d9e-a2e4-40a8-bd7e-b2ce5f527562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889131476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2889131476
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.416007584
Short name T538
Test name
Test status
Simulation time 21629308 ps
CPU time 0.89 seconds
Started Jul 23 06:44:22 PM PDT 24
Finished Jul 23 06:44:28 PM PDT 24
Peak memory 200352 kb
Host smart-e30c3adf-600c-4f4a-82af-5c16f8951c86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416007584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.416007584
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.4209136942
Short name T779
Test name
Test status
Simulation time 4210214178 ps
CPU time 18.81 seconds
Started Jul 23 06:44:28 PM PDT 24
Finished Jul 23 06:44:51 PM PDT 24
Peak memory 200724 kb
Host smart-ab27d0ec-bfd8-4722-b2e2-1b122c2b8da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209136942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.4209136942
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.1937080290
Short name T668
Test name
Test status
Simulation time 105767086253 ps
CPU time 1115.54 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 07:03:08 PM PDT 24
Peak memory 217252 kb
Host smart-cddcea99-766b-4acd-b4e3-f4e977caa550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1937080290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1937080290
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.4168626308
Short name T597
Test name
Test status
Simulation time 105701949 ps
CPU time 1.07 seconds
Started Jul 23 06:44:34 PM PDT 24
Finished Jul 23 06:44:41 PM PDT 24
Peak memory 200428 kb
Host smart-e1ffbff1-ceeb-4925-afe8-5c479ebec7d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168626308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.4168626308
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.2745448261
Short name T332
Test name
Test status
Simulation time 30734310 ps
CPU time 0.76 seconds
Started Jul 23 06:44:32 PM PDT 24
Finished Jul 23 06:44:38 PM PDT 24
Peak memory 200480 kb
Host smart-3f7f877c-ebe8-4b00-a8b8-6d0ed03d9fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745448261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.2745448261
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.550699409
Short name T695
Test name
Test status
Simulation time 58489244 ps
CPU time 0.96 seconds
Started Jul 23 06:44:30 PM PDT 24
Finished Jul 23 06:44:36 PM PDT 24
Peak memory 200460 kb
Host smart-859892bc-0610-4e9d-94d3-8f76bad84c0c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550699409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.550699409
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.3530252262
Short name T338
Test name
Test status
Simulation time 15984880 ps
CPU time 0.7 seconds
Started Jul 23 06:44:26 PM PDT 24
Finished Jul 23 06:44:32 PM PDT 24
Peak memory 199520 kb
Host smart-592a898c-2733-42d3-8dad-bb32c1adea34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530252262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3530252262
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.1582583989
Short name T466
Test name
Test status
Simulation time 69316891 ps
CPU time 1.06 seconds
Started Jul 23 06:44:36 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 200452 kb
Host smart-8672d095-3a02-42a3-a07d-ebfe83a9067c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582583989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.1582583989
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.3034567010
Short name T8
Test name
Test status
Simulation time 57627465 ps
CPU time 0.9 seconds
Started Jul 23 06:44:29 PM PDT 24
Finished Jul 23 06:44:34 PM PDT 24
Peak memory 200420 kb
Host smart-39e73769-6c84-47ce-b0dd-9682bd0b0728
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034567010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3034567010
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.3891438813
Short name T13
Test name
Test status
Simulation time 456598419 ps
CPU time 2.77 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:32 PM PDT 24
Peak memory 200472 kb
Host smart-65548754-bab9-4285-aad3-46c356ec3d8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891438813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3891438813
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.728330732
Short name T337
Test name
Test status
Simulation time 616331125 ps
CPU time 4.71 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:36 PM PDT 24
Peak memory 200476 kb
Host smart-951d384c-9992-4ddb-8e12-51f48f616f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728330732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_tim
eout.728330732
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.818459323
Short name T645
Test name
Test status
Simulation time 30542915 ps
CPU time 0.91 seconds
Started Jul 23 06:44:26 PM PDT 24
Finished Jul 23 06:44:32 PM PDT 24
Peak memory 200460 kb
Host smart-d5056717-26f2-451d-8b01-7832f7698db7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818459323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.clkmgr_idle_intersig_mubi.818459323
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.578020024
Short name T204
Test name
Test status
Simulation time 40476074 ps
CPU time 0.84 seconds
Started Jul 23 06:44:32 PM PDT 24
Finished Jul 23 06:44:38 PM PDT 24
Peak memory 200444 kb
Host smart-11ed034c-2432-4e35-8f4e-c3379e14d6c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578020024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_clk_byp_req_intersig_mubi.578020024
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.793625928
Short name T315
Test name
Test status
Simulation time 88634574 ps
CPU time 0.94 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:38 PM PDT 24
Peak memory 200448 kb
Host smart-93d468d7-2521-41cc-a1cc-9a156c0c97b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793625928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_ctrl_intersig_mubi.793625928
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.1984007482
Short name T430
Test name
Test status
Simulation time 21053534 ps
CPU time 0.8 seconds
Started Jul 23 06:44:27 PM PDT 24
Finished Jul 23 06:44:32 PM PDT 24
Peak memory 200432 kb
Host smart-05ad7a4f-f2ec-406c-81b7-e1685e315edf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984007482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1984007482
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.2607943689
Short name T448
Test name
Test status
Simulation time 733198090 ps
CPU time 2.78 seconds
Started Jul 23 06:44:32 PM PDT 24
Finished Jul 23 06:44:40 PM PDT 24
Peak memory 200588 kb
Host smart-fdc9bbaf-93c8-4359-b2e2-46f972b14fef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607943689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2607943689
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1237698228
Short name T267
Test name
Test status
Simulation time 58963581 ps
CPU time 1.07 seconds
Started Jul 23 06:44:24 PM PDT 24
Finished Jul 23 06:44:30 PM PDT 24
Peak memory 200640 kb
Host smart-d2af10ad-b521-44a0-81aa-af2edc9ee77f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237698228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1237698228
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.324224733
Short name T489
Test name
Test status
Simulation time 5749174354 ps
CPU time 45.82 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:45:30 PM PDT 24
Peak memory 200748 kb
Host smart-28a1b61e-8d6e-4598-8fcc-252330f28218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324224733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.324224733
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.3473144033
Short name T754
Test name
Test status
Simulation time 30257679 ps
CPU time 0.87 seconds
Started Jul 23 06:44:25 PM PDT 24
Finished Jul 23 06:44:31 PM PDT 24
Peak memory 200352 kb
Host smart-41106ce0-a883-4dec-aeb0-47316284fd1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473144033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3473144033
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.1558084066
Short name T329
Test name
Test status
Simulation time 41449722 ps
CPU time 0.87 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:45 PM PDT 24
Peak memory 200516 kb
Host smart-ae22532a-f0a1-4d9f-a3bf-8e2dc8eddb45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558084066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.1558084066
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1570358662
Short name T707
Test name
Test status
Simulation time 16587873 ps
CPU time 0.77 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 200444 kb
Host smart-3465fe2e-edeb-4154-86e2-3181d8cde052
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570358662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1570358662
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.3194643202
Short name T723
Test name
Test status
Simulation time 27378937 ps
CPU time 0.74 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:38 PM PDT 24
Peak memory 199640 kb
Host smart-a2581e74-c7bb-436c-861f-a1a7f3a0dc22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194643202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.3194643202
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3921573110
Short name T605
Test name
Test status
Simulation time 20527478 ps
CPU time 0.77 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 200456 kb
Host smart-7379a29b-3436-4ae2-8735-4d7f55532457
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921573110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.3921573110
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.1103708402
Short name T737
Test name
Test status
Simulation time 48757050 ps
CPU time 0.87 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 200464 kb
Host smart-1942e8c9-a0cf-4155-b489-d726a9a050dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103708402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.1103708402
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.3751316700
Short name T584
Test name
Test status
Simulation time 1520101490 ps
CPU time 5.95 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:44 PM PDT 24
Peak memory 200444 kb
Host smart-a82c44b8-6af4-495a-bf20-a06d31d86c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751316700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3751316700
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.2965831351
Short name T295
Test name
Test status
Simulation time 254161986 ps
CPU time 2.34 seconds
Started Jul 23 06:44:32 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 200484 kb
Host smart-948874eb-1858-433b-bf23-542a674e63f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965831351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.2965831351
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3242509955
Short name T793
Test name
Test status
Simulation time 63669259 ps
CPU time 1.16 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 200468 kb
Host smart-e5cb30e3-ec67-42b0-9153-e653fa2bc0ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242509955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.3242509955
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.2390591787
Short name T535
Test name
Test status
Simulation time 176908539 ps
CPU time 1.27 seconds
Started Jul 23 06:44:36 PM PDT 24
Finished Jul 23 06:44:43 PM PDT 24
Peak memory 200440 kb
Host smart-8c7b576f-9285-46b7-8a43-0dad17e9ea7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390591787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.2390591787
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3750650258
Short name T366
Test name
Test status
Simulation time 78122023 ps
CPU time 1.04 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:42 PM PDT 24
Peak memory 200444 kb
Host smart-16f8e63d-0d99-485e-b3ed-c1079904e893
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750650258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3750650258
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.2532031761
Short name T196
Test name
Test status
Simulation time 30075306 ps
CPU time 0.76 seconds
Started Jul 23 06:44:35 PM PDT 24
Finished Jul 23 06:44:41 PM PDT 24
Peak memory 200444 kb
Host smart-974643ca-9d51-411f-9c0a-a1a6c092fa97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532031761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2532031761
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.2703732981
Short name T704
Test name
Test status
Simulation time 1435191845 ps
CPU time 5.11 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:50 PM PDT 24
Peak memory 200572 kb
Host smart-52100d70-3d5f-4db0-b290-ab85423e444f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703732981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.2703732981
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.2522991882
Short name T277
Test name
Test status
Simulation time 15553807 ps
CPU time 0.8 seconds
Started Jul 23 06:44:31 PM PDT 24
Finished Jul 23 06:44:36 PM PDT 24
Peak memory 200428 kb
Host smart-921a464a-5767-4a0e-9311-1e9448f29259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522991882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.2522991882
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.2997583278
Short name T456
Test name
Test status
Simulation time 6449768178 ps
CPU time 47.89 seconds
Started Jul 23 06:44:37 PM PDT 24
Finished Jul 23 06:45:31 PM PDT 24
Peak memory 200752 kb
Host smart-03459bfc-d3ad-422e-a886-6e7d34aff8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997583278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.2997583278
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.1524965023
Short name T733
Test name
Test status
Simulation time 35645677 ps
CPU time 0.87 seconds
Started Jul 23 06:44:33 PM PDT 24
Finished Jul 23 06:44:39 PM PDT 24
Peak memory 200492 kb
Host smart-25d5f2e2-7874-4a56-8aa3-5f997f05f5e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524965023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1524965023
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.539299652
Short name T550
Test name
Test status
Simulation time 70252772 ps
CPU time 0.98 seconds
Started Jul 23 06:44:41 PM PDT 24
Finished Jul 23 06:44:48 PM PDT 24
Peak memory 200504 kb
Host smart-431486b2-2355-4658-ae42-fe3b518c85a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539299652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg
r_alert_test.539299652
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3767098277
Short name T109
Test name
Test status
Simulation time 14155627 ps
CPU time 0.75 seconds
Started Jul 23 06:44:43 PM PDT 24
Finished Jul 23 06:44:50 PM PDT 24
Peak memory 200468 kb
Host smart-581bb4b5-4524-4d3b-9d6f-8f0ea207974a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767098277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.3767098277
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.1612005239
Short name T306
Test name
Test status
Simulation time 25688425 ps
CPU time 0.77 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:44 PM PDT 24
Peak memory 199680 kb
Host smart-ebcdf53f-bb04-4765-b6ce-373903afb058
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612005239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1612005239
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.1347611062
Short name T552
Test name
Test status
Simulation time 17733982 ps
CPU time 0.81 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 200448 kb
Host smart-5a04ce5f-9cf0-4bb7-919c-e1ddb46eaf56
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347611062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.1347611062
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.3647637426
Short name T229
Test name
Test status
Simulation time 35154808 ps
CPU time 0.9 seconds
Started Jul 23 06:44:37 PM PDT 24
Finished Jul 23 06:44:44 PM PDT 24
Peak memory 200472 kb
Host smart-fb1baea0-a8e6-457a-a000-8f48c5970ad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647637426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3647637426
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.632301317
Short name T261
Test name
Test status
Simulation time 2594524939 ps
CPU time 11.6 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:55 PM PDT 24
Peak memory 200712 kb
Host smart-2ce7c07d-46c1-4078-b980-5b554f6c5e84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632301317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.632301317
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.3163915300
Short name T794
Test name
Test status
Simulation time 1936075303 ps
CPU time 14.55 seconds
Started Jul 23 06:44:43 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 200508 kb
Host smart-15a4a502-c343-4645-895d-53cbdfcfdc9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163915300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.3163915300
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.2491432945
Short name T414
Test name
Test status
Simulation time 48200012 ps
CPU time 0.86 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:46 PM PDT 24
Peak memory 200408 kb
Host smart-a16ae521-a3dc-47f0-a02f-b6b86540d5d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491432945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.2491432945
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1774318023
Short name T516
Test name
Test status
Simulation time 17342923 ps
CPU time 0.69 seconds
Started Jul 23 06:44:41 PM PDT 24
Finished Jul 23 06:44:47 PM PDT 24
Peak memory 200440 kb
Host smart-480a7904-d86f-4ea9-ad0b-e5bd25fb460b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774318023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1774318023
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1282848466
Short name T280
Test name
Test status
Simulation time 77497171 ps
CPU time 1.04 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:45 PM PDT 24
Peak memory 200456 kb
Host smart-16cc48fc-907c-46b9-b97c-bda5a51443bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282848466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.1282848466
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.1132590096
Short name T521
Test name
Test status
Simulation time 12976120 ps
CPU time 0.71 seconds
Started Jul 23 06:44:44 PM PDT 24
Finished Jul 23 06:44:50 PM PDT 24
Peak memory 200424 kb
Host smart-55223720-082f-47a6-8942-a9f666418f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132590096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.1132590096
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.2453847564
Short name T625
Test name
Test status
Simulation time 526833206 ps
CPU time 2.66 seconds
Started Jul 23 06:44:39 PM PDT 24
Finished Jul 23 06:44:47 PM PDT 24
Peak memory 200464 kb
Host smart-8854b956-275e-4e44-b045-45b318b8a78e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453847564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2453847564
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.902524831
Short name T233
Test name
Test status
Simulation time 24701047 ps
CPU time 0.86 seconds
Started Jul 23 06:44:44 PM PDT 24
Finished Jul 23 06:44:51 PM PDT 24
Peak memory 200404 kb
Host smart-a20ecae6-91b1-48ad-935b-109ae442fdb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902524831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.902524831
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.2509181167
Short name T14
Test name
Test status
Simulation time 12843388498 ps
CPU time 90.42 seconds
Started Jul 23 06:44:42 PM PDT 24
Finished Jul 23 06:46:18 PM PDT 24
Peak memory 200772 kb
Host smart-f8293132-c80d-4b25-ba84-f29674ebf2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509181167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.2509181167
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.2061514197
Short name T247
Test name
Test status
Simulation time 49725916 ps
CPU time 0.85 seconds
Started Jul 23 06:44:38 PM PDT 24
Finished Jul 23 06:44:45 PM PDT 24
Peak memory 200452 kb
Host smart-4bf2717f-2fb1-4692-9ee7-34d405fd40ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061514197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2061514197
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.178465463
Short name T682
Test name
Test status
Simulation time 75644226 ps
CPU time 0.97 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:52 PM PDT 24
Peak memory 200552 kb
Host smart-57e7ddc9-af11-4946-b254-c145d762d348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178465463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmg
r_alert_test.178465463
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3808481272
Short name T507
Test name
Test status
Simulation time 19396832 ps
CPU time 0.86 seconds
Started Jul 23 06:44:48 PM PDT 24
Finished Jul 23 06:44:55 PM PDT 24
Peak memory 200472 kb
Host smart-0339ebb4-4af8-4c39-8664-b17b45a58ecb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808481272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.3808481272
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.1326736002
Short name T697
Test name
Test status
Simulation time 15269959 ps
CPU time 0.75 seconds
Started Jul 23 06:44:45 PM PDT 24
Finished Jul 23 06:44:51 PM PDT 24
Peak memory 199652 kb
Host smart-7e8a4fe2-6ee7-406b-bc1f-49707e1cc9d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326736002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1326736002
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.4188792315
Short name T413
Test name
Test status
Simulation time 16138915 ps
CPU time 0.89 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 200452 kb
Host smart-1a027021-9408-4ae7-9b61-5eb85de79bb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188792315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.4188792315
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1344592383
Short name T198
Test name
Test status
Simulation time 230147043 ps
CPU time 1.5 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:55 PM PDT 24
Peak memory 200460 kb
Host smart-d882776c-8edd-4e39-b4fb-9afaf2850267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344592383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1344592383
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.3820341479
Short name T748
Test name
Test status
Simulation time 1280814787 ps
CPU time 9.34 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:45:00 PM PDT 24
Peak memory 200480 kb
Host smart-9dc529fe-5129-45c0-bfe1-aa3173556c00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820341479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.3820341479
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.1906148806
Short name T227
Test name
Test status
Simulation time 761919271 ps
CPU time 3.45 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:55 PM PDT 24
Peak memory 200524 kb
Host smart-18bf7ecf-8efb-481c-b2bd-e3d92a6721eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906148806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.1906148806
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.3911504565
Short name T823
Test name
Test status
Simulation time 122322057 ps
CPU time 1.35 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:54 PM PDT 24
Peak memory 200432 kb
Host smart-5649df4f-b9d6-468f-81bb-a6069354d9d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911504565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.3911504565
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2632982030
Short name T222
Test name
Test status
Simulation time 59754445 ps
CPU time 0.98 seconds
Started Jul 23 06:44:49 PM PDT 24
Finished Jul 23 06:44:56 PM PDT 24
Peak memory 200440 kb
Host smart-d21cdfa0-c612-4d16-a254-21ee4db87595
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632982030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.2632982030
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.2144527008
Short name T522
Test name
Test status
Simulation time 19680061 ps
CPU time 0.79 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:54 PM PDT 24
Peak memory 200440 kb
Host smart-018b4629-11f7-429b-8e90-ab5efa1c9cad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144527008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.2144527008
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.3884275882
Short name T501
Test name
Test status
Simulation time 21942559 ps
CPU time 0.83 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:44:53 PM PDT 24
Peak memory 200468 kb
Host smart-67f9715e-5a2e-4d3e-8a8b-5bd49abf7b1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884275882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.3884275882
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.2329461842
Short name T393
Test name
Test status
Simulation time 2366547948 ps
CPU time 7.87 seconds
Started Jul 23 06:44:49 PM PDT 24
Finished Jul 23 06:45:04 PM PDT 24
Peak memory 200608 kb
Host smart-6692dfaf-8f3b-47d2-921b-f8641915b293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329461842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.2329461842
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.1689673667
Short name T152
Test name
Test status
Simulation time 25690074 ps
CPU time 0.92 seconds
Started Jul 23 06:44:37 PM PDT 24
Finished Jul 23 06:44:44 PM PDT 24
Peak memory 200428 kb
Host smart-7d582b07-dbae-41ee-b904-e846464c8c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689673667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1689673667
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.1390259714
Short name T786
Test name
Test status
Simulation time 6102228978 ps
CPU time 29.3 seconds
Started Jul 23 06:44:46 PM PDT 24
Finished Jul 23 06:45:21 PM PDT 24
Peak memory 200732 kb
Host smart-f7f871f1-a98a-49a8-a8e8-51074ab6c691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390259714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.1390259714
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1624785347
Short name T698
Test name
Test status
Simulation time 39432187909 ps
CPU time 417.83 seconds
Started Jul 23 06:44:49 PM PDT 24
Finished Jul 23 06:51:53 PM PDT 24
Peak memory 217220 kb
Host smart-25ebee45-2227-46a9-a451-0707091b9271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1624785347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.1624785347
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.1752351986
Short name T569
Test name
Test status
Simulation time 67665166 ps
CPU time 1.06 seconds
Started Jul 23 06:44:47 PM PDT 24
Finished Jul 23 06:44:55 PM PDT 24
Peak memory 200332 kb
Host smart-34b5d10e-f969-4c00-ba9f-a187862c5292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752351986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1752351986
Directory /workspace/9.clkmgr_trans/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%