Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 138248922 1 T7 2598 T8 2808 T9 2724
auto[1] 252152 1 T7 602 T8 216 T9 118


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 138205852 1 T7 2756 T8 2860 T9 2734
auto[1] 295222 1 T7 444 T8 164 T9 108


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 138184096 1 T7 2456 T8 2836 T9 2546
auto[1] 316978 1 T7 744 T8 188 T9 296


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 134757608 1 T7 952 T8 3024 T9 48
auto[1] 3743466 1 T7 2248 T9 2794 T26 2156


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 85586050 1 T7 3030 T8 748 T9 2816
auto[1] 52915024 1 T7 170 T8 2276 T9 26


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 83310856 1 T7 492 T8 556 T9 22
auto[0] auto[0] auto[0] auto[0] auto[1] 51182134 1 T7 20 T8 2128 T9 26
auto[0] auto[0] auto[0] auto[1] auto[0] 18314 1 T7 66 T8 108 T6 20
auto[0] auto[0] auto[0] auto[1] auto[1] 4332 1 T8 44 T27 6 T1 128
auto[0] auto[0] auto[1] auto[0] auto[0] 1859272 1 T7 1706 T9 2492 T26 310
auto[0] auto[0] auto[1] auto[0] auto[1] 1667282 1 T7 124 T26 1632 T32 80
auto[0] auto[0] auto[1] auto[1] auto[0] 31684 1 T7 2 T9 6 T6 48
auto[0] auto[0] auto[1] auto[1] auto[1] 6248 1 T26 10 T114 6 T1 170
auto[0] auto[1] auto[0] auto[0] auto[0] 73388 1 T27 18 T32 40 T4 8970
auto[0] auto[1] auto[0] auto[0] auto[1] 768 1 T38 12 T1 98 T2 34
auto[0] auto[1] auto[0] auto[1] auto[0] 7298 1 T27 60 T1 170 T18 92
auto[0] auto[1] auto[0] auto[1] auto[1] 1598 1 T38 54 T1 194 T186 60
auto[0] auto[1] auto[1] auto[0] auto[0] 4912 1 T7 46 T6 2 T32 26
auto[0] auto[1] auto[1] auto[0] auto[1] 1568 1 T38 24 T1 56 T21 32
auto[0] auto[1] auto[1] auto[1] auto[0] 11238 1 T6 58 T114 66 T1 84
auto[0] auto[1] auto[1] auto[1] auto[1] 3204 1 T38 46 T1 116 T183 40
auto[1] auto[0] auto[0] auto[0] auto[0] 33662 1 T7 40 T6 2 T27 82
auto[1] auto[0] auto[0] auto[0] auto[1] 2636 1 T8 24 T27 24 T114 60
auto[1] auto[0] auto[0] auto[1] auto[0] 20342 1 T7 122 T6 48 T27 176
auto[1] auto[0] auto[0] auto[1] auto[1] 4920 1 T1 82 T181 48 T150 90
auto[1] auto[0] auto[1] auto[0] auto[0] 17322 1 T7 18 T9 76 T6 46
auto[1] auto[0] auto[1] auto[0] auto[1] 4394 1 T7 26 T26 16 T38 8
auto[1] auto[0] auto[1] auto[1] auto[0] 35084 1 T7 140 T9 112 T6 104
auto[1] auto[0] auto[1] auto[1] auto[1] 7370 1 T26 46 T114 80 T1 264
auto[1] auto[1] auto[0] auto[0] auto[0] 55956 1 T7 70 T8 84 T26 16
auto[1] auto[1] auto[0] auto[0] auto[1] 3460 1 T8 16 T27 34 T38 8
auto[1] auto[1] auto[0] auto[1] auto[0] 30392 1 T7 142 T26 70 T27 412
auto[1] auto[1] auto[0] auto[1] auto[1] 7552 1 T8 64 T27 122 T1 54
auto[1] auto[1] auto[1] auto[0] auto[0] 25332 1 T7 56 T9 108 T26 66
auto[1] auto[1] auto[1] auto[0] auto[1] 5980 1 T32 8 T38 50 T1 174
auto[1] auto[1] auto[1] auto[1] auto[0] 50998 1 T7 130 T26 76 T6 62
auto[1] auto[1] auto[1] auto[1] auto[1] 11578 1 T38 100 T1 234 T2 278

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