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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 981
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T807 /workspace/coverage/default/8.clkmgr_peri.215330348 Jul 25 07:14:35 PM PDT 24 Jul 25 07:14:36 PM PDT 24 122154212 ps
T808 /workspace/coverage/default/20.clkmgr_frequency_timeout.2724703639 Jul 25 07:15:11 PM PDT 24 Jul 25 07:15:17 PM PDT 24 1348238317 ps
T809 /workspace/coverage/default/1.clkmgr_regwen.3956497272 Jul 25 07:14:12 PM PDT 24 Jul 25 07:14:18 PM PDT 24 1707306311 ps
T810 /workspace/coverage/default/47.clkmgr_peri.198209317 Jul 25 07:16:24 PM PDT 24 Jul 25 07:16:25 PM PDT 24 18952641 ps
T811 /workspace/coverage/default/27.clkmgr_frequency.1325858745 Jul 25 07:15:28 PM PDT 24 Jul 25 07:15:42 PM PDT 24 2483316893 ps
T812 /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.443373273 Jul 25 07:15:53 PM PDT 24 Jul 25 07:15:54 PM PDT 24 50877080 ps
T813 /workspace/coverage/default/36.clkmgr_clk_status.3942136489 Jul 25 07:15:53 PM PDT 24 Jul 25 07:15:55 PM PDT 24 67295447 ps
T814 /workspace/coverage/default/38.clkmgr_frequency.595847566 Jul 25 07:15:56 PM PDT 24 Jul 25 07:15:59 PM PDT 24 586846773 ps
T815 /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3623267537 Jul 25 07:14:36 PM PDT 24 Jul 25 07:14:37 PM PDT 24 57058361 ps
T816 /workspace/coverage/default/26.clkmgr_clk_status.25052803 Jul 25 07:15:27 PM PDT 24 Jul 25 07:15:28 PM PDT 24 18220398 ps
T817 /workspace/coverage/default/45.clkmgr_trans.3050870080 Jul 25 07:16:11 PM PDT 24 Jul 25 07:16:12 PM PDT 24 27068484 ps
T818 /workspace/coverage/default/6.clkmgr_frequency_timeout.1291666833 Jul 25 07:14:37 PM PDT 24 Jul 25 07:14:39 PM PDT 24 140560972 ps
T819 /workspace/coverage/default/0.clkmgr_extclk.3397542032 Jul 25 07:14:17 PM PDT 24 Jul 25 07:14:19 PM PDT 24 318332753 ps
T820 /workspace/coverage/default/25.clkmgr_div_intersig_mubi.3125193851 Jul 25 07:15:21 PM PDT 24 Jul 25 07:15:22 PM PDT 24 40353913 ps
T821 /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.368716697 Jul 25 07:15:46 PM PDT 24 Jul 25 07:15:47 PM PDT 24 47777150 ps
T822 /workspace/coverage/default/32.clkmgr_extclk.1326428014 Jul 25 07:15:38 PM PDT 24 Jul 25 07:15:40 PM PDT 24 81721685 ps
T823 /workspace/coverage/default/5.clkmgr_stress_all.1663080989 Jul 25 07:14:26 PM PDT 24 Jul 25 07:15:10 PM PDT 24 5691468055 ps
T824 /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1808284061 Jul 25 07:16:25 PM PDT 24 Jul 25 07:16:26 PM PDT 24 31363009 ps
T825 /workspace/coverage/default/20.clkmgr_div_intersig_mubi.680690033 Jul 25 07:15:12 PM PDT 24 Jul 25 07:15:13 PM PDT 24 22241984 ps
T826 /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1548138244 Jul 25 07:15:40 PM PDT 24 Jul 25 07:15:41 PM PDT 24 22770127 ps
T827 /workspace/coverage/default/48.clkmgr_div_intersig_mubi.3113071520 Jul 25 07:16:23 PM PDT 24 Jul 25 07:16:24 PM PDT 24 116671507 ps
T828 /workspace/coverage/default/48.clkmgr_frequency.1240476005 Jul 25 07:16:26 PM PDT 24 Jul 25 07:16:36 PM PDT 24 1764982049 ps
T829 /workspace/coverage/default/29.clkmgr_clk_status.4163032454 Jul 25 07:15:38 PM PDT 24 Jul 25 07:15:39 PM PDT 24 21643820 ps
T830 /workspace/coverage/default/3.clkmgr_alert_test.2636670534 Jul 25 07:14:26 PM PDT 24 Jul 25 07:14:27 PM PDT 24 49111709 ps
T162 /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.639632630 Jul 25 07:16:09 PM PDT 24 Jul 25 07:21:24 PM PDT 24 36739231226 ps
T831 /workspace/coverage/default/2.clkmgr_trans.603521878 Jul 25 07:14:20 PM PDT 24 Jul 25 07:14:22 PM PDT 24 360658809 ps
T832 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.850724616 Jul 25 07:09:36 PM PDT 24 Jul 25 07:09:37 PM PDT 24 33453013 ps
T102 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1215521377 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:54 PM PDT 24 21558840 ps
T833 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2418126038 Jul 25 07:09:29 PM PDT 24 Jul 25 07:09:30 PM PDT 24 14215612 ps
T63 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3769839269 Jul 25 07:08:57 PM PDT 24 Jul 25 07:08:58 PM PDT 24 91607901 ps
T64 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3750130267 Jul 25 07:09:12 PM PDT 24 Jul 25 07:09:14 PM PDT 24 126085459 ps
T834 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.276133138 Jul 25 07:09:33 PM PDT 24 Jul 25 07:09:34 PM PDT 24 11744375 ps
T103 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.4113645905 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:54 PM PDT 24 108928415 ps
T104 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1626942090 Jul 25 07:09:01 PM PDT 24 Jul 25 07:09:02 PM PDT 24 109983125 ps
T65 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1643249068 Jul 25 07:09:01 PM PDT 24 Jul 25 07:09:02 PM PDT 24 93196141 ps
T86 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1613892649 Jul 25 07:08:58 PM PDT 24 Jul 25 07:08:59 PM PDT 24 42576712 ps
T835 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1905250304 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:57 PM PDT 24 24165288 ps
T66 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3273873255 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:03 PM PDT 24 178813029 ps
T67 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3000334833 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:57 PM PDT 24 159605671 ps
T87 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2866462953 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:54 PM PDT 24 59728136 ps
T836 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1000110724 Jul 25 07:09:15 PM PDT 24 Jul 25 07:09:17 PM PDT 24 28383674 ps
T88 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.94500405 Jul 25 07:08:49 PM PDT 24 Jul 25 07:08:51 PM PDT 24 58162339 ps
T96 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2223496512 Jul 25 07:09:13 PM PDT 24 Jul 25 07:09:20 PM PDT 24 120693299 ps
T70 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2716745325 Jul 25 07:09:12 PM PDT 24 Jul 25 07:09:14 PM PDT 24 209784251 ps
T89 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2085178546 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:52 PM PDT 24 18685826 ps
T837 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2589186795 Jul 25 07:09:40 PM PDT 24 Jul 25 07:09:41 PM PDT 24 21641468 ps
T97 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.615489067 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:56 PM PDT 24 593781925 ps
T163 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2811623508 Jul 25 07:08:57 PM PDT 24 Jul 25 07:08:58 PM PDT 24 23144748 ps
T838 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.4224866339 Jul 25 07:09:40 PM PDT 24 Jul 25 07:09:41 PM PDT 24 11255875 ps
T839 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2207432234 Jul 25 07:09:01 PM PDT 24 Jul 25 07:09:02 PM PDT 24 44410685 ps
T840 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3240420015 Jul 25 07:08:56 PM PDT 24 Jul 25 07:09:01 PM PDT 24 603156221 ps
T841 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.274586058 Jul 25 07:09:02 PM PDT 24 Jul 25 07:09:03 PM PDT 24 12368511 ps
T842 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1601077117 Jul 25 07:09:16 PM PDT 24 Jul 25 07:09:18 PM PDT 24 214604151 ps
T90 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1580889042 Jul 25 07:08:59 PM PDT 24 Jul 25 07:09:00 PM PDT 24 28411405 ps
T98 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3243612064 Jul 25 07:08:54 PM PDT 24 Jul 25 07:08:56 PM PDT 24 57680731 ps
T68 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3288277204 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:54 PM PDT 24 194800044 ps
T69 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1990756833 Jul 25 07:09:30 PM PDT 24 Jul 25 07:09:32 PM PDT 24 157532250 ps
T843 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3552029584 Jul 25 07:08:57 PM PDT 24 Jul 25 07:09:00 PM PDT 24 262499684 ps
T73 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.4224931343 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:55 PM PDT 24 215919816 ps
T844 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3077931126 Jul 25 07:08:54 PM PDT 24 Jul 25 07:08:55 PM PDT 24 20687391 ps
T845 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.863767061 Jul 25 07:09:18 PM PDT 24 Jul 25 07:09:18 PM PDT 24 14035596 ps
T846 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1926594209 Jul 25 07:09:15 PM PDT 24 Jul 25 07:09:18 PM PDT 24 110273784 ps
T847 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.4027627780 Jul 25 07:09:30 PM PDT 24 Jul 25 07:09:31 PM PDT 24 32226729 ps
T848 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1373865316 Jul 25 07:08:54 PM PDT 24 Jul 25 07:08:55 PM PDT 24 19150163 ps
T849 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3630432614 Jul 25 07:08:59 PM PDT 24 Jul 25 07:09:01 PM PDT 24 71319323 ps
T850 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.333373488 Jul 25 07:09:23 PM PDT 24 Jul 25 07:09:23 PM PDT 24 14895313 ps
T851 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.415736203 Jul 25 07:09:24 PM PDT 24 Jul 25 07:09:26 PM PDT 24 127483963 ps
T852 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.808974837 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:54 PM PDT 24 10745040 ps
T853 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3810249088 Jul 25 07:09:19 PM PDT 24 Jul 25 07:09:20 PM PDT 24 22244531 ps
T854 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3120157021 Jul 25 07:09:27 PM PDT 24 Jul 25 07:09:28 PM PDT 24 19837664 ps
T855 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.905373258 Jul 25 07:14:25 PM PDT 24 Jul 25 07:14:26 PM PDT 24 11151114 ps
T856 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3297605396 Jul 25 07:08:58 PM PDT 24 Jul 25 07:08:59 PM PDT 24 23620218 ps
T857 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2093639790 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:53 PM PDT 24 41193413 ps
T858 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2181359149 Jul 25 07:09:37 PM PDT 24 Jul 25 07:09:38 PM PDT 24 18912448 ps
T859 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1230332442 Jul 25 07:08:54 PM PDT 24 Jul 25 07:08:55 PM PDT 24 49203069 ps
T860 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.352944662 Jul 25 07:09:37 PM PDT 24 Jul 25 07:09:38 PM PDT 24 44597168 ps
T861 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1045161704 Jul 25 07:08:57 PM PDT 24 Jul 25 07:08:59 PM PDT 24 112647689 ps
T126 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.905622290 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:59 PM PDT 24 403195010 ps
T130 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2452830730 Jul 25 07:08:57 PM PDT 24 Jul 25 07:08:59 PM PDT 24 239551012 ps
T862 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2403965476 Jul 25 07:08:46 PM PDT 24 Jul 25 07:08:50 PM PDT 24 134058550 ps
T863 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2278052955 Jul 25 07:09:14 PM PDT 24 Jul 25 07:09:16 PM PDT 24 182457105 ps
T99 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2089667717 Jul 25 07:09:09 PM PDT 24 Jul 25 07:09:12 PM PDT 24 194421526 ps
T71 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1048847299 Jul 25 07:08:58 PM PDT 24 Jul 25 07:09:00 PM PDT 24 291465552 ps
T864 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3299382692 Jul 25 07:09:08 PM PDT 24 Jul 25 07:09:09 PM PDT 24 68853460 ps
T127 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1375314439 Jul 25 07:09:24 PM PDT 24 Jul 25 07:09:26 PM PDT 24 53527048 ps
T865 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2753947502 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:03 PM PDT 24 38324135 ps
T72 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3836152103 Jul 25 07:08:58 PM PDT 24 Jul 25 07:09:00 PM PDT 24 302499050 ps
T866 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3002520726 Jul 25 07:09:29 PM PDT 24 Jul 25 07:09:29 PM PDT 24 13375934 ps
T867 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1295684189 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:58 PM PDT 24 75892838 ps
T868 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1579081151 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:57 PM PDT 24 20306255 ps
T869 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1353982585 Jul 25 07:09:01 PM PDT 24 Jul 25 07:09:02 PM PDT 24 37193249 ps
T107 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1311235503 Jul 25 07:08:46 PM PDT 24 Jul 25 07:08:48 PM PDT 24 70753849 ps
T870 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.700603168 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:55 PM PDT 24 80066345 ps
T108 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.332337946 Jul 25 07:09:16 PM PDT 24 Jul 25 07:09:19 PM PDT 24 670791595 ps
T128 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3391000580 Jul 25 07:09:27 PM PDT 24 Jul 25 07:09:29 PM PDT 24 93148882 ps
T871 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2616177467 Jul 25 07:09:23 PM PDT 24 Jul 25 07:09:24 PM PDT 24 29297507 ps
T872 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1868312164 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:58 PM PDT 24 80734797 ps
T138 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3580617351 Jul 25 07:09:07 PM PDT 24 Jul 25 07:09:09 PM PDT 24 389940012 ps
T110 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2629705648 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:58 PM PDT 24 271128069 ps
T873 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1742678828 Jul 25 07:08:56 PM PDT 24 Jul 25 07:09:03 PM PDT 24 262027793 ps
T874 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1278315416 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:02 PM PDT 24 90247212 ps
T120 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.706598142 Jul 25 07:08:54 PM PDT 24 Jul 25 07:08:56 PM PDT 24 87744666 ps
T135 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.4034530259 Jul 25 07:09:18 PM PDT 24 Jul 25 07:09:20 PM PDT 24 93190215 ps
T133 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1832845375 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:55 PM PDT 24 237499880 ps
T875 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2867961684 Jul 25 07:09:17 PM PDT 24 Jul 25 07:09:20 PM PDT 24 251384207 ps
T876 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2392280741 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:54 PM PDT 24 224977567 ps
T877 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1793266015 Jul 25 07:09:01 PM PDT 24 Jul 25 07:09:02 PM PDT 24 16801384 ps
T878 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2598971925 Jul 25 07:09:08 PM PDT 24 Jul 25 07:09:09 PM PDT 24 50505022 ps
T879 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3231905618 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:54 PM PDT 24 20388198 ps
T880 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.4012626253 Jul 25 07:09:25 PM PDT 24 Jul 25 07:09:26 PM PDT 24 38936495 ps
T121 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3257628135 Jul 25 07:09:07 PM PDT 24 Jul 25 07:09:09 PM PDT 24 159184750 ps
T881 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3077711297 Jul 25 07:09:07 PM PDT 24 Jul 25 07:09:08 PM PDT 24 66753126 ps
T882 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3041882860 Jul 25 07:09:28 PM PDT 24 Jul 25 07:09:29 PM PDT 24 15270379 ps
T883 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3463346458 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:53 PM PDT 24 81469543 ps
T884 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1811907674 Jul 25 07:09:17 PM PDT 24 Jul 25 07:09:19 PM PDT 24 87258742 ps
T123 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2408442140 Jul 25 07:08:46 PM PDT 24 Jul 25 07:08:47 PM PDT 24 57514520 ps
T885 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1234986877 Jul 25 07:09:28 PM PDT 24 Jul 25 07:09:29 PM PDT 24 15116603 ps
T136 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.401003130 Jul 25 07:09:04 PM PDT 24 Jul 25 07:09:06 PM PDT 24 132576977 ps
T886 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.38742727 Jul 25 07:09:14 PM PDT 24 Jul 25 07:09:18 PM PDT 24 668102578 ps
T887 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1758597229 Jul 25 07:09:30 PM PDT 24 Jul 25 07:09:31 PM PDT 24 29204421 ps
T888 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3867769550 Jul 25 07:09:21 PM PDT 24 Jul 25 07:09:23 PM PDT 24 137109786 ps
T889 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.169842804 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:57 PM PDT 24 44765963 ps
T137 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1586708085 Jul 25 07:08:50 PM PDT 24 Jul 25 07:08:53 PM PDT 24 137920381 ps
T890 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.864893339 Jul 25 07:09:32 PM PDT 24 Jul 25 07:09:33 PM PDT 24 28120172 ps
T122 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2292889437 Jul 25 07:09:06 PM PDT 24 Jul 25 07:09:08 PM PDT 24 171457656 ps
T891 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3010748187 Jul 25 07:09:13 PM PDT 24 Jul 25 07:09:14 PM PDT 24 49330367 ps
T134 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.4096715871 Jul 25 07:09:03 PM PDT 24 Jul 25 07:09:04 PM PDT 24 60068835 ps
T892 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2896361991 Jul 25 07:08:54 PM PDT 24 Jul 25 07:08:54 PM PDT 24 61224113 ps
T893 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1605553880 Jul 25 07:09:31 PM PDT 24 Jul 25 07:09:32 PM PDT 24 14375145 ps
T894 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2199656520 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:57 PM PDT 24 19092600 ps
T895 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2568076996 Jul 25 07:09:09 PM PDT 24 Jul 25 07:09:10 PM PDT 24 27577022 ps
T896 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1996029019 Jul 25 07:09:31 PM PDT 24 Jul 25 07:09:32 PM PDT 24 45439857 ps
T897 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2104353840 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:57 PM PDT 24 38989207 ps
T898 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.4015256337 Jul 25 07:09:19 PM PDT 24 Jul 25 07:09:20 PM PDT 24 54195401 ps
T899 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3725609945 Jul 25 07:09:01 PM PDT 24 Jul 25 07:09:02 PM PDT 24 15664699 ps
T900 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3252080929 Jul 25 07:09:08 PM PDT 24 Jul 25 07:09:09 PM PDT 24 30403777 ps
T901 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.4264626339 Jul 25 07:08:57 PM PDT 24 Jul 25 07:08:58 PM PDT 24 17656569 ps
T100 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.308262493 Jul 25 07:08:54 PM PDT 24 Jul 25 07:08:58 PM PDT 24 365529139 ps
T131 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.651810328 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:54 PM PDT 24 63648863 ps
T902 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1468864609 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:54 PM PDT 24 29513900 ps
T903 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.991548891 Jul 25 07:08:50 PM PDT 24 Jul 25 07:08:58 PM PDT 24 431242118 ps
T904 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1713363013 Jul 25 07:09:17 PM PDT 24 Jul 25 07:09:17 PM PDT 24 14661613 ps
T905 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1822052683 Jul 25 07:09:30 PM PDT 24 Jul 25 07:09:30 PM PDT 24 20642899 ps
T906 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3570327950 Jul 25 07:09:10 PM PDT 24 Jul 25 07:09:16 PM PDT 24 11263769 ps
T907 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1341735404 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:54 PM PDT 24 76059696 ps
T908 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.491373068 Jul 25 07:09:18 PM PDT 24 Jul 25 07:09:20 PM PDT 24 59887160 ps
T909 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2193553075 Jul 25 07:08:53 PM PDT 24 Jul 25 07:09:00 PM PDT 24 264692515 ps
T910 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1875942363 Jul 25 07:09:31 PM PDT 24 Jul 25 07:09:32 PM PDT 24 33762877 ps
T911 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.788484172 Jul 25 07:08:57 PM PDT 24 Jul 25 07:08:59 PM PDT 24 104134136 ps
T101 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2400417543 Jul 25 07:08:58 PM PDT 24 Jul 25 07:09:00 PM PDT 24 230112109 ps
T140 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1491662178 Jul 25 07:09:01 PM PDT 24 Jul 25 07:09:03 PM PDT 24 127931567 ps
T912 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.616664205 Jul 25 07:09:16 PM PDT 24 Jul 25 07:09:18 PM PDT 24 68879526 ps
T124 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3461468672 Jul 25 07:09:17 PM PDT 24 Jul 25 07:09:19 PM PDT 24 106885598 ps
T913 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3719223330 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:53 PM PDT 24 80727872 ps
T914 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2840730440 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:58 PM PDT 24 27829270 ps
T915 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.220506197 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:56 PM PDT 24 136380235 ps
T916 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1110065165 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:58 PM PDT 24 71198184 ps
T917 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2958164465 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:56 PM PDT 24 12028229 ps
T111 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2370750436 Jul 25 07:09:16 PM PDT 24 Jul 25 07:09:19 PM PDT 24 264536842 ps
T918 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.99285092 Jul 25 07:09:11 PM PDT 24 Jul 25 07:09:14 PM PDT 24 328528026 ps
T919 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1307953536 Jul 25 07:08:57 PM PDT 24 Jul 25 07:08:58 PM PDT 24 20538086 ps
T920 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1001187965 Jul 25 07:09:19 PM PDT 24 Jul 25 07:09:20 PM PDT 24 40918914 ps
T921 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1219979609 Jul 25 07:09:02 PM PDT 24 Jul 25 07:09:04 PM PDT 24 320698284 ps
T922 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.639130665 Jul 25 07:08:53 PM PDT 24 Jul 25 07:08:54 PM PDT 24 37092254 ps
T923 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2736548151 Jul 25 07:09:14 PM PDT 24 Jul 25 07:09:19 PM PDT 24 13399818 ps
T924 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1103800464 Jul 25 07:09:26 PM PDT 24 Jul 25 07:09:27 PM PDT 24 54810933 ps
T925 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3307272383 Jul 25 07:09:17 PM PDT 24 Jul 25 07:09:19 PM PDT 24 41989190 ps
T926 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1791417391 Jul 25 07:09:29 PM PDT 24 Jul 25 07:09:30 PM PDT 24 22663061 ps
T927 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1721185672 Jul 25 07:09:04 PM PDT 24 Jul 25 07:09:05 PM PDT 24 37879079 ps
T928 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1126725177 Jul 25 07:08:58 PM PDT 24 Jul 25 07:09:01 PM PDT 24 113197864 ps
T929 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.128411802 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:58 PM PDT 24 111576055 ps
T930 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.460733528 Jul 25 07:09:03 PM PDT 24 Jul 25 07:09:05 PM PDT 24 311277392 ps
T931 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2173469322 Jul 25 07:08:57 PM PDT 24 Jul 25 07:09:00 PM PDT 24 135631188 ps
T932 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2974253844 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:01 PM PDT 24 37625370 ps
T933 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2922828249 Jul 25 07:09:07 PM PDT 24 Jul 25 07:09:08 PM PDT 24 70025194 ps
T934 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3850419520 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:52 PM PDT 24 39496432 ps
T935 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.249256384 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:58 PM PDT 24 63122465 ps
T936 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3668570734 Jul 25 07:09:30 PM PDT 24 Jul 25 07:09:31 PM PDT 24 18386267 ps
T937 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.685212052 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:02 PM PDT 24 46032094 ps
T938 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.752996026 Jul 25 07:09:28 PM PDT 24 Jul 25 07:09:29 PM PDT 24 16471015 ps
T939 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1343881062 Jul 25 07:09:28 PM PDT 24 Jul 25 07:09:29 PM PDT 24 94904064 ps
T940 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3556929591 Jul 25 07:09:04 PM PDT 24 Jul 25 07:09:06 PM PDT 24 66234661 ps
T941 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3956478080 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:52 PM PDT 24 51622684 ps
T942 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.4227887641 Jul 25 07:09:02 PM PDT 24 Jul 25 07:09:04 PM PDT 24 149456489 ps
T132 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3868444385 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:58 PM PDT 24 73782863 ps
T943 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3429325742 Jul 25 07:08:58 PM PDT 24 Jul 25 07:09:01 PM PDT 24 90261575 ps
T944 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1475984271 Jul 25 07:09:05 PM PDT 24 Jul 25 07:09:06 PM PDT 24 20106062 ps
T945 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1536449632 Jul 25 07:08:50 PM PDT 24 Jul 25 07:08:55 PM PDT 24 485195809 ps
T946 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3704357189 Jul 25 07:08:58 PM PDT 24 Jul 25 07:08:59 PM PDT 24 12947411 ps
T947 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1370502408 Jul 25 07:09:27 PM PDT 24 Jul 25 07:09:27 PM PDT 24 13807250 ps
T948 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2944600858 Jul 25 07:09:24 PM PDT 24 Jul 25 07:09:25 PM PDT 24 28209906 ps
T949 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3834520895 Jul 25 07:09:20 PM PDT 24 Jul 25 07:09:23 PM PDT 24 162454964 ps
T950 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1006093021 Jul 25 07:09:36 PM PDT 24 Jul 25 07:09:37 PM PDT 24 20724124 ps
T129 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3072119505 Jul 25 07:08:59 PM PDT 24 Jul 25 07:09:02 PM PDT 24 709997737 ps
T951 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3864404414 Jul 25 07:09:09 PM PDT 24 Jul 25 07:09:10 PM PDT 24 63305824 ps
T952 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3680820945 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:08 PM PDT 24 670248323 ps
T953 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1085963752 Jul 25 07:09:29 PM PDT 24 Jul 25 07:09:32 PM PDT 24 244778561 ps
T954 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.811627537 Jul 25 07:09:22 PM PDT 24 Jul 25 07:09:23 PM PDT 24 27308940 ps
T955 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.533375192 Jul 25 07:08:58 PM PDT 24 Jul 25 07:08:59 PM PDT 24 110715130 ps
T125 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1460121967 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:59 PM PDT 24 324552196 ps
T956 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2560528305 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:59 PM PDT 24 129197930 ps
T957 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1010080703 Jul 25 07:09:16 PM PDT 24 Jul 25 07:09:17 PM PDT 24 19202064 ps
T958 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.862659247 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:58 PM PDT 24 447208866 ps
T139 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.862840339 Jul 25 07:08:51 PM PDT 24 Jul 25 07:08:53 PM PDT 24 103009777 ps
T959 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2449534050 Jul 25 07:09:17 PM PDT 24 Jul 25 07:09:18 PM PDT 24 15288837 ps
T960 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2321172645 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:57 PM PDT 24 48508260 ps
T961 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1528461713 Jul 25 07:09:24 PM PDT 24 Jul 25 07:09:26 PM PDT 24 29322660 ps
T962 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.439864812 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:56 PM PDT 24 17291402 ps
T963 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2784233427 Jul 25 07:09:34 PM PDT 24 Jul 25 07:09:35 PM PDT 24 10725854 ps
T964 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.979489499 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:54 PM PDT 24 96935212 ps
T965 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2177603959 Jul 25 07:08:58 PM PDT 24 Jul 25 07:09:00 PM PDT 24 170333608 ps
T966 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.235860768 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:57 PM PDT 24 29884425 ps
T967 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.4269147759 Jul 25 07:09:36 PM PDT 24 Jul 25 07:09:41 PM PDT 24 57467784 ps
T968 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1151545379 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:01 PM PDT 24 19587573 ps
T969 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1207624845 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:01 PM PDT 24 42809017 ps
T970 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3035222464 Jul 25 07:09:02 PM PDT 24 Jul 25 07:09:03 PM PDT 24 34799393 ps
T971 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3279421230 Jul 25 07:09:19 PM PDT 24 Jul 25 07:09:20 PM PDT 24 24597385 ps
T972 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4220808363 Jul 25 07:09:24 PM PDT 24 Jul 25 07:09:25 PM PDT 24 25078414 ps
T973 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.514914614 Jul 25 07:09:13 PM PDT 24 Jul 25 07:09:14 PM PDT 24 18304836 ps
T974 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1407914274 Jul 25 07:08:58 PM PDT 24 Jul 25 07:08:59 PM PDT 24 40683153 ps
T975 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3466449794 Jul 25 07:08:52 PM PDT 24 Jul 25 07:08:54 PM PDT 24 87229745 ps
T109 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.970436133 Jul 25 07:09:09 PM PDT 24 Jul 25 07:09:16 PM PDT 24 1759629717 ps
T105 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3610325749 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:58 PM PDT 24 141004904 ps
T976 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3326616291 Jul 25 07:08:56 PM PDT 24 Jul 25 07:08:57 PM PDT 24 12042941 ps
T106 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.656672806 Jul 25 07:09:00 PM PDT 24 Jul 25 07:09:03 PM PDT 24 239189632 ps
T185 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1022282922 Jul 25 07:09:04 PM PDT 24 Jul 25 07:09:07 PM PDT 24 293666604 ps
T977 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2949037227 Jul 25 07:08:47 PM PDT 24 Jul 25 07:08:48 PM PDT 24 76154057 ps
T978 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.870635431 Jul 25 07:09:18 PM PDT 24 Jul 25 07:09:19 PM PDT 24 25949540 ps
T979 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2426671396 Jul 25 07:09:27 PM PDT 24 Jul 25 07:09:28 PM PDT 24 27137938 ps
T980 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.430924479 Jul 25 07:09:29 PM PDT 24 Jul 25 07:09:30 PM PDT 24 14230840 ps
T981 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.127428391 Jul 25 07:08:55 PM PDT 24 Jul 25 07:08:57 PM PDT 24 200054772 ps

Test location /workspace/coverage/default/39.clkmgr_stress_all.3477820557
Short name T6
Test name
Test status
Simulation time 1389704501 ps
CPU time 9.71 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:16:06 PM PDT 24
Peak memory 200636 kb
Host smart-ecadf8b2-77bf-4495-9428-ae5ea27aefc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477820557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.3477820557
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.1069818941
Short name T1
Test name
Test status
Simulation time 384932444776 ps
CPU time 1471.33 seconds
Started Jul 25 07:15:44 PM PDT 24
Finished Jul 25 07:40:16 PM PDT 24
Peak memory 217328 kb
Host smart-ae56d2f1-3e7e-4365-a716-2dc82e67f144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1069818941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.1069818941
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.3863669448
Short name T24
Test name
Test status
Simulation time 994415270 ps
CPU time 5.8 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:08 PM PDT 24
Peak memory 200668 kb
Host smart-38f7f229-fdf1-4407-a14f-d8b93f1edf63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863669448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3863669448
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3750130267
Short name T64
Test name
Test status
Simulation time 126085459 ps
CPU time 2.06 seconds
Started Jul 25 07:09:12 PM PDT 24
Finished Jul 25 07:09:14 PM PDT 24
Peak memory 201552 kb
Host smart-5a979349-1684-4399-891c-acffba491879
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750130267 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.3750130267
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.3222381451
Short name T50
Test name
Test status
Simulation time 161777236 ps
CPU time 2.09 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 215984 kb
Host smart-4a6ff68f-4f89-4796-8b2d-418c83b2108c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222381451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.3222381451
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.3375024781
Short name T174
Test name
Test status
Simulation time 41856461 ps
CPU time 0.79 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 199720 kb
Host smart-c8cedc2a-56b8-4a46-b4e2-7cd2945840a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375024781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.3375024781
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.3935423297
Short name T23
Test name
Test status
Simulation time 124782568 ps
CPU time 1.26 seconds
Started Jul 25 07:14:45 PM PDT 24
Finished Jul 25 07:14:46 PM PDT 24
Peak memory 200508 kb
Host smart-ef7549a7-65d5-4975-82aa-0fdc32177eda
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935423297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.3935423297
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.4178531933
Short name T2
Test name
Test status
Simulation time 6358323618 ps
CPU time 49.1 seconds
Started Jul 25 07:15:37 PM PDT 24
Finished Jul 25 07:16:27 PM PDT 24
Peak memory 200892 kb
Host smart-91babff4-5127-4614-ab0d-90fdd7baf721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178531933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.4178531933
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2223496512
Short name T96
Test name
Test status
Simulation time 120693299 ps
CPU time 1.8 seconds
Started Jul 25 07:09:13 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 201280 kb
Host smart-bf11c98f-2a9b-4002-9f8c-7a5811d2bfde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223496512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.2223496512
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.4224931343
Short name T73
Test name
Test status
Simulation time 215919816 ps
CPU time 2.62 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 209684 kb
Host smart-daf5d363-84c8-4699-ac10-2028783b3e3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224931343 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.4224931343
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.2674777548
Short name T39
Test name
Test status
Simulation time 27733936 ps
CPU time 0.81 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200492 kb
Host smart-1f360c62-29de-44d8-8351-8b2337b8d15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674777548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.2674777548
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.4127283110
Short name T78
Test name
Test status
Simulation time 22539893730 ps
CPU time 337.41 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:20:21 PM PDT 24
Peak memory 217288 kb
Host smart-2be4439e-c3b1-43d1-8afc-70ad60739705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4127283110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.4127283110
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.3872933113
Short name T10
Test name
Test status
Simulation time 998790984 ps
CPU time 5.07 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:15:35 PM PDT 24
Peak memory 200688 kb
Host smart-ab33019b-70a2-47a4-941e-e7854fad51f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872933113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.3872933113
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.862840339
Short name T139
Test name
Test status
Simulation time 103009777 ps
CPU time 1.76 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 209684 kb
Host smart-8f933010-32d4-4125-afe9-93662f32da3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862840339 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.clkmgr_shadow_reg_errors.862840339
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2400417543
Short name T101
Test name
Test status
Simulation time 230112109 ps
CPU time 2.6 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 201428 kb
Host smart-31c62b50-0077-4c3c-903f-5394d2e53f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400417543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2400417543
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.918945027
Short name T41
Test name
Test status
Simulation time 160233063967 ps
CPU time 975.63 seconds
Started Jul 25 07:15:04 PM PDT 24
Finished Jul 25 07:31:20 PM PDT 24
Peak memory 209204 kb
Host smart-5ca26251-1a28-4bf3-b401-b7d68b412855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=918945027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.918945027
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.1745164269
Short name T166
Test name
Test status
Simulation time 2220340188 ps
CPU time 9.25 seconds
Started Jul 25 07:14:56 PM PDT 24
Finished Jul 25 07:15:06 PM PDT 24
Peak memory 200856 kb
Host smart-fc8615cd-11cc-4283-a57c-c9434d34440c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745164269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.1745164269
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1781648147
Short name T75
Test name
Test status
Simulation time 65718289742 ps
CPU time 436.37 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:22:35 PM PDT 24
Peak memory 209196 kb
Host smart-4de7e65c-4cff-4b5e-af81-9b27607112e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1781648147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1781648147
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1087345671
Short name T93
Test name
Test status
Simulation time 75351659 ps
CPU time 1.04 seconds
Started Jul 25 07:14:14 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200516 kb
Host smart-473ef848-b8de-4264-9a91-5f4e57858f26
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087345671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.1087345671
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2408442140
Short name T123
Test name
Test status
Simulation time 57514520 ps
CPU time 1.31 seconds
Started Jul 25 07:08:46 PM PDT 24
Finished Jul 25 07:08:47 PM PDT 24
Peak memory 201312 kb
Host smart-8a91cad9-e7a6-48f5-8f53-8e8ba3baf87d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408442140 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.2408442140
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3072119505
Short name T129
Test name
Test status
Simulation time 709997737 ps
CPU time 2.83 seconds
Started Jul 25 07:08:59 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 201316 kb
Host smart-d5d214c7-3245-4591-97c5-19e9ca55e4f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072119505 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.3072119505
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1311235503
Short name T107
Test name
Test status
Simulation time 70753849 ps
CPU time 1.73 seconds
Started Jul 25 07:08:46 PM PDT 24
Finished Jul 25 07:08:48 PM PDT 24
Peak memory 201332 kb
Host smart-3840fe5a-5e90-485a-bbbc-378f0eabf58b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311235503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.1311235503
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.308262493
Short name T100
Test name
Test status
Simulation time 365529139 ps
CPU time 3.19 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201300 kb
Host smart-2260e778-0d05-4500-a2e6-b61547916a18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308262493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_tl_intg_err.308262493
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3610325749
Short name T105
Test name
Test status
Simulation time 141004904 ps
CPU time 2.54 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201124 kb
Host smart-8f2ed2f0-cfc6-49e2-8d62-5aa88a31bd64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610325749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3610325749
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.1881896007
Short name T321
Test name
Test status
Simulation time 2257200717 ps
CPU time 9.67 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:23 PM PDT 24
Peak memory 200836 kb
Host smart-062d4ff7-a5bd-4a14-a845-142887169d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881896007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.1881896007
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.94500405
Short name T88
Test name
Test status
Simulation time 58162339 ps
CPU time 1.62 seconds
Started Jul 25 07:08:49 PM PDT 24
Finished Jul 25 07:08:51 PM PDT 24
Peak memory 201240 kb
Host smart-3a270fbf-337a-4123-9de0-272d7768f1f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94500405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_csr_aliasing.94500405
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.991548891
Short name T903
Test name
Test status
Simulation time 431242118 ps
CPU time 8.03 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201184 kb
Host smart-0c7609a8-0d1c-48a6-b52a-d19258c226eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991548891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.991548891
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1215521377
Short name T102
Test name
Test status
Simulation time 21558840 ps
CPU time 0.79 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201056 kb
Host smart-9d6f492a-78fa-4b6e-9570-ae33c4a406d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215521377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1215521377
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2093639790
Short name T857
Test name
Test status
Simulation time 41193413 ps
CPU time 1.15 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 201096 kb
Host smart-be21d4f4-1fd9-40e3-94ef-82d880427943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093639790 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2093639790
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.439864812
Short name T962
Test name
Test status
Simulation time 17291402 ps
CPU time 0.84 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 201056 kb
Host smart-385056f8-6f1d-4d9c-ace2-29b94e8d2277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439864812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.c
lkmgr_csr_rw.439864812
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3570327950
Short name T906
Test name
Test status
Simulation time 11263769 ps
CPU time 0.65 seconds
Started Jul 25 07:09:10 PM PDT 24
Finished Jul 25 07:09:16 PM PDT 24
Peak memory 199728 kb
Host smart-7ebf8bbe-c35e-4a4d-9fb9-c6273325d406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570327950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.3570327950
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3466449794
Short name T975
Test name
Test status
Simulation time 87229745 ps
CPU time 1.47 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201296 kb
Host smart-eb0458cc-e0a5-4536-9a25-f45dcc23d370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466449794 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.3466449794
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1832845375
Short name T133
Test name
Test status
Simulation time 237499880 ps
CPU time 1.78 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 201276 kb
Host smart-f300ae6f-b021-4a80-878f-4be8fee61850
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832845375 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.1832845375
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.905622290
Short name T126
Test name
Test status
Simulation time 403195010 ps
CPU time 3.49 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 201684 kb
Host smart-1de9e9e6-ed4c-4ac8-abb8-51e6bc7b87cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905622290 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.905622290
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2403965476
Short name T862
Test name
Test status
Simulation time 134058550 ps
CPU time 3.23 seconds
Started Jul 25 07:08:46 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 201208 kb
Host smart-2236686c-d0fc-40dd-881d-549924ed5381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403965476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.2403965476
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3243612064
Short name T98
Test name
Test status
Simulation time 57680731 ps
CPU time 1.56 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 201304 kb
Host smart-819a9742-7a8d-40af-8edd-4570646e69a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243612064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.3243612064
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1045161704
Short name T861
Test name
Test status
Simulation time 112647689 ps
CPU time 1.75 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 201264 kb
Host smart-f459ea18-cf09-429b-bb39-0f646c20a3d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045161704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.1045161704
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.220506197
Short name T915
Test name
Test status
Simulation time 136380235 ps
CPU time 3.72 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 201144 kb
Host smart-2a09a63f-5d76-4f05-87ce-6fd66708bfb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220506197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_bit_bash.220506197
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1341735404
Short name T907
Test name
Test status
Simulation time 76059696 ps
CPU time 0.94 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 200960 kb
Host smart-e994d09c-2ef3-429c-857d-4038c9c3d539
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341735404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.1341735404
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.639130665
Short name T922
Test name
Test status
Simulation time 37092254 ps
CPU time 1.19 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201008 kb
Host smart-ab49cd4b-b4c5-44cb-8e68-2dfb642400da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639130665 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.639130665
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2866462953
Short name T87
Test name
Test status
Simulation time 59728136 ps
CPU time 0.93 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201044 kb
Host smart-ed0b6d94-7820-416b-8b8e-a82432e357e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866462953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.2866462953
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3231905618
Short name T879
Test name
Test status
Simulation time 20388198 ps
CPU time 0.69 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 199648 kb
Host smart-6d47e4aa-25dc-4030-b2b3-cea807e2af89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231905618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.3231905618
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1407914274
Short name T974
Test name
Test status
Simulation time 40683153 ps
CPU time 1.21 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 201100 kb
Host smart-8cc8d385-0f12-4cf8-a8bd-218ca38e859b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407914274 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.1407914274
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2949037227
Short name T977
Test name
Test status
Simulation time 76154057 ps
CPU time 1.44 seconds
Started Jul 25 07:08:47 PM PDT 24
Finished Jul 25 07:08:48 PM PDT 24
Peak memory 201300 kb
Host smart-435510a0-463b-420e-8538-a53941931686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949037227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.2949037227
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.700603168
Short name T870
Test name
Test status
Simulation time 80066345 ps
CPU time 1.58 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 201296 kb
Host smart-a9845678-5834-478c-b8d4-5d9ea7320d8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700603168 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.700603168
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3850419520
Short name T934
Test name
Test status
Simulation time 39496432 ps
CPU time 0.78 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:52 PM PDT 24
Peak memory 201024 kb
Host smart-06f2cd1b-2a24-4ecb-b1b1-5dc701744914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850419520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3850419520
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3077931126
Short name T844
Test name
Test status
Simulation time 20687391 ps
CPU time 0.68 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 199672 kb
Host smart-d80daf4f-0b37-4e8b-9344-60c3769cf296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077931126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.3077931126
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2392280741
Short name T876
Test name
Test status
Simulation time 224977567 ps
CPU time 1.67 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201196 kb
Host smart-77805b7f-2ed5-4bc6-a37f-5308bdd02ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392280741 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.2392280741
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1085963752
Short name T953
Test name
Test status
Simulation time 244778561 ps
CPU time 2.5 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 201472 kb
Host smart-17bec1c6-e7ba-49bb-925e-7d2108197464
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085963752 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.1085963752
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3288277204
Short name T68
Test name
Test status
Simulation time 194800044 ps
CPU time 3.16 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201836 kb
Host smart-0bb16385-8271-4ee1-a05a-0893b26e8cd2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288277204 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3288277204
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.38742727
Short name T886
Test name
Test status
Simulation time 668102578 ps
CPU time 3.57 seconds
Started Jul 25 07:09:14 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 201164 kb
Host smart-1138044e-410c-4d88-96ff-f52c3ef803db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38742727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkm
gr_tl_errors.38742727
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.615489067
Short name T97
Test name
Test status
Simulation time 593781925 ps
CPU time 2.91 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 201260 kb
Host smart-4c102e30-a769-42af-8666-e5e725fb90f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615489067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_tl_intg_err.615489067
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1475984271
Short name T944
Test name
Test status
Simulation time 20106062 ps
CPU time 0.89 seconds
Started Jul 25 07:09:05 PM PDT 24
Finished Jul 25 07:09:06 PM PDT 24
Peak memory 201032 kb
Host smart-827f6fd8-0df0-49d8-b925-dde21d25db97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475984271 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1475984271
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3077711297
Short name T881
Test name
Test status
Simulation time 66753126 ps
CPU time 0.96 seconds
Started Jul 25 07:09:07 PM PDT 24
Finished Jul 25 07:09:08 PM PDT 24
Peak memory 201068 kb
Host smart-2d8b38f2-7bbd-4685-a294-8f91eb87a352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077711297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.3077711297
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3725609945
Short name T899
Test name
Test status
Simulation time 15664699 ps
CPU time 0.69 seconds
Started Jul 25 07:09:01 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 199636 kb
Host smart-099108a4-76f8-4659-949f-00674a1cda01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725609945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.3725609945
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2922828249
Short name T933
Test name
Test status
Simulation time 70025194 ps
CPU time 1.09 seconds
Started Jul 25 07:09:07 PM PDT 24
Finished Jul 25 07:09:08 PM PDT 24
Peak memory 201076 kb
Host smart-79b04167-20c7-489e-b3c4-e2a8954ce415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922828249 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.2922828249
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1491662178
Short name T140
Test name
Test status
Simulation time 127931567 ps
CPU time 2.01 seconds
Started Jul 25 07:09:01 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 209684 kb
Host smart-d36e2d67-7c45-4b91-b80f-a34d19549d2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491662178 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.1491662178
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.979489499
Short name T964
Test name
Test status
Simulation time 96935212 ps
CPU time 2.05 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 209672 kb
Host smart-2480cffd-9eeb-4b8c-be43-81eee81e06fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979489499 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.979489499
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1926594209
Short name T846
Test name
Test status
Simulation time 110273784 ps
CPU time 3.12 seconds
Started Jul 25 07:09:15 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 201248 kb
Host smart-c26c8640-739b-4670-875f-1cd6d35edbe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926594209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.1926594209
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2568076996
Short name T895
Test name
Test status
Simulation time 27577022 ps
CPU time 0.99 seconds
Started Jul 25 07:09:09 PM PDT 24
Finished Jul 25 07:09:10 PM PDT 24
Peak memory 201124 kb
Host smart-62dc24e9-fdc0-4a52-989c-825b4da4e256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568076996 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.2568076996
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2207432234
Short name T839
Test name
Test status
Simulation time 44410685 ps
CPU time 0.87 seconds
Started Jul 25 07:09:01 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 200952 kb
Host smart-d8a7363d-d16b-474f-85ae-d3ae753ead56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207432234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.2207432234
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3864404414
Short name T951
Test name
Test status
Simulation time 63305824 ps
CPU time 0.77 seconds
Started Jul 25 07:09:09 PM PDT 24
Finished Jul 25 07:09:10 PM PDT 24
Peak memory 199756 kb
Host smart-11a74000-a088-457f-b135-49e2fefaa9ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864404414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.3864404414
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1613892649
Short name T86
Test name
Test status
Simulation time 42576712 ps
CPU time 1.05 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 201072 kb
Host smart-a1b34d7c-e5be-40e3-a8c5-8437bcfcf5a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613892649 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1613892649
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3836152103
Short name T72
Test name
Test status
Simulation time 302499050 ps
CPU time 2.73 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 201488 kb
Host smart-d8b93f20-5373-467c-9646-bca8f9cf767d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836152103 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.3836152103
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3580617351
Short name T138
Test name
Test status
Simulation time 389940012 ps
CPU time 2.47 seconds
Started Jul 25 07:09:07 PM PDT 24
Finished Jul 25 07:09:09 PM PDT 24
Peak memory 201524 kb
Host smart-ea57dec3-6313-48b3-a831-9c6a53409f6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580617351 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3580617351
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3556929591
Short name T940
Test name
Test status
Simulation time 66234661 ps
CPU time 1.94 seconds
Started Jul 25 07:09:04 PM PDT 24
Finished Jul 25 07:09:06 PM PDT 24
Peak memory 201324 kb
Host smart-7eac601d-1abf-4f0c-a886-830fed348468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556929591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.3556929591
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1126725177
Short name T928
Test name
Test status
Simulation time 113197864 ps
CPU time 2.43 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:09:01 PM PDT 24
Peak memory 201244 kb
Host smart-3768cba6-6f06-486d-9923-88611aaa607f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126725177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1126725177
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1528461713
Short name T961
Test name
Test status
Simulation time 29322660 ps
CPU time 1.06 seconds
Started Jul 25 07:09:24 PM PDT 24
Finished Jul 25 07:09:26 PM PDT 24
Peak memory 201120 kb
Host smart-104abfb9-8fd3-48ed-a1e0-bc9c650b84e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528461713 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.1528461713
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2811623508
Short name T163
Test name
Test status
Simulation time 23144748 ps
CPU time 0.88 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201044 kb
Host smart-311915d4-da84-43f1-b9c2-fc0e4a18100c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811623508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.2811623508
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.333373488
Short name T850
Test name
Test status
Simulation time 14895313 ps
CPU time 0.64 seconds
Started Jul 25 07:09:23 PM PDT 24
Finished Jul 25 07:09:23 PM PDT 24
Peak memory 199648 kb
Host smart-3f3f9f52-77eb-40fb-be91-1b160346f484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333373488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_intr_test.333373488
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2598971925
Short name T878
Test name
Test status
Simulation time 50505022 ps
CPU time 1.09 seconds
Started Jul 25 07:09:08 PM PDT 24
Finished Jul 25 07:09:09 PM PDT 24
Peak memory 201132 kb
Host smart-737f3652-c106-44c0-86db-82188229eab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598971925 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.2598971925
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.401003130
Short name T136
Test name
Test status
Simulation time 132576977 ps
CPU time 2.12 seconds
Started Jul 25 07:09:04 PM PDT 24
Finished Jul 25 07:09:06 PM PDT 24
Peak memory 209708 kb
Host smart-6c1d36f1-ad7e-42a3-a753-85c2a3423469
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401003130 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.clkmgr_shadow_reg_errors.401003130
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3273873255
Short name T66
Test name
Test status
Simulation time 178813029 ps
CPU time 2.64 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 201740 kb
Host smart-e752e718-ecbe-49fa-9d50-cbd136a5e8d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273873255 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.3273873255
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3010748187
Short name T891
Test name
Test status
Simulation time 49330367 ps
CPU time 1.63 seconds
Started Jul 25 07:09:13 PM PDT 24
Finished Jul 25 07:09:14 PM PDT 24
Peak memory 201240 kb
Host smart-89ec95f8-81a3-41bf-acd6-0ecc1e59574d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010748187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.3010748187
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.4227887641
Short name T942
Test name
Test status
Simulation time 149456489 ps
CPU time 1.73 seconds
Started Jul 25 07:09:02 PM PDT 24
Finished Jul 25 07:09:04 PM PDT 24
Peak memory 201224 kb
Host smart-5054bc9f-35a4-43cd-a20f-ac6414646085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227887641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.4227887641
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3279421230
Short name T971
Test name
Test status
Simulation time 24597385 ps
CPU time 1.33 seconds
Started Jul 25 07:09:19 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 209448 kb
Host smart-b15ce264-32b1-426a-bffc-c442b64b6956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279421230 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.3279421230
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2944600858
Short name T948
Test name
Test status
Simulation time 28209906 ps
CPU time 0.84 seconds
Started Jul 25 07:09:24 PM PDT 24
Finished Jul 25 07:09:25 PM PDT 24
Peak memory 201036 kb
Host smart-37865ec4-685b-47d1-a617-09f26b85a89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944600858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.2944600858
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3252080929
Short name T900
Test name
Test status
Simulation time 30403777 ps
CPU time 0.7 seconds
Started Jul 25 07:09:08 PM PDT 24
Finished Jul 25 07:09:09 PM PDT 24
Peak memory 199712 kb
Host smart-f92955c9-de7d-4de2-a987-d5f93e8da624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252080929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.3252080929
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1343881062
Short name T939
Test name
Test status
Simulation time 94904064 ps
CPU time 1.13 seconds
Started Jul 25 07:09:28 PM PDT 24
Finished Jul 25 07:09:29 PM PDT 24
Peak memory 201008 kb
Host smart-d3176da2-c891-48e7-9f0d-80d99f54bbd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343881062 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.1343881062
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1643249068
Short name T65
Test name
Test status
Simulation time 93196141 ps
CPU time 1.34 seconds
Started Jul 25 07:09:01 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 201308 kb
Host smart-1d307903-7fbe-4573-9eb6-f8e5bf2f7d73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643249068 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.1643249068
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3834520895
Short name T949
Test name
Test status
Simulation time 162454964 ps
CPU time 3.19 seconds
Started Jul 25 07:09:20 PM PDT 24
Finished Jul 25 07:09:23 PM PDT 24
Peak memory 201784 kb
Host smart-15c65903-f5a5-468c-901a-b709270b4c02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834520895 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.3834520895
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2867961684
Short name T875
Test name
Test status
Simulation time 251384207 ps
CPU time 2.6 seconds
Started Jul 25 07:09:17 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 201192 kb
Host smart-0fc3dd98-eb6e-4b89-a857-e53488e9e152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867961684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.2867961684
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.332337946
Short name T108
Test name
Test status
Simulation time 670791595 ps
CPU time 3.35 seconds
Started Jul 25 07:09:16 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 201300 kb
Host smart-87a3d3ab-8b7b-48b5-b805-115f643da309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332337946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_tl_intg_err.332337946
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4220808363
Short name T972
Test name
Test status
Simulation time 25078414 ps
CPU time 1.14 seconds
Started Jul 25 07:09:24 PM PDT 24
Finished Jul 25 07:09:25 PM PDT 24
Peak memory 201140 kb
Host smart-83940a3a-1dbe-4159-b53f-848bf20b6ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220808363 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.4220808363
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1721185672
Short name T927
Test name
Test status
Simulation time 37879079 ps
CPU time 0.82 seconds
Started Jul 25 07:09:04 PM PDT 24
Finished Jul 25 07:09:05 PM PDT 24
Peak memory 201044 kb
Host smart-64a9033d-d0aa-4c80-84c8-01509a87b676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721185672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.1721185672
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3297605396
Short name T856
Test name
Test status
Simulation time 23620218 ps
CPU time 0.69 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 199672 kb
Host smart-f00834ef-b796-4acd-835a-66d8a96bc81e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297605396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.3297605396
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3299382692
Short name T864
Test name
Test status
Simulation time 68853460 ps
CPU time 1.08 seconds
Started Jul 25 07:09:08 PM PDT 24
Finished Jul 25 07:09:09 PM PDT 24
Peak memory 201016 kb
Host smart-839a5122-e88a-4e3e-ada6-132425fd5692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299382692 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.3299382692
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3257628135
Short name T121
Test name
Test status
Simulation time 159184750 ps
CPU time 2.06 seconds
Started Jul 25 07:09:07 PM PDT 24
Finished Jul 25 07:09:09 PM PDT 24
Peak memory 209744 kb
Host smart-10bee965-5b48-4a83-839c-2ad2bfad0a6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257628135 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3257628135
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.460733528
Short name T930
Test name
Test status
Simulation time 311277392 ps
CPU time 2.38 seconds
Started Jul 25 07:09:03 PM PDT 24
Finished Jul 25 07:09:05 PM PDT 24
Peak memory 217884 kb
Host smart-fc89c094-6437-4ccf-9542-ccacdc4de1b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460733528 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.460733528
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3552029584
Short name T843
Test name
Test status
Simulation time 262499684 ps
CPU time 2.71 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 201228 kb
Host smart-c2179666-88a3-46cd-9a30-80c3b438c7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552029584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.3552029584
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1022282922
Short name T185
Test name
Test status
Simulation time 293666604 ps
CPU time 2.67 seconds
Started Jul 25 07:09:04 PM PDT 24
Finished Jul 25 07:09:07 PM PDT 24
Peak memory 201228 kb
Host smart-f0dd9171-5dec-4724-8042-c919b65b6e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022282922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.1022282922
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.811627537
Short name T954
Test name
Test status
Simulation time 27308940 ps
CPU time 1.09 seconds
Started Jul 25 07:09:22 PM PDT 24
Finished Jul 25 07:09:23 PM PDT 24
Peak memory 201120 kb
Host smart-6109ab1a-307c-4a08-b12a-2d04bb06b38d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811627537 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.811627537
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.752996026
Short name T938
Test name
Test status
Simulation time 16471015 ps
CPU time 0.8 seconds
Started Jul 25 07:09:28 PM PDT 24
Finished Jul 25 07:09:29 PM PDT 24
Peak memory 201064 kb
Host smart-db4fc979-b06d-4099-b02a-a8f8e0aaa2af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752996026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
clkmgr_csr_rw.752996026
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1353982585
Short name T869
Test name
Test status
Simulation time 37193249 ps
CPU time 0.71 seconds
Started Jul 25 07:09:01 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 199704 kb
Host smart-c2de1add-80e5-43d0-853f-7ec9d4e70865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353982585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.1353982585
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2278052955
Short name T863
Test name
Test status
Simulation time 182457105 ps
CPU time 1.47 seconds
Started Jul 25 07:09:14 PM PDT 24
Finished Jul 25 07:09:16 PM PDT 24
Peak memory 201080 kb
Host smart-a69757e3-2f30-4d16-bedd-0893303fef7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278052955 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.2278052955
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.4096715871
Short name T134
Test name
Test status
Simulation time 60068835 ps
CPU time 1.43 seconds
Started Jul 25 07:09:03 PM PDT 24
Finished Jul 25 07:09:04 PM PDT 24
Peak memory 201336 kb
Host smart-328149c4-5376-42bb-bc68-1a47f496a9c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096715871 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.4096715871
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1375314439
Short name T127
Test name
Test status
Simulation time 53527048 ps
CPU time 1.56 seconds
Started Jul 25 07:09:24 PM PDT 24
Finished Jul 25 07:09:26 PM PDT 24
Peak memory 209668 kb
Host smart-e44c312c-66d3-4451-86c4-2e449027999a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375314439 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.1375314439
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1000110724
Short name T836
Test name
Test status
Simulation time 28383674 ps
CPU time 1.9 seconds
Started Jul 25 07:09:15 PM PDT 24
Finished Jul 25 07:09:17 PM PDT 24
Peak memory 201252 kb
Host smart-5acd0c03-1e6e-4603-8d31-057e6a6fd367
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000110724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.1000110724
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2370750436
Short name T111
Test name
Test status
Simulation time 264536842 ps
CPU time 2.59 seconds
Started Jul 25 07:09:16 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 201280 kb
Host smart-63b27577-cf89-45a9-8f4b-cab86b7c4e55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370750436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.2370750436
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3307272383
Short name T925
Test name
Test status
Simulation time 41989190 ps
CPU time 1.31 seconds
Started Jul 25 07:09:17 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 201168 kb
Host smart-16d2611d-4e0b-4f39-8797-89222ba6d43d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307272383 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3307272383
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1010080703
Short name T957
Test name
Test status
Simulation time 19202064 ps
CPU time 0.85 seconds
Started Jul 25 07:09:16 PM PDT 24
Finished Jul 25 07:09:17 PM PDT 24
Peak memory 201108 kb
Host smart-f0fc0e25-8055-4d16-8abc-af9981db6e0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010080703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.1010080703
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3810249088
Short name T853
Test name
Test status
Simulation time 22244531 ps
CPU time 0.69 seconds
Started Jul 25 07:09:19 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 199744 kb
Host smart-1e5a3531-5813-4393-8f0b-ee7200adc810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810249088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.3810249088
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.4027627780
Short name T847
Test name
Test status
Simulation time 32226729 ps
CPU time 1.17 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:31 PM PDT 24
Peak memory 201208 kb
Host smart-ce7ef831-0592-4379-8be7-503b6dcc9fde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027627780 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.4027627780
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3461468672
Short name T124
Test name
Test status
Simulation time 106885598 ps
CPU time 1.88 seconds
Started Jul 25 07:09:17 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 209692 kb
Host smart-d8f36ef6-1ad6-4120-ae33-5bc228652819
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461468672 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3461468672
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2716745325
Short name T70
Test name
Test status
Simulation time 209784251 ps
CPU time 1.99 seconds
Started Jul 25 07:09:12 PM PDT 24
Finished Jul 25 07:09:14 PM PDT 24
Peak memory 209748 kb
Host smart-548477c9-ac38-4fb4-b8d9-718edf43fbe1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716745325 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2716745325
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.491373068
Short name T908
Test name
Test status
Simulation time 59887160 ps
CPU time 1.87 seconds
Started Jul 25 07:09:18 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 201228 kb
Host smart-5413d55d-112c-400b-ac83-73be0459f098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491373068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk
mgr_tl_errors.491373068
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.970436133
Short name T109
Test name
Test status
Simulation time 1759629717 ps
CPU time 6.51 seconds
Started Jul 25 07:09:09 PM PDT 24
Finished Jul 25 07:09:16 PM PDT 24
Peak memory 201288 kb
Host smart-d0b3f85f-79c3-4a7c-a2e2-bf93254d850e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970436133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_tl_intg_err.970436133
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.415736203
Short name T851
Test name
Test status
Simulation time 127483963 ps
CPU time 1.59 seconds
Started Jul 25 07:09:24 PM PDT 24
Finished Jul 25 07:09:26 PM PDT 24
Peak memory 201108 kb
Host smart-93de6557-bdc1-424f-8bac-5ca2f5b406d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415736203 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.415736203
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3041882860
Short name T882
Test name
Test status
Simulation time 15270379 ps
CPU time 0.8 seconds
Started Jul 25 07:09:28 PM PDT 24
Finished Jul 25 07:09:29 PM PDT 24
Peak memory 200972 kb
Host smart-c225988e-69bc-4302-b3c8-8acf9e8e764c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041882860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.3041882860
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.870635431
Short name T978
Test name
Test status
Simulation time 25949540 ps
CPU time 0.68 seconds
Started Jul 25 07:09:18 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 199620 kb
Host smart-58d0f1ac-c6d8-4e12-a4a0-067c7dfcf6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870635431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_intr_test.870635431
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.4012626253
Short name T880
Test name
Test status
Simulation time 38936495 ps
CPU time 0.93 seconds
Started Jul 25 07:09:25 PM PDT 24
Finished Jul 25 07:09:26 PM PDT 24
Peak memory 201040 kb
Host smart-9a458cbb-d9a1-4893-a297-7c2c58ef75ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012626253 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.4012626253
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3391000580
Short name T128
Test name
Test status
Simulation time 93148882 ps
CPU time 2.3 seconds
Started Jul 25 07:09:27 PM PDT 24
Finished Jul 25 07:09:29 PM PDT 24
Peak memory 209720 kb
Host smart-c92a89b1-8181-4281-8b18-9ba0ac25836b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391000580 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.3391000580
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.99285092
Short name T918
Test name
Test status
Simulation time 328528026 ps
CPU time 2.85 seconds
Started Jul 25 07:09:11 PM PDT 24
Finished Jul 25 07:09:14 PM PDT 24
Peak memory 201236 kb
Host smart-560de995-001d-4aa9-bb35-872f56c38309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99285092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkm
gr_tl_errors.99285092
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2089667717
Short name T99
Test name
Test status
Simulation time 194421526 ps
CPU time 2.1 seconds
Started Jul 25 07:09:09 PM PDT 24
Finished Jul 25 07:09:12 PM PDT 24
Peak memory 201328 kb
Host smart-903dd881-512a-4dad-9b87-25147dafabc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089667717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.2089667717
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3867769550
Short name T888
Test name
Test status
Simulation time 137109786 ps
CPU time 1.36 seconds
Started Jul 25 07:09:21 PM PDT 24
Finished Jul 25 07:09:23 PM PDT 24
Peak memory 201128 kb
Host smart-71993c05-fcfb-4253-9c9a-2dfbcfcdcee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867769550 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3867769550
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3668570734
Short name T936
Test name
Test status
Simulation time 18386267 ps
CPU time 0.77 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:31 PM PDT 24
Peak memory 200932 kb
Host smart-89d104f2-91c3-4163-9a9d-0fad7c54ccb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668570734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.3668570734
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2736548151
Short name T923
Test name
Test status
Simulation time 13399818 ps
CPU time 0.66 seconds
Started Jul 25 07:09:14 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 199648 kb
Host smart-d2a8f1c7-aedd-42d0-9211-7107041e8978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736548151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2736548151
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.4015256337
Short name T898
Test name
Test status
Simulation time 54195401 ps
CPU time 1.24 seconds
Started Jul 25 07:09:19 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 201100 kb
Host smart-ef2fea06-596a-4db4-8309-43437ea1c469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015256337 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.4015256337
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1990756833
Short name T69
Test name
Test status
Simulation time 157532250 ps
CPU time 1.92 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 201572 kb
Host smart-4df68218-fdb9-460b-9ccd-6dded00f20c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990756833 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.1990756833
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.4034530259
Short name T135
Test name
Test status
Simulation time 93190215 ps
CPU time 1.85 seconds
Started Jul 25 07:09:18 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 209676 kb
Host smart-8b875286-bc73-406c-99ff-f038f1b8c5f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034530259 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.4034530259
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1601077117
Short name T842
Test name
Test status
Simulation time 214604151 ps
CPU time 2.2 seconds
Started Jul 25 07:09:16 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 201308 kb
Host smart-412ad1c2-9e49-4d28-9485-7946e5003c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601077117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.1601077117
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.616664205
Short name T912
Test name
Test status
Simulation time 68879526 ps
CPU time 1.72 seconds
Started Jul 25 07:09:16 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 201284 kb
Host smart-91b3d7c6-2901-4dc3-9478-c04d4204f2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616664205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_tl_intg_err.616664205
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2104353840
Short name T897
Test name
Test status
Simulation time 38989207 ps
CPU time 1.5 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 201244 kb
Host smart-289e938a-4e81-47ab-97b2-e999aa02f5c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104353840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.2104353840
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1742678828
Short name T873
Test name
Test status
Simulation time 262027793 ps
CPU time 6.46 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 201140 kb
Host smart-e7672934-71a3-4657-a1ef-151ebc9840b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742678828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.1742678828
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2321172645
Short name T960
Test name
Test status
Simulation time 48508260 ps
CPU time 0.87 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 201040 kb
Host smart-b299893c-ad87-4139-bd3d-37db18f5987d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321172645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.2321172645
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.169842804
Short name T889
Test name
Test status
Simulation time 44765963 ps
CPU time 1.25 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 201104 kb
Host smart-bafe3fc4-8708-466c-b1ed-037451f711a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169842804 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.169842804
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.4113645905
Short name T103
Test name
Test status
Simulation time 108928415 ps
CPU time 1.08 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201048 kb
Host smart-fba16a87-7f98-4441-96ad-a1b1618b5c05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113645905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.4113645905
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.235860768
Short name T966
Test name
Test status
Simulation time 29884425 ps
CPU time 0.66 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 199540 kb
Host smart-18c1a11d-0ce4-4cbf-a0d7-9fae13aa8ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235860768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.235860768
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1468864609
Short name T902
Test name
Test status
Simulation time 29513900 ps
CPU time 1.03 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201076 kb
Host smart-48ba6efe-7598-48b6-9886-4d18a974ce2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468864609 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.1468864609
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3868444385
Short name T132
Test name
Test status
Simulation time 73782863 ps
CPU time 1.74 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 217856 kb
Host smart-72a8f877-032e-4afc-b0d8-39181394043d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868444385 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3868444385
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3240420015
Short name T840
Test name
Test status
Simulation time 603156221 ps
CPU time 4.84 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:09:01 PM PDT 24
Peak memory 201168 kb
Host smart-be5fb327-496a-4c15-b1f6-0324a77f28c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240420015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.3240420015
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1868312164
Short name T872
Test name
Test status
Simulation time 80734797 ps
CPU time 1.87 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201220 kb
Host smart-8d09868e-b477-4bb5-8522-ddefb8855962
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868312164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.1868312164
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2449534050
Short name T959
Test name
Test status
Simulation time 15288837 ps
CPU time 0.67 seconds
Started Jul 25 07:09:17 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 199652 kb
Host smart-8dec5f5a-4acb-4f32-aa26-9c05531b65e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449534050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2449534050
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1713363013
Short name T904
Test name
Test status
Simulation time 14661613 ps
CPU time 0.67 seconds
Started Jul 25 07:09:17 PM PDT 24
Finished Jul 25 07:09:17 PM PDT 24
Peak memory 199652 kb
Host smart-9c9f710d-2485-4a54-9067-e66877e72999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713363013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.1713363013
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.863767061
Short name T845
Test name
Test status
Simulation time 14035596 ps
CPU time 0.69 seconds
Started Jul 25 07:09:18 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 199704 kb
Host smart-0e5c301b-5aed-4261-a2bd-292a09a4a039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863767061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clk
mgr_intr_test.863767061
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1001187965
Short name T920
Test name
Test status
Simulation time 40918914 ps
CPU time 0.79 seconds
Started Jul 25 07:09:19 PM PDT 24
Finished Jul 25 07:09:20 PM PDT 24
Peak memory 199652 kb
Host smart-c3524c3f-4eb5-4d77-8309-604b6385b63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001187965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.1001187965
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3002520726
Short name T866
Test name
Test status
Simulation time 13375934 ps
CPU time 0.65 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:09:29 PM PDT 24
Peak memory 199740 kb
Host smart-df3b05f3-a2cf-4ebc-bdc0-c38d29cac535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002520726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.3002520726
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2418126038
Short name T833
Test name
Test status
Simulation time 14215612 ps
CPU time 0.73 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:09:30 PM PDT 24
Peak memory 199632 kb
Host smart-0a66c034-2191-4449-919f-b7f0c3170bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418126038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2418126038
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.430924479
Short name T980
Test name
Test status
Simulation time 14230840 ps
CPU time 0.73 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:09:30 PM PDT 24
Peak memory 199704 kb
Host smart-a4623519-f713-4cab-bfb6-582acb0d123a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430924479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clk
mgr_intr_test.430924479
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1370502408
Short name T947
Test name
Test status
Simulation time 13807250 ps
CPU time 0.68 seconds
Started Jul 25 07:09:27 PM PDT 24
Finished Jul 25 07:09:27 PM PDT 24
Peak memory 199656 kb
Host smart-5498de19-b09d-4d38-98b9-40d5cd9f47ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370502408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.1370502408
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2616177467
Short name T871
Test name
Test status
Simulation time 29297507 ps
CPU time 0.73 seconds
Started Jul 25 07:09:23 PM PDT 24
Finished Jul 25 07:09:24 PM PDT 24
Peak memory 199708 kb
Host smart-1e2969a3-5f7e-4b04-a123-81e696924d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616177467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.2616177467
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.850724616
Short name T832
Test name
Test status
Simulation time 33453013 ps
CPU time 0.7 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 199756 kb
Host smart-49633b2b-07ad-48b0-834d-c3515e0ff202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850724616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk
mgr_intr_test.850724616
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.127428391
Short name T981
Test name
Test status
Simulation time 200054772 ps
CPU time 2.01 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 201120 kb
Host smart-a326c07a-2a62-474d-a2dc-75101b27702e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127428391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_aliasing.127428391
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2193553075
Short name T909
Test name
Test status
Simulation time 264692515 ps
CPU time 6.76 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 201136 kb
Host smart-2d4b7fcb-ac89-4882-95ef-2ffb01e4721e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193553075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.2193553075
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1151545379
Short name T968
Test name
Test status
Simulation time 19587573 ps
CPU time 0.84 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:01 PM PDT 24
Peak memory 201040 kb
Host smart-2a21cea3-02aa-484e-b1e1-0ab39807079e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151545379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.1151545379
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3956478080
Short name T941
Test name
Test status
Simulation time 51622684 ps
CPU time 1.02 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:52 PM PDT 24
Peak memory 201128 kb
Host smart-ef753c9d-5c78-4741-b402-80c1e2d9e493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956478080 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.3956478080
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1793266015
Short name T877
Test name
Test status
Simulation time 16801384 ps
CPU time 0.77 seconds
Started Jul 25 07:09:01 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 200968 kb
Host smart-c8269c43-9f8f-4692-ae89-1697b21a7d16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793266015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.1793266015
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2958164465
Short name T917
Test name
Test status
Simulation time 12028229 ps
CPU time 0.69 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 199664 kb
Host smart-9d7eafc6-21eb-4672-9d8e-7424582933e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958164465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.2958164465
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1230332442
Short name T859
Test name
Test status
Simulation time 49203069 ps
CPU time 1.33 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 201264 kb
Host smart-0027f8f3-9af5-44d6-8532-24173c51917f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230332442 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.1230332442
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.706598142
Short name T120
Test name
Test status
Simulation time 87744666 ps
CPU time 1.67 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:56 PM PDT 24
Peak memory 201492 kb
Host smart-71e5a3c0-ce6d-44a8-b4e3-bb5742f7501c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706598142 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.706598142
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1110065165
Short name T916
Test name
Test status
Simulation time 71198184 ps
CPU time 2.21 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201260 kb
Host smart-0628b58a-d214-490a-a0c0-10d90c564182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110065165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.1110065165
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3120157021
Short name T854
Test name
Test status
Simulation time 19837664 ps
CPU time 0.7 seconds
Started Jul 25 07:09:27 PM PDT 24
Finished Jul 25 07:09:28 PM PDT 24
Peak memory 199664 kb
Host smart-3c3f43bd-c449-4db7-8db6-9bfae2e72124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120157021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.3120157021
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.4224866339
Short name T838
Test name
Test status
Simulation time 11255875 ps
CPU time 0.64 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:09:41 PM PDT 24
Peak memory 199796 kb
Host smart-63d47e39-be01-4ba6-b459-456a74d07121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224866339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.4224866339
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1791417391
Short name T926
Test name
Test status
Simulation time 22663061 ps
CPU time 0.75 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:09:30 PM PDT 24
Peak memory 199724 kb
Host smart-59c6b32b-7b3f-4241-9c60-f667b1f5d8c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791417391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.1791417391
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.864893339
Short name T890
Test name
Test status
Simulation time 28120172 ps
CPU time 0.69 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:09:33 PM PDT 24
Peak memory 199652 kb
Host smart-53912c64-972d-4f7d-9c6e-cc6565860e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864893339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clk
mgr_intr_test.864893339
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2589186795
Short name T837
Test name
Test status
Simulation time 21641468 ps
CPU time 0.69 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:09:41 PM PDT 24
Peak memory 199704 kb
Host smart-d85130ca-4110-41cc-a992-1bf710cd66fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589186795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.2589186795
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2784233427
Short name T963
Test name
Test status
Simulation time 10725854 ps
CPU time 0.67 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:35 PM PDT 24
Peak memory 199688 kb
Host smart-075b0a0d-a790-4d87-b48c-29da7263383d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784233427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.2784233427
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1996029019
Short name T896
Test name
Test status
Simulation time 45439857 ps
CPU time 0.73 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 199736 kb
Host smart-31f3e200-a2ce-4dff-a98b-10821b8a14c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996029019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.1996029019
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1875942363
Short name T910
Test name
Test status
Simulation time 33762877 ps
CPU time 0.71 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 199648 kb
Host smart-0b106533-6374-4345-bd68-1cc4f4af49ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875942363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.1875942363
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2426671396
Short name T979
Test name
Test status
Simulation time 27137938 ps
CPU time 0.65 seconds
Started Jul 25 07:09:27 PM PDT 24
Finished Jul 25 07:09:28 PM PDT 24
Peak memory 199536 kb
Host smart-d1e1d6f2-0bf6-4e4d-ad29-057317324d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426671396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2426671396
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2181359149
Short name T858
Test name
Test status
Simulation time 18912448 ps
CPU time 0.68 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:09:38 PM PDT 24
Peak memory 199668 kb
Host smart-59e616b2-4543-4de1-bfe3-ec15596a9935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181359149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.2181359149
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1295684189
Short name T867
Test name
Test status
Simulation time 75892838 ps
CPU time 1.96 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201192 kb
Host smart-e56872dc-c557-4a4c-b5f5-66d64e901b34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295684189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.1295684189
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3680820945
Short name T952
Test name
Test status
Simulation time 670248323 ps
CPU time 7.07 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:08 PM PDT 24
Peak memory 201200 kb
Host smart-e51eb5d4-b5b2-4968-81c2-77b424935764
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680820945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.3680820945
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.514914614
Short name T973
Test name
Test status
Simulation time 18304836 ps
CPU time 0.78 seconds
Started Jul 25 07:09:13 PM PDT 24
Finished Jul 25 07:09:14 PM PDT 24
Peak memory 200880 kb
Host smart-36113737-2dfe-430d-83ee-af1a8a262c77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514914614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.514914614
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.533375192
Short name T955
Test name
Test status
Simulation time 110715130 ps
CPU time 1.4 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 201132 kb
Host smart-64a68dcf-1392-417b-8e7f-e55b7b267532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533375192 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.533375192
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2199656520
Short name T894
Test name
Test status
Simulation time 19092600 ps
CPU time 0.79 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 200920 kb
Host smart-9b00e82e-0f00-4deb-8068-ba26d2810bb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199656520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.2199656520
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.808974837
Short name T852
Test name
Test status
Simulation time 10745040 ps
CPU time 0.68 seconds
Started Jul 25 07:08:53 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 199664 kb
Host smart-c73d3611-358b-481b-8551-d783e9a07348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808974837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkm
gr_intr_test.808974837
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2177603959
Short name T965
Test name
Test status
Simulation time 170333608 ps
CPU time 1.41 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 201036 kb
Host smart-4a541cec-0c54-4096-b90f-97f6d68f9856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177603959 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.2177603959
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.862659247
Short name T958
Test name
Test status
Simulation time 447208866 ps
CPU time 2.32 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201268 kb
Host smart-6eb99a66-547e-4e97-bb35-3985cffa3a08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862659247 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.clkmgr_shadow_reg_errors.862659247
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.651810328
Short name T131
Test name
Test status
Simulation time 63648863 ps
CPU time 1.71 seconds
Started Jul 25 07:08:52 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 210768 kb
Host smart-032f2a6c-5a0e-4371-9c68-ef38252b7a47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651810328 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.651810328
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1219979609
Short name T921
Test name
Test status
Simulation time 320698284 ps
CPU time 2.47 seconds
Started Jul 25 07:09:02 PM PDT 24
Finished Jul 25 07:09:04 PM PDT 24
Peak memory 201240 kb
Host smart-c9b38e4a-1ba1-4962-bfc1-79889d8ef970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219979609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.1219979609
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3463346458
Short name T883
Test name
Test status
Simulation time 81469543 ps
CPU time 1.54 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 201260 kb
Host smart-bc8200b3-7b63-48bd-a9a7-d9fd476fbc48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463346458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.3463346458
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1234986877
Short name T885
Test name
Test status
Simulation time 15116603 ps
CPU time 0.67 seconds
Started Jul 25 07:09:28 PM PDT 24
Finished Jul 25 07:09:29 PM PDT 24
Peak memory 199652 kb
Host smart-e47a5aa7-bb3a-481a-be01-67f34e1579ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234986877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.1234986877
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1758597229
Short name T887
Test name
Test status
Simulation time 29204421 ps
CPU time 0.7 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:31 PM PDT 24
Peak memory 199728 kb
Host smart-1986d28c-c855-4d03-a6ba-5ae9e61765b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758597229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.1758597229
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1103800464
Short name T924
Test name
Test status
Simulation time 54810933 ps
CPU time 0.75 seconds
Started Jul 25 07:09:26 PM PDT 24
Finished Jul 25 07:09:27 PM PDT 24
Peak memory 199656 kb
Host smart-e6cfba6b-b938-4e58-8eac-9ebae6b40ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103800464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.1103800464
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1006093021
Short name T950
Test name
Test status
Simulation time 20724124 ps
CPU time 0.72 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 199664 kb
Host smart-ddd93558-0a30-4e7d-9f5e-bb5089d2ddd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006093021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1006093021
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.4269147759
Short name T967
Test name
Test status
Simulation time 57467784 ps
CPU time 0.79 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:41 PM PDT 24
Peak memory 199652 kb
Host smart-076c24ba-7007-43a2-9fac-6824ec8b2513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269147759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.4269147759
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.352944662
Short name T860
Test name
Test status
Simulation time 44597168 ps
CPU time 0.75 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:09:38 PM PDT 24
Peak memory 199636 kb
Host smart-ccc07c7c-f9b4-43a6-92a4-31e25e583907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352944662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clk
mgr_intr_test.352944662
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.276133138
Short name T834
Test name
Test status
Simulation time 11744375 ps
CPU time 0.68 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:09:34 PM PDT 24
Peak memory 199616 kb
Host smart-38ff8587-80ce-4e80-a1d3-7b270d430fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276133138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clk
mgr_intr_test.276133138
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1822052683
Short name T905
Test name
Test status
Simulation time 20642899 ps
CPU time 0.67 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:30 PM PDT 24
Peak memory 199728 kb
Host smart-1d0b3d53-0a50-45ff-a2e3-1df985c2cd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822052683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.1822052683
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.905373258
Short name T855
Test name
Test status
Simulation time 11151114 ps
CPU time 0.65 seconds
Started Jul 25 07:14:25 PM PDT 24
Finished Jul 25 07:14:26 PM PDT 24
Peak memory 199668 kb
Host smart-d885c199-3cef-4490-9482-cc85de342672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905373258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clk
mgr_intr_test.905373258
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1605553880
Short name T893
Test name
Test status
Simulation time 14375145 ps
CPU time 0.76 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 199652 kb
Host smart-b5f61937-9934-492f-a776-2b19762d9e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605553880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.1605553880
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1626942090
Short name T104
Test name
Test status
Simulation time 109983125 ps
CPU time 1.34 seconds
Started Jul 25 07:09:01 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 201160 kb
Host smart-c109ca30-3f9d-4e86-9f3b-434f2422cefb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626942090 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1626942090
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2896361991
Short name T892
Test name
Test status
Simulation time 61224113 ps
CPU time 0.84 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:54 PM PDT 24
Peak memory 201196 kb
Host smart-953684fd-4575-4a82-925a-1b18859d1fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896361991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.2896361991
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1373865316
Short name T848
Test name
Test status
Simulation time 19150163 ps
CPU time 0.7 seconds
Started Jul 25 07:08:54 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 199788 kb
Host smart-0d129fd6-38ab-46fe-98a3-fa5cddf83cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373865316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.1373865316
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1580889042
Short name T90
Test name
Test status
Simulation time 28411405 ps
CPU time 1.02 seconds
Started Jul 25 07:08:59 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 201076 kb
Host smart-85e3e8a7-1512-4fb6-a0b7-fc28bdaceb7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580889042 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.1580889042
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1460121967
Short name T125
Test name
Test status
Simulation time 324552196 ps
CPU time 2.44 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 217692 kb
Host smart-30057695-31b5-46c3-bde0-abbdf6f37d4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460121967 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1460121967
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3719223330
Short name T913
Test name
Test status
Simulation time 80727872 ps
CPU time 1.7 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 201652 kb
Host smart-8401b756-d087-4d28-9d7b-e4d0986fad6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719223330 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3719223330
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1536449632
Short name T945
Test name
Test status
Simulation time 485195809 ps
CPU time 4.22 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:55 PM PDT 24
Peak memory 209464 kb
Host smart-f8044ee8-0fe7-4fcc-b417-283abb1dbaa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536449632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.1536449632
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2629705648
Short name T110
Test name
Test status
Simulation time 271128069 ps
CPU time 2.28 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201248 kb
Host smart-ef2998e6-94bc-49b3-b8bf-a5cf653e6774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629705648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.2629705648
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.4264626339
Short name T901
Test name
Test status
Simulation time 17656569 ps
CPU time 0.94 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201116 kb
Host smart-6c18d494-e063-4f93-a391-fa0ffb515747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264626339 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.4264626339
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2974253844
Short name T932
Test name
Test status
Simulation time 37625370 ps
CPU time 0.84 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:01 PM PDT 24
Peak memory 201068 kb
Host smart-00b08069-ac32-46f3-9658-c46ba7fa823c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974253844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.2974253844
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.274586058
Short name T841
Test name
Test status
Simulation time 12368511 ps
CPU time 0.7 seconds
Started Jul 25 07:09:02 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 199656 kb
Host smart-7a64e475-fbb2-4637-a3a0-e33b9ca86f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274586058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm
gr_intr_test.274586058
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.128411802
Short name T929
Test name
Test status
Simulation time 111576055 ps
CPU time 1.56 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201244 kb
Host smart-2827e2a1-1fd9-46e0-870b-6181a9dc212c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128411802 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.clkmgr_same_csr_outstanding.128411802
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1048847299
Short name T71
Test name
Test status
Simulation time 291465552 ps
CPU time 2.21 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 209728 kb
Host smart-066a2cb9-3836-4796-adf2-338bb2b49a7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048847299 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.1048847299
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2560528305
Short name T956
Test name
Test status
Simulation time 129197930 ps
CPU time 2.68 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 209668 kb
Host smart-988bd2cd-d3f4-41c0-beb0-0bbeb303a1ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560528305 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.2560528305
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3429325742
Short name T943
Test name
Test status
Simulation time 90261575 ps
CPU time 3.08 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:09:01 PM PDT 24
Peak memory 201256 kb
Host smart-18ca8c84-c178-49e1-aea9-1e6540998f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429325742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.3429325742
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2840730440
Short name T914
Test name
Test status
Simulation time 27829270 ps
CPU time 1.05 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 200976 kb
Host smart-b9f370d7-0833-4890-b6df-5aba2b509f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840730440 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.2840730440
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2085178546
Short name T89
Test name
Test status
Simulation time 18685826 ps
CPU time 0.82 seconds
Started Jul 25 07:08:51 PM PDT 24
Finished Jul 25 07:08:52 PM PDT 24
Peak memory 201048 kb
Host smart-ff036f4b-37bb-404c-a5c5-548fa131c858
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085178546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.2085178546
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3326616291
Short name T976
Test name
Test status
Simulation time 12042941 ps
CPU time 0.67 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 199656 kb
Host smart-8f212cdf-d4d1-4c9c-98d6-49ab12cf0acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326616291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3326616291
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1811907674
Short name T884
Test name
Test status
Simulation time 87258742 ps
CPU time 1.48 seconds
Started Jul 25 07:09:17 PM PDT 24
Finished Jul 25 07:09:19 PM PDT 24
Peak memory 201232 kb
Host smart-fb0e93ea-a313-42c0-8800-9edf4d911c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811907674 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.1811907674
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.788484172
Short name T911
Test name
Test status
Simulation time 104134136 ps
CPU time 1.28 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 201304 kb
Host smart-9c8366c6-0d41-4582-a9fa-afa810bbb487
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788484172 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.clkmgr_shadow_reg_errors.788484172
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3000334833
Short name T67
Test name
Test status
Simulation time 159605671 ps
CPU time 1.98 seconds
Started Jul 25 07:08:55 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 201644 kb
Host smart-5f4e84cc-15ba-4b4d-b500-e1b2e67c44c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000334833 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3000334833
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2753947502
Short name T865
Test name
Test status
Simulation time 38324135 ps
CPU time 2.27 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 201272 kb
Host smart-1c3b77d1-72a4-4364-b7d3-0e5d92faa44f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753947502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.2753947502
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.656672806
Short name T106
Test name
Test status
Simulation time 239189632 ps
CPU time 2.66 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 201216 kb
Host smart-98bfabef-5bcd-428f-9a35-e44372f6f030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656672806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.clkmgr_tl_intg_err.656672806
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3630432614
Short name T849
Test name
Test status
Simulation time 71319323 ps
CPU time 1.45 seconds
Started Jul 25 07:08:59 PM PDT 24
Finished Jul 25 07:09:01 PM PDT 24
Peak memory 201036 kb
Host smart-45765f8f-a94c-4827-819f-72e358292d77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630432614 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.3630432614
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1307953536
Short name T919
Test name
Test status
Simulation time 20538086 ps
CPU time 0.82 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201056 kb
Host smart-bda02453-bd44-4339-8d59-09d4994dd023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307953536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.1307953536
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3704357189
Short name T946
Test name
Test status
Simulation time 12947411 ps
CPU time 0.66 seconds
Started Jul 25 07:08:58 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 199724 kb
Host smart-25d12e99-82db-408c-a994-8c232de94c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704357189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.3704357189
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1207624845
Short name T969
Test name
Test status
Simulation time 42809017 ps
CPU time 1 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:01 PM PDT 24
Peak memory 201060 kb
Host smart-c6566c49-05ca-443d-80ab-87b14ec299a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207624845 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.1207624845
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1586708085
Short name T137
Test name
Test status
Simulation time 137920381 ps
CPU time 2.07 seconds
Started Jul 25 07:08:50 PM PDT 24
Finished Jul 25 07:08:53 PM PDT 24
Peak memory 201488 kb
Host smart-f94edd1a-dd6d-4926-aa0f-e0688fe4dae0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586708085 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1586708085
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2452830730
Short name T130
Test name
Test status
Simulation time 239551012 ps
CPU time 2.11 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:08:59 PM PDT 24
Peak memory 201492 kb
Host smart-80261abb-c8e9-4116-a3a4-eeb185dd2866
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452830730 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2452830730
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.249256384
Short name T935
Test name
Test status
Simulation time 63122465 ps
CPU time 2.23 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201204 kb
Host smart-7347ce67-e877-4797-ae04-bd3aa2abd4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249256384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.249256384
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2173469322
Short name T931
Test name
Test status
Simulation time 135631188 ps
CPU time 2.81 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:09:00 PM PDT 24
Peak memory 201068 kb
Host smart-8ec818e7-5994-49c9-afd3-7058cfdd4ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173469322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.2173469322
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.685212052
Short name T937
Test name
Test status
Simulation time 46032094 ps
CPU time 0.96 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 201116 kb
Host smart-51b22994-62cf-445c-8ecd-75e89c35c71c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685212052 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.685212052
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3035222464
Short name T970
Test name
Test status
Simulation time 34799393 ps
CPU time 0.78 seconds
Started Jul 25 07:09:02 PM PDT 24
Finished Jul 25 07:09:03 PM PDT 24
Peak memory 200988 kb
Host smart-0b6820e0-3f5b-432c-837c-9631a0a568a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035222464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3035222464
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1579081151
Short name T868
Test name
Test status
Simulation time 20306255 ps
CPU time 0.67 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 199604 kb
Host smart-bc1539b0-1ac4-4478-9f5c-22223fb01eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579081151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.1579081151
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1278315416
Short name T874
Test name
Test status
Simulation time 90247212 ps
CPU time 1.23 seconds
Started Jul 25 07:09:00 PM PDT 24
Finished Jul 25 07:09:02 PM PDT 24
Peak memory 201040 kb
Host smart-492e0019-5ae6-43e9-b98c-7f9235286ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278315416 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.1278315416
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3769839269
Short name T63
Test name
Test status
Simulation time 91607901 ps
CPU time 1.31 seconds
Started Jul 25 07:08:57 PM PDT 24
Finished Jul 25 07:08:58 PM PDT 24
Peak memory 201136 kb
Host smart-16ebdd0e-c9b9-48ce-92cf-09342d5f558b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769839269 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.3769839269
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2292889437
Short name T122
Test name
Test status
Simulation time 171457656 ps
CPU time 1.83 seconds
Started Jul 25 07:09:06 PM PDT 24
Finished Jul 25 07:09:08 PM PDT 24
Peak memory 209676 kb
Host smart-ef650d1f-72f3-46ec-ac2e-759838e000e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292889437 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.2292889437
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1905250304
Short name T835
Test name
Test status
Simulation time 24165288 ps
CPU time 1.38 seconds
Started Jul 25 07:08:56 PM PDT 24
Finished Jul 25 07:08:57 PM PDT 24
Peak memory 201316 kb
Host smart-0f8bb776-5fdb-4de1-bdb9-9e86be9eb194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905250304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.1905250304
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.916516117
Short name T361
Test name
Test status
Simulation time 51486609 ps
CPU time 0.85 seconds
Started Jul 25 07:14:14 PM PDT 24
Finished Jul 25 07:14:16 PM PDT 24
Peak memory 200512 kb
Host smart-b21ddb5e-6112-4429-bb44-1954e9e85e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916516117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_alert_test.916516117
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.126160912
Short name T171
Test name
Test status
Simulation time 15017564 ps
CPU time 0.67 seconds
Started Jul 25 07:14:15 PM PDT 24
Finished Jul 25 07:14:16 PM PDT 24
Peak memory 200420 kb
Host smart-f29a1015-c737-4c5f-a81d-fc07ea91c0f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126160912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.126160912
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.174487750
Short name T370
Test name
Test status
Simulation time 17547531 ps
CPU time 0.83 seconds
Started Jul 25 07:14:14 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200536 kb
Host smart-fe7444e4-632e-4a5b-bf6b-072d523b8072
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174487750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_div_intersig_mubi.174487750
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.3397542032
Short name T819
Test name
Test status
Simulation time 318332753 ps
CPU time 1.72 seconds
Started Jul 25 07:14:17 PM PDT 24
Finished Jul 25 07:14:19 PM PDT 24
Peak memory 200524 kb
Host smart-d6ad822a-1bcf-4575-8063-e8bca92c29c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397542032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3397542032
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.638797359
Short name T333
Test name
Test status
Simulation time 480888043 ps
CPU time 2.35 seconds
Started Jul 25 07:14:12 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200560 kb
Host smart-4f6d7604-4ac3-4cf4-9c9b-af669d7711aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638797359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.638797359
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.1967949617
Short name T59
Test name
Test status
Simulation time 620975047 ps
CPU time 4.66 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:18 PM PDT 24
Peak memory 200636 kb
Host smart-80539966-5f32-42b3-9fe2-12db0a674c67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967949617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.1967949617
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.705617140
Short name T516
Test name
Test status
Simulation time 31112997 ps
CPU time 0.97 seconds
Started Jul 25 07:14:14 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200508 kb
Host smart-a6b1649f-3326-4fe0-bca3-77612d43ac70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705617140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.705617140
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2104294844
Short name T353
Test name
Test status
Simulation time 14181977 ps
CPU time 0.75 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:14 PM PDT 24
Peak memory 200500 kb
Host smart-b1c02c4e-0856-46e2-b3e8-6fc02ca6658e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104294844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.2104294844
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.3362470139
Short name T239
Test name
Test status
Simulation time 28599368 ps
CPU time 0.85 seconds
Started Jul 25 07:14:14 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200512 kb
Host smart-d9b44104-282f-4a89-b328-a5afbd8a12f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362470139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.3362470139
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.1431946011
Short name T533
Test name
Test status
Simulation time 18562528 ps
CPU time 0.82 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:14 PM PDT 24
Peak memory 200516 kb
Host smart-1c40c327-3795-4607-b261-61707251bd79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431946011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.1431946011
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.657586350
Short name T416
Test name
Test status
Simulation time 867393359 ps
CPU time 3.89 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:17 PM PDT 24
Peak memory 200708 kb
Host smart-12cacda4-0e60-4d5b-8721-f450e2f910f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657586350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.657586350
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.902798682
Short name T62
Test name
Test status
Simulation time 462329364 ps
CPU time 2.85 seconds
Started Jul 25 07:14:16 PM PDT 24
Finished Jul 25 07:14:19 PM PDT 24
Peak memory 216040 kb
Host smart-f0cf2cb6-15af-4179-9a07-24e8d0028108
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902798682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_sec_cm.902798682
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.3976295491
Short name T145
Test name
Test status
Simulation time 22674778 ps
CPU time 0.9 seconds
Started Jul 25 07:14:04 PM PDT 24
Finished Jul 25 07:14:05 PM PDT 24
Peak memory 200464 kb
Host smart-702eb6fa-ce75-4502-ba9f-1aab0a5b8c81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976295491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3976295491
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_trans.3278082361
Short name T329
Test name
Test status
Simulation time 39088606 ps
CPU time 0.9 seconds
Started Jul 25 07:14:12 PM PDT 24
Finished Jul 25 07:14:13 PM PDT 24
Peak memory 200560 kb
Host smart-394b90fb-7d59-4ef6-bb6c-d82335c2914f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278082361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.3278082361
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.854633073
Short name T766
Test name
Test status
Simulation time 40553816 ps
CPU time 0.82 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:14 PM PDT 24
Peak memory 200472 kb
Host smart-0311d7e7-1c35-4f72-a29c-cdb816a5871b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854633073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_alert_test.854633073
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.317975231
Short name T91
Test name
Test status
Simulation time 27233819 ps
CPU time 0.94 seconds
Started Jul 25 07:14:14 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200544 kb
Host smart-0fc7f0bf-4229-4ed4-b133-8f4addc7426c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317975231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.317975231
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.3643209310
Short name T178
Test name
Test status
Simulation time 53007696 ps
CPU time 0.87 seconds
Started Jul 25 07:14:12 PM PDT 24
Finished Jul 25 07:14:13 PM PDT 24
Peak memory 199708 kb
Host smart-1ecb9b28-acd3-46a9-9ebc-77abde5acf7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643209310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3643209310
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3096037777
Short name T497
Test name
Test status
Simulation time 16060267 ps
CPU time 0.75 seconds
Started Jul 25 07:14:12 PM PDT 24
Finished Jul 25 07:14:13 PM PDT 24
Peak memory 200544 kb
Host smart-bc8d7d7d-4698-45cc-a7ab-45ae4c5bcbc2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096037777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3096037777
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.1922993343
Short name T614
Test name
Test status
Simulation time 81436578 ps
CPU time 1.14 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:14 PM PDT 24
Peak memory 200500 kb
Host smart-32fb7b6e-82f8-4109-bc81-aad947723ab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922993343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1922993343
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.3146748925
Short name T3
Test name
Test status
Simulation time 991895992 ps
CPU time 4.22 seconds
Started Jul 25 07:14:11 PM PDT 24
Finished Jul 25 07:14:16 PM PDT 24
Peak memory 200560 kb
Host smart-2f7e073d-58c3-46d6-9b4d-5c72f1b6638a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146748925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3146748925
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.2150093804
Short name T203
Test name
Test status
Simulation time 2320855644 ps
CPU time 9.72 seconds
Started Jul 25 07:14:15 PM PDT 24
Finished Jul 25 07:14:25 PM PDT 24
Peak memory 200864 kb
Host smart-756755cd-bac5-4bec-83ea-35c845cc6e91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150093804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.2150093804
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2812297413
Short name T643
Test name
Test status
Simulation time 155903514 ps
CPU time 1.28 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200508 kb
Host smart-22212945-e7ed-4c6b-9c1c-13865b287dd6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812297413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.2812297413
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2821207455
Short name T763
Test name
Test status
Simulation time 52994755 ps
CPU time 0.87 seconds
Started Jul 25 07:14:16 PM PDT 24
Finished Jul 25 07:14:17 PM PDT 24
Peak memory 200516 kb
Host smart-91f06353-52b8-4fdd-bfbc-5e200c2b4f21
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821207455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.2821207455
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1217671898
Short name T8
Test name
Test status
Simulation time 34186203 ps
CPU time 0.84 seconds
Started Jul 25 07:14:15 PM PDT 24
Finished Jul 25 07:14:16 PM PDT 24
Peak memory 200496 kb
Host smart-4a9d09f6-308c-4eb0-86ad-508b0f538376
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217671898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.1217671898
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.1776197312
Short name T704
Test name
Test status
Simulation time 22301351 ps
CPU time 0.81 seconds
Started Jul 25 07:14:14 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200512 kb
Host smart-13ef204b-263c-4f8a-8a15-2c40c9fbff46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776197312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1776197312
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.3956497272
Short name T809
Test name
Test status
Simulation time 1707306311 ps
CPU time 5.8 seconds
Started Jul 25 07:14:12 PM PDT 24
Finished Jul 25 07:14:18 PM PDT 24
Peak memory 200716 kb
Host smart-f0bf569b-1389-498e-8a2e-0bdd90524fbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956497272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3956497272
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.2059856751
Short name T751
Test name
Test status
Simulation time 19438840 ps
CPU time 0.86 seconds
Started Jul 25 07:14:13 PM PDT 24
Finished Jul 25 07:14:14 PM PDT 24
Peak memory 200448 kb
Host smart-c1175933-0edf-4f7a-957e-1cbe244822e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059856751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2059856751
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.615302800
Short name T248
Test name
Test status
Simulation time 12437931680 ps
CPU time 44.43 seconds
Started Jul 25 07:14:15 PM PDT 24
Finished Jul 25 07:15:00 PM PDT 24
Peak memory 200876 kb
Host smart-f678ffd1-e65c-452c-bef3-bf192d4b7da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615302800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.615302800
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.2495558534
Short name T650
Test name
Test status
Simulation time 22731479 ps
CPU time 0.86 seconds
Started Jul 25 07:14:15 PM PDT 24
Finished Jul 25 07:14:16 PM PDT 24
Peak memory 200500 kb
Host smart-996bee69-2ae5-4201-881d-18419dbfb7f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495558534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2495558534
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.3671603671
Short name T514
Test name
Test status
Simulation time 45164748 ps
CPU time 0.82 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 200552 kb
Host smart-ce45470e-6a01-485b-993c-f6c817807f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671603671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.3671603671
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.3958778974
Short name T439
Test name
Test status
Simulation time 27138161 ps
CPU time 0.83 seconds
Started Jul 25 07:14:44 PM PDT 24
Finished Jul 25 07:14:45 PM PDT 24
Peak memory 200536 kb
Host smart-74552be4-6ba2-46a7-a043-2492a99a8a9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958778974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.3958778974
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.3493793753
Short name T622
Test name
Test status
Simulation time 49756232 ps
CPU time 0.75 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:40 PM PDT 24
Peak memory 200428 kb
Host smart-ecca4c46-3c4e-47c9-88ca-4af52ad67cc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493793753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3493793753
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.344803384
Short name T424
Test name
Test status
Simulation time 24941525 ps
CPU time 0.85 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200492 kb
Host smart-ea5977bf-400a-4be8-ab66-29ff5ea6bbaf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344803384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_div_intersig_mubi.344803384
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.3199717057
Short name T271
Test name
Test status
Simulation time 82822027 ps
CPU time 1.05 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200520 kb
Host smart-b9932583-714b-461c-8586-0f9d70b5e666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199717057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3199717057
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.551513436
Short name T266
Test name
Test status
Simulation time 1275009213 ps
CPU time 9.9 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200580 kb
Host smart-07796df2-8756-4861-9330-33393dedc566
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551513436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.551513436
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.3554487196
Short name T524
Test name
Test status
Simulation time 1231833097 ps
CPU time 5.26 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:48 PM PDT 24
Peak memory 200600 kb
Host smart-2b3e62db-f545-44a5-9bf3-98a28ab9286c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554487196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.3554487196
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.574128245
Short name T454
Test name
Test status
Simulation time 45045802 ps
CPU time 0.85 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 200532 kb
Host smart-03f5c224-afdc-4f34-a522-bfc0ff733da9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574128245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_clk_byp_req_intersig_mubi.574128245
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.937307171
Short name T346
Test name
Test status
Simulation time 52022835 ps
CPU time 0.82 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 200528 kb
Host smart-d2e7bef8-ba39-4da9-af77-16251acb1116
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937307171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.937307171
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.3641649231
Short name T784
Test name
Test status
Simulation time 16595414 ps
CPU time 0.76 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 200496 kb
Host smart-d0a7753c-bcea-429b-afb1-6596f404fffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641649231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3641649231
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.2522568655
Short name T584
Test name
Test status
Simulation time 400869365 ps
CPU time 2.69 seconds
Started Jul 25 07:14:41 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200496 kb
Host smart-8a12ef15-64d6-4901-a988-884f8a5b3b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522568655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2522568655
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.1427503653
Short name T506
Test name
Test status
Simulation time 28265739 ps
CPU time 1.05 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200444 kb
Host smart-5495ff4c-7b9d-4e22-bc6b-b549a2992a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427503653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1427503653
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.91990885
Short name T742
Test name
Test status
Simulation time 2613201739 ps
CPU time 13.68 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:57 PM PDT 24
Peak memory 200836 kb
Host smart-d088e273-71ec-43f8-a287-08aebfce05e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91990885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_stress_all.91990885
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.4157767845
Short name T210
Test name
Test status
Simulation time 39994597 ps
CPU time 1.12 seconds
Started Jul 25 07:14:45 PM PDT 24
Finished Jul 25 07:14:47 PM PDT 24
Peak memory 200476 kb
Host smart-e249a82e-f28d-4f8d-b3d6-8e0bed6842ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157767845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.4157767845
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.288072598
Short name T601
Test name
Test status
Simulation time 11922903 ps
CPU time 0.81 seconds
Started Jul 25 07:14:46 PM PDT 24
Finished Jul 25 07:14:47 PM PDT 24
Peak memory 200480 kb
Host smart-d2b44c3d-d2e1-4eef-ba19-3b8fc97adb8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288072598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkm
gr_alert_test.288072598
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1955179646
Short name T168
Test name
Test status
Simulation time 43355310 ps
CPU time 0.82 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200524 kb
Host smart-01f23dc8-db78-41eb-86ea-5e7b447307b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955179646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1955179646
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.3482076597
Short name T617
Test name
Test status
Simulation time 25782555 ps
CPU time 0.75 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 199700 kb
Host smart-8d9124be-805c-4c96-8367-628ed3fa75c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482076597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3482076597
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.2668625781
Short name T341
Test name
Test status
Simulation time 237669645 ps
CPU time 1.53 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:45 PM PDT 24
Peak memory 200508 kb
Host smart-61320f09-bfdc-436e-8902-f0376e41704a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668625781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.2668625781
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.1833325660
Short name T463
Test name
Test status
Simulation time 237096754 ps
CPU time 1.49 seconds
Started Jul 25 07:14:44 PM PDT 24
Finished Jul 25 07:14:46 PM PDT 24
Peak memory 200476 kb
Host smart-bd62e9cd-d09b-480c-81e3-5408bf5db456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833325660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.1833325660
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.1331807680
Short name T645
Test name
Test status
Simulation time 1005878011 ps
CPU time 4.09 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:46 PM PDT 24
Peak memory 200572 kb
Host smart-791a2f19-cf62-4b28-800c-b0592425572d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331807680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1331807680
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.2417633288
Short name T608
Test name
Test status
Simulation time 1245191056 ps
CPU time 5.15 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:48 PM PDT 24
Peak memory 200600 kb
Host smart-00f6e6fd-4e76-410e-a477-dbaa1a60fef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417633288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.2417633288
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.875960129
Short name T198
Test name
Test status
Simulation time 66475050 ps
CPU time 1.14 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200496 kb
Host smart-aded003a-a1b9-424a-a1a8-610b59447052
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875960129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.clkmgr_idle_intersig_mubi.875960129
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1692170625
Short name T428
Test name
Test status
Simulation time 134880931 ps
CPU time 1.09 seconds
Started Jul 25 07:14:44 PM PDT 24
Finished Jul 25 07:14:45 PM PDT 24
Peak memory 200460 kb
Host smart-7a60fb21-2b8d-4f80-8d0a-4b0309dd03fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692170625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1692170625
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2096605509
Short name T410
Test name
Test status
Simulation time 27683572 ps
CPU time 0.95 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200508 kb
Host smart-0f60a50c-220c-4f48-8abb-a77e90e05c4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096605509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.2096605509
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.4263848104
Short name T422
Test name
Test status
Simulation time 19791199 ps
CPU time 0.81 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 200500 kb
Host smart-da0578ef-b8bc-440a-b073-881e83ea779b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263848104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.4263848104
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.529218050
Short name T427
Test name
Test status
Simulation time 694298271 ps
CPU time 3.04 seconds
Started Jul 25 07:14:46 PM PDT 24
Finished Jul 25 07:14:49 PM PDT 24
Peak memory 200660 kb
Host smart-be7b45d5-03f7-413e-a80f-187c39b07ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529218050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.529218050
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.53333687
Short name T731
Test name
Test status
Simulation time 240045996 ps
CPU time 1.45 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 200448 kb
Host smart-875b93f6-30f6-4cfb-a674-c5845056745c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53333687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.53333687
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.649998337
Short name T411
Test name
Test status
Simulation time 80135414 ps
CPU time 1.43 seconds
Started Jul 25 07:14:41 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200516 kb
Host smart-9aaefb00-037c-4add-bf0a-a4be9e798416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649998337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.649998337
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.3193187983
Short name T365
Test name
Test status
Simulation time 44825316 ps
CPU time 1.08 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200496 kb
Host smart-8e897eba-60b6-4028-bf49-0737639e5abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193187983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3193187983
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.1891427508
Short name T530
Test name
Test status
Simulation time 123104057 ps
CPU time 1.09 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200532 kb
Host smart-87829b5a-0c84-418a-97ef-ce4eca096ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891427508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.1891427508
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3265829720
Short name T529
Test name
Test status
Simulation time 87681254 ps
CPU time 1.04 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:55 PM PDT 24
Peak memory 200492 kb
Host smart-664ad2e1-3c28-49c3-a48d-bc5bb5e30881
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265829720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3265829720
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.2967883772
Short name T653
Test name
Test status
Simulation time 44643131 ps
CPU time 0.77 seconds
Started Jul 25 07:14:41 PM PDT 24
Finished Jul 25 07:14:42 PM PDT 24
Peak memory 199716 kb
Host smart-b87ab2dd-03e7-4998-abb8-97db7eb92ee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967883772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.2967883772
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.1688231690
Short name T802
Test name
Test status
Simulation time 102203511 ps
CPU time 1.03 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200504 kb
Host smart-b574809c-4d51-4355-8aca-fdef5b95ace4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688231690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.1688231690
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.2215655031
Short name T686
Test name
Test status
Simulation time 14051443 ps
CPU time 0.76 seconds
Started Jul 25 07:14:44 PM PDT 24
Finished Jul 25 07:14:45 PM PDT 24
Peak memory 200480 kb
Host smart-92e002f1-81eb-45c2-b33c-2c4f01184ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215655031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.2215655031
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.825063877
Short name T699
Test name
Test status
Simulation time 555922667 ps
CPU time 4.66 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:48 PM PDT 24
Peak memory 200568 kb
Host smart-31b2ed34-9d6b-410b-97de-30a4b47b7926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825063877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.825063877
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.636466632
Short name T332
Test name
Test status
Simulation time 2444282500 ps
CPU time 9.97 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200868 kb
Host smart-d59fb59e-44f9-478a-817a-0b9333746467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636466632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_ti
meout.636466632
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2585019262
Short name T641
Test name
Test status
Simulation time 23937741 ps
CPU time 0.83 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200516 kb
Host smart-50a371b0-c193-47a1-a583-c237b42b919b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585019262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.2585019262
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1218855684
Short name T164
Test name
Test status
Simulation time 13956858 ps
CPU time 0.72 seconds
Started Jul 25 07:14:48 PM PDT 24
Finished Jul 25 07:14:49 PM PDT 24
Peak memory 200512 kb
Host smart-a5df66ca-c6cf-4fd0-b1a0-5f7ef43dd1bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218855684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1218855684
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.895567502
Short name T27
Test name
Test status
Simulation time 47793962 ps
CPU time 1.01 seconds
Started Jul 25 07:14:54 PM PDT 24
Finished Jul 25 07:14:55 PM PDT 24
Peak memory 200500 kb
Host smart-90b2a79e-643d-4e05-acf6-d6eb8ec799e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895567502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_ctrl_intersig_mubi.895567502
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.2549066824
Short name T726
Test name
Test status
Simulation time 19242740 ps
CPU time 0.77 seconds
Started Jul 25 07:14:42 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200460 kb
Host smart-1eebe21c-65c9-463c-8a79-ac2088334948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549066824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2549066824
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.1391634752
Short name T781
Test name
Test status
Simulation time 277827212 ps
CPU time 2.01 seconds
Started Jul 25 07:14:57 PM PDT 24
Finished Jul 25 07:14:59 PM PDT 24
Peak memory 200496 kb
Host smart-95ea862d-b585-4785-963f-4d171f02f79d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391634752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1391634752
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.1543880580
Short name T403
Test name
Test status
Simulation time 22235790 ps
CPU time 0.85 seconds
Started Jul 25 07:14:43 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 200508 kb
Host smart-8db8194d-d5b7-4df4-ae40-3a59864f7947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543880580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1543880580
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.1848659123
Short name T592
Test name
Test status
Simulation time 118359490 ps
CPU time 1.08 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200540 kb
Host smart-e6444179-b445-4d99-a086-a734a67a3c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848659123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.1848659123
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.3548224684
Short name T342
Test name
Test status
Simulation time 111648637 ps
CPU time 1.07 seconds
Started Jul 25 07:14:45 PM PDT 24
Finished Jul 25 07:14:46 PM PDT 24
Peak memory 200512 kb
Host smart-8e3d7c78-5e69-4600-91e0-e5507ea49f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548224684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.3548224684
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.418867428
Short name T431
Test name
Test status
Simulation time 37039841 ps
CPU time 0.78 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200528 kb
Host smart-e7ec2e25-54e9-4b66-94bc-50bcf711ebfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418867428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkm
gr_alert_test.418867428
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2069158875
Short name T526
Test name
Test status
Simulation time 82713767 ps
CPU time 1.06 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200520 kb
Host smart-76390bf6-c110-4cc4-8f25-3139ae16120c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069158875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.2069158875
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.1146073816
Short name T628
Test name
Test status
Simulation time 51883516 ps
CPU time 0.79 seconds
Started Jul 25 07:14:54 PM PDT 24
Finished Jul 25 07:14:55 PM PDT 24
Peak memory 199724 kb
Host smart-e05a7b03-7ca0-4d1a-8348-914d10a9217e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146073816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1146073816
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2338979188
Short name T624
Test name
Test status
Simulation time 21731811 ps
CPU time 0.75 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200476 kb
Host smart-da070e73-0b74-41ed-84a4-696e626667de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338979188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.2338979188
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.3860452072
Short name T191
Test name
Test status
Simulation time 28992530 ps
CPU time 0.75 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200532 kb
Host smart-e7d06e7d-de0a-4abc-90cf-b6899587dccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860452072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3860452072
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3955638935
Short name T775
Test name
Test status
Simulation time 2239292240 ps
CPU time 17.28 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:15:09 PM PDT 24
Peak memory 200828 kb
Host smart-2cbb907c-f075-46d9-8471-3a75e4d37367
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955638935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3955638935
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.3612473481
Short name T201
Test name
Test status
Simulation time 1008245581 ps
CPU time 4.2 seconds
Started Jul 25 07:14:55 PM PDT 24
Finished Jul 25 07:14:59 PM PDT 24
Peak memory 200620 kb
Host smart-c3726340-1c45-47d1-a2f7-4c782f8ec7cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612473481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.3612473481
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.711507643
Short name T444
Test name
Test status
Simulation time 31131462 ps
CPU time 0.98 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200440 kb
Host smart-b61c3b08-d280-4381-bdb6-7b2bcf15ce3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711507643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.clkmgr_idle_intersig_mubi.711507643
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.3382004210
Short name T478
Test name
Test status
Simulation time 15953649 ps
CPU time 0.76 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200540 kb
Host smart-19a1ab4d-617f-4c68-81e8-7b68e38b1b45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382004210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.3382004210
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.54093122
Short name T623
Test name
Test status
Simulation time 24130760 ps
CPU time 0.77 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200532 kb
Host smart-b9bf5336-1e81-4e09-b2c9-61c150df545e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54093122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_lc_ctrl_intersig_mubi.54093122
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.1383200104
Short name T418
Test name
Test status
Simulation time 41260843 ps
CPU time 0.81 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200492 kb
Host smart-5de23232-e0c3-4b70-b752-5fbadab3d3c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383200104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1383200104
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.2335699728
Short name T155
Test name
Test status
Simulation time 1066157132 ps
CPU time 4.83 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:56 PM PDT 24
Peak memory 200660 kb
Host smart-1c694365-f561-4db4-9f4c-644d81d7ac01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335699728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.2335699728
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1817520838
Short name T806
Test name
Test status
Simulation time 52163833 ps
CPU time 0.91 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200460 kb
Host smart-e50bb5fb-388d-4c7f-a655-f1966cfa3560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817520838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1817520838
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.1887503039
Short name T771
Test name
Test status
Simulation time 2677635657 ps
CPU time 15.08 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:15:07 PM PDT 24
Peak memory 200960 kb
Host smart-d291a351-ef7e-49bf-8302-45cfb1973d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887503039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.1887503039
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.3571094637
Short name T669
Test name
Test status
Simulation time 23311229 ps
CPU time 0.89 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200528 kb
Host smart-f1c59b7e-bb70-40cc-9e84-d571a178aaa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571094637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3571094637
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.1645265080
Short name T307
Test name
Test status
Simulation time 54523640 ps
CPU time 0.9 seconds
Started Jul 25 07:14:55 PM PDT 24
Finished Jul 25 07:14:56 PM PDT 24
Peak memory 200468 kb
Host smart-64bd4f13-efd5-4e4e-a81d-8dea440b5cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645265080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.1645265080
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.929149788
Short name T769
Test name
Test status
Simulation time 190340759 ps
CPU time 1.27 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200500 kb
Host smart-1843f988-b87f-44f2-a491-00f3ecbbd955
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929149788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.929149788
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.1768001719
Short name T736
Test name
Test status
Simulation time 131109719 ps
CPU time 1.15 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200508 kb
Host smart-64fa397d-8014-4233-8d59-87b9a8d3eec4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768001719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.1768001719
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.3568428147
Short name T223
Test name
Test status
Simulation time 33423783 ps
CPU time 0.84 seconds
Started Jul 25 07:14:56 PM PDT 24
Finished Jul 25 07:14:57 PM PDT 24
Peak memory 200488 kb
Host smart-302995af-ff7c-4d80-9989-62f506c45c8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568428147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3568428147
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.2281005528
Short name T459
Test name
Test status
Simulation time 702186735 ps
CPU time 3.84 seconds
Started Jul 25 07:14:55 PM PDT 24
Finished Jul 25 07:14:59 PM PDT 24
Peak memory 200564 kb
Host smart-486c5c10-55a9-49ec-8e3a-0c44c42ac4b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281005528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2281005528
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.1739350772
Short name T33
Test name
Test status
Simulation time 2358854975 ps
CPU time 7.59 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:15:01 PM PDT 24
Peak memory 200896 kb
Host smart-bf7c8005-5bff-4355-80a3-7dc54057f53c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739350772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.1739350772
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3831458590
Short name T214
Test name
Test status
Simulation time 38535042 ps
CPU time 1.05 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200476 kb
Host smart-dcc5d867-ee26-4f81-a501-5fb0316c314d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831458590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.3831458590
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1045622034
Short name T739
Test name
Test status
Simulation time 24326588 ps
CPU time 0.92 seconds
Started Jul 25 07:14:56 PM PDT 24
Finished Jul 25 07:14:57 PM PDT 24
Peak memory 200508 kb
Host smart-b71324f6-ef8a-48ab-9aae-853cd7290562
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045622034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.1045622034
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3886096275
Short name T594
Test name
Test status
Simulation time 82419355 ps
CPU time 0.99 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200504 kb
Host smart-88609cbd-d830-4118-a9dc-fe2ddf19f56c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886096275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3886096275
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.3368542558
Short name T750
Test name
Test status
Simulation time 132059561 ps
CPU time 1.12 seconds
Started Jul 25 07:14:55 PM PDT 24
Finished Jul 25 07:14:56 PM PDT 24
Peak memory 200504 kb
Host smart-0ed02463-d9f3-4e76-9526-bc9ebcf3b1d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368542558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3368542558
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.309285294
Short name T84
Test name
Test status
Simulation time 1364487862 ps
CPU time 5.06 seconds
Started Jul 25 07:14:54 PM PDT 24
Finished Jul 25 07:14:59 PM PDT 24
Peak memory 200712 kb
Host smart-d05c7beb-11c1-4dcc-89b6-5ec6edef5ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309285294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.309285294
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.2441359601
Short name T567
Test name
Test status
Simulation time 26829111 ps
CPU time 0.82 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200452 kb
Host smart-af6afd5f-cf37-453a-82bf-104048ce9cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441359601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2441359601
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.1375903327
Short name T534
Test name
Test status
Simulation time 96295786151 ps
CPU time 655.68 seconds
Started Jul 25 07:14:51 PM PDT 24
Finished Jul 25 07:25:47 PM PDT 24
Peak memory 217340 kb
Host smart-d7db4ee0-75f9-4a97-a6d5-018928b866c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1375903327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.1375903327
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2318110362
Short name T799
Test name
Test status
Simulation time 91376391 ps
CPU time 1.08 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200564 kb
Host smart-fd9f6538-eda5-4b1a-b661-44855762ac2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318110362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2318110362
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1048006012
Short name T200
Test name
Test status
Simulation time 51663556 ps
CPU time 0.96 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200504 kb
Host smart-b416f136-b209-4d7a-9cdd-f9e80ed80612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048006012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1048006012
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.142028903
Short name T538
Test name
Test status
Simulation time 20904369 ps
CPU time 0.83 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:03 PM PDT 24
Peak memory 200512 kb
Host smart-0b95a19e-422c-4540-8c9b-4585f41a23a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142028903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.142028903
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.1245443579
Short name T728
Test name
Test status
Simulation time 42448036 ps
CPU time 0.75 seconds
Started Jul 25 07:14:56 PM PDT 24
Finished Jul 25 07:14:57 PM PDT 24
Peak memory 199672 kb
Host smart-32f58e71-faac-4b22-be1b-b86774ff6071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245443579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1245443579
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.311689176
Short name T316
Test name
Test status
Simulation time 30579407 ps
CPU time 0.82 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200520 kb
Host smart-e94d1926-50b8-4fe6-b3ae-57f12da3ed38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311689176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.311689176
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.1769490405
Short name T246
Test name
Test status
Simulation time 238800329 ps
CPU time 1.49 seconds
Started Jul 25 07:14:52 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200504 kb
Host smart-eef49e21-96e5-49b2-92ec-87356e0d74f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769490405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.1769490405
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.1598802902
Short name T785
Test name
Test status
Simulation time 1275002663 ps
CPU time 10.22 seconds
Started Jul 25 07:14:50 PM PDT 24
Finished Jul 25 07:15:01 PM PDT 24
Peak memory 200560 kb
Host smart-954202d2-15dc-4a60-aeb2-33f632a1bece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598802902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1598802902
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.1949428256
Short name T372
Test name
Test status
Simulation time 860082105 ps
CPU time 6.14 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:59 PM PDT 24
Peak memory 200624 kb
Host smart-6ffcb89d-0271-4b64-8a74-0dd98580ec10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949428256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.1949428256
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1885359312
Short name T117
Test name
Test status
Simulation time 28397394 ps
CPU time 0.91 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200532 kb
Host smart-212ee6f0-6600-4dbc-afee-e9c27c19284f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885359312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.1885359312
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.727128306
Short name T179
Test name
Test status
Simulation time 37078052 ps
CPU time 0.82 seconds
Started Jul 25 07:15:00 PM PDT 24
Finished Jul 25 07:15:01 PM PDT 24
Peak memory 200480 kb
Host smart-14a5680e-5fe7-4924-a3a0-5cd0b5072695
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727128306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.clkmgr_lc_clk_byp_req_intersig_mubi.727128306
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3438747268
Short name T322
Test name
Test status
Simulation time 64954835 ps
CPU time 0.99 seconds
Started Jul 25 07:14:58 PM PDT 24
Finished Jul 25 07:15:00 PM PDT 24
Peak memory 200508 kb
Host smart-bf8a4dbc-cfba-4a75-a659-dfb3f72df9ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438747268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.3438747268
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.4133896153
Short name T564
Test name
Test status
Simulation time 19983178 ps
CPU time 0.82 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200448 kb
Host smart-99a00beb-7caa-4354-827b-e156bc7949e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133896153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.4133896153
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.3268058932
Short name T619
Test name
Test status
Simulation time 603926012 ps
CPU time 3.06 seconds
Started Jul 25 07:15:00 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200700 kb
Host smart-225183ba-c4a9-4362-9724-de836055f4d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268058932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3268058932
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.1883816237
Short name T644
Test name
Test status
Simulation time 52661283 ps
CPU time 0.96 seconds
Started Jul 25 07:14:53 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 200452 kb
Host smart-cae0ffb9-0510-4e92-901e-2e792f9b3f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883816237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1883816237
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.4143093174
Short name T518
Test name
Test status
Simulation time 4792894478 ps
CPU time 25.67 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:27 PM PDT 24
Peak memory 200892 kb
Host smart-9ad5c822-2356-49b3-9429-2bdf37c904dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143093174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.4143093174
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.2929267573
Short name T77
Test name
Test status
Simulation time 89488832488 ps
CPU time 818.46 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:28:39 PM PDT 24
Peak memory 209212 kb
Host smart-3b089dd4-4feb-4eab-974f-3f66a247d821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2929267573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.2929267573
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.3879219130
Short name T293
Test name
Test status
Simulation time 25221243 ps
CPU time 0.84 seconds
Started Jul 25 07:14:50 PM PDT 24
Finished Jul 25 07:14:51 PM PDT 24
Peak memory 200504 kb
Host smart-10e0a33e-ab0b-48d9-a132-10e02716b041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879219130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.3879219130
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.175353510
Short name T556
Test name
Test status
Simulation time 43417090 ps
CPU time 0.84 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200476 kb
Host smart-22b808c6-d199-48ff-bfd8-657c7221a9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175353510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkm
gr_alert_test.175353510
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1881919649
Short name T95
Test name
Test status
Simulation time 22153948 ps
CPU time 0.82 seconds
Started Jul 25 07:14:59 PM PDT 24
Finished Jul 25 07:15:00 PM PDT 24
Peak memory 200688 kb
Host smart-92fe8705-c9c2-4cf4-8647-95567bc6ca1a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881919649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.1881919649
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.980064792
Short name T386
Test name
Test status
Simulation time 45657072 ps
CPU time 0.79 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200432 kb
Host smart-506eb492-de74-436d-89da-f480b8f45b20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980064792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.980064792
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.1450604510
Short name T20
Test name
Test status
Simulation time 79333303 ps
CPU time 1.01 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200512 kb
Host smart-90c283e7-0461-4f01-9af6-56d158b828c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450604510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.1450604510
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.149578150
Short name T709
Test name
Test status
Simulation time 25412390 ps
CPU time 0.93 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200528 kb
Host smart-f6676131-5090-4861-82a0-d5b1c6f26b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149578150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.149578150
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.2588924924
Short name T258
Test name
Test status
Simulation time 2248040920 ps
CPU time 13.43 seconds
Started Jul 25 07:15:04 PM PDT 24
Finished Jul 25 07:15:17 PM PDT 24
Peak memory 200828 kb
Host smart-a5300a6c-7887-4696-9c03-9683f28d3a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588924924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.2588924924
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.3196597424
Short name T738
Test name
Test status
Simulation time 1408917368 ps
CPU time 5.83 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:08 PM PDT 24
Peak memory 200640 kb
Host smart-2a9cbf91-8a66-40e0-87fa-954365c8b932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196597424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.3196597424
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2015527550
Short name T368
Test name
Test status
Simulation time 17592511 ps
CPU time 0.78 seconds
Started Jul 25 07:15:00 PM PDT 24
Finished Jul 25 07:15:01 PM PDT 24
Peak memory 200488 kb
Host smart-36173df7-e502-4c77-a617-443ecec32522
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015527550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2015527550
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2946460367
Short name T640
Test name
Test status
Simulation time 15979356 ps
CPU time 0.74 seconds
Started Jul 25 07:15:07 PM PDT 24
Finished Jul 25 07:15:08 PM PDT 24
Peak memory 200512 kb
Host smart-e8493368-b241-413d-9682-a7b2ad47d085
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946460367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.2946460367
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.4126745891
Short name T780
Test name
Test status
Simulation time 17848551 ps
CPU time 0.79 seconds
Started Jul 25 07:15:04 PM PDT 24
Finished Jul 25 07:15:05 PM PDT 24
Peak memory 200520 kb
Host smart-7a7c9593-dcf0-4af0-baad-cc3588a12028
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126745891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.4126745891
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.686575430
Short name T413
Test name
Test status
Simulation time 21292224 ps
CPU time 0.81 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200520 kb
Host smart-9c53e1ea-4a53-427c-bdfd-eadb988cba8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686575430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.686575430
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.2787085947
Short name T233
Test name
Test status
Simulation time 454246263 ps
CPU time 1.94 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:05 PM PDT 24
Peak memory 200508 kb
Host smart-fe01d011-e557-49a1-8da0-0a472b6a7b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787085947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.2787085947
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.2385133917
Short name T461
Test name
Test status
Simulation time 112708600 ps
CPU time 1.04 seconds
Started Jul 25 07:15:00 PM PDT 24
Finished Jul 25 07:15:01 PM PDT 24
Peak memory 200356 kb
Host smart-ba343158-975a-4a67-9a6e-0860de4126e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385133917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2385133917
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.1246859090
Short name T404
Test name
Test status
Simulation time 5307326313 ps
CPU time 23.85 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:26 PM PDT 24
Peak memory 200904 kb
Host smart-afe526a8-233f-4067-a776-8b8916628e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246859090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.1246859090
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3590937313
Short name T503
Test name
Test status
Simulation time 232512667 ps
CPU time 1.63 seconds
Started Jul 25 07:14:58 PM PDT 24
Finished Jul 25 07:14:59 PM PDT 24
Peak memory 200464 kb
Host smart-b918e411-1cd5-4d6a-afe3-736dbb1f19db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590937313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3590937313
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.2219489794
Short name T253
Test name
Test status
Simulation time 110125760 ps
CPU time 1.03 seconds
Started Jul 25 07:15:04 PM PDT 24
Finished Jul 25 07:15:05 PM PDT 24
Peak memory 200500 kb
Host smart-3a0858be-62a0-4121-a697-83cc1b9c0fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219489794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.2219489794
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.938255886
Short name T694
Test name
Test status
Simulation time 70725866 ps
CPU time 1.11 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:03 PM PDT 24
Peak memory 200512 kb
Host smart-5a6584b7-dbca-4ab5-b68c-e451a46dc5cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938255886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.938255886
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1208838613
Short name T481
Test name
Test status
Simulation time 28004784 ps
CPU time 0.79 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200420 kb
Host smart-7d9b6548-197c-41bc-a0dc-4f6c42dae540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208838613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1208838613
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.3745543935
Short name T324
Test name
Test status
Simulation time 32237068 ps
CPU time 0.9 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200524 kb
Host smart-63dcce49-cfa2-4855-a32a-30302e26afe8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745543935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.3745543935
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.1720059962
Short name T677
Test name
Test status
Simulation time 141419201 ps
CPU time 1.46 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200492 kb
Host smart-f85ba0ff-a2ea-4e72-ab66-8aad9d58523b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720059962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1720059962
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1586079998
Short name T770
Test name
Test status
Simulation time 2576194078 ps
CPU time 12.23 seconds
Started Jul 25 07:14:59 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200796 kb
Host smart-c20fce96-4ad4-4063-8d0f-19304711803b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586079998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1586079998
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.2096355439
Short name T519
Test name
Test status
Simulation time 1247463740 ps
CPU time 5.34 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:07 PM PDT 24
Peak memory 200608 kb
Host smart-be823561-c8da-4001-9893-19f0709183fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096355439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.2096355439
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.134431136
Short name T448
Test name
Test status
Simulation time 151999284 ps
CPU time 1.3 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:03 PM PDT 24
Peak memory 200484 kb
Host smart-947163fb-e06f-4a89-87b2-57447bd72031
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134431136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_idle_intersig_mubi.134431136
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.1611135330
Short name T254
Test name
Test status
Simulation time 60661408 ps
CPU time 0.98 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:03 PM PDT 24
Peak memory 200524 kb
Host smart-35e833ab-1609-4e66-b15c-cac7caab4ea4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611135330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.1611135330
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3078944941
Short name T597
Test name
Test status
Simulation time 15345036 ps
CPU time 0.75 seconds
Started Jul 25 07:15:00 PM PDT 24
Finished Jul 25 07:15:01 PM PDT 24
Peak memory 200508 kb
Host smart-88e4a462-e028-4642-a7a9-79587535e9c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078944941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.3078944941
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.534243126
Short name T795
Test name
Test status
Simulation time 39774113 ps
CPU time 0.86 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:03 PM PDT 24
Peak memory 200460 kb
Host smart-3f4b6b61-65f2-4a40-83e4-89c2347aa32b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534243126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.534243126
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.3025163036
Short name T54
Test name
Test status
Simulation time 1031461188 ps
CPU time 4.71 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:07 PM PDT 24
Peak memory 200680 kb
Host smart-3033e64c-ca3e-4bc0-a916-fe34e2a54c2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025163036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.3025163036
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.260595169
Short name T146
Test name
Test status
Simulation time 24473782 ps
CPU time 0.89 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200456 kb
Host smart-ce36203d-1f62-4963-895f-c49defff3e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260595169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.260595169
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2510357092
Short name T484
Test name
Test status
Simulation time 5671170529 ps
CPU time 32.71 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200896 kb
Host smart-3dafcd76-6d4d-4c6a-88d1-eaf8ca60e2f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510357092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2510357092
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.474096362
Short name T360
Test name
Test status
Simulation time 95744266 ps
CPU time 1.19 seconds
Started Jul 25 07:15:08 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200520 kb
Host smart-c7ff1bfc-8108-4628-b190-8f01bef4a857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474096362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.474096362
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.1566779277
Short name T28
Test name
Test status
Simulation time 16882464 ps
CPU time 0.82 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200532 kb
Host smart-014177ad-66a5-48dc-90ae-ace93c6d0a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566779277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.1566779277
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3331915930
Short name T655
Test name
Test status
Simulation time 53913651 ps
CPU time 0.93 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200500 kb
Host smart-59ad341b-a847-4be7-bd6a-249fcadf36e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331915930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.3331915930
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.3967056819
Short name T744
Test name
Test status
Simulation time 13969987 ps
CPU time 0.72 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 199696 kb
Host smart-8fc52331-1dcb-4623-9501-f1f5087c2af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967056819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3967056819
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1522425718
Short name T452
Test name
Test status
Simulation time 34597923 ps
CPU time 0.78 seconds
Started Jul 25 07:15:07 PM PDT 24
Finished Jul 25 07:15:08 PM PDT 24
Peak memory 200512 kb
Host smart-a91d3a73-7d52-4978-b994-8f247df5914d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522425718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1522425718
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.1485144626
Short name T606
Test name
Test status
Simulation time 29070214 ps
CPU time 0.96 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:03 PM PDT 24
Peak memory 200500 kb
Host smart-3efe4d21-1c6e-4688-8e9b-389284bdd82c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485144626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.1485144626
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.3027223906
Short name T447
Test name
Test status
Simulation time 314034681 ps
CPU time 1.8 seconds
Started Jul 25 07:15:02 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200572 kb
Host smart-1527e943-e29e-48c8-a2f6-1308f9b13194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027223906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.3027223906
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.4142958083
Short name T5
Test name
Test status
Simulation time 617731639 ps
CPU time 5.02 seconds
Started Jul 25 07:15:07 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200628 kb
Host smart-81183203-baab-43c0-be4e-86bab9ccde3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142958083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.4142958083
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3456306631
Short name T220
Test name
Test status
Simulation time 26613833 ps
CPU time 0.93 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200504 kb
Host smart-96f869d4-7a6b-43e7-99f0-0878d5e3d031
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456306631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.3456306631
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.1509388385
Short name T535
Test name
Test status
Simulation time 40800029 ps
CPU time 0.83 seconds
Started Jul 25 07:15:01 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200516 kb
Host smart-a85acf42-69c7-4705-a1a7-7e374023dfb8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509388385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.1509388385
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3582758184
Short name T805
Test name
Test status
Simulation time 80770738 ps
CPU time 1.02 seconds
Started Jul 25 07:15:08 PM PDT 24
Finished Jul 25 07:15:09 PM PDT 24
Peak memory 200516 kb
Host smart-31d81246-d352-4179-9e0a-abcf737fd998
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582758184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.3582758184
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2593012853
Short name T218
Test name
Test status
Simulation time 15169423 ps
CPU time 0.74 seconds
Started Jul 25 07:15:04 PM PDT 24
Finished Jul 25 07:15:05 PM PDT 24
Peak memory 200488 kb
Host smart-bd6684a2-cfe4-41ce-9fda-61aa7f5f5393
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593012853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2593012853
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3272743073
Short name T701
Test name
Test status
Simulation time 431232490 ps
CPU time 2.72 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200520 kb
Host smart-ae8401ba-f069-49b6-be0b-35318d5d873a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272743073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3272743073
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.1872543947
Short name T387
Test name
Test status
Simulation time 139766500 ps
CPU time 1.21 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200452 kb
Host smart-a4b9f51a-0113-47fb-96e8-2b0e009ea755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872543947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.1872543947
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.375429927
Short name T80
Test name
Test status
Simulation time 1645846248 ps
CPU time 7.12 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:17 PM PDT 24
Peak memory 200624 kb
Host smart-760d161d-1711-44d9-95c2-cae272b860b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375429927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.375429927
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.923782285
Short name T627
Test name
Test status
Simulation time 112229068119 ps
CPU time 719.99 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:27:09 PM PDT 24
Peak memory 209200 kb
Host smart-e6413712-49c3-4acf-8de9-a7b2adfa964e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=923782285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.923782285
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.327861333
Short name T421
Test name
Test status
Simulation time 22282352 ps
CPU time 0.85 seconds
Started Jul 25 07:15:03 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200500 kb
Host smart-f6f923c0-fe52-4ef9-be28-0baeb7b966af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327861333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.327861333
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3789991081
Short name T221
Test name
Test status
Simulation time 15515492 ps
CPU time 0.76 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200484 kb
Host smart-544f057e-af3d-4374-a281-dcfa1f1381ed
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789991081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.3789991081
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.3326475646
Short name T412
Test name
Test status
Simulation time 11097770 ps
CPU time 0.66 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 199620 kb
Host smart-2844a2b3-09b2-4186-8937-12d39e746aed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326475646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.3326475646
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1102937369
Short name T362
Test name
Test status
Simulation time 94376651 ps
CPU time 1.06 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200524 kb
Host smart-4018fc1f-1cf7-4eda-ae39-131ae0f5f9e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102937369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.1102937369
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.3165788770
Short name T724
Test name
Test status
Simulation time 21451516 ps
CPU time 0.86 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200500 kb
Host smart-3e2d871c-9b18-4227-8c0d-bee465a7e80a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165788770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.3165788770
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.3863512893
Short name T339
Test name
Test status
Simulation time 1223404063 ps
CPU time 5.66 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200452 kb
Host smart-9f932ca6-3699-484f-ab58-21d94ceab854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863512893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3863512893
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.1785361901
Short name T224
Test name
Test status
Simulation time 974041967 ps
CPU time 7.83 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200580 kb
Host smart-fe4aabc7-6ebb-4299-9d14-d0005d6e8c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785361901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.1785361901
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1058730986
Short name T560
Test name
Test status
Simulation time 64943001 ps
CPU time 1.02 seconds
Started Jul 25 07:15:14 PM PDT 24
Finished Jul 25 07:15:15 PM PDT 24
Peak memory 200500 kb
Host smart-b7a04b3a-060f-4075-b6d5-5519732ebe77
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058730986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.1058730986
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.4268522343
Short name T269
Test name
Test status
Simulation time 33680275 ps
CPU time 0.84 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200524 kb
Host smart-07b680c5-2c0f-4bf7-9bfb-5b0fc0f83223
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268522343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.4268522343
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1818059970
Short name T215
Test name
Test status
Simulation time 14896388 ps
CPU time 0.75 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200484 kb
Host smart-2fd3c0c9-8d85-42f5-859b-4fdecc763d40
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818059970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.1818059970
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.2729366658
Short name T642
Test name
Test status
Simulation time 12693846 ps
CPU time 0.7 seconds
Started Jul 25 07:15:08 PM PDT 24
Finished Jul 25 07:15:09 PM PDT 24
Peak memory 200436 kb
Host smart-046450ab-eb52-4058-8204-6ec5a9a3dff0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729366658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.2729366658
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.1942287404
Short name T796
Test name
Test status
Simulation time 532458965 ps
CPU time 2.71 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200660 kb
Host smart-279a0a50-40f5-4ae6-863a-97517e55f8e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942287404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1942287404
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.2855074422
Short name T666
Test name
Test status
Simulation time 38010416 ps
CPU time 0.87 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200492 kb
Host smart-c1024497-ee76-4371-a436-e8d1848c745e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855074422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2855074422
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.1076305584
Short name T730
Test name
Test status
Simulation time 2977875480 ps
CPU time 15.66 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:27 PM PDT 24
Peak memory 200908 kb
Host smart-59761a56-5848-4606-bc3d-26df9a5575f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076305584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.1076305584
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.4234673962
Short name T79
Test name
Test status
Simulation time 66972830781 ps
CPU time 364.97 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:21:14 PM PDT 24
Peak memory 209228 kb
Host smart-660ef66b-a19d-4e43-96fb-6515e51a7d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4234673962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.4234673962
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.4228881618
Short name T451
Test name
Test status
Simulation time 25580705 ps
CPU time 0.75 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:14 PM PDT 24
Peak memory 200476 kb
Host smart-150128f1-bf82-4106-9cfa-eacc2c87b7fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228881618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.4228881618
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.2068457549
Short name T609
Test name
Test status
Simulation time 38269183 ps
CPU time 0.8 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:21 PM PDT 24
Peak memory 200528 kb
Host smart-4ae6790c-e5fe-4b8f-8b2b-f52b79932119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068457549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.2068457549
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.732396618
Short name T60
Test name
Test status
Simulation time 22513566 ps
CPU time 0.8 seconds
Started Jul 25 07:14:20 PM PDT 24
Finished Jul 25 07:14:21 PM PDT 24
Peak memory 200460 kb
Host smart-4601bb36-4f54-41db-af15-1b99776504a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732396618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.732396618
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.2385785365
Short name T402
Test name
Test status
Simulation time 19159238 ps
CPU time 0.75 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 199720 kb
Host smart-d3354a41-9bea-4b12-b80b-e03c0d61a09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385785365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2385785365
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.3688893619
Short name T449
Test name
Test status
Simulation time 24779453 ps
CPU time 0.82 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200516 kb
Host smart-a42357e4-01e9-43d2-bdbd-cb9f10649888
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688893619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.3688893619
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.3113161012
Short name T328
Test name
Test status
Simulation time 18730364 ps
CPU time 0.89 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200524 kb
Host smart-2a3dd3fa-0f46-4996-bfde-793fba332aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113161012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.3113161012
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.3616401632
Short name T732
Test name
Test status
Simulation time 1825514717 ps
CPU time 8.48 seconds
Started Jul 25 07:14:18 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200808 kb
Host smart-8a04ab5c-0748-43fb-9433-084eb0ba1238
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616401632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.3616401632
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.2163126614
Short name T729
Test name
Test status
Simulation time 1335812253 ps
CPU time 9.86 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:31 PM PDT 24
Peak memory 200604 kb
Host smart-f17f4d65-fc9a-464f-8365-e5ce5d7291b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163126614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.2163126614
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2617674896
Short name T778
Test name
Test status
Simulation time 19505634 ps
CPU time 0.87 seconds
Started Jul 25 07:14:25 PM PDT 24
Finished Jul 25 07:14:25 PM PDT 24
Peak memory 200464 kb
Host smart-c943b54e-d519-4e27-a495-be4aa48a02f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617674896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.2617674896
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.996004240
Short name T351
Test name
Test status
Simulation time 21168262 ps
CPU time 0.82 seconds
Started Jul 25 07:14:19 PM PDT 24
Finished Jul 25 07:14:20 PM PDT 24
Peak memory 200496 kb
Host smart-d78847b3-0554-43b3-a093-edff0b3f7ccf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996004240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_clk_byp_req_intersig_mubi.996004240
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.207049136
Short name T152
Test name
Test status
Simulation time 23629532 ps
CPU time 0.81 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200536 kb
Host smart-1ddc39ac-c0dd-4b6e-8bf3-3e2dc6fefa12
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207049136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_ctrl_intersig_mubi.207049136
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.1101583253
Short name T327
Test name
Test status
Simulation time 15907050 ps
CPU time 0.77 seconds
Started Jul 25 07:14:20 PM PDT 24
Finished Jul 25 07:14:21 PM PDT 24
Peak memory 200452 kb
Host smart-caf56ce3-2c32-4184-9577-15a03ba693ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101583253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1101583253
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.1153797076
Short name T83
Test name
Test status
Simulation time 235449353 ps
CPU time 1.81 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:23 PM PDT 24
Peak memory 200428 kb
Host smart-fbcdc53f-c165-4fea-904c-8bcfd7cf82fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153797076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1153797076
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.995012988
Short name T52
Test name
Test status
Simulation time 319886756 ps
CPU time 3.24 seconds
Started Jul 25 07:14:18 PM PDT 24
Finished Jul 25 07:14:21 PM PDT 24
Peak memory 221392 kb
Host smart-2ea00abf-9456-4c3f-80fb-c9664dbde34e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995012988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr
_sec_cm.995012988
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.3294483855
Short name T49
Test name
Test status
Simulation time 15991299 ps
CPU time 0.8 seconds
Started Jul 25 07:14:19 PM PDT 24
Finished Jul 25 07:14:20 PM PDT 24
Peak memory 200428 kb
Host smart-098b0a4b-695a-4d4f-8db7-8e49ec42fb05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294483855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3294483855
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2392374280
Short name T30
Test name
Test status
Simulation time 250945642 ps
CPU time 1.71 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200572 kb
Host smart-fd6f4492-fd92-4efa-9976-978663dd9157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392374280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2392374280
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.603521878
Short name T831
Test name
Test status
Simulation time 360658809 ps
CPU time 1.88 seconds
Started Jul 25 07:14:20 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200508 kb
Host smart-27e1b187-4aa2-4ce1-8d76-2777930da40b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603521878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.603521878
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.3203202153
Short name T492
Test name
Test status
Simulation time 15896452 ps
CPU time 0.77 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200484 kb
Host smart-76e16132-be14-4914-a90c-185a16e85bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203202153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.3203202153
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.4264452349
Short name T576
Test name
Test status
Simulation time 19764414 ps
CPU time 0.82 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200560 kb
Host smart-35a35a07-137e-493c-8af9-b981df77f075
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264452349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.4264452349
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1161349568
Short name T173
Test name
Test status
Simulation time 40580785 ps
CPU time 0.82 seconds
Started Jul 25 07:15:13 PM PDT 24
Finished Jul 25 07:15:14 PM PDT 24
Peak memory 199728 kb
Host smart-e484e936-adf6-4026-83fd-af0c916ba4f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161349568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1161349568
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.680690033
Short name T825
Test name
Test status
Simulation time 22241984 ps
CPU time 0.86 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200512 kb
Host smart-a1bad021-c113-4626-8995-6851b513e1c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680690033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.680690033
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.1462342075
Short name T378
Test name
Test status
Simulation time 60359960 ps
CPU time 0.98 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200552 kb
Host smart-bb27d6c4-7811-4ef1-a301-f31baadd6461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462342075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1462342075
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.2603857205
Short name T660
Test name
Test status
Simulation time 201070288 ps
CPU time 2.22 seconds
Started Jul 25 07:15:13 PM PDT 24
Finished Jul 25 07:15:15 PM PDT 24
Peak memory 200584 kb
Host smart-e3dd3a76-0f98-4f51-90f5-6c2f616bb7ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603857205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2603857205
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.2724703639
Short name T808
Test name
Test status
Simulation time 1348238317 ps
CPU time 5.89 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:17 PM PDT 24
Peak memory 200632 kb
Host smart-659b668b-e3d9-4790-a89f-e8cfff566600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724703639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.2724703639
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3119100951
Short name T283
Test name
Test status
Simulation time 121390021 ps
CPU time 1.04 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200468 kb
Host smart-f5887194-c926-4609-bbe5-643ac47810f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119100951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.3119100951
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.260750501
Short name T549
Test name
Test status
Simulation time 22952866 ps
CPU time 0.87 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200540 kb
Host smart-3554a90a-d5a1-413d-ae2e-38ad72575b56
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260750501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_clk_byp_req_intersig_mubi.260750501
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.895024445
Short name T309
Test name
Test status
Simulation time 31520739 ps
CPU time 0.81 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200508 kb
Host smart-3f9c7be6-28d2-48ee-9110-e2b8087e7bad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895024445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_ctrl_intersig_mubi.895024445
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.72375744
Short name T559
Test name
Test status
Simulation time 21363009 ps
CPU time 0.8 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200488 kb
Host smart-358669d4-f1fa-49c2-8ba7-f8be83493194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72375744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.72375744
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.3923929929
Short name T544
Test name
Test status
Simulation time 924619002 ps
CPU time 3.83 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:15 PM PDT 24
Peak memory 200700 kb
Host smart-89b5786d-509b-4d1b-bd00-b1640f1ea92e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923929929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.3923929929
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.1746291993
Short name T705
Test name
Test status
Simulation time 67123026 ps
CPU time 0.98 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200496 kb
Host smart-80c85d41-dd3e-4ace-ac31-1a0ddc4ef1f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746291993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.1746291993
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.999488751
Short name T272
Test name
Test status
Simulation time 4406706567 ps
CPU time 18.83 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:29 PM PDT 24
Peak memory 200872 kb
Host smart-28d44f3d-461a-45e7-99ed-b7096ff8b6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999488751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.999488751
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.2061985307
Short name T118
Test name
Test status
Simulation time 131889317 ps
CPU time 1.21 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200504 kb
Host smart-dce08e08-03e4-4ff8-bb81-d144695a0e99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061985307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2061985307
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.3105435579
Short name T440
Test name
Test status
Simulation time 57152312 ps
CPU time 0.9 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200504 kb
Host smart-4a79a9b8-88fe-44f7-8e3a-327274454594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105435579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.3105435579
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.4072901617
Short name T554
Test name
Test status
Simulation time 24350602 ps
CPU time 0.88 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200480 kb
Host smart-864137f1-bbfd-4032-8d05-5c4916b9bbc9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072901617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.4072901617
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.3999634372
Short name T725
Test name
Test status
Simulation time 63115197 ps
CPU time 0.83 seconds
Started Jul 25 07:15:11 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 199704 kb
Host smart-6c8e79af-3706-49d5-b080-fd9fc980e3fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999634372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.3999634372
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1579525457
Short name T482
Test name
Test status
Simulation time 18589462 ps
CPU time 0.81 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200468 kb
Host smart-9ed1833b-8d53-4bff-94b0-b2943bf8497d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579525457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1579525457
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.2081530138
Short name T301
Test name
Test status
Simulation time 13784728 ps
CPU time 0.75 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200496 kb
Host smart-963c7e81-7c10-478b-9092-00fc0b1d2304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081530138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2081530138
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.3387328866
Short name T790
Test name
Test status
Simulation time 2137472015 ps
CPU time 9.45 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200644 kb
Host smart-ff775f49-14cc-41d2-bd9e-7ddd8ec4571c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387328866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3387328866
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.1972494549
Short name T311
Test name
Test status
Simulation time 536176335 ps
CPU time 2.29 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200644 kb
Host smart-5f381223-20b2-4ee1-b71c-695e9c5a62af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972494549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.1972494549
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.251858527
Short name T430
Test name
Test status
Simulation time 53207219 ps
CPU time 0.86 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200480 kb
Host smart-cbf452b8-aed6-4b9a-af1a-718f59188f35
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251858527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_idle_intersig_mubi.251858527
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1992449762
Short name T55
Test name
Test status
Simulation time 39898750 ps
CPU time 0.89 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200492 kb
Host smart-2aa19b1c-3541-4ac1-b9a6-12fe12991aba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992449762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.1992449762
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.708819489
Short name T374
Test name
Test status
Simulation time 95148608 ps
CPU time 1.12 seconds
Started Jul 25 07:15:10 PM PDT 24
Finished Jul 25 07:15:11 PM PDT 24
Peak memory 200508 kb
Host smart-739c1e13-00a2-4788-b348-28717e1f3e0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708819489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_ctrl_intersig_mubi.708819489
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.543987591
Short name T469
Test name
Test status
Simulation time 23565493 ps
CPU time 0.77 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:13 PM PDT 24
Peak memory 200452 kb
Host smart-e9006386-cbcc-41b0-8c4e-80989267d75f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543987591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.543987591
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.4169481109
Short name T460
Test name
Test status
Simulation time 1047971183 ps
CPU time 3.87 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:14 PM PDT 24
Peak memory 200660 kb
Host smart-a96a73d9-3ca5-4957-afa5-e21e8722ba3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169481109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.4169481109
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.4080948904
Short name T721
Test name
Test status
Simulation time 40138341 ps
CPU time 0.92 seconds
Started Jul 25 07:15:12 PM PDT 24
Finished Jul 25 07:15:14 PM PDT 24
Peak memory 200432 kb
Host smart-c8b31af3-f119-4ba6-98c4-5e0bd64d427a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080948904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.4080948904
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.605122906
Short name T12
Test name
Test status
Simulation time 3340550672 ps
CPU time 25.11 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:45 PM PDT 24
Peak memory 200888 kb
Host smart-56f0fe32-e158-4277-8aac-e535ea76fc04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605122906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.605122906
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.3494013765
Short name T349
Test name
Test status
Simulation time 58560200 ps
CPU time 0.98 seconds
Started Jul 25 07:15:09 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200476 kb
Host smart-a9cafe13-f164-4e9f-9d2b-7b8573bb6d53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494013765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.3494013765
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.2719182426
Short name T40
Test name
Test status
Simulation time 63757017 ps
CPU time 0.91 seconds
Started Jul 25 07:15:17 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200528 kb
Host smart-fb597e17-b2af-4f29-b944-33442ca8e0a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719182426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.2719182426
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1377704266
Short name T92
Test name
Test status
Simulation time 71075574 ps
CPU time 0.97 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200516 kb
Host smart-cc1e140a-b6d7-44e7-8df0-4c6615bc9537
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377704266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.1377704266
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.2662711086
Short name T172
Test name
Test status
Simulation time 48710164 ps
CPU time 0.8 seconds
Started Jul 25 07:15:23 PM PDT 24
Finished Jul 25 07:15:24 PM PDT 24
Peak memory 199732 kb
Host smart-a4df42d4-2bc1-48d7-aab7-c10cc0003e84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662711086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2662711086
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.1393102028
Short name T384
Test name
Test status
Simulation time 72619676 ps
CPU time 0.98 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200500 kb
Host smart-6fc33e05-b439-4d1e-ab57-e3bbb63528ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393102028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.1393102028
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.2833008768
Short name T507
Test name
Test status
Simulation time 61525736 ps
CPU time 0.91 seconds
Started Jul 25 07:15:22 PM PDT 24
Finished Jul 25 07:15:23 PM PDT 24
Peak memory 200508 kb
Host smart-fbd73276-28b5-46d9-8aeb-4b712e368d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833008768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2833008768
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.798261828
Short name T707
Test name
Test status
Simulation time 1536256922 ps
CPU time 7.12 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:25 PM PDT 24
Peak memory 200560 kb
Host smart-a771810e-8387-4e87-a67a-00e215870ac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798261828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.798261828
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.3797347811
Short name T230
Test name
Test status
Simulation time 512655471 ps
CPU time 2.68 seconds
Started Jul 25 07:15:17 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200644 kb
Host smart-6167441d-b53b-4237-b0ca-a87573336ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797347811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.3797347811
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.3603727388
Short name T267
Test name
Test status
Simulation time 20790047 ps
CPU time 0.83 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:19 PM PDT 24
Peak memory 200516 kb
Host smart-a260ab98-836d-40b4-863c-5447d89831ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603727388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.3603727388
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3122309437
Short name T211
Test name
Test status
Simulation time 15205102 ps
CPU time 0.8 seconds
Started Jul 25 07:15:22 PM PDT 24
Finished Jul 25 07:15:23 PM PDT 24
Peak memory 200532 kb
Host smart-fecbf25d-7c56-4f0a-9c94-389fe5daa2b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122309437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3122309437
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.3644012769
Short name T186
Test name
Test status
Simulation time 20355074 ps
CPU time 0.82 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200516 kb
Host smart-6158af5f-1c5f-48f8-85ae-055da48119c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644012769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.3644012769
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3718861468
Short name T209
Test name
Test status
Simulation time 39095749 ps
CPU time 0.81 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200536 kb
Host smart-8c46656b-1cd4-48f4-8b3f-4c04b6df415b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718861468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3718861468
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.1698813536
Short name T85
Test name
Test status
Simulation time 167517190 ps
CPU time 1.49 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200432 kb
Host smart-24d45589-9632-4a0f-9193-79de47b96f4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698813536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.1698813536
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.78464667
Short name T407
Test name
Test status
Simulation time 84037647 ps
CPU time 1.04 seconds
Started Jul 25 07:15:22 PM PDT 24
Finished Jul 25 07:15:23 PM PDT 24
Peak memory 200452 kb
Host smart-a858d55f-4253-4ca0-bfda-29cba14b0274
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78464667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.78464667
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.348710269
Short name T578
Test name
Test status
Simulation time 1240946801 ps
CPU time 7.33 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:26 PM PDT 24
Peak memory 200780 kb
Host smart-a7cc7ade-498a-4047-8dbe-86178b86136e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348710269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.348710269
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.3411981367
Short name T295
Test name
Test status
Simulation time 51888826 ps
CPU time 1.09 seconds
Started Jul 25 07:15:23 PM PDT 24
Finished Jul 25 07:15:24 PM PDT 24
Peak memory 200460 kb
Host smart-0d383243-ca23-43e4-9661-f02af0ed8e05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411981367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3411981367
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.1636669706
Short name T356
Test name
Test status
Simulation time 29632192 ps
CPU time 0.78 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200528 kb
Host smart-c0e45bd2-4049-462d-8023-3637710758dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636669706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.1636669706
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.505112031
Short name T94
Test name
Test status
Simulation time 61040703 ps
CPU time 1.02 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200552 kb
Host smart-d2f39318-3727-47c6-a0c6-0d1a0a80ddb7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505112031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.505112031
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.1689869488
Short name T45
Test name
Test status
Simulation time 46253740 ps
CPU time 0.82 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 199700 kb
Host smart-94d20ec3-0c58-4201-86d5-844c69d5f690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689869488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1689869488
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.1598752946
Short name T616
Test name
Test status
Simulation time 18043124 ps
CPU time 0.8 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200500 kb
Host smart-7b9f9a7e-f724-4c37-9173-d5c0636f069a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598752946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.1598752946
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.4118684937
Short name T229
Test name
Test status
Simulation time 93191194 ps
CPU time 1.03 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200496 kb
Host smart-16672c96-2822-47fb-a258-f3c44fcd6d96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118684937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.4118684937
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.1027802997
Short name T336
Test name
Test status
Simulation time 1490744845 ps
CPU time 6.81 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:26 PM PDT 24
Peak memory 200568 kb
Host smart-b81c8a42-cbff-45f7-bd56-57031d5cd5d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027802997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1027802997
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.3431050802
Short name T678
Test name
Test status
Simulation time 1814950552 ps
CPU time 13.58 seconds
Started Jul 25 07:15:21 PM PDT 24
Finished Jul 25 07:15:35 PM PDT 24
Peak memory 200600 kb
Host smart-5b611efa-1726-463d-90d8-1e5aac2a3acc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431050802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.3431050802
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.3300491948
Short name T340
Test name
Test status
Simulation time 30173766 ps
CPU time 0.83 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200536 kb
Host smart-f8b083f8-c59e-44a1-beca-609fd2c94cce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300491948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.3300491948
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.517357820
Short name T681
Test name
Test status
Simulation time 24513003 ps
CPU time 0.88 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200488 kb
Host smart-5f71a228-6ea1-47a6-9c59-c93847933e6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517357820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.clkmgr_lc_clk_byp_req_intersig_mubi.517357820
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.76611774
Short name T323
Test name
Test status
Simulation time 50761103 ps
CPU time 0.99 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200532 kb
Host smart-ea1a0bd0-0b60-442d-a401-927d0bea4228
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76611774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_lc_ctrl_intersig_mubi.76611774
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.1807912083
Short name T629
Test name
Test status
Simulation time 18995016 ps
CPU time 0.76 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200448 kb
Host smart-faf0cd43-5d21-42b8-9848-f81965fde870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807912083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1807912083
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.3623221421
Short name T113
Test name
Test status
Simulation time 1417763853 ps
CPU time 5.53 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:24 PM PDT 24
Peak memory 200688 kb
Host smart-207cebe8-b14a-4658-b16c-abf1b221f6c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623221421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3623221421
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.1145549692
Short name T695
Test name
Test status
Simulation time 62670252 ps
CPU time 1.05 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200508 kb
Host smart-2b4912b2-450f-4491-8a4d-9ae85327cc8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145549692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1145549692
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.703657270
Short name T605
Test name
Test status
Simulation time 147065435 ps
CPU time 1.34 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200472 kb
Host smart-9e3fb598-a7bf-470f-9e48-6d084d3bf2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703657270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.703657270
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.2037905871
Short name T160
Test name
Test status
Simulation time 25953713210 ps
CPU time 388.09 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:21:48 PM PDT 24
Peak memory 209160 kb
Host smart-5a447b98-369d-4586-9e07-22b56ded66ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2037905871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2037905871
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.3579118400
Short name T270
Test name
Test status
Simulation time 139849347 ps
CPU time 1.32 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200472 kb
Host smart-dfb91b43-b632-4165-a6d7-cc44227a784c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579118400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3579118400
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.1065586410
Short name T57
Test name
Test status
Simulation time 17841200 ps
CPU time 0.8 seconds
Started Jul 25 07:15:31 PM PDT 24
Finished Jul 25 07:15:32 PM PDT 24
Peak memory 200500 kb
Host smart-f68b96dc-0152-4caf-84a8-b5752e9d414a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065586410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.1065586410
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.2959664243
Short name T180
Test name
Test status
Simulation time 36866340 ps
CPU time 0.87 seconds
Started Jul 25 07:15:17 PM PDT 24
Finished Jul 25 07:15:19 PM PDT 24
Peak memory 200516 kb
Host smart-5de32069-2e5d-406e-b4f6-e0db8ee31dc5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959664243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.2959664243
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.2037924844
Short name T654
Test name
Test status
Simulation time 41077092 ps
CPU time 0.78 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 199708 kb
Host smart-333002f2-6c4e-44ff-bddb-e826ae955c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037924844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2037924844
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1705555724
Short name T788
Test name
Test status
Simulation time 18487815 ps
CPU time 0.81 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200492 kb
Host smart-e4e5de15-3a15-42a6-85b8-d17b585a888f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705555724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1705555724
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.1163078946
Short name T672
Test name
Test status
Simulation time 51704182 ps
CPU time 0.88 seconds
Started Jul 25 07:15:24 PM PDT 24
Finished Jul 25 07:15:25 PM PDT 24
Peak memory 200500 kb
Host smart-e7664f1c-ba27-4b35-9523-1a19fbf79698
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163078946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1163078946
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3613755855
Short name T712
Test name
Test status
Simulation time 861570415 ps
CPU time 4.32 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:23 PM PDT 24
Peak memory 200560 kb
Host smart-24efecaa-76b9-4e1e-b5d3-49c7bdfffa19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613755855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3613755855
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.2757613861
Short name T82
Test name
Test status
Simulation time 1035541021 ps
CPU time 4.46 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:25 PM PDT 24
Peak memory 200636 kb
Host smart-56ace9bb-619f-402c-ab30-ad0842b0af86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757613861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.2757613861
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2351515587
Short name T680
Test name
Test status
Simulation time 25433675 ps
CPU time 0.77 seconds
Started Jul 25 07:15:21 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200560 kb
Host smart-bbb3d639-e64b-4c0b-9785-303d98c90242
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351515587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.2351515587
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2496914320
Short name T566
Test name
Test status
Simulation time 13762090 ps
CPU time 0.73 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200520 kb
Host smart-0192df0c-6e89-41b8-8918-3c2807fb5019
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496914320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2496914320
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.4234031291
Short name T764
Test name
Test status
Simulation time 18428581 ps
CPU time 0.79 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200480 kb
Host smart-63a4db2b-8f2c-419d-85ef-fabe24690f0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234031291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.4234031291
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.86247335
Short name T159
Test name
Test status
Simulation time 30587034 ps
CPU time 0.84 seconds
Started Jul 25 07:15:21 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200456 kb
Host smart-9caf715f-7d3b-4b18-afd6-4dc77b0a72bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86247335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.86247335
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.3424237181
Short name T441
Test name
Test status
Simulation time 1252820537 ps
CPU time 5.9 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:26 PM PDT 24
Peak memory 200680 kb
Host smart-b446b0f0-a6c5-4e0f-b004-f6b8421e2844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424237181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3424237181
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.611889121
Short name T573
Test name
Test status
Simulation time 22595467 ps
CPU time 0.87 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:19 PM PDT 24
Peak memory 200444 kb
Host smart-c9fe12c1-c8fa-4fa0-b966-648801adcc02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611889121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.611889121
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.894314741
Short name T499
Test name
Test status
Simulation time 9052089267 ps
CPU time 49.54 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:16:08 PM PDT 24
Peak memory 200892 kb
Host smart-b8998227-d61a-450b-8572-e1497f0309f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894314741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.894314741
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.3663613478
Short name T528
Test name
Test status
Simulation time 20446157 ps
CPU time 0.83 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:19 PM PDT 24
Peak memory 200460 kb
Host smart-77b62d89-59ae-4f85-a63d-a98e58fa31bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663613478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.3663613478
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3083350104
Short name T579
Test name
Test status
Simulation time 59259008 ps
CPU time 0.86 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:28 PM PDT 24
Peak memory 200508 kb
Host smart-3aca6a96-501a-408f-a8ae-04a6fb2eda5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083350104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3083350104
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1174241691
Short name T558
Test name
Test status
Simulation time 15966787 ps
CPU time 0.76 seconds
Started Jul 25 07:15:21 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200540 kb
Host smart-8a06027b-034d-4fc0-99eb-8d13e447be07
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174241691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1174241691
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.2133771909
Short name T496
Test name
Test status
Simulation time 25225662 ps
CPU time 0.75 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:29 PM PDT 24
Peak memory 199704 kb
Host smart-f7a83392-2d77-4727-86e8-5c6b001c0ebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133771909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.2133771909
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.3125193851
Short name T820
Test name
Test status
Simulation time 40353913 ps
CPU time 0.89 seconds
Started Jul 25 07:15:21 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200532 kb
Host smart-35df3a3a-33bf-46a5-ac6e-338c0ce6a8fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125193851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.3125193851
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.4069544065
Short name T280
Test name
Test status
Simulation time 21948190 ps
CPU time 0.85 seconds
Started Jul 25 07:15:18 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200492 kb
Host smart-8a3da07f-f2e4-48b8-b0f8-13aedaa628b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069544065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.4069544065
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.1372837631
Short name T490
Test name
Test status
Simulation time 1241215477 ps
CPU time 5.91 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:26 PM PDT 24
Peak memory 200596 kb
Host smart-395a2b33-ecfb-490d-a0a3-3d1cb512fca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372837631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.1372837631
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.2894610397
Short name T473
Test name
Test status
Simulation time 1651493277 ps
CPU time 7.41 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:36 PM PDT 24
Peak memory 200604 kb
Host smart-3fd22131-1e8a-4073-a322-206d41d057ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894610397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.2894610397
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.1288899615
Short name T369
Test name
Test status
Simulation time 21960549 ps
CPU time 0.74 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:28 PM PDT 24
Peak memory 200508 kb
Host smart-46961424-3ba2-45c2-96c1-69e780305108
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288899615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.1288899615
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.717315141
Short name T486
Test name
Test status
Simulation time 74910672 ps
CPU time 0.99 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200500 kb
Host smart-c8d136f2-aa48-493d-9d4b-c9dc7a30a756
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717315141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_clk_byp_req_intersig_mubi.717315141
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.3652964051
Short name T659
Test name
Test status
Simulation time 129533220 ps
CPU time 1.09 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200476 kb
Host smart-95861c92-b195-4f46-98b7-ec379c424c06
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652964051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.3652964051
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.2861110648
Short name T298
Test name
Test status
Simulation time 61157229 ps
CPU time 0.9 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200408 kb
Host smart-d73eb20c-7d38-4b59-8316-cdf07916edb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861110648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2861110648
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.3138752102
Short name T154
Test name
Test status
Simulation time 237312858 ps
CPU time 1.66 seconds
Started Jul 25 07:15:20 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200448 kb
Host smart-cf3866c0-91b2-4ac0-863f-97ded4027ba6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138752102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3138752102
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.1935014414
Short name T446
Test name
Test status
Simulation time 37315799 ps
CPU time 0.92 seconds
Started Jul 25 07:15:19 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200464 kb
Host smart-3d9f6005-0909-4f9c-9803-b872b388b213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935014414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.1935014414
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.3049439894
Short name T685
Test name
Test status
Simulation time 390307568 ps
CPU time 3.01 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200628 kb
Host smart-596acc1e-c7ff-4a65-a14d-0149c0489268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049439894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.3049439894
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.3762064990
Short name T187
Test name
Test status
Simulation time 119213173506 ps
CPU time 1101.38 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:33:50 PM PDT 24
Peak memory 207464 kb
Host smart-fabbd613-68f5-45a4-95be-29d28732201e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3762064990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3762064990
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.1493606803
Short name T735
Test name
Test status
Simulation time 40837425 ps
CPU time 0.91 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200496 kb
Host smart-8f32103e-71a9-445a-adaa-af550341931a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493606803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1493606803
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.875848935
Short name T182
Test name
Test status
Simulation time 37032434 ps
CPU time 0.76 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:39 PM PDT 24
Peak memory 200528 kb
Host smart-b70a4aef-39b7-4a72-a17b-0d8021fc7637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875848935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkm
gr_alert_test.875848935
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2449858785
Short name T393
Test name
Test status
Simulation time 21427772 ps
CPU time 0.88 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:28 PM PDT 24
Peak memory 200528 kb
Host smart-353e65b0-44f8-428d-b0f7-f39f2d851554
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449858785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.2449858785
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.25052803
Short name T816
Test name
Test status
Simulation time 18220398 ps
CPU time 0.68 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:28 PM PDT 24
Peak memory 200424 kb
Host smart-17235104-0309-444f-b978-6d81ff7c50fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25052803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.25052803
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.1998427074
Short name T607
Test name
Test status
Simulation time 26811627 ps
CPU time 0.81 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200500 kb
Host smart-47cbf727-94f1-4316-86da-955853273569
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998427074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.1998427074
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.3240377375
Short name T583
Test name
Test status
Simulation time 15353107 ps
CPU time 0.77 seconds
Started Jul 25 07:15:31 PM PDT 24
Finished Jul 25 07:15:32 PM PDT 24
Peak memory 200452 kb
Host smart-21a7452f-101a-49e7-b49d-9cfb7c06ae2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240377375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3240377375
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.3431775304
Short name T17
Test name
Test status
Simulation time 1542717939 ps
CPU time 7.02 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:37 PM PDT 24
Peak memory 200588 kb
Host smart-1cf2ff2f-849d-48e6-9b92-0195c3a51aec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431775304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3431775304
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.84928383
Short name T511
Test name
Test status
Simulation time 2411901411 ps
CPU time 10.17 seconds
Started Jul 25 07:15:26 PM PDT 24
Finished Jul 25 07:15:36 PM PDT 24
Peak memory 200916 kb
Host smart-c1497b71-c8e5-4b50-a5e4-d7bfd9afa89d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84928383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_tim
eout.84928383
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.3041572731
Short name T247
Test name
Test status
Simulation time 108420020 ps
CPU time 1.02 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200504 kb
Host smart-bd2b817b-ca9a-43e3-8358-7d5b9a994770
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041572731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.3041572731
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.2187872588
Short name T505
Test name
Test status
Simulation time 34579192 ps
CPU time 0.88 seconds
Started Jul 25 07:15:33 PM PDT 24
Finished Jul 25 07:15:35 PM PDT 24
Peak memory 200512 kb
Host smart-0b91c5c7-56f5-497a-8fd9-d05ffec690fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187872588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.2187872588
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1388058684
Short name T610
Test name
Test status
Simulation time 13886616 ps
CPU time 0.74 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200472 kb
Host smart-7bc0963f-82bc-4930-9d5a-27e73b647973
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388058684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.1388058684
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.4070046233
Short name T282
Test name
Test status
Simulation time 37529728 ps
CPU time 0.77 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200476 kb
Host smart-09cae352-57ae-48e4-b1b9-1981206c3222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070046233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.4070046233
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.180036954
Short name T488
Test name
Test status
Simulation time 255191388 ps
CPU time 2.03 seconds
Started Jul 25 07:15:31 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200476 kb
Host smart-291ff626-70af-47eb-90db-5d4454f47267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180036954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.180036954
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.46209979
Short name T512
Test name
Test status
Simulation time 15809119 ps
CPU time 0.83 seconds
Started Jul 25 07:15:25 PM PDT 24
Finished Jul 25 07:15:26 PM PDT 24
Peak memory 200448 kb
Host smart-82da380c-1401-49a8-885e-096f43c8f8cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46209979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.46209979
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.3753637792
Short name T476
Test name
Test status
Simulation time 153419599 ps
CPU time 1.4 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200516 kb
Host smart-82c5caa0-0dab-494d-993d-85fcf68d1967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753637792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.3753637792
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.4247706446
Short name T161
Test name
Test status
Simulation time 42763811163 ps
CPU time 288.36 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:20:15 PM PDT 24
Peak memory 217368 kb
Host smart-9478da53-7584-48d6-8513-a872d4b30f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4247706446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.4247706446
Directory /workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.clkmgr_trans.3511318080
Short name T673
Test name
Test status
Simulation time 43304756 ps
CPU time 0.79 seconds
Started Jul 25 07:15:33 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200516 kb
Host smart-577cbcb7-8e50-4e5e-831a-01a4ef01aa0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511318080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3511318080
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.1357962139
Short name T379
Test name
Test status
Simulation time 52226994 ps
CPU time 0.87 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200500 kb
Host smart-6a6d0515-26ef-4323-8e60-a79155e4f6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357962139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.1357962139
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3588085657
Short name T363
Test name
Test status
Simulation time 20502119 ps
CPU time 0.81 seconds
Started Jul 25 07:15:26 PM PDT 24
Finished Jul 25 07:15:27 PM PDT 24
Peak memory 200488 kb
Host smart-d02fa676-782d-43d9-a324-55584bc928b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588085657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.3588085657
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.2559173688
Short name T746
Test name
Test status
Simulation time 57787755 ps
CPU time 0.83 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 199720 kb
Host smart-84c972ac-80a3-4445-a64e-a55d5aa5909e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559173688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.2559173688
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3723500175
Short name T296
Test name
Test status
Simulation time 22749715 ps
CPU time 0.86 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:28 PM PDT 24
Peak memory 200516 kb
Host smart-56699ef4-03a4-48dc-9f8f-bb7baf38e264
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723500175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3723500175
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.1795576587
Short name T227
Test name
Test status
Simulation time 23762679 ps
CPU time 0.86 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200484 kb
Host smart-8027c3f9-4840-4ba6-a1dc-69e5cb5b0874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795576587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.1795576587
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.1325858745
Short name T811
Test name
Test status
Simulation time 2483316893 ps
CPU time 13.87 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:42 PM PDT 24
Peak memory 200808 kb
Host smart-a4a66afc-e575-4885-b09e-3ffea7925eb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325858745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1325858745
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.4286212745
Short name T436
Test name
Test status
Simulation time 742534903 ps
CPU time 5.87 seconds
Started Jul 25 07:15:25 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200552 kb
Host smart-6f4f68eb-b581-4e2c-8ce5-519ae1fb096e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286212745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.4286212745
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.1525128637
Short name T471
Test name
Test status
Simulation time 68229438 ps
CPU time 1 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200528 kb
Host smart-c2715062-fba3-4f6f-aa9a-1780b751352e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525128637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.1525128637
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3591635528
Short name T286
Test name
Test status
Simulation time 36349689 ps
CPU time 0.8 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:28 PM PDT 24
Peak memory 200504 kb
Host smart-5f2f51bc-ba2f-43cf-8186-6625ffca339a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591635528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3591635528
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2697444226
Short name T455
Test name
Test status
Simulation time 96987407 ps
CPU time 1.03 seconds
Started Jul 25 07:15:32 PM PDT 24
Finished Jul 25 07:15:33 PM PDT 24
Peak memory 200520 kb
Host smart-4a88d384-fe51-430b-8f5e-930ac16bda59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697444226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.2697444226
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.145032639
Short name T37
Test name
Test status
Simulation time 44848688 ps
CPU time 0.86 seconds
Started Jul 25 07:15:26 PM PDT 24
Finished Jul 25 07:15:27 PM PDT 24
Peak memory 200476 kb
Host smart-4dc08acc-efa8-4b38-8623-00dde44bb5f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145032639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.145032639
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.3779967262
Short name T713
Test name
Test status
Simulation time 140340567 ps
CPU time 1.13 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200452 kb
Host smart-8ec51ef0-fc04-442c-87de-9ed8adf3261a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779967262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.3779967262
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.1481977705
Short name T357
Test name
Test status
Simulation time 19535608 ps
CPU time 0.84 seconds
Started Jul 25 07:15:33 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200452 kb
Host smart-dde5521f-ff72-4094-9fc6-ceea0d7466ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481977705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.1481977705
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.379906425
Short name T141
Test name
Test status
Simulation time 3032512286 ps
CPU time 12.59 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:15:43 PM PDT 24
Peak memory 200856 kb
Host smart-27415b57-2edb-4539-a752-5d3d22add4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379906425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.379906425
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.2781120713
Short name T195
Test name
Test status
Simulation time 29118699 ps
CPU time 0.93 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:15:32 PM PDT 24
Peak memory 200512 kb
Host smart-13961c0c-4d29-414d-a43b-1b20c38e92ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781120713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.2781120713
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.390969846
Short name T718
Test name
Test status
Simulation time 31058837 ps
CPU time 0.72 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:29 PM PDT 24
Peak memory 200512 kb
Host smart-a1c1c2dd-a849-4e9f-8eec-011529960dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390969846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkm
gr_alert_test.390969846
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1239720029
Short name T761
Test name
Test status
Simulation time 19626715 ps
CPU time 0.89 seconds
Started Jul 25 07:15:32 PM PDT 24
Finished Jul 25 07:15:33 PM PDT 24
Peak memory 200500 kb
Host smart-48d10444-ff4e-43ca-b837-ae5e236f23d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239720029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.1239720029
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.4226958719
Short name T525
Test name
Test status
Simulation time 13011163 ps
CPU time 0.7 seconds
Started Jul 25 07:15:33 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 199728 kb
Host smart-590ef0e8-a300-4d71-aabd-05e15d67f1cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226958719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.4226958719
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.370554008
Short name T303
Test name
Test status
Simulation time 22487731 ps
CPU time 0.87 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200480 kb
Host smart-f5b7103d-fbf6-4906-886d-d916bc266b1c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370554008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_div_intersig_mubi.370554008
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.455763595
Short name T325
Test name
Test status
Simulation time 18405702 ps
CPU time 0.82 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200512 kb
Host smart-52deb7e6-54e4-4324-a0eb-ab531164d032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455763595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.455763595
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.3099656788
Short name T268
Test name
Test status
Simulation time 512555886 ps
CPU time 2.79 seconds
Started Jul 25 07:15:28 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200568 kb
Host smart-1f96a55c-2ea0-4848-b660-00a438872f1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099656788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.3099656788
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.3525639926
Short name T767
Test name
Test status
Simulation time 618584834 ps
CPU time 3.7 seconds
Started Jul 25 07:15:31 PM PDT 24
Finished Jul 25 07:15:35 PM PDT 24
Peak memory 200652 kb
Host smart-958ea020-62ed-43be-92d9-680fa43b9d65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525639926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.3525639926
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.389604094
Short name T259
Test name
Test status
Simulation time 18096772 ps
CPU time 0.8 seconds
Started Jul 25 07:15:31 PM PDT 24
Finished Jul 25 07:15:32 PM PDT 24
Peak memory 200520 kb
Host smart-23356dd2-5a55-407c-8e09-71d9fe619f3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389604094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_idle_intersig_mubi.389604094
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.3789509527
Short name T792
Test name
Test status
Simulation time 19006680 ps
CPU time 0.82 seconds
Started Jul 25 07:15:33 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200504 kb
Host smart-6fa0744a-c746-4805-84d7-018408ecdb36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789509527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.3789509527
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3428812122
Short name T225
Test name
Test status
Simulation time 89350440 ps
CPU time 1 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200504 kb
Host smart-18fb6314-c156-49e4-9b6c-0471f29b9570
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428812122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.3428812122
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.2936042089
Short name T638
Test name
Test status
Simulation time 170654260 ps
CPU time 1.17 seconds
Started Jul 25 07:15:31 PM PDT 24
Finished Jul 25 07:15:32 PM PDT 24
Peak memory 200448 kb
Host smart-7d82ac5a-3dc2-400e-84e1-10a42485d099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936042089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2936042089
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.578090727
Short name T679
Test name
Test status
Simulation time 16673480 ps
CPU time 0.8 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 200448 kb
Host smart-f5f5cb16-a69b-4725-b217-6fc78d49dbdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578090727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.578090727
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.2518370426
Short name T753
Test name
Test status
Simulation time 6253640034 ps
CPU time 33.69 seconds
Started Jul 25 07:15:30 PM PDT 24
Finished Jul 25 07:16:04 PM PDT 24
Peak memory 200916 kb
Host smart-c68e8b56-34a6-4f60-ae94-9d9dcee6fd5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518370426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.2518370426
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.2826833217
Short name T219
Test name
Test status
Simulation time 47908494 ps
CPU time 0.94 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200500 kb
Host smart-d0f10f61-8608-4a36-9a69-b57e2295f694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826833217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2826833217
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.87657413
Short name T213
Test name
Test status
Simulation time 114245784 ps
CPU time 1.08 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:41 PM PDT 24
Peak memory 200464 kb
Host smart-ea47cfc8-924d-4a00-904f-c2fe201eef31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87657413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmg
r_alert_test.87657413
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.1087224741
Short name T671
Test name
Test status
Simulation time 21132196 ps
CPU time 0.86 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200508 kb
Host smart-ac648ec1-b1eb-47db-b5ca-6f7554ef6dff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087224741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.1087224741
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.4163032454
Short name T829
Test name
Test status
Simulation time 21643820 ps
CPU time 0.73 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:39 PM PDT 24
Peak memory 199728 kb
Host smart-b7aa6dc5-3ddd-4793-99e4-a2b1a0a687ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163032454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.4163032454
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.3368683508
Short name T719
Test name
Test status
Simulation time 29869557 ps
CPU time 0.78 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:37 PM PDT 24
Peak memory 200500 kb
Host smart-8d390879-db69-4064-8df6-ef23af8887f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368683508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.3368683508
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1914322588
Short name T663
Test name
Test status
Simulation time 73662466 ps
CPU time 0.87 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:29 PM PDT 24
Peak memory 200532 kb
Host smart-dc6d6b8a-63e4-40ed-a556-1686a1e1961c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914322588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1914322588
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.1072691026
Short name T779
Test name
Test status
Simulation time 1788758491 ps
CPU time 7.81 seconds
Started Jul 25 07:15:33 PM PDT 24
Finished Jul 25 07:15:41 PM PDT 24
Peak memory 200768 kb
Host smart-f312f273-506a-4e3b-8de0-5ae7dbd85ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072691026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.1072691026
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.3254858373
Short name T494
Test name
Test status
Simulation time 1241407888 ps
CPU time 5.23 seconds
Started Jul 25 07:15:31 PM PDT 24
Finished Jul 25 07:15:36 PM PDT 24
Peak memory 200596 kb
Host smart-012f52ba-4ade-4688-b085-1d3d9ab05d10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254858373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.3254858373
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.303068375
Short name T216
Test name
Test status
Simulation time 25322258 ps
CPU time 0.79 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:39 PM PDT 24
Peak memory 200504 kb
Host smart-134b5047-b705-4b07-9a44-3ffa559b2894
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303068375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_idle_intersig_mubi.303068375
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.3057656920
Short name T367
Test name
Test status
Simulation time 32173573 ps
CPU time 0.86 seconds
Started Jul 25 07:15:43 PM PDT 24
Finished Jul 25 07:15:44 PM PDT 24
Peak memory 200512 kb
Host smart-e95e9ef4-5159-4c9e-9f97-275d6c4b25eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057656920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.3057656920
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2848890223
Short name T756
Test name
Test status
Simulation time 14705538 ps
CPU time 0.76 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200508 kb
Host smart-d6683391-1df9-4825-b5da-dcbcedaf708a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848890223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.2848890223
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.955686544
Short name T737
Test name
Test status
Simulation time 47371891 ps
CPU time 0.88 seconds
Started Jul 25 07:15:29 PM PDT 24
Finished Jul 25 07:15:31 PM PDT 24
Peak memory 200464 kb
Host smart-964ef9c3-65a7-4289-97bf-db2993867447
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955686544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.955686544
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.2122850874
Short name T4
Test name
Test status
Simulation time 1468338013 ps
CPU time 5.56 seconds
Started Jul 25 07:15:35 PM PDT 24
Finished Jul 25 07:15:41 PM PDT 24
Peak memory 200596 kb
Host smart-89ca0784-d94d-4d24-acf9-b5feca608f95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122850874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2122850874
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.2984677059
Short name T147
Test name
Test status
Simulation time 58316675 ps
CPU time 0.97 seconds
Started Jul 25 07:15:27 PM PDT 24
Finished Jul 25 07:15:28 PM PDT 24
Peak memory 200496 kb
Host smart-28d19a27-d0b7-4d24-89ea-bc19e6960289
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984677059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.2984677059
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_trans.2826992867
Short name T443
Test name
Test status
Simulation time 40395740 ps
CPU time 1.07 seconds
Started Jul 25 07:15:32 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200428 kb
Host smart-f5cc2e5b-a51b-441c-8491-44be54d0be84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826992867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.2826992867
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.2636670534
Short name T830
Test name
Test status
Simulation time 49111709 ps
CPU time 0.84 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200504 kb
Host smart-d94a2319-048d-4772-94ae-f281ccc59aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636670534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.2636670534
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1017841546
Short name T517
Test name
Test status
Simulation time 103079608 ps
CPU time 1.18 seconds
Started Jul 25 07:14:28 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200516 kb
Host smart-53190f06-9495-455c-a2be-24fb8bc037a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017841546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1017841546
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.844891554
Short name T175
Test name
Test status
Simulation time 35537046 ps
CPU time 0.75 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 199716 kb
Host smart-4a9a577f-432a-42e6-bda6-09e4c5cb099a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844891554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.844891554
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.2274394260
Short name T400
Test name
Test status
Simulation time 15237264 ps
CPU time 0.75 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 200516 kb
Host smart-ef8c4718-9dc0-4347-a5e3-fbdfb1e8c3ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274394260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.2274394260
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.3811313272
Short name T585
Test name
Test status
Simulation time 68224537 ps
CPU time 1 seconds
Started Jul 25 07:14:20 PM PDT 24
Finished Jul 25 07:14:21 PM PDT 24
Peak memory 200524 kb
Host smart-1f8e890b-e883-4e70-975b-9e24323866b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811313272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.3811313272
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.498548575
Short name T587
Test name
Test status
Simulation time 351272626 ps
CPU time 2.22 seconds
Started Jul 25 07:14:24 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200552 kb
Host smart-f21154c4-239b-40d4-894c-341de6bb74af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498548575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.498548575
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.2482495578
Short name T758
Test name
Test status
Simulation time 1707805084 ps
CPU time 8.9 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:30 PM PDT 24
Peak memory 200632 kb
Host smart-dbd0e39d-7811-41d6-937a-b6c0f4143ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482495578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.2482495578
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.4150607743
Short name T25
Test name
Test status
Simulation time 46782824 ps
CPU time 0.86 seconds
Started Jul 25 07:14:24 PM PDT 24
Finished Jul 25 07:14:25 PM PDT 24
Peak memory 200512 kb
Host smart-d165a113-affb-454f-8b7f-267f805bcc81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150607743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.4150607743
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.2623786572
Short name T364
Test name
Test status
Simulation time 22472226 ps
CPU time 0.9 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200536 kb
Host smart-90cfd008-1a9e-4ef6-99fd-86cafd55f4d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623786572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.2623786572
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3913301062
Short name T493
Test name
Test status
Simulation time 52283740 ps
CPU time 0.9 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200472 kb
Host smart-102363b9-e150-410f-8011-eeefef460801
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913301062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.3913301062
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.2563789195
Short name T260
Test name
Test status
Simulation time 45288587 ps
CPU time 0.88 seconds
Started Jul 25 07:14:20 PM PDT 24
Finished Jul 25 07:14:21 PM PDT 24
Peak memory 200464 kb
Host smart-68c73ce0-90e3-46db-8684-bc672e5988af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563789195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2563789195
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.3197117686
Short name T297
Test name
Test status
Simulation time 230417096 ps
CPU time 1.71 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:30 PM PDT 24
Peak memory 200288 kb
Host smart-6426f83e-7c8d-4af3-8571-ecf7241d12e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197117686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3197117686
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.1452420717
Short name T53
Test name
Test status
Simulation time 162913201 ps
CPU time 2.13 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 216020 kb
Host smart-72efded1-9bd9-4983-a198-3cf734995f25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452420717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.1452420717
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.605219460
Short name T142
Test name
Test status
Simulation time 85144973 ps
CPU time 0.99 seconds
Started Jul 25 07:14:21 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200476 kb
Host smart-fe7d9611-1439-4936-848d-0e92e14e582f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605219460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.605219460
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.1426046668
Short name T43
Test name
Test status
Simulation time 14382519510 ps
CPU time 55.64 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:15:22 PM PDT 24
Peak memory 200844 kb
Host smart-b3a0c423-9354-4662-8aba-2a354b744a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426046668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.1426046668
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.1373667010
Short name T563
Test name
Test status
Simulation time 92923841 ps
CPU time 1.1 seconds
Started Jul 25 07:14:25 PM PDT 24
Finished Jul 25 07:14:26 PM PDT 24
Peak memory 200516 kb
Host smart-3b41e8b7-516f-4384-83c7-fd5ce1ceabe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373667010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1373667010
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1116760985
Short name T574
Test name
Test status
Simulation time 17424346 ps
CPU time 0.8 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:39 PM PDT 24
Peak memory 200544 kb
Host smart-5808974a-5c2a-45b0-bba8-68712d19b4df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116760985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1116760985
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.2282465453
Short name T183
Test name
Test status
Simulation time 73764687 ps
CPU time 0.98 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:37 PM PDT 24
Peak memory 200516 kb
Host smart-9af804d4-b7e9-49bb-a0b8-7b68e2c15ac5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282465453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.2282465453
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.4050566822
Short name T665
Test name
Test status
Simulation time 16204678 ps
CPU time 0.74 seconds
Started Jul 25 07:15:37 PM PDT 24
Finished Jul 25 07:15:38 PM PDT 24
Peak memory 199752 kb
Host smart-e73160ce-0934-40f5-9369-e789d72ceba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050566822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.4050566822
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.3999743516
Short name T804
Test name
Test status
Simulation time 86545765 ps
CPU time 0.98 seconds
Started Jul 25 07:15:37 PM PDT 24
Finished Jul 25 07:15:38 PM PDT 24
Peak memory 200496 kb
Host smart-a30b781a-9c55-4d56-8f13-6ab036b2b51e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999743516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.3999743516
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.2231430381
Short name T580
Test name
Test status
Simulation time 17634151 ps
CPU time 0.78 seconds
Started Jul 25 07:15:37 PM PDT 24
Finished Jul 25 07:15:38 PM PDT 24
Peak memory 200468 kb
Host smart-82592792-0caa-46cd-aa8f-b8ae3c57ec22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231430381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2231430381
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.2800347208
Short name T425
Test name
Test status
Simulation time 2120347240 ps
CPU time 15.79 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:52 PM PDT 24
Peak memory 200788 kb
Host smart-b54abe2f-f912-467c-be15-41856990bfc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800347208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2800347208
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.2333972237
Short name T708
Test name
Test status
Simulation time 626625188 ps
CPU time 2.57 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:38 PM PDT 24
Peak memory 200624 kb
Host smart-283664f0-aed2-491c-9995-cb2d35099a6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333972237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.2333972237
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2025550889
Short name T483
Test name
Test status
Simulation time 22280775 ps
CPU time 0.85 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200496 kb
Host smart-cdce72f5-a9de-4a69-806a-eaf33159d53c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025550889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.2025550889
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1797885703
Short name T793
Test name
Test status
Simulation time 40477812 ps
CPU time 0.84 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200456 kb
Host smart-132d813c-aaba-4f08-b05b-1bbd482dbed0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797885703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.1797885703
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.992086844
Short name T691
Test name
Test status
Simulation time 19144464 ps
CPU time 0.77 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:08 PM PDT 24
Peak memory 200492 kb
Host smart-39e362dd-7774-4ae8-8354-f5a84d7f238b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992086844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_ctrl_intersig_mubi.992086844
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.3715860313
Short name T755
Test name
Test status
Simulation time 41948935 ps
CPU time 0.83 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:37 PM PDT 24
Peak memory 200524 kb
Host smart-a1b02207-4802-4cbf-9897-29955e15f755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715860313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3715860313
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.164791981
Short name T334
Test name
Test status
Simulation time 1191789878 ps
CPU time 4.45 seconds
Started Jul 25 07:15:37 PM PDT 24
Finished Jul 25 07:15:42 PM PDT 24
Peak memory 200700 kb
Host smart-4c03cd62-f776-4edb-a5e9-e5dbf5eb935f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164791981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.164791981
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.936839808
Short name T485
Test name
Test status
Simulation time 55308971 ps
CPU time 0.97 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200400 kb
Host smart-ebef259f-98c4-40cf-8751-129a97958e88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936839808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.936839808
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.668013811
Short name T359
Test name
Test status
Simulation time 9638438707 ps
CPU time 43.12 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:16:19 PM PDT 24
Peak memory 200888 kb
Host smart-9799f4fe-a2cb-4e25-a526-89b9da15457e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668013811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.668013811
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.2364062769
Short name T668
Test name
Test status
Simulation time 214528048741 ps
CPU time 932.28 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:31:12 PM PDT 24
Peak memory 209212 kb
Host smart-30d2f9ca-2f7f-4acd-87b7-19b72e5306f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2364062769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2364062769
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.388227330
Short name T287
Test name
Test status
Simulation time 32486609 ps
CPU time 0.75 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:37 PM PDT 24
Peak memory 200508 kb
Host smart-567092a8-3841-4ca2-be35-ef459f8cea42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388227330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.388227330
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1751671074
Short name T698
Test name
Test status
Simulation time 70464037 ps
CPU time 0.96 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200472 kb
Host smart-b88c4cd7-7af8-4ae4-b9de-7733b157f8f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751671074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1751671074
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3428988791
Short name T632
Test name
Test status
Simulation time 52354788 ps
CPU time 0.85 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:39 PM PDT 24
Peak memory 200472 kb
Host smart-ba4c3141-1bc2-4f0f-bdd2-696cd151c5d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428988791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.3428988791
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.2625018920
Short name T397
Test name
Test status
Simulation time 91119507 ps
CPU time 0.88 seconds
Started Jul 25 07:15:37 PM PDT 24
Finished Jul 25 07:15:38 PM PDT 24
Peak memory 200428 kb
Host smart-4eef82c8-7da7-4bef-b9b7-59ccd4307fb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625018920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2625018920
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.1125313110
Short name T635
Test name
Test status
Simulation time 53949767 ps
CPU time 0.99 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200520 kb
Host smart-9181048b-1044-4e29-9326-799acac47b49
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125313110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.1125313110
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.58899200
Short name T434
Test name
Test status
Simulation time 38090860 ps
CPU time 0.94 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200460 kb
Host smart-057347ac-20ce-4f46-a293-76340ab8d8c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58899200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.58899200
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1154914642
Short name T409
Test name
Test status
Simulation time 1051894685 ps
CPU time 4.92 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:43 PM PDT 24
Peak memory 200588 kb
Host smart-68a8d3b9-99ba-4f64-b3d8-403c12105375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154914642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1154914642
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.1904858798
Short name T202
Test name
Test status
Simulation time 262911512 ps
CPU time 2.6 seconds
Started Jul 25 07:15:41 PM PDT 24
Finished Jul 25 07:15:44 PM PDT 24
Peak memory 200572 kb
Host smart-ea28af85-b316-44a2-9492-b751664728c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904858798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.1904858798
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3979091934
Short name T740
Test name
Test status
Simulation time 26768096 ps
CPU time 0.81 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:39 PM PDT 24
Peak memory 200516 kb
Host smart-d13fd02c-43e1-4113-8263-c4e54115fbe2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979091934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.3979091934
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1548138244
Short name T826
Test name
Test status
Simulation time 22770127 ps
CPU time 0.82 seconds
Started Jul 25 07:15:40 PM PDT 24
Finished Jul 25 07:15:41 PM PDT 24
Peak memory 200548 kb
Host smart-24884fee-d983-4a34-9bfa-f907850e9671
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548138244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1548138244
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1089617154
Short name T207
Test name
Test status
Simulation time 13383186 ps
CPU time 0.72 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:39 PM PDT 24
Peak memory 200508 kb
Host smart-9e16da11-6c2b-41d8-9bd9-0ab27c401e1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089617154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.1089617154
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.3983409517
Short name T29
Test name
Test status
Simulation time 35708863 ps
CPU time 0.77 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:37 PM PDT 24
Peak memory 200452 kb
Host smart-b5dba827-5fba-4d8b-8055-8094bd8b3a6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983409517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.3983409517
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.2633121678
Short name T700
Test name
Test status
Simulation time 314004061 ps
CPU time 2.15 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:42 PM PDT 24
Peak memory 200512 kb
Host smart-4cd7d6a0-c72c-403a-bc2a-e099726f3856
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633121678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.2633121678
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.964563538
Short name T500
Test name
Test status
Simulation time 41520606 ps
CPU time 0.9 seconds
Started Jul 25 07:15:36 PM PDT 24
Finished Jul 25 07:15:38 PM PDT 24
Peak memory 200464 kb
Host smart-47fe559a-8f0e-4fc0-941e-723b15898bac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964563538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.964563538
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.3485531787
Short name T661
Test name
Test status
Simulation time 11241702265 ps
CPU time 57.34 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:16:36 PM PDT 24
Peak memory 200920 kb
Host smart-93bef46d-e9cc-4da0-b08b-0ff936d2cbad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485531787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.3485531787
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.198363924
Short name T74
Test name
Test status
Simulation time 28134613183 ps
CPU time 459.13 seconds
Started Jul 25 07:15:40 PM PDT 24
Finished Jul 25 07:23:19 PM PDT 24
Peak memory 209132 kb
Host smart-5b5e7540-9ba7-4341-986a-b44955f7f9b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=198363924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.198363924
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.244258702
Short name T243
Test name
Test status
Simulation time 51060656 ps
CPU time 1.01 seconds
Started Jul 25 07:15:42 PM PDT 24
Finished Jul 25 07:15:43 PM PDT 24
Peak memory 200496 kb
Host smart-8bf4dfe6-beb1-4370-a0fe-fa15df81a2e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244258702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.244258702
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.2780825068
Short name T621
Test name
Test status
Simulation time 33074888 ps
CPU time 0.81 seconds
Started Jul 25 07:15:51 PM PDT 24
Finished Jul 25 07:15:52 PM PDT 24
Peak memory 200508 kb
Host smart-27d2687e-eede-49d2-9d1c-d44161fc9699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780825068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.2780825068
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3282875188
Short name T479
Test name
Test status
Simulation time 89227153 ps
CPU time 1.11 seconds
Started Jul 25 07:15:46 PM PDT 24
Finished Jul 25 07:15:47 PM PDT 24
Peak memory 200528 kb
Host smart-d1aca759-21ec-4eb7-9738-73a8608a5fbc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282875188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3282875188
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.1970734790
Short name T541
Test name
Test status
Simulation time 47365687 ps
CPU time 0.79 seconds
Started Jul 25 07:15:40 PM PDT 24
Finished Jul 25 07:15:41 PM PDT 24
Peak memory 199704 kb
Host smart-fdf9ac5f-8a27-41d8-a930-e008a300d235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970734790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1970734790
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2546033139
Short name T589
Test name
Test status
Simulation time 27915059 ps
CPU time 0.81 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200496 kb
Host smart-a5f08914-e5aa-4460-a100-4e55f8156f70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546033139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2546033139
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.1326428014
Short name T822
Test name
Test status
Simulation time 81721685 ps
CPU time 1.07 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200480 kb
Host smart-19d1f68a-143a-41fc-a74f-969338406e68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326428014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1326428014
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.451553269
Short name T532
Test name
Test status
Simulation time 905043973 ps
CPU time 4.27 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:42 PM PDT 24
Peak memory 200576 kb
Host smart-47f16d39-b53d-4e92-b0e4-29a34b2334b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451553269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.451553269
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.796289322
Short name T190
Test name
Test status
Simulation time 1833890884 ps
CPU time 7.45 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:47 PM PDT 24
Peak memory 200600 kb
Host smart-5f0e8789-26fa-4618-8b50-aa4b40f1c63b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796289322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti
meout.796289322
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.3221415721
Short name T639
Test name
Test status
Simulation time 28296908 ps
CPU time 0.91 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:41 PM PDT 24
Peak memory 200460 kb
Host smart-8f454d66-7537-4a12-b68e-b926bdb657b0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221415721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.3221415721
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1818697442
Short name T498
Test name
Test status
Simulation time 18710206 ps
CPU time 0.85 seconds
Started Jul 25 07:15:58 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200508 kb
Host smart-c2059e51-e7d8-4299-9442-d6ec313befc8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818697442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.1818697442
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.871207808
Short name T181
Test name
Test status
Simulation time 18620255 ps
CPU time 0.8 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200520 kb
Host smart-95200eb1-54f1-4435-8550-580fc32a64e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871207808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_ctrl_intersig_mubi.871207808
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.3228072825
Short name T553
Test name
Test status
Simulation time 41710259 ps
CPU time 0.88 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200412 kb
Host smart-70df9533-c332-45b1-83e1-9b67d8b211d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228072825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3228072825
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.2979132188
Short name T204
Test name
Test status
Simulation time 260390104 ps
CPU time 1.49 seconds
Started Jul 25 07:15:51 PM PDT 24
Finished Jul 25 07:15:53 PM PDT 24
Peak memory 200456 kb
Host smart-4bd5f526-967a-42d0-88dd-aca29b500954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979132188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.2979132188
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.3452371432
Short name T722
Test name
Test status
Simulation time 76558464 ps
CPU time 1.05 seconds
Started Jul 25 07:15:39 PM PDT 24
Finished Jul 25 07:15:41 PM PDT 24
Peak memory 200412 kb
Host smart-6d130e70-c29f-4ace-a556-8c9bef65321d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452371432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3452371432
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.4267379131
Short name T383
Test name
Test status
Simulation time 6138933979 ps
CPU time 44.54 seconds
Started Jul 25 07:15:43 PM PDT 24
Finished Jul 25 07:16:28 PM PDT 24
Peak memory 200904 kb
Host smart-38d47262-6061-4019-b4e5-ed8c4a75003e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267379131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.4267379131
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.192787684
Short name T44
Test name
Test status
Simulation time 36280295 ps
CPU time 1.02 seconds
Started Jul 25 07:15:38 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200476 kb
Host smart-6700460b-6c41-4b10-8d72-8046c8f42e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192787684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.192787684
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1943583486
Short name T457
Test name
Test status
Simulation time 82250652 ps
CPU time 0.9 seconds
Started Jul 25 07:15:46 PM PDT 24
Finished Jul 25 07:15:47 PM PDT 24
Peak memory 200484 kb
Host smart-bb8a089e-db43-4f6c-af4c-924553502f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943583486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1943583486
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2263737285
Short name T61
Test name
Test status
Simulation time 22119995 ps
CPU time 0.83 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200512 kb
Host smart-3e280517-acbf-469d-8f3a-6e9eb46abf6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263737285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.2263737285
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.349343114
Short name T762
Test name
Test status
Simulation time 26486548 ps
CPU time 0.73 seconds
Started Jul 25 07:15:51 PM PDT 24
Finished Jul 25 07:15:52 PM PDT 24
Peak memory 199732 kb
Host smart-be9a6af6-72f0-4a25-a641-0b2bb03f9870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349343114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.349343114
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3978853549
Short name T276
Test name
Test status
Simulation time 35849966 ps
CPU time 0.8 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200488 kb
Host smart-f5929df5-de1e-460a-9c74-5149613d4f76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978853549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.3978853549
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.3374794803
Short name T637
Test name
Test status
Simulation time 18396006 ps
CPU time 0.8 seconds
Started Jul 25 07:15:51 PM PDT 24
Finished Jul 25 07:15:52 PM PDT 24
Peak memory 200496 kb
Host smart-deaaec61-7f91-4898-84a1-69590e7a10f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374794803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.3374794803
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.1523753112
Short name T264
Test name
Test status
Simulation time 1163120373 ps
CPU time 9.09 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 200576 kb
Host smart-3f863719-ce6d-4347-9451-39bb7a5e90c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523753112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.1523753112
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.1742860670
Short name T312
Test name
Test status
Simulation time 1696890149 ps
CPU time 11.88 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:16:01 PM PDT 24
Peak memory 200624 kb
Host smart-93a2dd68-f030-47b7-8194-a388214ad39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742860670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.1742860670
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.1136315124
Short name T284
Test name
Test status
Simulation time 110081866 ps
CPU time 1.28 seconds
Started Jul 25 07:15:50 PM PDT 24
Finished Jul 25 07:15:52 PM PDT 24
Peak memory 200500 kb
Host smart-44faffdd-5c8d-4577-bde7-3276f2dfac47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136315124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.1136315124
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3601756162
Short name T598
Test name
Test status
Simulation time 67763637 ps
CPU time 0.95 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200492 kb
Host smart-92ded957-2e72-4e89-8a70-c7664e4e6bd9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601756162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3601756162
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3940705144
Short name T537
Test name
Test status
Simulation time 22500217 ps
CPU time 0.77 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200504 kb
Host smart-a40ac23d-950f-4dc4-a853-2be2db4a8a70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940705144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.3940705144
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.1513527299
Short name T338
Test name
Test status
Simulation time 18926402 ps
CPU time 0.82 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200424 kb
Host smart-c25dc8a0-7718-4846-8891-c70f42ce920d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513527299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1513527299
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.1767406452
Short name T588
Test name
Test status
Simulation time 1024754384 ps
CPU time 4.41 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:52 PM PDT 24
Peak memory 200684 kb
Host smart-3f64c4c0-1218-4e71-bc72-e834489369d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767406452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1767406452
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.3341526022
Short name T274
Test name
Test status
Simulation time 59988118 ps
CPU time 0.97 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200428 kb
Host smart-95a8b363-bd79-43d5-9a14-4b6f364ee090
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341526022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.3341526022
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.511654269
Short name T263
Test name
Test status
Simulation time 66552091 ps
CPU time 0.96 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200512 kb
Host smart-98957d98-51fd-4361-9bf4-ecfc5c7d3c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511654269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.511654269
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.1424032205
Short name T391
Test name
Test status
Simulation time 91625664 ps
CPU time 1.14 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200524 kb
Host smart-f20e8338-86f2-4297-8ab2-16e9beaa297e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424032205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1424032205
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.1803859091
Short name T465
Test name
Test status
Simulation time 37577087 ps
CPU time 0.8 seconds
Started Jul 25 07:15:45 PM PDT 24
Finished Jul 25 07:15:46 PM PDT 24
Peak memory 200508 kb
Host smart-5602d069-01a5-4095-8d32-2243f04c2472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803859091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.1803859091
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.175470930
Short name T151
Test name
Test status
Simulation time 15402003 ps
CPU time 0.72 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200568 kb
Host smart-2ddcfffb-e8da-48a2-8ea9-b613fefd69d7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175470930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.175470930
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.1276591013
Short name T47
Test name
Test status
Simulation time 42509732 ps
CPU time 0.76 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200464 kb
Host smart-3ef12b68-0813-40ef-a132-5b1536a4cd5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276591013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.1276591013
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.64090667
Short name T702
Test name
Test status
Simulation time 22454225 ps
CPU time 0.83 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:47 PM PDT 24
Peak memory 200480 kb
Host smart-8f94c6f6-5338-4ad2-8458-12e883496b9d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64090667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.clkmgr_div_intersig_mubi.64090667
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.1488567704
Short name T703
Test name
Test status
Simulation time 121678653 ps
CPU time 1.15 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:15:51 PM PDT 24
Peak memory 200488 kb
Host smart-c38d16cb-ee93-4c59-85f2-411058270a81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488567704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.1488567704
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.3255665271
Short name T36
Test name
Test status
Simulation time 1053348424 ps
CPU time 5.1 seconds
Started Jul 25 07:15:46 PM PDT 24
Finished Jul 25 07:15:51 PM PDT 24
Peak memory 200644 kb
Host smart-89174e02-a847-4154-bf5c-c077b89a6cca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255665271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3255665271
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.643548439
Short name T565
Test name
Test status
Simulation time 1832762181 ps
CPU time 8.54 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 200576 kb
Host smart-7ff21c6d-d7cc-45a0-a104-5c3c995640a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643548439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti
meout.643548439
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.3731420408
Short name T337
Test name
Test status
Simulation time 23449567 ps
CPU time 0.84 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200512 kb
Host smart-afa136f3-ee35-401c-a7bf-2de699fd253f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731420408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.3731420408
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.3667194445
Short name T194
Test name
Test status
Simulation time 14670690 ps
CPU time 0.78 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200512 kb
Host smart-4cc924b7-0457-420d-83e1-8a1f7ba44296
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667194445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.3667194445
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.185206596
Short name T262
Test name
Test status
Simulation time 38074508 ps
CPU time 0.96 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200460 kb
Host smart-e9ad97b9-41b3-4b07-830e-83204a7a24b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185206596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_ctrl_intersig_mubi.185206596
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.3864388958
Short name T310
Test name
Test status
Simulation time 32696373 ps
CPU time 0.78 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200464 kb
Host smart-fb17bd91-26f5-431a-861d-906a9c44cbb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864388958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.3864388958
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2112811973
Short name T569
Test name
Test status
Simulation time 364599292 ps
CPU time 2.61 seconds
Started Jul 25 07:15:46 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200416 kb
Host smart-e74dd155-fe55-40f8-a479-b89c9252ae65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112811973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2112811973
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.2654184995
Short name T646
Test name
Test status
Simulation time 18334757 ps
CPU time 0.83 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200444 kb
Host smart-a5cd15a2-0675-4cbd-b6c5-9dbf057563ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654184995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2654184995
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.3157022020
Short name T376
Test name
Test status
Simulation time 3296444482 ps
CPU time 18.01 seconds
Started Jul 25 07:15:45 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200948 kb
Host smart-2a3c191a-ed19-4aa1-9dec-72afa6180712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157022020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.3157022020
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.3878466490
Short name T596
Test name
Test status
Simulation time 20980132 ps
CPU time 0.74 seconds
Started Jul 25 07:15:45 PM PDT 24
Finished Jul 25 07:15:45 PM PDT 24
Peak memory 200528 kb
Host smart-819b5ca2-462d-4843-ac37-02bf678903d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878466490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.3878466490
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.2379206697
Short name T568
Test name
Test status
Simulation time 115987438 ps
CPU time 1.06 seconds
Started Jul 25 07:15:53 PM PDT 24
Finished Jul 25 07:15:54 PM PDT 24
Peak memory 200504 kb
Host smart-fd5f3966-c39b-4e97-bddf-df748837a4ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379206697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.2379206697
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.1987235895
Short name T438
Test name
Test status
Simulation time 19775629 ps
CPU time 0.83 seconds
Started Jul 25 07:15:52 PM PDT 24
Finished Jul 25 07:15:53 PM PDT 24
Peak memory 200528 kb
Host smart-b1f03a78-4c90-410c-9fd8-82f5a7eea092
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987235895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.1987235895
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.2711808899
Short name T177
Test name
Test status
Simulation time 47850154 ps
CPU time 0.81 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 199708 kb
Host smart-290674ae-ae84-40ff-9257-1bfaecb1ad13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711808899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2711808899
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.4144666077
Short name T468
Test name
Test status
Simulation time 63898906 ps
CPU time 0.84 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200512 kb
Host smart-572be2b8-7888-4c15-92b6-f591a3a637b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144666077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.4144666077
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.754448210
Short name T797
Test name
Test status
Simulation time 43486801 ps
CPU time 0.9 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200484 kb
Host smart-4214ca36-0e73-4fe3-991f-31e21787dc98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754448210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.754448210
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2809357182
Short name T300
Test name
Test status
Simulation time 578087253 ps
CPU time 2.66 seconds
Started Jul 25 07:15:50 PM PDT 24
Finished Jul 25 07:15:53 PM PDT 24
Peak memory 200592 kb
Host smart-5e262dc0-29a0-4aa1-ba39-a2c7ea541abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809357182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2809357182
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.1754181434
Short name T648
Test name
Test status
Simulation time 387511843 ps
CPU time 2.73 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200632 kb
Host smart-b7bff368-43af-4c81-a52d-ad2d421671b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754181434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.1754181434
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.368716697
Short name T821
Test name
Test status
Simulation time 47777150 ps
CPU time 0.83 seconds
Started Jul 25 07:15:46 PM PDT 24
Finished Jul 25 07:15:47 PM PDT 24
Peak memory 200508 kb
Host smart-78276db0-cb3f-43a4-8888-0c5f1a7b3235
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368716697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_idle_intersig_mubi.368716697
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2649681300
Short name T32
Test name
Test status
Simulation time 32992527 ps
CPU time 0.91 seconds
Started Jul 25 07:15:50 PM PDT 24
Finished Jul 25 07:15:51 PM PDT 24
Peak memory 200508 kb
Host smart-1471f52c-c2c6-4da0-9498-11dadafa3291
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649681300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2649681300
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.2000294380
Short name T555
Test name
Test status
Simulation time 41631468 ps
CPU time 0.93 seconds
Started Jul 25 07:15:50 PM PDT 24
Finished Jul 25 07:15:51 PM PDT 24
Peak memory 200560 kb
Host smart-26e14fe0-b020-4ba4-a3aa-d87dd44d7939
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000294380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.2000294380
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.1941363765
Short name T281
Test name
Test status
Simulation time 24100458 ps
CPU time 0.77 seconds
Started Jul 25 07:15:49 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200500 kb
Host smart-3a4a355a-af5b-4798-85dc-1fb56bcafe15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941363765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1941363765
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.578458313
Short name T157
Test name
Test status
Simulation time 473201886 ps
CPU time 3 seconds
Started Jul 25 07:15:51 PM PDT 24
Finished Jul 25 07:15:54 PM PDT 24
Peak memory 200708 kb
Host smart-15bbe81e-4ab2-4843-a146-427560fbdb42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578458313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.578458313
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.511743328
Short name T405
Test name
Test status
Simulation time 65837761 ps
CPU time 1.01 seconds
Started Jul 25 07:15:48 PM PDT 24
Finished Jul 25 07:15:49 PM PDT 24
Peak memory 200452 kb
Host smart-0da43899-58d7-4c9d-9c28-78677fff403e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511743328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.511743328
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.2620902642
Short name T550
Test name
Test status
Simulation time 7519141164 ps
CPU time 53.6 seconds
Started Jul 25 07:15:54 PM PDT 24
Finished Jul 25 07:16:48 PM PDT 24
Peak memory 200892 kb
Host smart-94142f36-6401-463c-8488-9329064f9660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620902642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.2620902642
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.2930842945
Short name T344
Test name
Test status
Simulation time 31557006998 ps
CPU time 517.76 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:24:33 PM PDT 24
Peak memory 217428 kb
Host smart-ecb04859-26f7-4218-89c2-78c0b36d02c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2930842945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.2930842945
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1183843609
Short name T462
Test name
Test status
Simulation time 26817069 ps
CPU time 0.76 seconds
Started Jul 25 07:15:47 PM PDT 24
Finished Jul 25 07:15:48 PM PDT 24
Peak memory 200520 kb
Host smart-5610b0e2-0573-481f-9c4e-d39ae72267b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183843609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1183843609
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3184218249
Short name T602
Test name
Test status
Simulation time 30113685 ps
CPU time 0.91 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200484 kb
Host smart-ac904f83-b2b5-4902-a9ad-b189223d3cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184218249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3184218249
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1956634487
Short name T683
Test name
Test status
Simulation time 66525002 ps
CPU time 0.95 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200524 kb
Host smart-8a9523b0-57e6-4d82-9201-befa5efc4ef3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956634487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.1956634487
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.3942136489
Short name T813
Test name
Test status
Simulation time 67295447 ps
CPU time 0.84 seconds
Started Jul 25 07:15:53 PM PDT 24
Finished Jul 25 07:15:55 PM PDT 24
Peak memory 200448 kb
Host smart-a574a7f7-9351-4b8b-b1e4-295ed7c54ed4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942136489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.3942136489
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.1362911543
Short name T261
Test name
Test status
Simulation time 31273035 ps
CPU time 0.8 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200500 kb
Host smart-de4df413-90dd-4b10-8704-a66e1064df4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362911543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.1362911543
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.3079532951
Short name T734
Test name
Test status
Simulation time 97163340 ps
CPU time 1.06 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200528 kb
Host smart-35c9478f-78cf-4990-8f6d-6bca821db2fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079532951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3079532951
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.3716059653
Short name T34
Test name
Test status
Simulation time 195318801 ps
CPU time 2.15 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200560 kb
Host smart-5fab935e-ec02-4312-8e6e-6c4918dffc75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716059653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.3716059653
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.2632845820
Short name T803
Test name
Test status
Simulation time 1662765618 ps
CPU time 7.31 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:16:04 PM PDT 24
Peak memory 200600 kb
Host smart-36c7b7e2-b9a1-442f-860b-90c132a014c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632845820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.2632845820
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.558868827
Short name T426
Test name
Test status
Simulation time 26586672 ps
CPU time 0.81 seconds
Started Jul 25 07:15:53 PM PDT 24
Finished Jul 25 07:15:54 PM PDT 24
Peak memory 200516 kb
Host smart-0373f5e0-1ea4-4cec-a5f2-677b979a2129
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558868827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_idle_intersig_mubi.558868827
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.443373273
Short name T812
Test name
Test status
Simulation time 50877080 ps
CPU time 0.87 seconds
Started Jul 25 07:15:53 PM PDT 24
Finished Jul 25 07:15:54 PM PDT 24
Peak memory 200508 kb
Host smart-9ce6e122-9d9d-434b-b238-2c0978a486c1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443373273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_clk_byp_req_intersig_mubi.443373273
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3607630878
Short name T620
Test name
Test status
Simulation time 122092376 ps
CPU time 1.13 seconds
Started Jul 25 07:15:59 PM PDT 24
Finished Jul 25 07:16:00 PM PDT 24
Peak memory 200516 kb
Host smart-7016d31d-63a9-4799-90ad-1d197de8c018
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607630878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.3607630878
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1270947403
Short name T56
Test name
Test status
Simulation time 13708628 ps
CPU time 0.73 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200448 kb
Host smart-08f233bb-a05d-4261-b8b1-617a4941a8e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270947403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1270947403
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.2102625747
Short name T158
Test name
Test status
Simulation time 774331504 ps
CPU time 4.84 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:16:00 PM PDT 24
Peak memory 200660 kb
Host smart-c5e50821-45a0-4a89-a397-644e81e99b00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102625747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2102625747
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.2063534441
Short name T366
Test name
Test status
Simulation time 322654871 ps
CPU time 1.73 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 200452 kb
Host smart-827557b9-f626-4f70-8f52-707cbb439e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063534441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.2063534441
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.3846831253
Short name T547
Test name
Test status
Simulation time 4997680306 ps
CPU time 22.2 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:16:18 PM PDT 24
Peak memory 200848 kb
Host smart-56684f5b-4003-498d-ab99-e5727460f0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846831253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.3846831253
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.2508179811
Short name T599
Test name
Test status
Simulation time 123847753 ps
CPU time 1.25 seconds
Started Jul 25 07:15:58 PM PDT 24
Finished Jul 25 07:16:00 PM PDT 24
Peak memory 200500 kb
Host smart-475e244a-eab9-4c99-911d-ec118da495e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508179811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.2508179811
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3421551562
Short name T256
Test name
Test status
Simulation time 67723043 ps
CPU time 0.98 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 200504 kb
Host smart-b096a814-2e91-43e8-8efb-db01fc13c19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421551562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3421551562
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.3666944786
Short name T273
Test name
Test status
Simulation time 26644907 ps
CPU time 0.96 seconds
Started Jul 25 07:16:01 PM PDT 24
Finished Jul 25 07:16:02 PM PDT 24
Peak memory 200536 kb
Host smart-94e4c1fe-7f9f-4c9e-a0b3-bf15bac7f3e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666944786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.3666944786
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.4213522374
Short name T791
Test name
Test status
Simulation time 15582575 ps
CPU time 0.7 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 199720 kb
Host smart-f4b16609-acf5-4451-bbf4-5659770f207a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213522374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.4213522374
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.2627262645
Short name T548
Test name
Test status
Simulation time 44494670 ps
CPU time 0.96 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200464 kb
Host smart-285ca9da-6a14-43af-8f3c-8df9deaa52d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627262645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.2627262645
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.2727819750
Short name T170
Test name
Test status
Simulation time 19335531 ps
CPU time 0.81 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200448 kb
Host smart-f25a9e9f-8c12-4204-903a-b38281230bce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727819750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2727819750
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.2569547156
Short name T415
Test name
Test status
Simulation time 401099186 ps
CPU time 2.06 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 200560 kb
Host smart-ef503ebd-58dc-43d5-b311-98f6c00b1811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569547156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2569547156
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.2990572964
Short name T450
Test name
Test status
Simulation time 2066063754 ps
CPU time 9.83 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:16:06 PM PDT 24
Peak memory 200836 kb
Host smart-14abc7ab-e899-46f5-b529-2c5ce5313ef8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990572964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.2990572964
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.359651490
Short name T288
Test name
Test status
Simulation time 61495013 ps
CPU time 1.09 seconds
Started Jul 25 07:15:53 PM PDT 24
Finished Jul 25 07:15:54 PM PDT 24
Peak memory 200468 kb
Host smart-310d7716-ef0f-4e61-b787-a0ab1d7acba8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359651490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.clkmgr_idle_intersig_mubi.359651490
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3256527724
Short name T582
Test name
Test status
Simulation time 46498064 ps
CPU time 0.82 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200520 kb
Host smart-130a13a3-9706-48b2-82d6-c86de4d46d3c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256527724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.3256527724
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1384234648
Short name T652
Test name
Test status
Simulation time 18926072 ps
CPU time 0.73 seconds
Started Jul 25 07:15:58 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 200504 kb
Host smart-8ef0c953-62cd-41ed-b038-332a611cabe0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384234648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.1384234648
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.3488195793
Short name T290
Test name
Test status
Simulation time 17256042 ps
CPU time 0.81 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200448 kb
Host smart-e8fb4f81-87f7-4a2c-b0c4-9026a23ff374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488195793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3488195793
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1641205104
Short name T513
Test name
Test status
Simulation time 751765225 ps
CPU time 3.65 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200700 kb
Host smart-d35c2d69-0e45-476f-8e0a-73e0e65b7ae0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641205104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1641205104
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.3618100301
Short name T252
Test name
Test status
Simulation time 160409031 ps
CPU time 1.28 seconds
Started Jul 25 07:15:53 PM PDT 24
Finished Jul 25 07:15:54 PM PDT 24
Peak memory 200428 kb
Host smart-f149910d-89cb-4b31-bc2f-2eac0547e1ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618100301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3618100301
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.4083956823
Short name T320
Test name
Test status
Simulation time 2513324844 ps
CPU time 19.54 seconds
Started Jul 25 07:15:52 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200884 kb
Host smart-ffc9588e-0c2c-4af1-9229-92e771f824d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083956823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.4083956823
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.566827905
Short name T527
Test name
Test status
Simulation time 412911228 ps
CPU time 2.31 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200476 kb
Host smart-a59c154d-43a2-4e9d-b8e4-e7900701e5ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566827905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.566827905
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.528817147
Short name T326
Test name
Test status
Simulation time 21904040 ps
CPU time 0.76 seconds
Started Jul 25 07:15:58 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200508 kb
Host smart-65dfcf1f-7fce-4b7b-81cf-63152a99eddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528817147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkm
gr_alert_test.528817147
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.4014374611
Short name T81
Test name
Test status
Simulation time 24136985 ps
CPU time 0.93 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200564 kb
Host smart-3a81438f-8138-4db0-92b6-2e2d393de5b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014374611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.4014374611
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.1451299232
Short name T385
Test name
Test status
Simulation time 58194526 ps
CPU time 0.82 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 199704 kb
Host smart-7d60f020-db13-4ccd-b6ec-7bb8dafbe785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451299232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1451299232
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.1529619052
Short name T749
Test name
Test status
Simulation time 40268488 ps
CPU time 0.82 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200488 kb
Host smart-9acbe79f-4000-4384-b3e5-360ba1d50626
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529619052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.1529619052
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.1676907819
Short name T651
Test name
Test status
Simulation time 33876222 ps
CPU time 0.83 seconds
Started Jul 25 07:15:52 PM PDT 24
Finished Jul 25 07:15:53 PM PDT 24
Peak memory 200484 kb
Host smart-7cbb0c7f-774c-4c03-833b-567bd27f0696
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676907819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1676907819
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.595847566
Short name T814
Test name
Test status
Simulation time 586846773 ps
CPU time 2.85 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200540 kb
Host smart-9d0c5537-5373-4283-b7de-7a75a0c866cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595847566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.595847566
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.1398810191
Short name T723
Test name
Test status
Simulation time 1575755077 ps
CPU time 11.86 seconds
Started Jul 25 07:15:54 PM PDT 24
Finished Jul 25 07:16:06 PM PDT 24
Peak memory 200612 kb
Host smart-81428970-f309-4ebb-8f9a-7c928a837f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398810191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.1398810191
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3194131577
Short name T570
Test name
Test status
Simulation time 56046144 ps
CPU time 1.11 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 200528 kb
Host smart-44353418-d56a-411a-b488-f44b9ed326c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194131577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.3194131577
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.958883375
Short name T543
Test name
Test status
Simulation time 29448807 ps
CPU time 0.83 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200528 kb
Host smart-9d30e885-a62a-4f33-8611-a63ebce52e5d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958883375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_clk_byp_req_intersig_mubi.958883375
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.978881498
Short name T317
Test name
Test status
Simulation time 33462539 ps
CPU time 0.86 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200204 kb
Host smart-f9ab1542-7a8d-47be-9223-293878c84125
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978881498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_ctrl_intersig_mubi.978881498
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.2563722447
Short name T192
Test name
Test status
Simulation time 13559228 ps
CPU time 0.73 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200496 kb
Host smart-f48ddc2f-5864-4749-89e9-7250dabf12a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563722447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.2563722447
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.3370241666
Short name T656
Test name
Test status
Simulation time 1356977817 ps
CPU time 6.12 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:16:01 PM PDT 24
Peak memory 200640 kb
Host smart-34432e8a-a23e-4e3d-aa84-3bf38ade7e52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370241666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.3370241666
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2165326030
Short name T417
Test name
Test status
Simulation time 25234272 ps
CPU time 0.85 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200472 kb
Host smart-28812f0a-376c-4524-8e84-7e5b5bc7e8ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165326030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2165326030
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.3890929117
Short name T557
Test name
Test status
Simulation time 6285140314 ps
CPU time 44.73 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:16:42 PM PDT 24
Peak memory 200876 kb
Host smart-27b9ed03-d204-4c00-85f8-5ff247a10d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890929117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.3890929117
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.1297794107
Short name T76
Test name
Test status
Simulation time 47795266351 ps
CPU time 514.92 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:24:31 PM PDT 24
Peak memory 217304 kb
Host smart-25a79efc-345d-45eb-a555-92ecc5599df3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1297794107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1297794107
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.3200222273
Short name T217
Test name
Test status
Simulation time 54390081 ps
CPU time 0.9 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200460 kb
Host smart-96d47e14-fecb-4bf8-bb73-21b52345b9bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200222273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3200222273
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.3209114179
Short name T354
Test name
Test status
Simulation time 16563377 ps
CPU time 0.72 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200544 kb
Host smart-40389c6d-b95a-4fdc-82c6-0ebb98feb8cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209114179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.3209114179
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.770904184
Short name T18
Test name
Test status
Simulation time 20872429 ps
CPU time 0.96 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200176 kb
Host smart-67d85e23-f53e-4d94-8289-d350cb0a70b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770904184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.770904184
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.681442870
Short name T501
Test name
Test status
Simulation time 36347728 ps
CPU time 0.8 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 199728 kb
Host smart-c602eb38-3902-49d2-9743-1afa5ec300ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681442870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.681442870
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.2993914512
Short name T760
Test name
Test status
Simulation time 46508250 ps
CPU time 0.82 seconds
Started Jul 25 07:15:58 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200496 kb
Host smart-4ead054d-6da2-47ba-a552-dd2368899ef1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993914512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.2993914512
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.684778470
Short name T26
Test name
Test status
Simulation time 26139267 ps
CPU time 0.79 seconds
Started Jul 25 07:15:58 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200528 kb
Host smart-8b818d4b-bd82-4936-b7d4-2e01e6f076ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684778470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.684778470
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.3461151955
Short name T19
Test name
Test status
Simulation time 315918109 ps
CPU time 3.05 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:16:00 PM PDT 24
Peak memory 200536 kb
Host smart-5a90b5f8-3bbd-4dce-8066-408488b9d4c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461151955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3461151955
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.575177215
Short name T634
Test name
Test status
Simulation time 736547936 ps
CPU time 2.91 seconds
Started Jul 25 07:16:03 PM PDT 24
Finished Jul 25 07:16:06 PM PDT 24
Peak memory 200624 kb
Host smart-e4f5774a-b560-4784-866c-6b505ae520f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575177215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_ti
meout.575177215
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.3276009085
Short name T688
Test name
Test status
Simulation time 31064245 ps
CPU time 1.02 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 200500 kb
Host smart-06f3b3c2-36cb-4cda-9949-96cf0f695b3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276009085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.3276009085
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2869038204
Short name T618
Test name
Test status
Simulation time 14188122 ps
CPU time 0.76 seconds
Started Jul 25 07:15:59 PM PDT 24
Finished Jul 25 07:16:00 PM PDT 24
Peak memory 200524 kb
Host smart-67ecc003-4c80-4cf9-a920-9888a55744f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869038204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2869038204
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1098086409
Short name T664
Test name
Test status
Simulation time 24002347 ps
CPU time 0.73 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200520 kb
Host smart-fde14737-7971-4076-816e-d9e9dd221284
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098086409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.1098086409
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.2839607584
Short name T772
Test name
Test status
Simulation time 19902187 ps
CPU time 0.87 seconds
Started Jul 25 07:15:57 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 200444 kb
Host smart-f5b8710c-1745-49ba-b2df-7726362e5e05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839607584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.2839607584
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.674154902
Short name T776
Test name
Test status
Simulation time 439751891 ps
CPU time 2.55 seconds
Started Jul 25 07:15:53 PM PDT 24
Finished Jul 25 07:15:56 PM PDT 24
Peak memory 200484 kb
Host smart-3a24beff-4da6-4eab-920a-658ea84d57b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674154902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.674154902
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.3596439166
Short name T265
Test name
Test status
Simulation time 23421338 ps
CPU time 0.89 seconds
Started Jul 25 07:15:56 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200424 kb
Host smart-c6eaab0a-12be-4ea2-9a28-981a303ad6ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596439166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.3596439166
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_trans.352791777
Short name T279
Test name
Test status
Simulation time 166750069 ps
CPU time 1.34 seconds
Started Jul 25 07:15:54 PM PDT 24
Finished Jul 25 07:15:55 PM PDT 24
Peak memory 200512 kb
Host smart-d795ee96-2f75-4805-bae8-7167e304de5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352791777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.352791777
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.3000801527
Short name T615
Test name
Test status
Simulation time 33660401 ps
CPU time 0.88 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200480 kb
Host smart-513db3e8-401e-4602-91f5-3d8f9931d99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000801527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.3000801527
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1825123120
Short name T358
Test name
Test status
Simulation time 57120353 ps
CPU time 0.97 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200564 kb
Host smart-2801736d-6853-4074-a05b-9b215d76ed73
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825123120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1825123120
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.3591041391
Short name T674
Test name
Test status
Simulation time 31384190 ps
CPU time 0.75 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 199712 kb
Host smart-7467bb08-9bfc-42ee-a582-b816aa68ee15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591041391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3591041391
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1657984645
Short name T388
Test name
Test status
Simulation time 99045951 ps
CPU time 1.15 seconds
Started Jul 25 07:14:29 PM PDT 24
Finished Jul 25 07:14:30 PM PDT 24
Peak memory 200496 kb
Host smart-6b48d5a2-98fb-4b67-a988-8e86b441c789
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657984645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1657984645
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.1383788431
Short name T509
Test name
Test status
Simulation time 16325013 ps
CPU time 0.78 seconds
Started Jul 25 07:14:29 PM PDT 24
Finished Jul 25 07:14:30 PM PDT 24
Peak memory 200452 kb
Host smart-bdcde20c-edec-46b4-b3c3-9dfd68d6ad68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383788431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1383788431
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.1004850464
Short name T515
Test name
Test status
Simulation time 1279287588 ps
CPU time 10.09 seconds
Started Jul 25 07:14:28 PM PDT 24
Finished Jul 25 07:14:38 PM PDT 24
Peak memory 200560 kb
Host smart-f338bfcd-e799-4f52-9ff3-44d802b39cdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004850464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1004850464
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.2178476808
Short name T380
Test name
Test status
Simulation time 740818512 ps
CPU time 5.38 seconds
Started Jul 25 07:14:28 PM PDT 24
Finished Jul 25 07:14:34 PM PDT 24
Peak memory 200600 kb
Host smart-2d8a7c5d-2a17-4f32-a1ae-c51833c3ce4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178476808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.2178476808
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.2339683844
Short name T352
Test name
Test status
Simulation time 64388112 ps
CPU time 1.12 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200532 kb
Host smart-7894b8c2-2b70-4d18-8896-f44d1c942b53
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339683844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.2339683844
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.638446094
Short name T786
Test name
Test status
Simulation time 20486143 ps
CPU time 0.87 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200228 kb
Host smart-3b33d3a1-b58a-4cc7-8889-bd1e3afc42b0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638446094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_lc_clk_byp_req_intersig_mubi.638446094
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2414581291
Short name T696
Test name
Test status
Simulation time 83343167 ps
CPU time 1.08 seconds
Started Jul 25 07:14:28 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200484 kb
Host smart-0bb6b6f3-6a20-472d-b376-6bea9bd6a193
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414581291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2414581291
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.813831356
Short name T591
Test name
Test status
Simulation time 32683944 ps
CPU time 0.79 seconds
Started Jul 25 07:14:28 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200496 kb
Host smart-065a9e01-725c-4a40-98d3-53ef9082ceed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813831356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.813831356
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.2266335383
Short name T196
Test name
Test status
Simulation time 785952879 ps
CPU time 4.56 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:32 PM PDT 24
Peak memory 200656 kb
Host smart-e8f91e05-f13c-48ba-8bcd-a6e345abbcd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266335383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2266335383
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.2078221870
Short name T51
Test name
Test status
Simulation time 224968695 ps
CPU time 2.08 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:30 PM PDT 24
Peak memory 215968 kb
Host smart-ef6cffc3-94a7-4176-9615-a2dce79e4a34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078221870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.2078221870
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.1509039824
Short name T373
Test name
Test status
Simulation time 63103537 ps
CPU time 0.95 seconds
Started Jul 25 07:14:28 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200476 kb
Host smart-8dedc0e9-455a-4fbf-8d4d-6b6292d2e4ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509039824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1509039824
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.2336919992
Short name T289
Test name
Test status
Simulation time 2478879470 ps
CPU time 9.67 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 200928 kb
Host smart-9ed0e0d8-5ae6-472a-a91e-81c2270aafd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336919992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.2336919992
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.513141433
Short name T394
Test name
Test status
Simulation time 157035454 ps
CPU time 1.3 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200512 kb
Host smart-04ba909b-b6f6-4fc9-be09-8e1dc202da4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513141433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.513141433
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.2978338101
Short name T458
Test name
Test status
Simulation time 22762139 ps
CPU time 0.76 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200516 kb
Host smart-758b630e-4304-4036-acc9-7050b8013679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978338101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.2978338101
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.2276046418
Short name T625
Test name
Test status
Simulation time 75493683 ps
CPU time 1 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200508 kb
Host smart-d2e7f3ab-a624-4ac8-a8c5-ccf643c1d566
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276046418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.2276046418
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.3496089767
Short name T46
Test name
Test status
Simulation time 93469858 ps
CPU time 0.92 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200336 kb
Host smart-c0620dc3-5ef3-4449-953f-c0dcfcf5ab93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496089767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.3496089767
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.3309766015
Short name T330
Test name
Test status
Simulation time 34098413 ps
CPU time 0.79 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200428 kb
Host smart-9f524361-9aed-4ce1-b1ce-14236ff48204
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309766015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.3309766015
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.3784008390
Short name T523
Test name
Test status
Simulation time 93218816 ps
CPU time 1.01 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200460 kb
Host smart-5d0f57bc-95b6-42fc-940d-2d292b1832f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784008390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.3784008390
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.4246263688
Short name T676
Test name
Test status
Simulation time 448287119 ps
CPU time 2.63 seconds
Started Jul 25 07:16:01 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200568 kb
Host smart-47a2d719-7ded-4a43-bf40-6f062d14b116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246263688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.4246263688
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.4282592975
Short name T437
Test name
Test status
Simulation time 2042333858 ps
CPU time 6.61 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 200596 kb
Host smart-b9f2abef-5ae9-487e-b5f9-31eab9f7a8d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282592975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.4282592975
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1244885267
Short name T754
Test name
Test status
Simulation time 33359610 ps
CPU time 0.99 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200484 kb
Host smart-18cbbb23-b8e8-4dae-8fed-c1c6bfae99fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244885267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1244885267
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1690727322
Short name T604
Test name
Test status
Simulation time 35307293 ps
CPU time 0.8 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200496 kb
Host smart-c6548eb3-2e92-4cd7-b976-c1b4f2ace578
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690727322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1690727322
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.1160040311
Short name T662
Test name
Test status
Simulation time 85503774 ps
CPU time 1.02 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200508 kb
Host smart-c9f52233-c27f-49bd-a65c-be7f026e8762
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160040311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.1160040311
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.3982015761
Short name T577
Test name
Test status
Simulation time 103380075 ps
CPU time 1.03 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200408 kb
Host smart-3968b436-b0e3-4633-94fa-2196670897eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982015761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.3982015761
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.160945086
Short name T234
Test name
Test status
Simulation time 919965186 ps
CPU time 3.82 seconds
Started Jul 25 07:16:01 PM PDT 24
Finished Jul 25 07:16:04 PM PDT 24
Peak memory 200664 kb
Host smart-955cb154-5876-48e8-9ea5-7b85def39ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160945086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.160945086
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.2841322410
Short name T375
Test name
Test status
Simulation time 246498988 ps
CPU time 1.49 seconds
Started Jul 25 07:15:55 PM PDT 24
Finished Jul 25 07:15:57 PM PDT 24
Peak memory 200452 kb
Host smart-ac005740-a236-473d-8bad-9f40fc2a05c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841322410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2841322410
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.1819849814
Short name T249
Test name
Test status
Simulation time 2667674325 ps
CPU time 11.08 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:19 PM PDT 24
Peak memory 200800 kb
Host smart-32df0e17-d947-4212-b9e8-811c1f9537fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819849814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.1819849814
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2894155542
Short name T275
Test name
Test status
Simulation time 49095061 ps
CPU time 0.87 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200496 kb
Host smart-42a74429-dee1-4d47-bbd9-32f55ebdf733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894155542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2894155542
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.2471636513
Short name T647
Test name
Test status
Simulation time 41614272 ps
CPU time 0.8 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200556 kb
Host smart-93622df9-d7f3-4883-87e4-dda21f183c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471636513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.2471636513
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.401573662
Short name T22
Test name
Test status
Simulation time 19185213 ps
CPU time 0.79 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:09 PM PDT 24
Peak memory 200440 kb
Host smart-bb54d22e-dbe8-49ee-bc8b-1282d4945615
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401573662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.401573662
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.2656387569
Short name T382
Test name
Test status
Simulation time 35123707 ps
CPU time 0.83 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 199732 kb
Host smart-7895d91a-c7d5-473a-be35-2e38bc87f005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656387569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2656387569
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.1413767754
Short name T396
Test name
Test status
Simulation time 136617073 ps
CPU time 1.18 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:04 PM PDT 24
Peak memory 200548 kb
Host smart-de232403-160f-49e7-9ddc-0a452ff20c57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413767754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.1413767754
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.842781999
Short name T236
Test name
Test status
Simulation time 60311765 ps
CPU time 0.94 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:09 PM PDT 24
Peak memory 200408 kb
Host smart-2d405b09-037b-4cb2-bb2b-895b6da9492c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842781999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.842781999
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.419279847
Short name T13
Test name
Test status
Simulation time 2122722175 ps
CPU time 12.33 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:15 PM PDT 24
Peak memory 200760 kb
Host smart-dfc329ec-1f22-4790-9eea-725c074bf630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419279847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.419279847
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.2538722922
Short name T783
Test name
Test status
Simulation time 142718426 ps
CPU time 1.56 seconds
Started Jul 25 07:16:05 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200616 kb
Host smart-de25b6ec-5413-4442-bb2f-464da5ad7706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538722922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.2538722922
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.4182026161
Short name T414
Test name
Test status
Simulation time 14826758 ps
CPU time 0.82 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200464 kb
Host smart-f538e6d1-d2c7-4a36-8ea7-8b4e9d895a39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182026161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.4182026161
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3336674348
Short name T9
Test name
Test status
Simulation time 36066767 ps
CPU time 0.81 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200520 kb
Host smart-f791405d-1074-4795-aac1-2dc3761f013e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336674348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3336674348
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.152967127
Short name T466
Test name
Test status
Simulation time 50052917 ps
CPU time 0.94 seconds
Started Jul 25 07:16:05 PM PDT 24
Finished Jul 25 07:16:06 PM PDT 24
Peak memory 200500 kb
Host smart-de7bfa30-15ed-44d5-9920-eeb51ff94acf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152967127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_ctrl_intersig_mubi.152967127
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.2222512435
Short name T193
Test name
Test status
Simulation time 76359575 ps
CPU time 0.87 seconds
Started Jul 25 07:16:03 PM PDT 24
Finished Jul 25 07:16:04 PM PDT 24
Peak memory 200492 kb
Host smart-56ec4ca7-efdf-4bd8-9e62-449a0142c60d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222512435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2222512435
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.791767046
Short name T743
Test name
Test status
Simulation time 32345746 ps
CPU time 0.88 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200468 kb
Host smart-220ffd31-f5c0-4ab7-afec-dcda025bf914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791767046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.791767046
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.1278963966
Short name T423
Test name
Test status
Simulation time 1012493909 ps
CPU time 6.3 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:08 PM PDT 24
Peak memory 200844 kb
Host smart-5b423b0e-7cbb-4a70-a432-cfd6dfc33ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278963966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.1278963966
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.14005838
Short name T510
Test name
Test status
Simulation time 132181272919 ps
CPU time 613.35 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:26:23 PM PDT 24
Peak memory 217328 kb
Host smart-7024482d-5915-49d7-a8c8-327a127808d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=14005838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.14005838
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.2004082426
Short name T630
Test name
Test status
Simulation time 16093951 ps
CPU time 0.73 seconds
Started Jul 25 07:16:16 PM PDT 24
Finished Jul 25 07:16:17 PM PDT 24
Peak memory 200400 kb
Host smart-ea2de038-4487-43a1-874d-93abdcd130b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004082426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2004082426
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.2860812179
Short name T251
Test name
Test status
Simulation time 20897254 ps
CPU time 0.85 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200508 kb
Host smart-af7a9c40-a9c2-4215-abf6-d1e3e392ccd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860812179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.2860812179
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.4130172730
Short name T636
Test name
Test status
Simulation time 22619141 ps
CPU time 0.79 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200496 kb
Host smart-34c26a07-e789-44c4-8d82-ac0c51d1d86e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130172730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.4130172730
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.2131295340
Short name T165
Test name
Test status
Simulation time 12502841 ps
CPU time 0.72 seconds
Started Jul 25 07:16:05 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200412 kb
Host smart-7e113d15-a704-4b25-aade-ad67d45152ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131295340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2131295340
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.3062701362
Short name T38
Test name
Test status
Simulation time 27293523 ps
CPU time 0.84 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200492 kb
Host smart-0a642b38-d73d-4647-bb1e-6ea6bce7a1ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062701362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.3062701362
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.3108905116
Short name T226
Test name
Test status
Simulation time 59808074 ps
CPU time 0.91 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200476 kb
Host smart-46424c4d-22bb-4274-a583-5fe24d14358c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108905116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.3108905116
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3443599715
Short name T419
Test name
Test status
Simulation time 239986303 ps
CPU time 1.66 seconds
Started Jul 25 07:16:03 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200564 kb
Host smart-5312c09c-dcd7-4206-a900-635466a9b753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443599715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3443599715
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.3625508747
Short name T658
Test name
Test status
Simulation time 1180483610 ps
CPU time 4.55 seconds
Started Jul 25 07:16:07 PM PDT 24
Finished Jul 25 07:16:12 PM PDT 24
Peak memory 200608 kb
Host smart-421b5189-cf12-41cf-a43f-edaa7821ffa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625508747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.3625508747
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.1796943288
Short name T115
Test name
Test status
Simulation time 127926681 ps
CPU time 1.33 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200468 kb
Host smart-e9439b16-b1ce-483f-95e8-0b8a185c9d6b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796943288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.1796943288
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3724884071
Short name T464
Test name
Test status
Simulation time 18578246 ps
CPU time 0.77 seconds
Started Jul 25 07:16:05 PM PDT 24
Finished Jul 25 07:16:06 PM PDT 24
Peak memory 200560 kb
Host smart-05095d30-cccd-461f-92c5-c4e9b1cd34a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724884071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3724884071
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3395319116
Short name T714
Test name
Test status
Simulation time 16839250 ps
CPU time 0.77 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200508 kb
Host smart-bc97855f-e1b1-49a2-a2ca-e4a13f3ab084
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395319116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.3395319116
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.2542240088
Short name T208
Test name
Test status
Simulation time 14599202 ps
CPU time 0.75 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200468 kb
Host smart-5d270771-f255-4bd6-bbcd-c9915af63063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542240088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2542240088
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.1275319175
Short name T156
Test name
Test status
Simulation time 868748733 ps
CPU time 3.54 seconds
Started Jul 25 07:16:03 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200716 kb
Host smart-2bc8d2af-2829-4624-9e10-18d36ae7a7f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275319175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1275319175
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.3347111227
Short name T715
Test name
Test status
Simulation time 96797586 ps
CPU time 1.09 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200408 kb
Host smart-7d7c5837-5fc5-47c4-b10d-1c000f4d1fca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347111227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3347111227
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.1344663648
Short name T502
Test name
Test status
Simulation time 4137021137 ps
CPU time 31.01 seconds
Started Jul 25 07:16:01 PM PDT 24
Finished Jul 25 07:16:32 PM PDT 24
Peak memory 200892 kb
Host smart-c75039f0-93d3-433b-828d-aca256accf65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344663648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.1344663648
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.3652745271
Short name T31
Test name
Test status
Simulation time 52926426913 ps
CPU time 487.37 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:24:12 PM PDT 24
Peak memory 217368 kb
Host smart-5c8f2410-1049-4cb0-8a31-e17f33bc6cce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3652745271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.3652745271
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.1553385657
Short name T670
Test name
Test status
Simulation time 23287181 ps
CPU time 0.76 seconds
Started Jul 25 07:16:03 PM PDT 24
Finished Jul 25 07:16:04 PM PDT 24
Peak memory 200544 kb
Host smart-53d67d02-265f-4f58-aa08-b17717eb140c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553385657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1553385657
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.4041738277
Short name T319
Test name
Test status
Simulation time 40475049 ps
CPU time 0.86 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:09 PM PDT 24
Peak memory 200472 kb
Host smart-4f777fe4-b000-4560-a8ba-c4547b4b9b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041738277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.4041738277
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2679264072
Short name T432
Test name
Test status
Simulation time 136198535 ps
CPU time 1.17 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200524 kb
Host smart-a40bbb0f-fe76-44a7-9a49-6bcfadb0e9c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679264072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.2679264072
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.1792319012
Short name T611
Test name
Test status
Simulation time 53108477 ps
CPU time 0.78 seconds
Started Jul 25 07:16:07 PM PDT 24
Finished Jul 25 07:16:08 PM PDT 24
Peak memory 199640 kb
Host smart-743424a4-2124-46f6-8f39-49dd2eb6d247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792319012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1792319012
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2898661092
Short name T546
Test name
Test status
Simulation time 250381444 ps
CPU time 1.49 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:06 PM PDT 24
Peak memory 200480 kb
Host smart-72bc3674-213d-4513-b82e-3af26e7229dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898661092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.2898661092
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3212957768
Short name T188
Test name
Test status
Simulation time 26984435 ps
CPU time 0.9 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200464 kb
Host smart-d088afef-c24e-4677-804a-be899b39fefd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212957768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3212957768
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.2717126860
Short name T285
Test name
Test status
Simulation time 1879337407 ps
CPU time 7 seconds
Started Jul 25 07:16:05 PM PDT 24
Finished Jul 25 07:16:12 PM PDT 24
Peak memory 200556 kb
Host smart-3a39b3b1-3b58-4be1-a395-49811d237b90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717126860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.2717126860
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.4064337623
Short name T345
Test name
Test status
Simulation time 1132674778 ps
CPU time 4.68 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200640 kb
Host smart-0b44d9d3-059d-43b0-b2a9-b42611925f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064337623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.4064337623
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1894418209
Short name T314
Test name
Test status
Simulation time 32710244 ps
CPU time 0.76 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200496 kb
Host smart-7201e58f-bded-4de7-9a54-3330f726c451
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894418209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1894418209
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.367441707
Short name T212
Test name
Test status
Simulation time 15058832 ps
CPU time 0.83 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200516 kb
Host smart-0d29be0f-74b5-483d-a13f-ed44bf653a0e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367441707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_clk_byp_req_intersig_mubi.367441707
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.929406801
Short name T572
Test name
Test status
Simulation time 150683740 ps
CPU time 1.26 seconds
Started Jul 25 07:16:02 PM PDT 24
Finished Jul 25 07:16:03 PM PDT 24
Peak memory 200536 kb
Host smart-d2d58a07-0eb2-4810-8e5a-ca6cc3d921fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929406801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.929406801
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.3510091213
Short name T711
Test name
Test status
Simulation time 33478888 ps
CPU time 0.86 seconds
Started Jul 25 07:16:06 PM PDT 24
Finished Jul 25 07:16:07 PM PDT 24
Peak memory 200448 kb
Host smart-ef23e556-a4e4-4eb3-a9c8-f33b8b6d261f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510091213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3510091213
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.1918973066
Short name T153
Test name
Test status
Simulation time 790291467 ps
CPU time 4.66 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 200644 kb
Host smart-fcaea0d1-59d7-4deb-8d40-9016b865ef98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918973066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1918973066
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.2814380480
Short name T222
Test name
Test status
Simulation time 73064083 ps
CPU time 1.01 seconds
Started Jul 25 07:16:00 PM PDT 24
Finished Jul 25 07:16:01 PM PDT 24
Peak memory 200448 kb
Host smart-adfbfbea-2b4d-40dd-a692-54d860865972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814380480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2814380480
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.2817333696
Short name T521
Test name
Test status
Simulation time 2975663705 ps
CPU time 12.47 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:21 PM PDT 24
Peak memory 200928 kb
Host smart-0cad1703-9557-4707-aa8a-43ff62defe63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817333696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.2817333696
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.4012442964
Short name T682
Test name
Test status
Simulation time 59237381 ps
CPU time 1.04 seconds
Started Jul 25 07:16:04 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200484 kb
Host smart-ffe6363b-2ee4-4833-998a-1d5752bd4448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012442964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.4012442964
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1536529671
Short name T169
Test name
Test status
Simulation time 95134464 ps
CPU time 0.98 seconds
Started Jul 25 07:16:07 PM PDT 24
Finished Jul 25 07:16:08 PM PDT 24
Peak memory 200468 kb
Host smart-04b8c0f1-1ce8-4c60-b622-516e6d8749c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536529671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1536529671
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.137851578
Short name T21
Test name
Test status
Simulation time 97551465 ps
CPU time 1.16 seconds
Started Jul 25 07:16:17 PM PDT 24
Finished Jul 25 07:16:18 PM PDT 24
Peak memory 200540 kb
Host smart-25ba7af8-a5b2-4e34-8305-f21db6f62f40
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137851578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.137851578
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.2769476863
Short name T752
Test name
Test status
Simulation time 40590816 ps
CPU time 0.78 seconds
Started Jul 25 07:16:13 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 199684 kb
Host smart-49fb79b2-3221-472f-8d83-e12fb91c784f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769476863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2769476863
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.4229636139
Short name T435
Test name
Test status
Simulation time 43147612 ps
CPU time 0.83 seconds
Started Jul 25 07:23:18 PM PDT 24
Finished Jul 25 07:23:19 PM PDT 24
Peak memory 200508 kb
Host smart-8b9dcff9-4949-4256-ac5c-9a980e1085ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229636139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.4229636139
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.884991525
Short name T561
Test name
Test status
Simulation time 55640869 ps
CPU time 0.89 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:13 PM PDT 24
Peak memory 200532 kb
Host smart-dcc9d1d6-5344-4ac9-ac9a-88d679fb41eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884991525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.884991525
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.816466020
Short name T429
Test name
Test status
Simulation time 943998280 ps
CPU time 4.7 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:15 PM PDT 24
Peak memory 200560 kb
Host smart-2bdc13d4-29a4-4dd9-94da-fd199db705fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816466020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.816466020
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.2549476724
Short name T244
Test name
Test status
Simulation time 2058868963 ps
CPU time 10.87 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:23 PM PDT 24
Peak memory 200856 kb
Host smart-d80d07b6-4b71-4be2-b494-a3be8eeedbf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549476724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.2549476724
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3707429171
Short name T745
Test name
Test status
Simulation time 63286834 ps
CPU time 0.88 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200500 kb
Host smart-aacbf847-e4da-4ad5-a43d-1b8599adec2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707429171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.3707429171
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3567797284
Short name T292
Test name
Test status
Simulation time 19346280 ps
CPU time 0.81 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:09 PM PDT 24
Peak memory 200480 kb
Host smart-eb2a030c-bb2c-4736-a0f1-2c18390b1688
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567797284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.3567797284
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.581731887
Short name T235
Test name
Test status
Simulation time 26641571 ps
CPU time 0.95 seconds
Started Jul 25 07:16:13 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 200484 kb
Host smart-8383a1e8-1196-4adf-9b6e-13e119189d0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581731887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_ctrl_intersig_mubi.581731887
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.2129588432
Short name T757
Test name
Test status
Simulation time 37114872 ps
CPU time 0.86 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:12 PM PDT 24
Peak memory 200496 kb
Host smart-a8be1b4a-856a-43ee-a1ed-28995e32289e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129588432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2129588432
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.2522682729
Short name T470
Test name
Test status
Simulation time 980569593 ps
CPU time 4.27 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:16 PM PDT 24
Peak memory 200668 kb
Host smart-b74e7590-d137-47f4-b3a6-ac290e18b8d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522682729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.2522682729
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1990027178
Short name T716
Test name
Test status
Simulation time 42474212 ps
CPU time 0.94 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200464 kb
Host smart-7cb428a0-9183-478a-aa68-20b811f38171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990027178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1990027178
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3277678271
Short name T35
Test name
Test status
Simulation time 3135499335 ps
CPU time 23.95 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:35 PM PDT 24
Peak memory 200888 kb
Host smart-7b988477-c580-480b-8a01-b51ae7948a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277678271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3277678271
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.639632630
Short name T162
Test name
Test status
Simulation time 36739231226 ps
CPU time 314.93 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:21:24 PM PDT 24
Peak memory 209220 kb
Host smart-4eb3ecc8-5f23-4074-9939-735ac3bfb9b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=639632630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.639632630
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.clkmgr_trans.3020700371
Short name T612
Test name
Test status
Simulation time 56207102 ps
CPU time 0.87 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200552 kb
Host smart-88bd962e-316b-439e-9482-8241ac93ff14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020700371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3020700371
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.2437619901
Short name T520
Test name
Test status
Simulation time 18280147 ps
CPU time 0.79 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200520 kb
Host smart-d877b014-b45c-4cc1-ab02-00b047d25e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437619901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.2437619901
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.224215868
Short name T343
Test name
Test status
Simulation time 18611456 ps
CPU time 0.76 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200512 kb
Host smart-cad12e98-075e-4cef-b6f0-6a08aa757b7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224215868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.224215868
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3024155637
Short name T48
Test name
Test status
Simulation time 33516955 ps
CPU time 0.72 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 199684 kb
Host smart-b2aa91b1-d459-4535-97fc-6adb9316e40c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024155637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3024155637
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2263413211
Short name T733
Test name
Test status
Simulation time 54611974 ps
CPU time 1.05 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200508 kb
Host smart-fd521a4a-77f6-4f98-8c9d-3cc86c7b26d0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263413211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2263413211
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.592945960
Short name T633
Test name
Test status
Simulation time 34933831 ps
CPU time 0.86 seconds
Started Jul 25 07:16:08 PM PDT 24
Finished Jul 25 07:16:09 PM PDT 24
Peak memory 200508 kb
Host smart-12008f2e-19d4-4595-a2d5-e27f7214a771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592945960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.592945960
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.1652522273
Short name T16
Test name
Test status
Simulation time 434980289 ps
CPU time 3.92 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:15 PM PDT 24
Peak memory 200560 kb
Host smart-62ae6c89-38bf-44ec-a019-cad8d0258bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652522273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1652522273
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.2360619401
Short name T794
Test name
Test status
Simulation time 1855554224 ps
CPU time 7.4 seconds
Started Jul 25 07:16:16 PM PDT 24
Finished Jul 25 07:16:24 PM PDT 24
Peak memory 200636 kb
Host smart-74209ab9-52a1-4d26-920a-c8d0e4470e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360619401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.2360619401
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2350486398
Short name T759
Test name
Test status
Simulation time 127726147 ps
CPU time 1.31 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200464 kb
Host smart-f1b6541b-3c3f-42b8-bce6-b063b320851a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350486398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2350486398
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.2946998272
Short name T245
Test name
Test status
Simulation time 23269052 ps
CPU time 0.78 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200512 kb
Host smart-f99230c7-4e47-44fe-aef7-b05fd0f71b74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946998272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.2946998272
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.4048379984
Short name T801
Test name
Test status
Simulation time 71659491 ps
CPU time 0.95 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200508 kb
Host smart-2a88bf23-13fa-44d2-9791-c90ee126c40f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048379984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.4048379984
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.138213127
Short name T228
Test name
Test status
Simulation time 13136760 ps
CPU time 0.72 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200452 kb
Host smart-1e3c80b8-47dc-438c-b565-49ea9144e2f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138213127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.138213127
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2323597584
Short name T536
Test name
Test status
Simulation time 749647163 ps
CPU time 3.56 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:15 PM PDT 24
Peak memory 200708 kb
Host smart-14bdb42a-394e-4b71-bd87-ca6340434b78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323597584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2323597584
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.3051698195
Short name T148
Test name
Test status
Simulation time 42763588 ps
CPU time 0.96 seconds
Started Jul 25 07:16:16 PM PDT 24
Finished Jul 25 07:16:17 PM PDT 24
Peak memory 200452 kb
Host smart-acb8ba86-8b56-4517-9edd-f4537e9a67eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051698195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3051698195
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.993579990
Short name T143
Test name
Test status
Simulation time 498821269 ps
CPU time 2.42 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 200544 kb
Host smart-47bdf7ba-2f17-4433-ad08-54662d29c35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993579990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.993579990
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.3050870080
Short name T817
Test name
Test status
Simulation time 27068484 ps
CPU time 0.9 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:12 PM PDT 24
Peak memory 200408 kb
Host smart-dbe147e0-f9e0-4405-9a63-399ed021f9ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050870080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3050870080
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.2269503467
Short name T433
Test name
Test status
Simulation time 17405470 ps
CPU time 0.81 seconds
Started Jul 25 07:16:17 PM PDT 24
Finished Jul 25 07:16:18 PM PDT 24
Peak memory 200564 kb
Host smart-5ae57444-f279-453d-bde1-31632f87986a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269503467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.2269503467
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.971381062
Short name T539
Test name
Test status
Simulation time 87905942 ps
CPU time 1.11 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:13 PM PDT 24
Peak memory 200512 kb
Host smart-a154f755-2509-450b-a6f8-5755a8fbd339
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971381062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.971381062
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1123395316
Short name T777
Test name
Test status
Simulation time 29521435 ps
CPU time 0.78 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:13 PM PDT 24
Peak memory 199756 kb
Host smart-949e6b18-1864-4f2c-ad93-6452c4e762b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123395316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1123395316
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.1762449480
Short name T377
Test name
Test status
Simulation time 22586419 ps
CPU time 0.84 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:10 PM PDT 24
Peak memory 200520 kb
Host smart-b9e90434-7b3f-42a3-96a3-6db9febfbe81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762449480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.1762449480
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.3310356379
Short name T237
Test name
Test status
Simulation time 26073525 ps
CPU time 0.93 seconds
Started Jul 25 07:16:13 PM PDT 24
Finished Jul 25 07:16:14 PM PDT 24
Peak memory 200484 kb
Host smart-82e3b543-de9d-4346-8967-9150497ef024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310356379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3310356379
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.4260891749
Short name T631
Test name
Test status
Simulation time 373982471 ps
CPU time 2.13 seconds
Started Jul 25 07:16:09 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200636 kb
Host smart-1124c8ab-1f1f-4696-82bf-c25fa66c8df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260891749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.4260891749
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.1240581157
Short name T531
Test name
Test status
Simulation time 2063006629 ps
CPU time 10.83 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:22 PM PDT 24
Peak memory 200784 kb
Host smart-c094b1ff-a35d-49ff-9d57-7401f1138447
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240581157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.1240581157
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1277371506
Short name T747
Test name
Test status
Simulation time 41022298 ps
CPU time 0.8 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:12 PM PDT 24
Peak memory 200496 kb
Host smart-6a629930-f92f-4f3c-b04d-211c00de3d48
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277371506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1277371506
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1415760033
Short name T626
Test name
Test status
Simulation time 27261381 ps
CPU time 0.87 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:12 PM PDT 24
Peak memory 200508 kb
Host smart-83492ed9-dcc3-4675-a952-fe0468a7bc63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415760033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1415760033
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3175917948
Short name T308
Test name
Test status
Simulation time 28332839 ps
CPU time 0.97 seconds
Started Jul 25 07:16:13 PM PDT 24
Finished Jul 25 07:16:15 PM PDT 24
Peak memory 200508 kb
Host smart-e982151a-b0eb-442f-b738-790788d4998f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175917948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.3175917948
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.1791038506
Short name T487
Test name
Test status
Simulation time 19271941 ps
CPU time 0.83 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:13 PM PDT 24
Peak memory 200504 kb
Host smart-311a13b7-9234-489e-9185-e72d8c685b9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791038506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.1791038506
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.3091159870
Short name T693
Test name
Test status
Simulation time 534824769 ps
CPU time 3.27 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:15 PM PDT 24
Peak memory 200680 kb
Host smart-857420ac-5315-4dd6-a95c-eca5758074e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091159870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.3091159870
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.1037353560
Short name T315
Test name
Test status
Simulation time 21685606 ps
CPU time 0.84 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:11 PM PDT 24
Peak memory 200472 kb
Host smart-fd6c3ad3-cb86-4cb1-9f9a-378a7dc0b541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037353560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.1037353560
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.2551451573
Short name T250
Test name
Test status
Simulation time 1075074133 ps
CPU time 6.15 seconds
Started Jul 25 07:16:11 PM PDT 24
Finished Jul 25 07:16:17 PM PDT 24
Peak memory 200648 kb
Host smart-9226c0ba-276c-413a-94d3-5a7947cc379d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551451573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.2551451573
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.2509428306
Short name T798
Test name
Test status
Simulation time 34258001 ps
CPU time 1.03 seconds
Started Jul 25 07:16:12 PM PDT 24
Finished Jul 25 07:16:13 PM PDT 24
Peak memory 200452 kb
Host smart-af0ec542-b7b6-4a4e-88b9-4a2813991ca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509428306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2509428306
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.1236965750
Short name T306
Test name
Test status
Simulation time 31348431 ps
CPU time 0.8 seconds
Started Jul 25 07:16:22 PM PDT 24
Finished Jul 25 07:16:23 PM PDT 24
Peak memory 200476 kb
Host smart-7cef1ad0-a9e3-4291-9685-ee2b8052725b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236965750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.1236965750
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.4282461800
Short name T167
Test name
Test status
Simulation time 22334077 ps
CPU time 0.8 seconds
Started Jul 25 07:16:26 PM PDT 24
Finished Jul 25 07:16:27 PM PDT 24
Peak memory 200520 kb
Host smart-d80e1e98-f2ab-43e2-958b-43351553e408
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282461800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.4282461800
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.2995627935
Short name T710
Test name
Test status
Simulation time 18167308 ps
CPU time 0.73 seconds
Started Jul 25 07:16:20 PM PDT 24
Finished Jul 25 07:16:21 PM PDT 24
Peak memory 199700 kb
Host smart-dc5f171c-e6db-485f-b482-02fe5376e96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995627935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2995627935
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.3568272077
Short name T491
Test name
Test status
Simulation time 65249369 ps
CPU time 0.93 seconds
Started Jul 25 07:16:20 PM PDT 24
Finished Jul 25 07:16:21 PM PDT 24
Peak memory 200504 kb
Host smart-0538dd73-7361-4685-97bc-a824e25595a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568272077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.3568272077
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.597706663
Short name T305
Test name
Test status
Simulation time 19278607 ps
CPU time 0.89 seconds
Started Jul 25 07:16:17 PM PDT 24
Finished Jul 25 07:16:18 PM PDT 24
Peak memory 200576 kb
Host smart-c3803e85-d0f9-4de6-8cb1-c876c3d38f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597706663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.597706663
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.3112523272
Short name T552
Test name
Test status
Simulation time 917359922 ps
CPU time 7.45 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:18 PM PDT 24
Peak memory 200588 kb
Host smart-e0aade99-a9be-485e-8021-ceee25fa0276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112523272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3112523272
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.810625622
Short name T542
Test name
Test status
Simulation time 514172226 ps
CPU time 2.64 seconds
Started Jul 25 07:16:23 PM PDT 24
Finished Jul 25 07:16:26 PM PDT 24
Peak memory 200632 kb
Host smart-e7044966-f468-4224-8954-8c3e422c2609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810625622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_ti
meout.810625622
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1808284061
Short name T824
Test name
Test status
Simulation time 31363009 ps
CPU time 0.92 seconds
Started Jul 25 07:16:25 PM PDT 24
Finished Jul 25 07:16:26 PM PDT 24
Peak memory 200512 kb
Host smart-2d299827-3ca6-4fa6-985d-4bef7cc06871
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808284061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.1808284061
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2560778349
Short name T381
Test name
Test status
Simulation time 21866709 ps
CPU time 0.83 seconds
Started Jul 25 07:16:20 PM PDT 24
Finished Jul 25 07:16:21 PM PDT 24
Peak memory 200524 kb
Host smart-d7a22678-2bb0-4596-b6cd-9f6729758ac0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560778349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2560778349
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.2711791497
Short name T667
Test name
Test status
Simulation time 94545722 ps
CPU time 1.12 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:26 PM PDT 24
Peak memory 200504 kb
Host smart-6ff98e1a-8faf-4abc-9592-faef685bbe3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711791497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.2711791497
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.198209317
Short name T810
Test name
Test status
Simulation time 18952641 ps
CPU time 0.82 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:25 PM PDT 24
Peak memory 200480 kb
Host smart-83122e79-1d00-4157-b085-d7de6e8431b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198209317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.198209317
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.120495094
Short name T112
Test name
Test status
Simulation time 303926673 ps
CPU time 2.13 seconds
Started Jul 25 07:16:20 PM PDT 24
Finished Jul 25 07:16:22 PM PDT 24
Peak memory 200544 kb
Host smart-aa999806-64ee-4d3b-8fdc-cf69fe1346c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120495094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.120495094
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.4187489273
Short name T593
Test name
Test status
Simulation time 56066151 ps
CPU time 1.05 seconds
Started Jul 25 07:16:10 PM PDT 24
Finished Jul 25 07:16:12 PM PDT 24
Peak memory 200496 kb
Host smart-4b37ebf5-0fa2-4dac-a240-bcf3c5ae4abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187489273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.4187489273
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.3233214206
Short name T765
Test name
Test status
Simulation time 849488197 ps
CPU time 7.26 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:31 PM PDT 24
Peak memory 200844 kb
Host smart-de21d5be-c0c0-43bd-a391-d15ea1f9ff48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233214206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.3233214206
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.1675222977
Short name T255
Test name
Test status
Simulation time 209537970 ps
CPU time 1.68 seconds
Started Jul 25 07:16:20 PM PDT 24
Finished Jul 25 07:16:22 PM PDT 24
Peak memory 200528 kb
Host smart-133d5bdc-0454-4c7c-ba0d-ed411b12958a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675222977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1675222977
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.3187438165
Short name T453
Test name
Test status
Simulation time 18504736 ps
CPU time 0.82 seconds
Started Jul 25 07:16:19 PM PDT 24
Finished Jul 25 07:16:20 PM PDT 24
Peak memory 200480 kb
Host smart-d9c7e25d-e14e-4a6a-956f-e1cd0f21f69e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187438165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.3187438165
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1977754958
Short name T7
Test name
Test status
Simulation time 69118941 ps
CPU time 1 seconds
Started Jul 25 07:16:27 PM PDT 24
Finished Jul 25 07:16:29 PM PDT 24
Peak memory 200536 kb
Host smart-3e9a57ed-9a74-4e04-a050-2d91cdc87f24
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977754958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.1977754958
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.3913836923
Short name T495
Test name
Test status
Simulation time 19606450 ps
CPU time 0.68 seconds
Started Jul 25 07:16:21 PM PDT 24
Finished Jul 25 07:16:22 PM PDT 24
Peak memory 199668 kb
Host smart-6c0828f5-2efb-49d1-96f0-eb304054cfea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913836923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3913836923
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.3113071520
Short name T827
Test name
Test status
Simulation time 116671507 ps
CPU time 1.13 seconds
Started Jul 25 07:16:23 PM PDT 24
Finished Jul 25 07:16:24 PM PDT 24
Peak memory 200512 kb
Host smart-411a8636-cd7a-4af7-a9a8-3097319b322c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113071520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.3113071520
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.1901729570
Short name T395
Test name
Test status
Simulation time 23524628 ps
CPU time 0.85 seconds
Started Jul 25 07:16:28 PM PDT 24
Finished Jul 25 07:16:29 PM PDT 24
Peak memory 200452 kb
Host smart-4cdf9c35-ae2c-464b-a9cc-b76efd27c6c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901729570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.1901729570
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.1240476005
Short name T828
Test name
Test status
Simulation time 1764982049 ps
CPU time 10.24 seconds
Started Jul 25 07:16:26 PM PDT 24
Finished Jul 25 07:16:36 PM PDT 24
Peak memory 200788 kb
Host smart-28da6f86-1868-4bfe-8e84-8e477f853afb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240476005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1240476005
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.1551944437
Short name T467
Test name
Test status
Simulation time 859448874 ps
CPU time 6.55 seconds
Started Jul 25 07:16:22 PM PDT 24
Finished Jul 25 07:16:29 PM PDT 24
Peak memory 200640 kb
Host smart-0820b951-ee87-4612-b490-0f99d57857bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551944437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.1551944437
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1189489960
Short name T199
Test name
Test status
Simulation time 51001467 ps
CPU time 0.93 seconds
Started Jul 25 07:16:25 PM PDT 24
Finished Jul 25 07:16:26 PM PDT 24
Peak memory 200500 kb
Host smart-db09c848-ad69-4228-9598-5ad5842c858b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189489960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.1189489960
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3365626564
Short name T782
Test name
Test status
Simulation time 153908370 ps
CPU time 1.19 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:25 PM PDT 24
Peak memory 200508 kb
Host smart-ce5d7e93-1474-47aa-af7c-ca1a3dedaf80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365626564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3365626564
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.186493768
Short name T581
Test name
Test status
Simulation time 60130837 ps
CPU time 1.01 seconds
Started Jul 25 07:16:23 PM PDT 24
Finished Jul 25 07:16:24 PM PDT 24
Peak memory 200456 kb
Host smart-e3130aa9-1fdc-49c6-8161-39a044817c68
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186493768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.clkmgr_lc_ctrl_intersig_mubi.186493768
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.1211076973
Short name T184
Test name
Test status
Simulation time 17615642 ps
CPU time 0.8 seconds
Started Jul 25 07:16:22 PM PDT 24
Finished Jul 25 07:16:23 PM PDT 24
Peak memory 200452 kb
Host smart-49dc09ca-679f-443e-97da-6e8ccbdb048c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211076973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1211076973
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.2905969342
Short name T689
Test name
Test status
Simulation time 411941307 ps
CPU time 2.36 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:27 PM PDT 24
Peak memory 200556 kb
Host smart-3aafe1e3-c12b-4174-9bb5-34d2d54e3ffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905969342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2905969342
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.1510395183
Short name T595
Test name
Test status
Simulation time 71981798 ps
CPU time 1.03 seconds
Started Jul 25 07:16:23 PM PDT 24
Finished Jul 25 07:16:24 PM PDT 24
Peak memory 200412 kb
Host smart-932ed7fb-fef7-4ab6-b404-52607c5e97e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510395183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.1510395183
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.1068562338
Short name T371
Test name
Test status
Simulation time 3263292646 ps
CPU time 17.47 seconds
Started Jul 25 07:16:26 PM PDT 24
Finished Jul 25 07:16:44 PM PDT 24
Peak memory 200852 kb
Host smart-5f4baa24-743a-4596-8b24-5bba6108515a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068562338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.1068562338
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.2072201249
Short name T706
Test name
Test status
Simulation time 93791965 ps
CPU time 1.16 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:25 PM PDT 24
Peak memory 200508 kb
Host smart-628764cc-e182-40c8-ad5b-81f28a60f14e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072201249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.2072201249
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.108565388
Short name T603
Test name
Test status
Simulation time 62941804 ps
CPU time 0.94 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:25 PM PDT 24
Peak memory 200464 kb
Host smart-d3529eb5-927d-4171-b586-709fe06f1709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108565388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkm
gr_alert_test.108565388
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.410033839
Short name T278
Test name
Test status
Simulation time 22559449 ps
CPU time 0.9 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:25 PM PDT 24
Peak memory 200504 kb
Host smart-d62ab93f-68f3-42da-9ecf-31f6b0976987
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410033839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.410033839
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.563299431
Short name T176
Test name
Test status
Simulation time 56520413 ps
CPU time 0.77 seconds
Started Jul 25 07:16:26 PM PDT 24
Finished Jul 25 07:16:27 PM PDT 24
Peak memory 200424 kb
Host smart-9215f002-5d98-4e68-aad2-8348d8159c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563299431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.563299431
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.1693009401
Short name T150
Test name
Test status
Simulation time 91041809 ps
CPU time 1.06 seconds
Started Jul 25 07:16:19 PM PDT 24
Finished Jul 25 07:16:21 PM PDT 24
Peak memory 200488 kb
Host smart-566edf33-691a-4bb2-ba32-5ef534dc1d62
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693009401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.1693009401
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.2748061300
Short name T390
Test name
Test status
Simulation time 35808461 ps
CPU time 0.85 seconds
Started Jul 25 07:16:28 PM PDT 24
Finished Jul 25 07:16:29 PM PDT 24
Peak memory 200512 kb
Host smart-e861ec80-a64a-444b-a73c-4a668205afb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748061300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2748061300
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.3460567335
Short name T406
Test name
Test status
Simulation time 2023115835 ps
CPU time 9.11 seconds
Started Jul 25 07:16:18 PM PDT 24
Finished Jul 25 07:16:28 PM PDT 24
Peak memory 200764 kb
Host smart-cc0d174f-1cd5-46c4-852f-16a3e27c22be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460567335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3460567335
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.2608936375
Short name T240
Test name
Test status
Simulation time 856296163 ps
CPU time 6.57 seconds
Started Jul 25 07:16:26 PM PDT 24
Finished Jul 25 07:16:33 PM PDT 24
Peak memory 200592 kb
Host smart-82187879-ba8e-44dd-bb25-9672c3da9dd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608936375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.2608936375
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2668519796
Short name T242
Test name
Test status
Simulation time 92626994 ps
CPU time 1.09 seconds
Started Jul 25 07:16:22 PM PDT 24
Finished Jul 25 07:16:23 PM PDT 24
Peak memory 200508 kb
Host smart-e97c89ee-0b8c-48e2-b79a-2e52cff3d55d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668519796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.2668519796
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2880340929
Short name T442
Test name
Test status
Simulation time 63144578 ps
CPU time 1.03 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:25 PM PDT 24
Peak memory 200488 kb
Host smart-14c81d10-0111-459c-ae81-145f20a8cd39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880340929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.2880340929
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.1293401024
Short name T522
Test name
Test status
Simulation time 41527565 ps
CPU time 0.81 seconds
Started Jul 25 07:16:22 PM PDT 24
Finished Jul 25 07:16:23 PM PDT 24
Peak memory 200496 kb
Host smart-1f1fc967-2fd2-4793-b2ae-ae17bd5d51b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293401024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.1293401024
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.1746184985
Short name T389
Test name
Test status
Simulation time 16485332 ps
CPU time 0.74 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:25 PM PDT 24
Peak memory 200488 kb
Host smart-ae3829ea-6098-407f-a5d3-cc729d310bb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746184985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1746184985
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.4009233823
Short name T475
Test name
Test status
Simulation time 1280063710 ps
CPU time 4.88 seconds
Started Jul 25 07:16:24 PM PDT 24
Finished Jul 25 07:16:29 PM PDT 24
Peak memory 200676 kb
Host smart-f5bf56d2-ea88-4ddc-9084-5b9b5c26bade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009233823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.4009233823
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.4061568990
Short name T690
Test name
Test status
Simulation time 23253269 ps
CPU time 0.8 seconds
Started Jul 25 07:16:25 PM PDT 24
Finished Jul 25 07:16:26 PM PDT 24
Peak memory 200468 kb
Host smart-ad922b10-8a28-486e-b15e-990252f68ce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061568990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.4061568990
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.21767896
Short name T335
Test name
Test status
Simulation time 2484109298 ps
CPU time 19.93 seconds
Started Jul 25 07:16:20 PM PDT 24
Finished Jul 25 07:16:40 PM PDT 24
Peak memory 200868 kb
Host smart-40005b86-b1bc-4845-98b6-4b66b068ce21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21767896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_stress_all.21767896
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.120364140
Short name T600
Test name
Test status
Simulation time 55364212579 ps
CPU time 503.49 seconds
Started Jul 25 07:16:25 PM PDT 24
Finished Jul 25 07:24:49 PM PDT 24
Peak memory 209196 kb
Host smart-811f28a2-59c2-4c1d-ad9d-44bcefaa28d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=120364140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.120364140
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1293688322
Short name T197
Test name
Test status
Simulation time 97361568 ps
CPU time 1.16 seconds
Started Jul 25 07:16:20 PM PDT 24
Finished Jul 25 07:16:21 PM PDT 24
Peak memory 200456 kb
Host smart-4e2be061-c04e-4431-a44c-83888f933124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293688322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1293688322
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.4128756028
Short name T348
Test name
Test status
Simulation time 31456124 ps
CPU time 0.76 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 200580 kb
Host smart-6f1ca805-61a6-4d02-96c9-fa38a5f8ba45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128756028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.4128756028
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2606048760
Short name T347
Test name
Test status
Simulation time 23456712 ps
CPU time 0.82 seconds
Started Jul 25 07:14:25 PM PDT 24
Finished Jul 25 07:14:26 PM PDT 24
Peak memory 200504 kb
Host smart-3d7cddd6-00b2-48bd-bfed-12e4b000238b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606048760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.2606048760
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.2349225459
Short name T474
Test name
Test status
Simulation time 19787771 ps
CPU time 0.7 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 199744 kb
Host smart-30c4b75d-71a1-4844-b05f-ffb62dac947f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349225459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2349225459
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.3171175029
Short name T420
Test name
Test status
Simulation time 24958350 ps
CPU time 0.91 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200504 kb
Host smart-091e1b9a-4a40-4f22-9c85-a22e29408541
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171175029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.3171175029
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.182614964
Short name T787
Test name
Test status
Simulation time 24771623 ps
CPU time 0.87 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 200476 kb
Host smart-be170bbc-7236-450f-a1c7-b948d648bf84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182614964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.182614964
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.3356267616
Short name T11
Test name
Test status
Simulation time 2001992358 ps
CPU time 14.88 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:42 PM PDT 24
Peak memory 200768 kb
Host smart-2bf23fc4-e788-483d-a30b-e64910905154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356267616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.3356267616
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.3935474969
Short name T119
Test name
Test status
Simulation time 1032686044 ps
CPU time 4.78 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:32 PM PDT 24
Peak memory 200636 kb
Host smart-fd537023-0fd6-4628-94f9-e4ae8e5823e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935474969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.3935474969
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1649625723
Short name T586
Test name
Test status
Simulation time 33763637 ps
CPU time 0.82 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200484 kb
Host smart-101b225d-cafb-490a-828a-d866a0d12e31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649625723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.1649625723
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.856123980
Short name T720
Test name
Test status
Simulation time 27039583 ps
CPU time 0.8 seconds
Started Jul 25 07:14:31 PM PDT 24
Finished Jul 25 07:14:32 PM PDT 24
Peak memory 200468 kb
Host smart-b6adfa14-2254-45d1-a1bf-a067c0789935
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856123980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_clk_byp_req_intersig_mubi.856123980
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2870628506
Short name T545
Test name
Test status
Simulation time 54258159 ps
CPU time 1.03 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 200476 kb
Host smart-a0a9f1b5-2685-435c-8129-b3cf25f8de18
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870628506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.2870628506
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.2890370343
Short name T318
Test name
Test status
Simulation time 23343686 ps
CPU time 0.76 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200528 kb
Host smart-c470fc9f-90dc-45ce-bbd3-1c185611bbab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890370343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2890370343
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.3610666959
Short name T508
Test name
Test status
Simulation time 201029206 ps
CPU time 1.57 seconds
Started Jul 25 07:14:27 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200476 kb
Host smart-be4638b1-7f0b-4a0b-b34a-5dc0535f7fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610666959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.3610666959
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.3462842280
Short name T445
Test name
Test status
Simulation time 26645156 ps
CPU time 0.89 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 200472 kb
Host smart-e104cf63-a649-4226-9ef2-df5ece2afb1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462842280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3462842280
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.1663080989
Short name T823
Test name
Test status
Simulation time 5691468055 ps
CPU time 44.12 seconds
Started Jul 25 07:14:26 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200888 kb
Host smart-b6ec5c81-d7be-43c3-b31a-1de930b47cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663080989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.1663080989
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.2511520998
Short name T291
Test name
Test status
Simulation time 37662735 ps
CPU time 1.03 seconds
Started Jul 25 07:14:25 PM PDT 24
Finished Jul 25 07:14:27 PM PDT 24
Peak memory 200512 kb
Host smart-2d5e5d54-f547-4600-92c4-2de076fd3ef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511520998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2511520998
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.4212172365
Short name T562
Test name
Test status
Simulation time 76153369 ps
CPU time 1.02 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200512 kb
Host smart-6518d8c9-c2a5-4617-98d9-d42b0ea87486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212172365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.4212172365
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3850401379
Short name T313
Test name
Test status
Simulation time 16688804 ps
CPU time 0.77 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:40 PM PDT 24
Peak memory 200380 kb
Host smart-b4c42125-b7b1-4270-b4ee-3059121f9a61
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850401379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.3850401379
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.2962944127
Short name T408
Test name
Test status
Simulation time 23037043 ps
CPU time 0.74 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:40 PM PDT 24
Peak memory 199712 kb
Host smart-287ecadb-c18e-40a6-afb3-b322719235c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962944127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2962944127
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.613693924
Short name T774
Test name
Test status
Simulation time 17492197 ps
CPU time 0.78 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 200464 kb
Host smart-2f8e2298-0220-45e4-91c3-4db61b3d03c1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613693924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.clkmgr_div_intersig_mubi.613693924
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.3104820057
Short name T727
Test name
Test status
Simulation time 42584487 ps
CPU time 0.96 seconds
Started Jul 25 07:14:30 PM PDT 24
Finished Jul 25 07:14:31 PM PDT 24
Peak memory 200508 kb
Host smart-67587c87-85fb-4537-a20f-b54ee7171955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104820057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3104820057
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.2585354281
Short name T14
Test name
Test status
Simulation time 553275582 ps
CPU time 4.55 seconds
Started Jul 25 07:14:34 PM PDT 24
Finished Jul 25 07:14:39 PM PDT 24
Peak memory 200512 kb
Host smart-c74a986d-5755-4620-8993-ea3ce6f6133f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585354281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2585354281
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.1291666833
Short name T818
Test name
Test status
Simulation time 140560972 ps
CPU time 1.67 seconds
Started Jul 25 07:14:37 PM PDT 24
Finished Jul 25 07:14:39 PM PDT 24
Peak memory 200612 kb
Host smart-c260b5ef-a91f-4c4e-ad51-8cf4ed914ac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291666833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.1291666833
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.809947955
Short name T768
Test name
Test status
Simulation time 82260671 ps
CPU time 1.07 seconds
Started Jul 25 07:14:34 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 200512 kb
Host smart-68ea021f-59ba-4385-9318-f7b2fa5298a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809947955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.clkmgr_idle_intersig_mubi.809947955
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2903523314
Short name T189
Test name
Test status
Simulation time 48091235 ps
CPU time 0.98 seconds
Started Jul 25 07:14:34 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 200520 kb
Host smart-7cef6a08-58e8-4a26-89d1-2e0f0712f1a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903523314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2903523314
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.403830841
Short name T489
Test name
Test status
Simulation time 20465906 ps
CPU time 0.79 seconds
Started Jul 25 07:14:40 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200520 kb
Host smart-4803ec8c-b0e6-4898-bc43-b413c0875248
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403830841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_ctrl_intersig_mubi.403830841
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.3738542169
Short name T355
Test name
Test status
Simulation time 21322268 ps
CPU time 0.8 seconds
Started Jul 25 07:14:41 PM PDT 24
Finished Jul 25 07:14:42 PM PDT 24
Peak memory 200472 kb
Host smart-07cf7986-2b16-4edb-aab5-c5e25fee7ea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738542169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3738542169
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.2226037310
Short name T590
Test name
Test status
Simulation time 49891551 ps
CPU time 0.86 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200472 kb
Host smart-3257d416-fa1f-4631-a50f-755f17dcdaec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226037310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2226037310
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.237322597
Short name T540
Test name
Test status
Simulation time 23439444 ps
CPU time 0.87 seconds
Started Jul 25 07:14:28 PM PDT 24
Finished Jul 25 07:14:29 PM PDT 24
Peak memory 200496 kb
Host smart-5b99ee40-de34-43a2-9e51-4162bde6a620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237322597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.237322597
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.4226335393
Short name T42
Test name
Test status
Simulation time 7028625856 ps
CPU time 25.47 seconds
Started Jul 25 07:14:41 PM PDT 24
Finished Jul 25 07:15:07 PM PDT 24
Peak memory 200884 kb
Host smart-aa8be225-be70-46a9-8423-5d31bd93a439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226335393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.4226335393
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.2197732143
Short name T116
Test name
Test status
Simulation time 129530079 ps
CPU time 1.3 seconds
Started Jul 25 07:14:40 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200460 kb
Host smart-a830929c-d5dd-46ed-aee9-b0cba61160a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197732143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.2197732143
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3399266279
Short name T399
Test name
Test status
Simulation time 45164901 ps
CPU time 0.83 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200552 kb
Host smart-4cb808c1-dda7-475c-abfd-6736097fcb12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399266279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3399266279
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3623267537
Short name T815
Test name
Test status
Simulation time 57058361 ps
CPU time 0.92 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200532 kb
Host smart-d0ba7842-5e4b-48f6-ada7-981d337c8f3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623267537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.3623267537
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.2860427822
Short name T575
Test name
Test status
Simulation time 37160697 ps
CPU time 0.77 seconds
Started Jul 25 07:14:38 PM PDT 24
Finished Jul 25 07:14:39 PM PDT 24
Peak memory 200408 kb
Host smart-286e6546-b286-4caa-8866-2efe1f848fa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860427822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2860427822
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3952531353
Short name T114
Test name
Test status
Simulation time 23690164 ps
CPU time 0.89 seconds
Started Jul 25 07:14:37 PM PDT 24
Finished Jul 25 07:14:38 PM PDT 24
Peak memory 200528 kb
Host smart-d26a747b-78c5-43fc-b347-76705f8bcbe9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952531353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.3952531353
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.483654449
Short name T257
Test name
Test status
Simulation time 48300326 ps
CPU time 0.86 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200524 kb
Host smart-841ec914-164b-41e0-b0b5-f618d9cd2597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483654449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.483654449
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.2687564474
Short name T480
Test name
Test status
Simulation time 2370855067 ps
CPU time 13.26 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200804 kb
Host smart-d495fe53-6ff8-4703-a756-06b96849b88a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687564474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.2687564474
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.1790667786
Short name T231
Test name
Test status
Simulation time 379377774 ps
CPU time 2.58 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:38 PM PDT 24
Peak memory 200604 kb
Host smart-4dc613e2-726c-47fa-b8cc-ca2b6a6789fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790667786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.1790667786
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1147781207
Short name T294
Test name
Test status
Simulation time 166633977 ps
CPU time 1.3 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200488 kb
Host smart-48fb4d51-02ab-432d-9daf-512d468e2b8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147781207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.1147781207
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1848692381
Short name T789
Test name
Test status
Simulation time 18187475 ps
CPU time 0.79 seconds
Started Jul 25 07:14:37 PM PDT 24
Finished Jul 25 07:14:38 PM PDT 24
Peak memory 200512 kb
Host smart-86fd322d-f468-4950-9166-64a127e2f554
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848692381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.1848692381
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.71560765
Short name T551
Test name
Test status
Simulation time 14213198 ps
CPU time 0.78 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200528 kb
Host smart-91843092-3004-4f29-935f-736b89e5040e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71560765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_lc_ctrl_intersig_mubi.71560765
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.2664899081
Short name T205
Test name
Test status
Simulation time 17048133 ps
CPU time 0.75 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200492 kb
Host smart-631451f5-8be4-4d3d-abea-e3afb39e0136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664899081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2664899081
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.5919988
Short name T350
Test name
Test status
Simulation time 1095018555 ps
CPU time 6.57 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:42 PM PDT 24
Peak memory 200696 kb
Host smart-6189ab75-2963-4040-afa7-37e4cb1b6ed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5919988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.5919988
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.3506947304
Short name T277
Test name
Test status
Simulation time 68298816 ps
CPU time 1 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:40 PM PDT 24
Peak memory 200428 kb
Host smart-9a5fe316-5b7e-4724-a60c-683d67843899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506947304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3506947304
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.1773107485
Short name T657
Test name
Test status
Simulation time 9617330963 ps
CPU time 42.16 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:15:21 PM PDT 24
Peak memory 200864 kb
Host smart-892527fa-a0c4-4816-8d8f-8c26ed0685b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773107485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.1773107485
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.2822342873
Short name T15
Test name
Test status
Simulation time 17555939305 ps
CPU time 257.55 seconds
Started Jul 25 07:14:34 PM PDT 24
Finished Jul 25 07:18:51 PM PDT 24
Peak memory 209204 kb
Host smart-9447ae04-9a2d-4bd8-beee-0527ca529389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2822342873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.2822342873
Directory /workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.clkmgr_trans.1757587863
Short name T472
Test name
Test status
Simulation time 38390801 ps
CPU time 0.88 seconds
Started Jul 25 07:14:40 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200484 kb
Host smart-bbf20b4d-d914-4c9f-b5c9-336474f48456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757587863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1757587863
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.3161861779
Short name T684
Test name
Test status
Simulation time 26845991 ps
CPU time 0.79 seconds
Started Jul 25 07:14:32 PM PDT 24
Finished Jul 25 07:14:33 PM PDT 24
Peak memory 200504 kb
Host smart-aa3eb204-9c48-4e92-aa98-bd9bae770b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161861779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.3161861779
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2734816207
Short name T304
Test name
Test status
Simulation time 51747706 ps
CPU time 0.84 seconds
Started Jul 25 07:14:34 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 200516 kb
Host smart-1e5cda32-33ad-48b8-858a-2f7166c975e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734816207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.2734816207
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.1556403552
Short name T571
Test name
Test status
Simulation time 45324314 ps
CPU time 0.81 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 199720 kb
Host smart-96a8b96d-4d08-4120-859d-b8532a5decd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556403552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1556403552
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.2125781098
Short name T613
Test name
Test status
Simulation time 27675634 ps
CPU time 0.85 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200512 kb
Host smart-3d175c69-c4e2-45d3-a193-a4215ec6c164
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125781098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.2125781098
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.4026923611
Short name T477
Test name
Test status
Simulation time 24630963 ps
CPU time 0.81 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200488 kb
Host smart-63792cb9-8215-44c5-8fbd-027b1e577951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026923611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.4026923611
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.2267564094
Short name T697
Test name
Test status
Simulation time 1401480175 ps
CPU time 11.07 seconds
Started Jul 25 07:14:37 PM PDT 24
Finished Jul 25 07:14:48 PM PDT 24
Peak memory 200596 kb
Host smart-f6d224b4-4872-445b-96d7-3eb9b3e5fbd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267564094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2267564094
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.4051218061
Short name T299
Test name
Test status
Simulation time 1941647799 ps
CPU time 13.7 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:53 PM PDT 24
Peak memory 200460 kb
Host smart-302298f5-69ea-4c45-bb59-192c75a296af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051218061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.4051218061
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1721922287
Short name T232
Test name
Test status
Simulation time 23062055 ps
CPU time 0.77 seconds
Started Jul 25 07:14:33 PM PDT 24
Finished Jul 25 07:14:34 PM PDT 24
Peak memory 200508 kb
Host smart-c5ef2923-cdbb-49bd-a331-eafbdc6b6e2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721922287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1721922287
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.573710083
Short name T692
Test name
Test status
Simulation time 36036995 ps
CPU time 0.88 seconds
Started Jul 25 07:14:38 PM PDT 24
Finished Jul 25 07:14:39 PM PDT 24
Peak memory 200532 kb
Host smart-946a0ec5-bec1-4699-a745-23eb3be985a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573710083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.clkmgr_lc_clk_byp_req_intersig_mubi.573710083
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3506626404
Short name T741
Test name
Test status
Simulation time 103760146 ps
CPU time 1 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200484 kb
Host smart-9a1ff7d8-c0c6-4a8f-8558-6034dfb850a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506626404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.3506626404
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.215330348
Short name T807
Test name
Test status
Simulation time 122154212 ps
CPU time 1.04 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200496 kb
Host smart-e36aa65c-ac76-41ba-94f5-a94a7d4b7455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215330348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.215330348
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.3988953820
Short name T401
Test name
Test status
Simulation time 1546312890 ps
CPU time 4.92 seconds
Started Jul 25 07:14:38 PM PDT 24
Finished Jul 25 07:14:43 PM PDT 24
Peak memory 200752 kb
Host smart-4d522c08-8e86-484c-85c0-3c7f933822bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988953820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.3988953820
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.2412027287
Short name T649
Test name
Test status
Simulation time 24235880 ps
CPU time 0.82 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200468 kb
Host smart-4120d06e-e5cd-40d0-bed3-a3e2b3cf42c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412027287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2412027287
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.1830305808
Short name T144
Test name
Test status
Simulation time 7317095713 ps
CPU time 39.96 seconds
Started Jul 25 07:14:38 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200936 kb
Host smart-bd00644b-caa6-4b57-a72f-b111fc3bbcfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830305808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.1830305808
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.3126803996
Short name T748
Test name
Test status
Simulation time 59833702 ps
CPU time 0.96 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200492 kb
Host smart-ab08a671-0649-4c15-bbd8-438e601ea04c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126803996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3126803996
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.2810961597
Short name T504
Test name
Test status
Simulation time 55972340 ps
CPU time 0.86 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200512 kb
Host smart-fecd93fd-d9a0-4a13-9e0f-45718da58aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810961597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.2810961597
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.580113274
Short name T717
Test name
Test status
Simulation time 42711246 ps
CPU time 0.81 seconds
Started Jul 25 07:14:40 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200520 kb
Host smart-d704d7c7-f1ce-43d7-878b-5357801d9270
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580113274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.580113274
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.363034468
Short name T773
Test name
Test status
Simulation time 106510638 ps
CPU time 0.93 seconds
Started Jul 25 07:14:40 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200400 kb
Host smart-f03723ee-a11d-49a6-8a33-627e98d20fc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363034468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.363034468
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.322490671
Short name T398
Test name
Test status
Simulation time 53758426 ps
CPU time 1.09 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200508 kb
Host smart-a2b5ddaa-28b8-49fb-a387-d1689de3eccd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322490671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_div_intersig_mubi.322490671
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.542867084
Short name T302
Test name
Test status
Simulation time 28214375 ps
CPU time 0.85 seconds
Started Jul 25 07:14:34 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 200500 kb
Host smart-10c3612f-ac20-4cb9-8993-1a0cbef3862b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542867084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.542867084
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.1153703223
Short name T238
Test name
Test status
Simulation time 320047587 ps
CPU time 2.99 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:39 PM PDT 24
Peak memory 200528 kb
Host smart-85b14b29-c65d-4d7b-993b-6fe5431c1776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153703223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1153703223
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.2837065976
Short name T456
Test name
Test status
Simulation time 255128128 ps
CPU time 2.51 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:38 PM PDT 24
Peak memory 200624 kb
Host smart-f672bde0-126e-41be-9a55-0eb0ce1cc81b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837065976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.2837065976
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.856056838
Short name T800
Test name
Test status
Simulation time 75898130 ps
CPU time 1.17 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200496 kb
Host smart-cacc2a66-518a-4f3c-b4b9-b714fa85d77f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856056838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_idle_intersig_mubi.856056838
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1581501505
Short name T392
Test name
Test status
Simulation time 168176087 ps
CPU time 1.23 seconds
Started Jul 25 07:14:40 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200508 kb
Host smart-b33d9515-ceaf-484c-9804-aadab031e54c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581501505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1581501505
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.2643647014
Short name T675
Test name
Test status
Simulation time 25294138 ps
CPU time 0.89 seconds
Started Jul 25 07:14:38 PM PDT 24
Finished Jul 25 07:14:39 PM PDT 24
Peak memory 200512 kb
Host smart-8bd960ba-3086-46ac-9175-f6cc85e0845e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643647014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.2643647014
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.2801988233
Short name T206
Test name
Test status
Simulation time 44100007 ps
CPU time 0.8 seconds
Started Jul 25 07:14:39 PM PDT 24
Finished Jul 25 07:14:40 PM PDT 24
Peak memory 200480 kb
Host smart-5f0cd44a-c33a-42d4-8217-f513c5a6810f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801988233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2801988233
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.4288012913
Short name T241
Test name
Test status
Simulation time 692759944 ps
CPU time 2.71 seconds
Started Jul 25 07:14:38 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200724 kb
Host smart-f65fb504-5596-4353-8812-1e25b790a2f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288012913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.4288012913
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.226132711
Short name T331
Test name
Test status
Simulation time 112831521 ps
CPU time 1.11 seconds
Started Jul 25 07:14:38 PM PDT 24
Finished Jul 25 07:14:39 PM PDT 24
Peak memory 200452 kb
Host smart-f651558f-1ef3-45a1-9e01-c96411d0f560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226132711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.226132711
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.1954359509
Short name T149
Test name
Test status
Simulation time 2133951866 ps
CPU time 16.05 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200832 kb
Host smart-5510c891-ee13-49b4-b008-5d121b1d0ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954359509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.1954359509
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.4013859268
Short name T687
Test name
Test status
Simulation time 15487520998 ps
CPU time 246.08 seconds
Started Jul 25 07:14:36 PM PDT 24
Finished Jul 25 07:18:43 PM PDT 24
Peak memory 209224 kb
Host smart-b87a0cd3-5ae5-411c-9b60-448bd58e1996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4013859268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.4013859268
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.3259595908
Short name T58
Test name
Test status
Simulation time 112378428 ps
CPU time 1.19 seconds
Started Jul 25 07:14:35 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200464 kb
Host smart-57ddec62-2ff9-432f-8e3d-a8ede213b715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259595908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3259595908
Directory /workspace/9.clkmgr_trans/latest
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