Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101587838

1

T5

1242

T6

3184

T4

130174

auto[1]

223812

1

T6

1300

T15

184

T38

794

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101530894

1

T5

1242

T6

3508

T4

130174

auto[1]

280756

1

T6

976

T15

40

T38

424

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101482712

1

T5

1242

T6

3362

T4

130174

auto[1]

328938

1

T6

1122

T15

180

T17

18

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94021996

1

T5

1242

T6

2690

T4

130174

auto[1]

7789654

1

T6

1794

T15

436

T17

1760

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65740430

1

T5

1224

T6

3814

T4

130154

auto[1]

36071220

1

T5

18

T6

670

T4

20

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58655290

1

T5

1224

T6

1082

T4

130154

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

35089780

1

T5

18

T6

222

T4

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

18030

1

T6

266

T38

82

T104

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4614

1

T6

62

T189

36

T144

34

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

6684404

1

T6

1546

T15

240

T17

1742

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

919850

1

T6

78

T38

54

T91

88

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

26096

1

T6

10

T15

32

T38

218

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5964

1

T38

10

T8

90

T10

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49278

1

T6

20

T38

36

T91

36

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1090

1

T149

30

T12

2

T24

18

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

7844

1

T6

76

T38

66

T8

168

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2204

1

T12

50

T24

82

T190

36

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

5360

1

T8

210

T118

24

T28

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1520

1

T8

72

T10

26

T28

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9038

1

T8

264

T118

70

T28

64

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2350

1

T28

60

T24

60

T191

38

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49632

1

T6

16

T15

16

T38

70

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2564

1

T8

150

T189

10

T144

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

18530

1

T6

124

T38

114

T91

128

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4596

1

T189

68

T144

136

T118

78

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

14570

1

T6

30

T15

10

T17

18

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3186

1

T8

308

T80

14

T145

26

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27820

1

T6

72

T15

114

T38

46

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5968

1

T8

170

T80

58

T145

144

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

77362

1

T6

60

T38

4

T104

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3754

1

T6

72

T10

48

T189

40

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29318

1

T6

492

T38

100

T104

64

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8110

1

T6

198

T189

130

T144

66

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24708

1

T6

20

T15

2

T38

50

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5490

1

T6

38

T38

10

T91

56

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

43150

1

T15

38

T38

76

T91

220

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10180

1

T38

82

T8

146

T10

52