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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.47 99.11 95.68 100.00 100.00 98.71 97.02 98.80


Total test records in report: 975
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T804 /workspace/coverage/default/43.clkmgr_clk_status.1211400313 Jul 26 06:35:31 PM PDT 24 Jul 26 06:35:32 PM PDT 24 16774419 ps
T805 /workspace/coverage/default/22.clkmgr_stress_all.2968729739 Jul 26 06:33:55 PM PDT 24 Jul 26 06:34:16 PM PDT 24 4181782149 ps
T806 /workspace/coverage/default/18.clkmgr_alert_test.2601115177 Jul 26 06:33:32 PM PDT 24 Jul 26 06:33:33 PM PDT 24 32999814 ps
T807 /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2068878395 Jul 26 06:35:54 PM PDT 24 Jul 26 06:35:55 PM PDT 24 20600589 ps
T808 /workspace/coverage/default/34.clkmgr_extclk.117954594 Jul 26 06:34:49 PM PDT 24 Jul 26 06:34:50 PM PDT 24 23416898 ps
T809 /workspace/coverage/default/36.clkmgr_alert_test.3361469430 Jul 26 06:34:57 PM PDT 24 Jul 26 06:34:57 PM PDT 24 16266295 ps
T810 /workspace/coverage/default/47.clkmgr_stress_all.3103140361 Jul 26 06:35:48 PM PDT 24 Jul 26 06:36:03 PM PDT 24 1771518083 ps
T811 /workspace/coverage/default/49.clkmgr_trans.4026564096 Jul 26 06:35:59 PM PDT 24 Jul 26 06:36:00 PM PDT 24 29738064 ps
T812 /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1538779750 Jul 26 06:35:45 PM PDT 24 Jul 26 06:35:46 PM PDT 24 17400787 ps
T813 /workspace/coverage/default/47.clkmgr_frequency.1499329780 Jul 26 06:35:46 PM PDT 24 Jul 26 06:35:52 PM PDT 24 675665167 ps
T814 /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2164013664 Jul 26 06:33:07 PM PDT 24 Jul 26 06:33:09 PM PDT 24 206131843 ps
T815 /workspace/coverage/default/31.clkmgr_frequency.1846598099 Jul 26 06:34:34 PM PDT 24 Jul 26 06:34:39 PM PDT 24 558366967 ps
T816 /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.1169013629 Jul 26 06:33:27 PM PDT 24 Jul 26 06:33:28 PM PDT 24 33416828 ps
T817 /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1611773883 Jul 26 06:34:49 PM PDT 24 Jul 26 06:34:50 PM PDT 24 59048705 ps
T818 /workspace/coverage/default/12.clkmgr_peri.128431081 Jul 26 06:33:06 PM PDT 24 Jul 26 06:33:07 PM PDT 24 12473604 ps
T819 /workspace/coverage/default/40.clkmgr_clk_status.1304064276 Jul 26 06:35:20 PM PDT 24 Jul 26 06:35:21 PM PDT 24 41738578 ps
T820 /workspace/coverage/default/15.clkmgr_frequency_timeout.3618090460 Jul 26 06:33:18 PM PDT 24 Jul 26 06:33:25 PM PDT 24 1597055497 ps
T821 /workspace/coverage/default/3.clkmgr_clk_status.1807983151 Jul 26 06:32:18 PM PDT 24 Jul 26 06:32:18 PM PDT 24 21974874 ps
T822 /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.3638128176 Jul 26 06:34:55 PM PDT 24 Jul 26 06:39:26 PM PDT 24 27059911623 ps
T823 /workspace/coverage/default/3.clkmgr_frequency_timeout.4111547663 Jul 26 06:32:17 PM PDT 24 Jul 26 06:32:31 PM PDT 24 1941359255 ps
T107 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.142066763 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:21 PM PDT 24 55094362 ps
T108 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.583415160 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 20514439 ps
T56 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3203082241 Jul 26 05:38:08 PM PDT 24 Jul 26 05:38:10 PM PDT 24 113701676 ps
T83 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1919606877 Jul 26 05:38:03 PM PDT 24 Jul 26 05:38:03 PM PDT 24 36251434 ps
T134 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3484660597 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:34 PM PDT 24 299415775 ps
T824 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3761259867 Jul 26 05:38:09 PM PDT 24 Jul 26 05:38:09 PM PDT 24 14209198 ps
T84 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1750254441 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:21 PM PDT 24 194246370 ps
T825 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3660891738 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:56 PM PDT 24 43566301 ps
T171 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3073110254 Jul 26 05:38:22 PM PDT 24 Jul 26 05:38:25 PM PDT 24 259236852 ps
T826 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.510134923 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 27916814 ps
T85 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3376594818 Jul 26 05:38:07 PM PDT 24 Jul 26 05:38:08 PM PDT 24 27739814 ps
T827 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2477390473 Jul 26 05:38:34 PM PDT 24 Jul 26 05:38:35 PM PDT 24 21633439 ps
T86 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2607604565 Jul 26 05:38:35 PM PDT 24 Jul 26 05:38:36 PM PDT 24 26025981 ps
T100 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2938387182 Jul 26 05:37:51 PM PDT 24 Jul 26 05:37:53 PM PDT 24 221036432 ps
T828 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1121188415 Jul 26 05:38:30 PM PDT 24 Jul 26 05:38:31 PM PDT 24 21698781 ps
T57 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1157483128 Jul 26 05:38:17 PM PDT 24 Jul 26 05:38:19 PM PDT 24 96163379 ps
T101 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2602831407 Jul 26 05:38:06 PM PDT 24 Jul 26 05:38:08 PM PDT 24 296479341 ps
T829 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2820595395 Jul 26 05:38:23 PM PDT 24 Jul 26 05:38:23 PM PDT 24 33748904 ps
T102 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2806575535 Jul 26 05:38:07 PM PDT 24 Jul 26 05:38:09 PM PDT 24 381222624 ps
T105 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1273112018 Jul 26 05:38:06 PM PDT 24 Jul 26 05:38:09 PM PDT 24 139280303 ps
T830 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3277559283 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:58 PM PDT 24 257083253 ps
T831 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2095918591 Jul 26 05:38:07 PM PDT 24 Jul 26 05:38:08 PM PDT 24 16379545 ps
T832 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.539463365 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 12555151 ps
T833 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3477894665 Jul 26 05:38:38 PM PDT 24 Jul 26 05:38:42 PM PDT 24 941291578 ps
T834 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3712320929 Jul 26 05:38:30 PM PDT 24 Jul 26 05:38:31 PM PDT 24 31360182 ps
T87 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2179660826 Jul 26 05:37:57 PM PDT 24 Jul 26 05:37:58 PM PDT 24 30489487 ps
T58 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.773546318 Jul 26 05:38:18 PM PDT 24 Jul 26 05:38:20 PM PDT 24 274577104 ps
T88 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.905220736 Jul 26 05:38:05 PM PDT 24 Jul 26 05:38:06 PM PDT 24 15808198 ps
T59 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2291359906 Jul 26 05:37:51 PM PDT 24 Jul 26 05:37:53 PM PDT 24 64917425 ps
T89 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2155963873 Jul 26 05:37:50 PM PDT 24 Jul 26 05:37:51 PM PDT 24 36258632 ps
T835 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.595181985 Jul 26 05:38:18 PM PDT 24 Jul 26 05:38:19 PM PDT 24 16863219 ps
T90 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.817354217 Jul 26 05:38:18 PM PDT 24 Jul 26 05:38:19 PM PDT 24 18213920 ps
T836 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2340751464 Jul 26 05:38:31 PM PDT 24 Jul 26 05:38:32 PM PDT 24 53340986 ps
T837 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1234074597 Jul 26 05:38:06 PM PDT 24 Jul 26 05:38:08 PM PDT 24 39994361 ps
T838 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1868310959 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:05 PM PDT 24 22033107 ps
T839 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.6378239 Jul 26 05:38:18 PM PDT 24 Jul 26 05:38:19 PM PDT 24 15964681 ps
T60 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1108309198 Jul 26 05:38:38 PM PDT 24 Jul 26 05:38:40 PM PDT 24 295880001 ps
T840 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3602317987 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:55 PM PDT 24 32214259 ps
T841 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1928141641 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:57 PM PDT 24 584039556 ps
T62 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2197084673 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:22 PM PDT 24 125373755 ps
T842 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.179747136 Jul 26 05:37:51 PM PDT 24 Jul 26 05:37:53 PM PDT 24 77667813 ps
T113 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2916134787 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:57 PM PDT 24 464478971 ps
T188 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3498285990 Jul 26 05:38:09 PM PDT 24 Jul 26 05:38:12 PM PDT 24 133995448 ps
T65 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.178792145 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:07 PM PDT 24 400363817 ps
T114 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2033228389 Jul 26 05:38:30 PM PDT 24 Jul 26 05:38:33 PM PDT 24 391091731 ps
T843 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.4020798589 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:56 PM PDT 24 17888972 ps
T844 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.458192882 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:56 PM PDT 24 250640906 ps
T845 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.218993948 Jul 26 05:38:01 PM PDT 24 Jul 26 05:38:02 PM PDT 24 27270201 ps
T846 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3054954980 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:05 PM PDT 24 36306979 ps
T847 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3394491453 Jul 26 05:38:23 PM PDT 24 Jul 26 05:38:24 PM PDT 24 29612738 ps
T848 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1004442323 Jul 26 05:38:19 PM PDT 24 Jul 26 05:38:20 PM PDT 24 26581751 ps
T849 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1960229929 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:24 PM PDT 24 488668608 ps
T850 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1686433599 Jul 26 05:38:35 PM PDT 24 Jul 26 05:38:35 PM PDT 24 14495000 ps
T851 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1082725845 Jul 26 05:38:25 PM PDT 24 Jul 26 05:38:26 PM PDT 24 39772478 ps
T61 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2595778378 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:34 PM PDT 24 169128088 ps
T852 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1475254289 Jul 26 05:38:03 PM PDT 24 Jul 26 05:38:04 PM PDT 24 26822189 ps
T109 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.874683356 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:34 PM PDT 24 60649533 ps
T853 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2750563415 Jul 26 05:38:18 PM PDT 24 Jul 26 05:38:19 PM PDT 24 50737581 ps
T854 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3479409707 Jul 26 05:38:09 PM PDT 24 Jul 26 05:38:10 PM PDT 24 12110530 ps
T855 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1337051188 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:58 PM PDT 24 288530546 ps
T856 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4038847682 Jul 26 05:38:29 PM PDT 24 Jul 26 05:38:30 PM PDT 24 43231719 ps
T857 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3214479473 Jul 26 05:37:56 PM PDT 24 Jul 26 05:38:05 PM PDT 24 2184683768 ps
T858 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1954984659 Jul 26 05:38:36 PM PDT 24 Jul 26 05:38:37 PM PDT 24 28779711 ps
T859 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.686914633 Jul 26 05:38:31 PM PDT 24 Jul 26 05:38:32 PM PDT 24 17509812 ps
T68 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3417704374 Jul 26 05:38:22 PM PDT 24 Jul 26 05:38:24 PM PDT 24 74663334 ps
T66 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.207121848 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:57 PM PDT 24 262943158 ps
T860 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3187465981 Jul 26 05:37:50 PM PDT 24 Jul 26 05:37:51 PM PDT 24 23479503 ps
T67 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.44558816 Jul 26 05:38:19 PM PDT 24 Jul 26 05:38:22 PM PDT 24 160987063 ps
T861 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1642713464 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:22 PM PDT 24 74441318 ps
T862 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3213158633 Jul 26 05:38:38 PM PDT 24 Jul 26 05:38:39 PM PDT 24 62434737 ps
T863 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.4176473041 Jul 26 05:37:50 PM PDT 24 Jul 26 05:37:52 PM PDT 24 147714389 ps
T864 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.4132678242 Jul 26 05:38:37 PM PDT 24 Jul 26 05:38:38 PM PDT 24 14710086 ps
T115 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1467725266 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:54 PM PDT 24 106748109 ps
T865 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1731920090 Jul 26 05:38:31 PM PDT 24 Jul 26 05:38:35 PM PDT 24 460081659 ps
T63 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1085497259 Jul 26 05:38:09 PM PDT 24 Jul 26 05:38:11 PM PDT 24 161713769 ps
T123 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3568373972 Jul 26 05:38:19 PM PDT 24 Jul 26 05:38:21 PM PDT 24 165539065 ps
T64 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3145585405 Jul 26 05:38:25 PM PDT 24 Jul 26 05:38:27 PM PDT 24 101366561 ps
T866 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.442196485 Jul 26 05:38:08 PM PDT 24 Jul 26 05:38:12 PM PDT 24 571280642 ps
T867 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3567983061 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:34 PM PDT 24 35855208 ps
T868 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.68875823 Jul 26 05:38:23 PM PDT 24 Jul 26 05:38:24 PM PDT 24 34738595 ps
T119 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3281786320 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:56 PM PDT 24 168644475 ps
T869 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.776717056 Jul 26 05:38:21 PM PDT 24 Jul 26 05:38:23 PM PDT 24 211293638 ps
T120 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.4109449939 Jul 26 05:38:07 PM PDT 24 Jul 26 05:38:09 PM PDT 24 358708066 ps
T870 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.483675726 Jul 26 05:37:51 PM PDT 24 Jul 26 05:37:52 PM PDT 24 16399338 ps
T121 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.565032293 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:06 PM PDT 24 61713255 ps
T871 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1666619264 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:06 PM PDT 24 43289192 ps
T872 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2246873002 Jul 26 05:38:21 PM PDT 24 Jul 26 05:38:22 PM PDT 24 73888019 ps
T873 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2354316789 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:54 PM PDT 24 270393077 ps
T127 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.4199507605 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:57 PM PDT 24 115519482 ps
T874 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3509829047 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:56 PM PDT 24 45471538 ps
T875 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2455587124 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:32 PM PDT 24 26706691 ps
T876 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3938058109 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:59 PM PDT 24 909056878 ps
T877 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.802597688 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:34 PM PDT 24 58177562 ps
T878 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1550773095 Jul 26 05:38:21 PM PDT 24 Jul 26 05:38:22 PM PDT 24 62882876 ps
T122 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2382084467 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:53 PM PDT 24 78303922 ps
T879 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3699232328 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:53 PM PDT 24 10780268 ps
T880 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1946202067 Jul 26 05:38:42 PM PDT 24 Jul 26 05:38:43 PM PDT 24 13702908 ps
T881 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1357217845 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:05 PM PDT 24 40216481 ps
T882 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.698157617 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:05 PM PDT 24 49701029 ps
T128 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2832851575 Jul 26 05:38:34 PM PDT 24 Jul 26 05:38:36 PM PDT 24 107144718 ps
T883 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.4111608966 Jul 26 05:37:56 PM PDT 24 Jul 26 05:37:59 PM PDT 24 253250048 ps
T884 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2233093488 Jul 26 05:38:37 PM PDT 24 Jul 26 05:38:37 PM PDT 24 34460207 ps
T885 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.185447310 Jul 26 05:37:55 PM PDT 24 Jul 26 05:38:03 PM PDT 24 736503662 ps
T886 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2707085092 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:55 PM PDT 24 52978463 ps
T133 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.590743020 Jul 26 05:37:49 PM PDT 24 Jul 26 05:37:51 PM PDT 24 118164526 ps
T887 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1577995521 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:33 PM PDT 24 13386458 ps
T111 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1830460694 Jul 26 05:38:25 PM PDT 24 Jul 26 05:38:27 PM PDT 24 213926374 ps
T129 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1307591830 Jul 26 05:38:21 PM PDT 24 Jul 26 05:38:22 PM PDT 24 63559391 ps
T132 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.493836641 Jul 26 05:38:29 PM PDT 24 Jul 26 05:38:31 PM PDT 24 77748691 ps
T888 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3491319147 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:33 PM PDT 24 13204987 ps
T889 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1267920876 Jul 26 05:38:39 PM PDT 24 Jul 26 05:38:40 PM PDT 24 46074901 ps
T130 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1347149282 Jul 26 05:38:07 PM PDT 24 Jul 26 05:38:10 PM PDT 24 428212715 ps
T890 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1876551145 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:33 PM PDT 24 16120438 ps
T891 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1828827356 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:21 PM PDT 24 41418834 ps
T892 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1506948369 Jul 26 05:38:05 PM PDT 24 Jul 26 05:38:06 PM PDT 24 49361283 ps
T893 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.4052349174 Jul 26 05:38:39 PM PDT 24 Jul 26 05:38:39 PM PDT 24 17909145 ps
T894 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1263692711 Jul 26 05:38:35 PM PDT 24 Jul 26 05:38:36 PM PDT 24 20901394 ps
T895 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3370205010 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:57 PM PDT 24 87899516 ps
T131 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.4233290142 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:06 PM PDT 24 67181170 ps
T896 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1537873325 Jul 26 05:38:34 PM PDT 24 Jul 26 05:38:34 PM PDT 24 25186057 ps
T897 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1328839972 Jul 26 05:38:21 PM PDT 24 Jul 26 05:38:23 PM PDT 24 94227574 ps
T898 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1593242161 Jul 26 05:37:52 PM PDT 24 Jul 26 05:37:54 PM PDT 24 229172225 ps
T899 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1507327141 Jul 26 05:37:47 PM PDT 24 Jul 26 05:37:48 PM PDT 24 39159308 ps
T900 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2057665384 Jul 26 05:37:53 PM PDT 24 Jul 26 05:37:55 PM PDT 24 71383262 ps
T110 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.4267579373 Jul 26 05:37:44 PM PDT 24 Jul 26 05:37:48 PM PDT 24 300350478 ps
T901 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1322935249 Jul 26 05:37:45 PM PDT 24 Jul 26 05:37:48 PM PDT 24 297271801 ps
T902 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.968258060 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 37922852 ps
T903 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.992848155 Jul 26 05:37:57 PM PDT 24 Jul 26 05:37:58 PM PDT 24 67753502 ps
T904 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3244721868 Jul 26 05:38:08 PM PDT 24 Jul 26 05:38:11 PM PDT 24 162912227 ps
T905 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3340209904 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:44 PM PDT 24 145456589 ps
T906 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.690560401 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 57046160 ps
T907 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2053241508 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 19427230 ps
T908 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.632536059 Jul 26 05:38:34 PM PDT 24 Jul 26 05:38:34 PM PDT 24 11419665 ps
T909 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2366371444 Jul 26 05:38:34 PM PDT 24 Jul 26 05:38:35 PM PDT 24 15098309 ps
T910 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.11445344 Jul 26 05:38:33 PM PDT 24 Jul 26 05:38:33 PM PDT 24 36264597 ps
T911 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2818743361 Jul 26 05:37:50 PM PDT 24 Jul 26 05:37:51 PM PDT 24 50338174 ps
T912 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1811691405 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 33207689 ps
T913 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3170683562 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:56 PM PDT 24 96628574 ps
T124 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.341737645 Jul 26 05:37:53 PM PDT 24 Jul 26 05:37:55 PM PDT 24 75638047 ps
T914 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2480635506 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:56 PM PDT 24 71840253 ps
T915 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.2766061222 Jul 26 05:38:30 PM PDT 24 Jul 26 05:38:31 PM PDT 24 90039445 ps
T916 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1727617400 Jul 26 05:37:56 PM PDT 24 Jul 26 05:37:57 PM PDT 24 15382582 ps
T917 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.13042882 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:33 PM PDT 24 42911294 ps
T918 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.583815102 Jul 26 05:38:31 PM PDT 24 Jul 26 05:38:32 PM PDT 24 44090856 ps
T919 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1929547180 Jul 26 05:38:25 PM PDT 24 Jul 26 05:38:27 PM PDT 24 29943307 ps
T920 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2711369589 Jul 26 05:37:49 PM PDT 24 Jul 26 05:37:56 PM PDT 24 260920076 ps
T921 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3080917756 Jul 26 05:37:54 PM PDT 24 Jul 26 05:37:56 PM PDT 24 92392361 ps
T922 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3650696695 Jul 26 05:37:50 PM PDT 24 Jul 26 05:37:51 PM PDT 24 24080934 ps
T923 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.3342790568 Jul 26 05:38:19 PM PDT 24 Jul 26 05:38:20 PM PDT 24 44406180 ps
T924 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3918780955 Jul 26 05:38:06 PM PDT 24 Jul 26 05:38:07 PM PDT 24 18780164 ps
T925 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2126747914 Jul 26 05:37:49 PM PDT 24 Jul 26 05:37:51 PM PDT 24 135356935 ps
T926 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2023981728 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:57 PM PDT 24 49543945 ps
T927 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2429788925 Jul 26 05:38:02 PM PDT 24 Jul 26 05:38:04 PM PDT 24 103202785 ps
T928 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2934153623 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:40 PM PDT 24 63718425 ps
T929 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.694134385 Jul 26 05:37:49 PM PDT 24 Jul 26 05:37:53 PM PDT 24 139138151 ps
T930 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3089330895 Jul 26 05:38:21 PM PDT 24 Jul 26 05:38:22 PM PDT 24 101039353 ps
T931 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3116463924 Jul 26 05:38:03 PM PDT 24 Jul 26 05:38:04 PM PDT 24 30271878 ps
T932 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3821457330 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:36 PM PDT 24 472228038 ps
T933 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2777547969 Jul 26 05:38:23 PM PDT 24 Jul 26 05:38:23 PM PDT 24 46110900 ps
T934 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.4290818322 Jul 26 05:38:31 PM PDT 24 Jul 26 05:38:32 PM PDT 24 33011914 ps
T935 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3692699048 Jul 26 05:38:09 PM PDT 24 Jul 26 05:38:10 PM PDT 24 18343734 ps
T936 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1158722878 Jul 26 05:38:22 PM PDT 24 Jul 26 05:38:23 PM PDT 24 27474553 ps
T937 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1526946396 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:56 PM PDT 24 34906749 ps
T938 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1335455568 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:21 PM PDT 24 16454785 ps
T939 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1053747240 Jul 26 05:38:09 PM PDT 24 Jul 26 05:38:12 PM PDT 24 159638400 ps
T940 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3623445934 Jul 26 05:38:34 PM PDT 24 Jul 26 05:38:35 PM PDT 24 48553596 ps
T941 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3027924093 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:33 PM PDT 24 65872831 ps
T942 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3547647697 Jul 26 05:37:46 PM PDT 24 Jul 26 05:37:48 PM PDT 24 154795240 ps
T943 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.644427780 Jul 26 05:38:04 PM PDT 24 Jul 26 05:38:07 PM PDT 24 38424775 ps
T944 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2630868638 Jul 26 05:38:23 PM PDT 24 Jul 26 05:38:24 PM PDT 24 11678811 ps
T945 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3989913167 Jul 26 05:38:05 PM PDT 24 Jul 26 05:38:07 PM PDT 24 34003615 ps
T946 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2650842090 Jul 26 05:38:31 PM PDT 24 Jul 26 05:38:33 PM PDT 24 152711793 ps
T947 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3723995013 Jul 26 05:38:25 PM PDT 24 Jul 26 05:38:27 PM PDT 24 108670558 ps
T948 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2647362859 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 40830051 ps
T949 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4261492776 Jul 26 05:37:55 PM PDT 24 Jul 26 05:37:56 PM PDT 24 27853598 ps
T125 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1878334558 Jul 26 05:38:21 PM PDT 24 Jul 26 05:38:23 PM PDT 24 104627212 ps
T950 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.4041155604 Jul 26 05:38:33 PM PDT 24 Jul 26 05:38:34 PM PDT 24 108124196 ps
T951 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3878949694 Jul 26 05:38:33 PM PDT 24 Jul 26 05:38:34 PM PDT 24 28128909 ps
T952 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.735805146 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 11712823 ps
T953 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3998608457 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:33 PM PDT 24 15727083 ps
T126 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.458548575 Jul 26 05:38:42 PM PDT 24 Jul 26 05:38:44 PM PDT 24 126224012 ps
T954 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1757991409 Jul 26 05:37:56 PM PDT 24 Jul 26 05:37:58 PM PDT 24 99046983 ps
T955 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.952152703 Jul 26 05:37:50 PM PDT 24 Jul 26 05:37:51 PM PDT 24 70756407 ps
T956 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2368788036 Jul 26 05:38:06 PM PDT 24 Jul 26 05:38:07 PM PDT 24 93715828 ps
T112 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3493695529 Jul 26 05:38:19 PM PDT 24 Jul 26 05:38:22 PM PDT 24 139124073 ps
T957 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3567991035 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 13251295 ps
T958 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3358486931 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 20844103 ps
T959 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1429469559 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:44 PM PDT 24 252162993 ps
T960 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.549856904 Jul 26 05:38:33 PM PDT 24 Jul 26 05:38:33 PM PDT 24 19684114 ps
T961 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1271613992 Jul 26 05:38:18 PM PDT 24 Jul 26 05:38:21 PM PDT 24 173909111 ps
T962 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.4210897454 Jul 26 05:37:49 PM PDT 24 Jul 26 05:37:50 PM PDT 24 47670391 ps
T963 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2248869254 Jul 26 05:38:39 PM PDT 24 Jul 26 05:38:40 PM PDT 24 19200867 ps
T964 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2678882140 Jul 26 05:37:51 PM PDT 24 Jul 26 05:37:52 PM PDT 24 103122862 ps
T965 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1925318682 Jul 26 05:37:47 PM PDT 24 Jul 26 05:37:50 PM PDT 24 254953245 ps
T966 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.256553805 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 78335297 ps
T967 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3377143239 Jul 26 05:37:51 PM PDT 24 Jul 26 05:37:52 PM PDT 24 41924832 ps
T968 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2136053234 Jul 26 05:38:22 PM PDT 24 Jul 26 05:38:23 PM PDT 24 102479402 ps
T969 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2191227786 Jul 26 05:38:18 PM PDT 24 Jul 26 05:38:20 PM PDT 24 219921422 ps
T970 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3041422217 Jul 26 05:38:08 PM PDT 24 Jul 26 05:38:09 PM PDT 24 26133958 ps
T106 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1355291208 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:24 PM PDT 24 286954477 ps
T971 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3378914466 Jul 26 05:37:45 PM PDT 24 Jul 26 05:37:47 PM PDT 24 23337273 ps
T972 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2800580668 Jul 26 05:38:22 PM PDT 24 Jul 26 05:38:25 PM PDT 24 339229282 ps
T973 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3332225365 Jul 26 05:38:32 PM PDT 24 Jul 26 05:38:33 PM PDT 24 32642720 ps
T974 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1716926083 Jul 26 05:38:35 PM PDT 24 Jul 26 05:38:37 PM PDT 24 183692199 ps
T975 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.32407965 Jul 26 05:38:20 PM PDT 24 Jul 26 05:38:23 PM PDT 24 124770879 ps

Test location /workspace/coverage/default/6.clkmgr_frequency.3654459126
Short name T4
Test name
Test status
Simulation time 679726609 ps
CPU time 6.07 seconds
Started Jul 26 06:32:43 PM PDT 24
Finished Jul 26 06:32:50 PM PDT 24
Peak memory 200524 kb
Host smart-47688dc9-e713-4a6b-8994-883c54e6cd90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654459126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3654459126
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.385518651
Short name T8
Test name
Test status
Simulation time 105718407942 ps
CPU time 662.77 seconds
Started Jul 26 06:35:51 PM PDT 24
Finished Jul 26 06:46:54 PM PDT 24
Peak memory 217344 kb
Host smart-1818f0e9-ceb9-497a-b561-1ffdd0ea4ea1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=385518651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.385518651
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.3561512829
Short name T14
Test name
Test status
Simulation time 45524465 ps
CPU time 0.81 seconds
Started Jul 26 06:35:54 PM PDT 24
Finished Jul 26 06:35:55 PM PDT 24
Peak memory 199664 kb
Host smart-5a1bffbf-f1b8-427f-96a3-cf7df0146771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561512829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3561512829
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3203082241
Short name T56
Test name
Test status
Simulation time 113701676 ps
CPU time 1.47 seconds
Started Jul 26 05:38:08 PM PDT 24
Finished Jul 26 05:38:10 PM PDT 24
Peak memory 201176 kb
Host smart-f6156296-4218-49ff-a924-2a80076c49f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203082241 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.3203082241
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.3441938964
Short name T29
Test name
Test status
Simulation time 944447669 ps
CPU time 3.95 seconds
Started Jul 26 06:34:52 PM PDT 24
Finished Jul 26 06:34:56 PM PDT 24
Peak memory 200656 kb
Host smart-29b3884f-6bd6-4f74-9656-842f6e7b636b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441938964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.3441938964
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.3841542940
Short name T43
Test name
Test status
Simulation time 286462787 ps
CPU time 3.11 seconds
Started Jul 26 06:32:10 PM PDT 24
Finished Jul 26 06:32:13 PM PDT 24
Peak memory 221356 kb
Host smart-6c9fec88-b054-4bf8-819a-366a99282424
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841542940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.3841542940
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.1450739493
Short name T24
Test name
Test status
Simulation time 6820420040 ps
CPU time 30.06 seconds
Started Jul 26 06:35:58 PM PDT 24
Finished Jul 26 06:36:29 PM PDT 24
Peak memory 200824 kb
Host smart-7e9d390a-e438-45ad-9072-ecf8c375ba08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450739493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.1450739493
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.442802907
Short name T20
Test name
Test status
Simulation time 55742418 ps
CPU time 1.02 seconds
Started Jul 26 06:34:41 PM PDT 24
Finished Jul 26 06:34:42 PM PDT 24
Peak memory 200364 kb
Host smart-faa763f5-55fb-4636-8311-dde827b0deaf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442802907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_idle_intersig_mubi.442802907
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2938387182
Short name T100
Test name
Test status
Simulation time 221036432 ps
CPU time 2.13 seconds
Started Jul 26 05:37:51 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 201216 kb
Host smart-e1269256-9a1b-40e9-8411-f12dc072c32a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938387182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.2938387182
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.764137387
Short name T163
Test name
Test status
Simulation time 46850355 ps
CPU time 0.87 seconds
Started Jul 26 06:33:39 PM PDT 24
Finished Jul 26 06:33:40 PM PDT 24
Peak memory 200476 kb
Host smart-c4a77137-b905-4b7d-93f8-fcc0fd45109c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764137387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkm
gr_alert_test.764137387
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3914252047
Short name T91
Test name
Test status
Simulation time 29947601 ps
CPU time 0.97 seconds
Started Jul 26 06:33:25 PM PDT 24
Finished Jul 26 06:33:26 PM PDT 24
Peak memory 200408 kb
Host smart-19cf69df-7360-424e-af77-ebe827852f7b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914252047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.3914252047
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2197084673
Short name T62
Test name
Test status
Simulation time 125373755 ps
CPU time 2.02 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 209648 kb
Host smart-06c7b6f5-b2c7-4dc6-8b6b-c94e1b3b29ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197084673 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.2197084673
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.4143553435
Short name T33
Test name
Test status
Simulation time 205100119250 ps
CPU time 984.55 seconds
Started Jul 26 06:35:30 PM PDT 24
Finished Jul 26 06:51:54 PM PDT 24
Peak memory 209152 kb
Host smart-7fa12fcf-8145-4497-abbf-e21f67959434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4143553435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.4143553435
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.2971378072
Short name T39
Test name
Test status
Simulation time 189129577195 ps
CPU time 965.56 seconds
Started Jul 26 06:33:59 PM PDT 24
Finished Jul 26 06:50:05 PM PDT 24
Peak memory 209108 kb
Host smart-be0ede0a-fa0e-408d-a1f5-c07407f9d746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2971378072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2971378072
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1355291208
Short name T106
Test name
Test status
Simulation time 286954477 ps
CPU time 3.06 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:24 PM PDT 24
Peak memory 201168 kb
Host smart-a3718637-19d2-4657-9c45-06000ef76f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355291208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.1355291208
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2382084467
Short name T122
Test name
Test status
Simulation time 78303922 ps
CPU time 1.27 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 201280 kb
Host smart-d50cbf11-fd7e-49c7-b134-60df7cb2ddf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382084467 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.2382084467
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2472702086
Short name T144
Test name
Test status
Simulation time 26237701 ps
CPU time 0.85 seconds
Started Jul 26 06:35:56 PM PDT 24
Finished Jul 26 06:35:57 PM PDT 24
Peak memory 200448 kb
Host smart-b9e6c77c-e526-4596-a67f-7394921e2a10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472702086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.2472702086
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.1839554057
Short name T74
Test name
Test status
Simulation time 85709724791 ps
CPU time 583.34 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:43:34 PM PDT 24
Peak memory 217312 kb
Host smart-88f274c1-6f52-47ed-b42e-df804b2cac1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1839554057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1839554057
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1878334558
Short name T125
Test name
Test status
Simulation time 104627212 ps
CPU time 1.9 seconds
Started Jul 26 05:38:21 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 201492 kb
Host smart-f314f591-1cc1-43bc-861e-4fecf1c34dcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878334558 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.1878334558
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2291359906
Short name T59
Test name
Test status
Simulation time 64917425 ps
CPU time 1.71 seconds
Started Jul 26 05:37:51 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 209596 kb
Host smart-da5a8324-68e3-4538-a238-a53676b1ad7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291359906 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.2291359906
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.2200190654
Short name T152
Test name
Test status
Simulation time 1547956079 ps
CPU time 8.48 seconds
Started Jul 26 06:31:50 PM PDT 24
Finished Jul 26 06:31:59 PM PDT 24
Peak memory 200656 kb
Host smart-c40270df-302f-4545-950a-77ce10f707a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200190654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.2200190654
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3493695529
Short name T112
Test name
Test status
Simulation time 139124073 ps
CPU time 2.86 seconds
Started Jul 26 05:38:19 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 201224 kb
Host smart-7aa48a43-4d09-4680-a665-d5aca0f5e04b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493695529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.3493695529
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1467725266
Short name T115
Test name
Test status
Simulation time 106748109 ps
CPU time 2.4 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 201264 kb
Host smart-f3f5152b-a6cb-4fac-9450-5049a07facd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467725266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.1467725266
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3377143239
Short name T967
Test name
Test status
Simulation time 41924832 ps
CPU time 1.23 seconds
Started Jul 26 05:37:51 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 200936 kb
Host smart-2ee124fa-09d7-493d-90cb-e9b76e2ec838
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377143239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.3377143239
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.694134385
Short name T929
Test name
Test status
Simulation time 139138151 ps
CPU time 3.91 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 201240 kb
Host smart-ddd2bde4-1830-485a-925e-cd9bd5e2e4b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694134385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.694134385
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1507327141
Short name T899
Test name
Test status
Simulation time 39159308 ps
CPU time 0.83 seconds
Started Jul 26 05:37:47 PM PDT 24
Finished Jul 26 05:37:48 PM PDT 24
Peak memory 201184 kb
Host smart-1e50eecb-e77e-4ad9-8673-6c325b67bb9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507327141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1507327141
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3650696695
Short name T922
Test name
Test status
Simulation time 24080934 ps
CPU time 0.97 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 201004 kb
Host smart-312db2df-29ed-44e3-b717-6aafb5fc9b9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650696695 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.3650696695
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.4210897454
Short name T962
Test name
Test status
Simulation time 47670391 ps
CPU time 0.87 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:50 PM PDT 24
Peak memory 200996 kb
Host smart-fac8a1d3-e39a-4e68-9637-a0a0df754f59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210897454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.4210897454
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3187465981
Short name T860
Test name
Test status
Simulation time 23479503 ps
CPU time 0.68 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 199476 kb
Host smart-a7299215-e044-4aa4-8959-aa4309549832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187465981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.3187465981
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3370205010
Short name T895
Test name
Test status
Simulation time 87899516 ps
CPU time 1.32 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 201052 kb
Host smart-c4af62fc-c3cd-4fa6-86f0-5c6152482bbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370205010 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.3370205010
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.590743020
Short name T133
Test name
Test status
Simulation time 118164526 ps
CPU time 1.98 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 201428 kb
Host smart-87e9e672-d294-400e-b686-203c0031919c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590743020 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.clkmgr_shadow_reg_errors.590743020
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1322935249
Short name T901
Test name
Test status
Simulation time 297271801 ps
CPU time 3.1 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:37:48 PM PDT 24
Peak memory 201172 kb
Host smart-ad1e7806-6a27-4c7b-bbe1-82393bd35964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322935249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.1322935249
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1526946396
Short name T937
Test name
Test status
Simulation time 34906749 ps
CPU time 1.15 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 200892 kb
Host smart-5dc7235b-79c2-4000-8f01-83419dea7e99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526946396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.1526946396
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2711369589
Short name T920
Test name
Test status
Simulation time 260920076 ps
CPU time 6.34 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 201212 kb
Host smart-76281c8f-6be4-4c57-aa62-e3d8242a7fe5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711369589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.2711369589
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2678882140
Short name T964
Test name
Test status
Simulation time 103122862 ps
CPU time 1 seconds
Started Jul 26 05:37:51 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 201052 kb
Host smart-69808688-0084-4193-82a4-9e8ccdbe9f1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678882140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2678882140
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.4176473041
Short name T863
Test name
Test status
Simulation time 147714389 ps
CPU time 1.55 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 201084 kb
Host smart-045467ba-2af7-4897-b7d5-1ae1b8ea5625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176473041 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.4176473041
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2155963873
Short name T89
Test name
Test status
Simulation time 36258632 ps
CPU time 0.89 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 200952 kb
Host smart-2a7aa6a3-446c-4fa1-89df-4ce1d50a6faa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155963873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.2155963873
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.483675726
Short name T870
Test name
Test status
Simulation time 16399338 ps
CPU time 0.66 seconds
Started Jul 26 05:37:51 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 199608 kb
Host smart-dd789cf0-d536-4543-b727-4dd5a73c9644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483675726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkm
gr_intr_test.483675726
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3547647697
Short name T942
Test name
Test status
Simulation time 154795240 ps
CPU time 1.49 seconds
Started Jul 26 05:37:46 PM PDT 24
Finished Jul 26 05:37:48 PM PDT 24
Peak memory 201384 kb
Host smart-27c5f0ad-8909-4cae-a538-5075cb3864aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547647697 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.3547647697
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3281786320
Short name T119
Test name
Test status
Simulation time 168644475 ps
CPU time 1.9 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 217696 kb
Host smart-fb95ba08-a72c-41b1-9478-8b28e4c12673
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281786320 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.3281786320
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1928141641
Short name T841
Test name
Test status
Simulation time 584039556 ps
CPU time 5.13 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 201208 kb
Host smart-98e3a5b2-d2a9-49d6-a207-867381d09b31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928141641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.1928141641
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.142066763
Short name T107
Test name
Test status
Simulation time 55094362 ps
CPU time 1.19 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:21 PM PDT 24
Peak memory 201088 kb
Host smart-e04bfdd3-3119-4a25-a5fa-33b2fedaaceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142066763 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.142066763
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2777547969
Short name T933
Test name
Test status
Simulation time 46110900 ps
CPU time 0.87 seconds
Started Jul 26 05:38:23 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 200840 kb
Host smart-b455ec34-d735-41aa-8546-173d1cb6ab29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777547969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.2777547969
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2820595395
Short name T829
Test name
Test status
Simulation time 33748904 ps
CPU time 0.73 seconds
Started Jul 26 05:38:23 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 199492 kb
Host smart-417b7fc7-f3b4-4157-b3cc-8b8e58cddd5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820595395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.2820595395
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3089330895
Short name T930
Test name
Test status
Simulation time 101039353 ps
CPU time 1.26 seconds
Started Jul 26 05:38:21 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 201000 kb
Host smart-ad2cb6a7-e1aa-44b9-9427-8993e1d74abe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089330895 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.3089330895
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3417704374
Short name T68
Test name
Test status
Simulation time 74663334 ps
CPU time 1.54 seconds
Started Jul 26 05:38:22 PM PDT 24
Finished Jul 26 05:38:24 PM PDT 24
Peak memory 201284 kb
Host smart-96e2ba7e-f098-4e86-9939-26c4b2914989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417704374 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.3417704374
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.773546318
Short name T58
Test name
Test status
Simulation time 274577104 ps
CPU time 2.31 seconds
Started Jul 26 05:38:18 PM PDT 24
Finished Jul 26 05:38:20 PM PDT 24
Peak memory 217696 kb
Host smart-b1515920-4acb-4d44-b63a-c24a6dcd4e3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773546318 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.773546318
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2800580668
Short name T972
Test name
Test status
Simulation time 339229282 ps
CPU time 3.13 seconds
Started Jul 26 05:38:22 PM PDT 24
Finished Jul 26 05:38:25 PM PDT 24
Peak memory 201152 kb
Host smart-bf1d6f03-3bbf-444f-98ee-981671d821ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800580668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.2800580668
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1004442323
Short name T848
Test name
Test status
Simulation time 26581751 ps
CPU time 1.02 seconds
Started Jul 26 05:38:19 PM PDT 24
Finished Jul 26 05:38:20 PM PDT 24
Peak memory 200968 kb
Host smart-f0e7f422-8e74-4478-9a87-9551cb5fea1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004442323 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1004442323
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2750563415
Short name T853
Test name
Test status
Simulation time 50737581 ps
CPU time 0.9 seconds
Started Jul 26 05:38:18 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 201032 kb
Host smart-b72e4e1f-33b4-4731-a7f7-6ed4527ea29f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750563415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.2750563415
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1335455568
Short name T938
Test name
Test status
Simulation time 16454785 ps
CPU time 0.65 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:21 PM PDT 24
Peak memory 199620 kb
Host smart-d70fec07-e56c-4156-8d39-2014920ab3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335455568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.1335455568
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2136053234
Short name T968
Test name
Test status
Simulation time 102479402 ps
CPU time 1.55 seconds
Started Jul 26 05:38:22 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 201436 kb
Host smart-e1d9ee8f-b7d5-496b-98aa-ef4f3de205dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136053234 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.2136053234
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3568373972
Short name T123
Test name
Test status
Simulation time 165539065 ps
CPU time 2.64 seconds
Started Jul 26 05:38:19 PM PDT 24
Finished Jul 26 05:38:21 PM PDT 24
Peak memory 209652 kb
Host smart-ef227ecf-bde9-47b1-9a51-28db1d1cb1aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568373972 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3568373972
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1960229929
Short name T849
Test name
Test status
Simulation time 488668608 ps
CPU time 4.32 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:24 PM PDT 24
Peak memory 201216 kb
Host smart-ee08b7e2-0307-42b8-8d39-312c373b1cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960229929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.1960229929
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1830460694
Short name T111
Test name
Test status
Simulation time 213926374 ps
CPU time 2.67 seconds
Started Jul 26 05:38:25 PM PDT 24
Finished Jul 26 05:38:27 PM PDT 24
Peak memory 201224 kb
Host smart-51316f39-19ce-4109-bdc1-c8ea87ec79a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830460694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.1830460694
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1828827356
Short name T891
Test name
Test status
Simulation time 41418834 ps
CPU time 1.23 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:21 PM PDT 24
Peak memory 201040 kb
Host smart-a5356209-f4c2-4985-8776-67dcb20c5564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828827356 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.1828827356
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.6378239
Short name T839
Test name
Test status
Simulation time 15964681 ps
CPU time 0.81 seconds
Started Jul 26 05:38:18 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 201000 kb
Host smart-b62fde70-5049-42e4-a110-7435e5b5995f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6378239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_csr_rw.6378239
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2630868638
Short name T944
Test name
Test status
Simulation time 11678811 ps
CPU time 0.71 seconds
Started Jul 26 05:38:23 PM PDT 24
Finished Jul 26 05:38:24 PM PDT 24
Peak memory 199632 kb
Host smart-63c156e1-5ae1-4638-a8d6-00889065c343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630868638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.2630868638
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1750254441
Short name T84
Test name
Test status
Simulation time 194246370 ps
CPU time 1.79 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:21 PM PDT 24
Peak memory 201172 kb
Host smart-1184b274-d645-4715-a513-421eaf01d6f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750254441 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1750254441
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1307591830
Short name T129
Test name
Test status
Simulation time 63559391 ps
CPU time 1.33 seconds
Started Jul 26 05:38:21 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 201216 kb
Host smart-58b7b550-582d-4fbb-abd5-efb6cea8f708
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307591830 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.1307591830
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1157483128
Short name T57
Test name
Test status
Simulation time 96163379 ps
CPU time 1.94 seconds
Started Jul 26 05:38:17 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 209684 kb
Host smart-59e1e3a7-b783-4e7d-a4d7-7bd59d53bb17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157483128 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1157483128
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1929547180
Short name T919
Test name
Test status
Simulation time 29943307 ps
CPU time 1.83 seconds
Started Jul 26 05:38:25 PM PDT 24
Finished Jul 26 05:38:27 PM PDT 24
Peak memory 201140 kb
Host smart-df07c8da-0026-4c90-a30f-0c4f84d10100
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929547180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.1929547180
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1642713464
Short name T861
Test name
Test status
Simulation time 74441318 ps
CPU time 1.67 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 201220 kb
Host smart-fc6c9f6c-4233-4298-9ba2-cd9c20d9a4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642713464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1642713464
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1550773095
Short name T878
Test name
Test status
Simulation time 62882876 ps
CPU time 1.01 seconds
Started Jul 26 05:38:21 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 201216 kb
Host smart-0783499f-4a49-42cc-8da6-e9ec531f182a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550773095 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.1550773095
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.817354217
Short name T90
Test name
Test status
Simulation time 18213920 ps
CPU time 0.86 seconds
Started Jul 26 05:38:18 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 200876 kb
Host smart-e48f4142-ae03-4df4-91df-75682a3b71dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817354217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
clkmgr_csr_rw.817354217
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3394491453
Short name T847
Test name
Test status
Simulation time 29612738 ps
CPU time 0.69 seconds
Started Jul 26 05:38:23 PM PDT 24
Finished Jul 26 05:38:24 PM PDT 24
Peak memory 199688 kb
Host smart-3a1e9d65-e78c-4eaa-98ed-2ff3cc2376eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394491453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.3394491453
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2246873002
Short name T872
Test name
Test status
Simulation time 73888019 ps
CPU time 1.05 seconds
Started Jul 26 05:38:21 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 200916 kb
Host smart-e2ea3207-6f7c-4464-ab5c-cc03e94e05ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246873002 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.2246873002
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2191227786
Short name T969
Test name
Test status
Simulation time 219921422 ps
CPU time 1.58 seconds
Started Jul 26 05:38:18 PM PDT 24
Finished Jul 26 05:38:20 PM PDT 24
Peak memory 201264 kb
Host smart-4272f923-bd5c-47aa-af76-d5202df0a508
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191227786 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.2191227786
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1328839972
Short name T897
Test name
Test status
Simulation time 94227574 ps
CPU time 1.97 seconds
Started Jul 26 05:38:21 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 201560 kb
Host smart-22bb4812-4387-4396-a73f-3670d000fb15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328839972 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1328839972
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3073110254
Short name T171
Test name
Test status
Simulation time 259236852 ps
CPU time 2.6 seconds
Started Jul 26 05:38:22 PM PDT 24
Finished Jul 26 05:38:25 PM PDT 24
Peak memory 201152 kb
Host smart-f90c8e44-9448-41a3-adac-b120ae87ff1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073110254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.3073110254
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3723995013
Short name T947
Test name
Test status
Simulation time 108670558 ps
CPU time 1.9 seconds
Started Jul 26 05:38:25 PM PDT 24
Finished Jul 26 05:38:27 PM PDT 24
Peak memory 201168 kb
Host smart-54edc8cf-d093-4903-a8d3-3d87cda97935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723995013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.3723995013
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1158722878
Short name T936
Test name
Test status
Simulation time 27474553 ps
CPU time 1.1 seconds
Started Jul 26 05:38:22 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 200984 kb
Host smart-fc2603a8-8ff6-4edf-86ad-e82a480f8333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158722878 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.1158722878
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.595181985
Short name T835
Test name
Test status
Simulation time 16863219 ps
CPU time 0.79 seconds
Started Jul 26 05:38:18 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 200964 kb
Host smart-ec45cfa2-bc0d-4c55-975f-1d3e530251e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595181985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
clkmgr_csr_rw.595181985
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1082725845
Short name T851
Test name
Test status
Simulation time 39772478 ps
CPU time 0.75 seconds
Started Jul 26 05:38:25 PM PDT 24
Finished Jul 26 05:38:26 PM PDT 24
Peak memory 199664 kb
Host smart-2f83ffe3-1cfa-44cd-aa79-cf658b8f686e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082725845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.1082725845
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.68875823
Short name T868
Test name
Test status
Simulation time 34738595 ps
CPU time 1.01 seconds
Started Jul 26 05:38:23 PM PDT 24
Finished Jul 26 05:38:24 PM PDT 24
Peak memory 200848 kb
Host smart-6d5ce8a5-7e74-4444-ae4c-bf4c7d9f83f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68875823 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.clkmgr_same_csr_outstanding.68875823
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.44558816
Short name T67
Test name
Test status
Simulation time 160987063 ps
CPU time 2.62 seconds
Started Jul 26 05:38:19 PM PDT 24
Finished Jul 26 05:38:22 PM PDT 24
Peak memory 209640 kb
Host smart-6510c088-ee52-4cae-8cee-1ec7e5d343a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44558816 -assert nopostproc +UVM_TESTNAME=
clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.44558816
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.3342790568
Short name T923
Test name
Test status
Simulation time 44406180 ps
CPU time 1.34 seconds
Started Jul 26 05:38:19 PM PDT 24
Finished Jul 26 05:38:20 PM PDT 24
Peak memory 201152 kb
Host smart-16a9f621-76f6-466b-8aac-9986ca571c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342790568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.3342790568
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4038847682
Short name T856
Test name
Test status
Simulation time 43231719 ps
CPU time 1.15 seconds
Started Jul 26 05:38:29 PM PDT 24
Finished Jul 26 05:38:30 PM PDT 24
Peak memory 201120 kb
Host smart-e25327c9-75ee-48a1-b7dc-4e5b92cf3ca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038847682 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.4038847682
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1954984659
Short name T858
Test name
Test status
Simulation time 28779711 ps
CPU time 0.8 seconds
Started Jul 26 05:38:36 PM PDT 24
Finished Jul 26 05:38:37 PM PDT 24
Peak memory 200644 kb
Host smart-ee13653a-7155-4cf4-8fda-318826043506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954984659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.1954984659
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.4052349174
Short name T893
Test name
Test status
Simulation time 17909145 ps
CPU time 0.66 seconds
Started Jul 26 05:38:39 PM PDT 24
Finished Jul 26 05:38:39 PM PDT 24
Peak memory 199680 kb
Host smart-8851819c-f1c9-495b-a41d-fb3799339280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052349174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.4052349174
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2607604565
Short name T86
Test name
Test status
Simulation time 26025981 ps
CPU time 1 seconds
Started Jul 26 05:38:35 PM PDT 24
Finished Jul 26 05:38:36 PM PDT 24
Peak memory 200912 kb
Host smart-af8b966a-5f25-461d-80c3-41a2bd047f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607604565 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.2607604565
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3145585405
Short name T64
Test name
Test status
Simulation time 101366561 ps
CPU time 1.85 seconds
Started Jul 26 05:38:25 PM PDT 24
Finished Jul 26 05:38:27 PM PDT 24
Peak memory 209692 kb
Host smart-404fc76e-7834-404b-847b-0b802c0a7dbe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145585405 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3145585405
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1271613992
Short name T961
Test name
Test status
Simulation time 173909111 ps
CPU time 2.89 seconds
Started Jul 26 05:38:18 PM PDT 24
Finished Jul 26 05:38:21 PM PDT 24
Peak memory 209688 kb
Host smart-f399ea2e-bc6f-4cac-8305-3989f613c313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271613992 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.1271613992
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.32407965
Short name T975
Test name
Test status
Simulation time 124770879 ps
CPU time 2.21 seconds
Started Jul 26 05:38:20 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 201140 kb
Host smart-b97b6c57-ee04-4850-9fba-8f0c9ab59c30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32407965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkm
gr_tl_errors.32407965
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.776717056
Short name T869
Test name
Test status
Simulation time 211293638 ps
CPU time 2 seconds
Started Jul 26 05:38:21 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 201188 kb
Host smart-e2dd1fa0-737c-4ea8-9281-2c5f455f7f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776717056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_tl_intg_err.776717056
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3027924093
Short name T941
Test name
Test status
Simulation time 65872831 ps
CPU time 1.39 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 200976 kb
Host smart-2b228179-7ccb-4c88-a5a1-6987d71dbbe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027924093 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3027924093
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2233093488
Short name T884
Test name
Test status
Simulation time 34460207 ps
CPU time 0.85 seconds
Started Jul 26 05:38:37 PM PDT 24
Finished Jul 26 05:38:37 PM PDT 24
Peak memory 200960 kb
Host smart-78aa5715-f223-4e32-bdd9-af87a3cfcd9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233093488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.2233093488
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.13042882
Short name T917
Test name
Test status
Simulation time 42911294 ps
CPU time 0.73 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199684 kb
Host smart-9abc2190-03f0-4324-b160-0f462d76b89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13042882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkm
gr_intr_test.13042882
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.968258060
Short name T902
Test name
Test status
Simulation time 37922852 ps
CPU time 1.08 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 201004 kb
Host smart-78d95cc5-c4d1-472d-9636-f8bf0ba5de65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968258060 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 16.clkmgr_same_csr_outstanding.968258060
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2595778378
Short name T61
Test name
Test status
Simulation time 169128088 ps
CPU time 1.53 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 201232 kb
Host smart-1d7f2ea2-3dfa-4d51-9f66-e0ce0a436126
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595778378 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.2595778378
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1429469559
Short name T959
Test name
Test status
Simulation time 252162993 ps
CPU time 3.19 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:44 PM PDT 24
Peak memory 217816 kb
Host smart-bf5ddb14-286a-4b64-a8b2-7443046678bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429469559 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.1429469559
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.802597688
Short name T877
Test name
Test status
Simulation time 58177562 ps
CPU time 1.93 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 201168 kb
Host smart-d7ee90b2-aeae-4f85-89f6-dccf01e12c19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802597688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk
mgr_tl_errors.802597688
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2650842090
Short name T946
Test name
Test status
Simulation time 152711793 ps
CPU time 1.67 seconds
Started Jul 26 05:38:31 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 201244 kb
Host smart-c0f25b22-52fa-4702-81df-782866162c79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650842090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.2650842090
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.583415160
Short name T108
Test name
Test status
Simulation time 20514439 ps
CPU time 0.91 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 201096 kb
Host smart-935f30d2-4ade-4731-bc61-7a97170c3c55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583415160 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.583415160
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1267920876
Short name T889
Test name
Test status
Simulation time 46074901 ps
CPU time 0.86 seconds
Started Jul 26 05:38:39 PM PDT 24
Finished Jul 26 05:38:40 PM PDT 24
Peak memory 201044 kb
Host smart-f18966cd-9f51-44f7-a7ca-4e8a34c2bd7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267920876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.1267920876
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.4132678242
Short name T864
Test name
Test status
Simulation time 14710086 ps
CPU time 0.68 seconds
Started Jul 26 05:38:37 PM PDT 24
Finished Jul 26 05:38:38 PM PDT 24
Peak memory 199596 kb
Host smart-d069812d-ee52-44e0-9199-c149be990f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132678242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.4132678242
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2340751464
Short name T836
Test name
Test status
Simulation time 53340986 ps
CPU time 1 seconds
Started Jul 26 05:38:31 PM PDT 24
Finished Jul 26 05:38:32 PM PDT 24
Peak memory 201040 kb
Host smart-8963ac4c-70ed-46bf-af4e-4742f29dac5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340751464 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2340751464
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1716926083
Short name T974
Test name
Test status
Simulation time 183692199 ps
CPU time 2.04 seconds
Started Jul 26 05:38:35 PM PDT 24
Finished Jul 26 05:38:37 PM PDT 24
Peak memory 209708 kb
Host smart-5b6dc8b8-2444-4128-9759-49d2521688d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716926083 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.1716926083
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3821457330
Short name T932
Test name
Test status
Simulation time 472228038 ps
CPU time 3.69 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:36 PM PDT 24
Peak memory 201672 kb
Host smart-1652405a-effa-4499-9a88-c4a2c72e4e43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821457330 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.3821457330
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3477894665
Short name T833
Test name
Test status
Simulation time 941291578 ps
CPU time 4.42 seconds
Started Jul 26 05:38:38 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 201212 kb
Host smart-b2dfb527-bf97-426f-aa3b-8936149a887a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477894665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3477894665
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2033228389
Short name T114
Test name
Test status
Simulation time 391091731 ps
CPU time 3.2 seconds
Started Jul 26 05:38:30 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 201228 kb
Host smart-a4c06d62-3f80-4aa4-a86f-512c726809de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033228389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.2033228389
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3484660597
Short name T134
Test name
Test status
Simulation time 299415775 ps
CPU time 2.31 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 201144 kb
Host smart-a7ce48f0-3ef5-4891-a5ee-07937f691214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484660597 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3484660597
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.256553805
Short name T966
Test name
Test status
Simulation time 78335297 ps
CPU time 0.88 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 200992 kb
Host smart-affd792a-e434-4e37-95ae-5b2eb7e67320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256553805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
clkmgr_csr_rw.256553805
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.549856904
Short name T960
Test name
Test status
Simulation time 19684114 ps
CPU time 0.67 seconds
Started Jul 26 05:38:33 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199608 kb
Host smart-df0d188a-916d-4561-a4ee-4493760fa911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549856904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_intr_test.549856904
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.2766061222
Short name T915
Test name
Test status
Simulation time 90039445 ps
CPU time 1.4 seconds
Started Jul 26 05:38:30 PM PDT 24
Finished Jul 26 05:38:31 PM PDT 24
Peak memory 201020 kb
Host smart-a65d2200-c46f-4586-9473-ee6961b48464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766061222 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.2766061222
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.458548575
Short name T126
Test name
Test status
Simulation time 126224012 ps
CPU time 2.1 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:44 PM PDT 24
Peak memory 201484 kb
Host smart-15fceead-4a96-4fda-9097-c23421bec3df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458548575 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.clkmgr_shadow_reg_errors.458548575
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2832851575
Short name T128
Test name
Test status
Simulation time 107144718 ps
CPU time 2.47 seconds
Started Jul 26 05:38:34 PM PDT 24
Finished Jul 26 05:38:36 PM PDT 24
Peak memory 209760 kb
Host smart-34b68f43-a5af-44ee-99e2-3a78a94cbd1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832851575 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.2832851575
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3567983061
Short name T867
Test name
Test status
Simulation time 35855208 ps
CPU time 1.96 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 201156 kb
Host smart-91a578b8-7939-4ae5-92e3-a8f3a4439b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567983061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.3567983061
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.874683356
Short name T109
Test name
Test status
Simulation time 60649533 ps
CPU time 1.56 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 201236 kb
Host smart-5fd936e9-4818-4700-9801-2452b68853b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874683356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_tl_intg_err.874683356
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3712320929
Short name T834
Test name
Test status
Simulation time 31360182 ps
CPU time 1.11 seconds
Started Jul 26 05:38:30 PM PDT 24
Finished Jul 26 05:38:31 PM PDT 24
Peak memory 201220 kb
Host smart-2dd96c07-6792-420a-beb7-0bd6b1efa164
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712320929 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3712320929
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1121188415
Short name T828
Test name
Test status
Simulation time 21698781 ps
CPU time 0.83 seconds
Started Jul 26 05:38:30 PM PDT 24
Finished Jul 26 05:38:31 PM PDT 24
Peak memory 201012 kb
Host smart-af303fb4-985e-4527-a933-ff6efd4c13a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121188415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.1121188415
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.690560401
Short name T906
Test name
Test status
Simulation time 57046160 ps
CPU time 0.76 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 199596 kb
Host smart-a867c38b-59f9-4f45-b520-7393786feeee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690560401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_intr_test.690560401
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.583815102
Short name T918
Test name
Test status
Simulation time 44090856 ps
CPU time 1.18 seconds
Started Jul 26 05:38:31 PM PDT 24
Finished Jul 26 05:38:32 PM PDT 24
Peak memory 200980 kb
Host smart-9c152b05-ac6a-40d9-8ae1-c029b6c124a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583815102 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 19.clkmgr_same_csr_outstanding.583815102
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.493836641
Short name T132
Test name
Test status
Simulation time 77748691 ps
CPU time 1.46 seconds
Started Jul 26 05:38:29 PM PDT 24
Finished Jul 26 05:38:31 PM PDT 24
Peak memory 201292 kb
Host smart-b92a1024-164c-4003-9d2b-e68ca7aaaca4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493836641 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.clkmgr_shadow_reg_errors.493836641
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1108309198
Short name T60
Test name
Test status
Simulation time 295880001 ps
CPU time 2.22 seconds
Started Jul 26 05:38:38 PM PDT 24
Finished Jul 26 05:38:40 PM PDT 24
Peak memory 201520 kb
Host smart-bcae73ec-b01c-453f-9162-b30c01e44d74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108309198 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.1108309198
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1731920090
Short name T865
Test name
Test status
Simulation time 460081659 ps
CPU time 3.91 seconds
Started Jul 26 05:38:31 PM PDT 24
Finished Jul 26 05:38:35 PM PDT 24
Peak memory 201152 kb
Host smart-181b0d53-d491-4668-934d-cc47c7b61958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731920090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.1731920090
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3340209904
Short name T905
Test name
Test status
Simulation time 145456589 ps
CPU time 2.84 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:44 PM PDT 24
Peak memory 201180 kb
Host smart-3a8d834d-d951-4be9-a948-1bd9544759ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340209904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.3340209904
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.179747136
Short name T842
Test name
Test status
Simulation time 77667813 ps
CPU time 1.32 seconds
Started Jul 26 05:37:51 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 200936 kb
Host smart-f23edf1f-ca44-4fd0-93f6-59c57d63663b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179747136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_aliasing.179747136
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3938058109
Short name T876
Test name
Test status
Simulation time 909056878 ps
CPU time 7.44 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:59 PM PDT 24
Peak memory 201064 kb
Host smart-d0330ebd-f34b-491c-8038-f8d6faa6c8fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938058109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.3938058109
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2818743361
Short name T911
Test name
Test status
Simulation time 50338174 ps
CPU time 0.87 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 200992 kb
Host smart-cd812a53-9cbf-411d-92ba-0aebd90e01a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818743361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.2818743361
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3378914466
Short name T971
Test name
Test status
Simulation time 23337273 ps
CPU time 0.93 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:37:47 PM PDT 24
Peak memory 201000 kb
Host smart-78e747d3-7e8c-4fbe-93f1-0f71802efd59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378914466 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.3378914466
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2707085092
Short name T886
Test name
Test status
Simulation time 52978463 ps
CPU time 0.87 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 200924 kb
Host smart-3560d654-3c5e-4f13-a8e8-83ebd9f243bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707085092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.2707085092
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3699232328
Short name T879
Test name
Test status
Simulation time 10780268 ps
CPU time 0.66 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 199612 kb
Host smart-e64e2a11-935f-4038-bb8a-3f3dae80a610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699232328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.3699232328
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3509829047
Short name T874
Test name
Test status
Simulation time 45471538 ps
CPU time 1.25 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 200896 kb
Host smart-ab055104-3c11-4eec-874c-e5aa54bebb04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509829047 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.3509829047
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.952152703
Short name T955
Test name
Test status
Simulation time 70756407 ps
CPU time 1.24 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 201268 kb
Host smart-94ccffe4-a54e-459c-93f6-5db2adfa8242
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952152703 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.clkmgr_shadow_reg_errors.952152703
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2126747914
Short name T925
Test name
Test status
Simulation time 135356935 ps
CPU time 1.94 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 209652 kb
Host smart-dc7b993d-a2e0-4796-88e3-119a259654f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126747914 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.2126747914
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.458192882
Short name T844
Test name
Test status
Simulation time 250640906 ps
CPU time 4.26 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 201072 kb
Host smart-f2dc36d0-9da0-42a7-acca-eb7a4c5513d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458192882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.458192882
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1925318682
Short name T965
Test name
Test status
Simulation time 254953245 ps
CPU time 2.63 seconds
Started Jul 26 05:37:47 PM PDT 24
Finished Jul 26 05:37:50 PM PDT 24
Peak memory 201396 kb
Host smart-9b5251b0-cdf2-4827-9536-64f029753a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925318682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.1925318682
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2053241508
Short name T907
Test name
Test status
Simulation time 19427230 ps
CPU time 0.68 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 199524 kb
Host smart-f8f1fd76-25ba-4306-becc-896b3f35cb73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053241508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2053241508
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.4041155604
Short name T950
Test name
Test status
Simulation time 108124196 ps
CPU time 0.85 seconds
Started Jul 26 05:38:33 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 199584 kb
Host smart-0462f621-e1fc-4420-9d66-75973efa033e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041155604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.4041155604
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.4290818322
Short name T934
Test name
Test status
Simulation time 33011914 ps
CPU time 0.71 seconds
Started Jul 26 05:38:31 PM PDT 24
Finished Jul 26 05:38:32 PM PDT 24
Peak memory 199684 kb
Host smart-d821fa17-1105-4104-bb08-cf599b12d291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290818322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.4290818322
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3998608457
Short name T953
Test name
Test status
Simulation time 15727083 ps
CPU time 0.65 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199616 kb
Host smart-c3a5789b-bdc1-4503-a8e6-67746595570d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998608457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.3998608457
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3878949694
Short name T951
Test name
Test status
Simulation time 28128909 ps
CPU time 0.68 seconds
Started Jul 26 05:38:33 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 199596 kb
Host smart-d6749603-705e-4bfd-b02d-ec1074316884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878949694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.3878949694
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2455587124
Short name T875
Test name
Test status
Simulation time 26706691 ps
CPU time 0.67 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:32 PM PDT 24
Peak memory 199576 kb
Host smart-a157b60b-6da5-4676-b139-3d3c068a7b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455587124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2455587124
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2934153623
Short name T928
Test name
Test status
Simulation time 63718425 ps
CPU time 0.78 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:40 PM PDT 24
Peak memory 199564 kb
Host smart-084b1164-bfde-4b50-8312-8e72859fecdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934153623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.2934153623
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2366371444
Short name T909
Test name
Test status
Simulation time 15098309 ps
CPU time 0.68 seconds
Started Jul 26 05:38:34 PM PDT 24
Finished Jul 26 05:38:35 PM PDT 24
Peak memory 199648 kb
Host smart-9871e5f4-016c-4c95-a97f-1ff219f85784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366371444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.2366371444
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1577995521
Short name T887
Test name
Test status
Simulation time 13386458 ps
CPU time 0.64 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199676 kb
Host smart-3311c5f4-3d3f-4681-9ded-ce2ec15ab418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577995521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.1577995521
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.735805146
Short name T952
Test name
Test status
Simulation time 11712823 ps
CPU time 0.68 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 199668 kb
Host smart-71b22f62-db12-4177-88f1-d91356686073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735805146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk
mgr_intr_test.735805146
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2057665384
Short name T900
Test name
Test status
Simulation time 71383262 ps
CPU time 1.85 seconds
Started Jul 26 05:37:53 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 201076 kb
Host smart-86923062-92b2-4f87-8227-5dcd4312b390
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057665384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.2057665384
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3214479473
Short name T857
Test name
Test status
Simulation time 2184683768 ps
CPU time 9.24 seconds
Started Jul 26 05:37:56 PM PDT 24
Finished Jul 26 05:38:05 PM PDT 24
Peak memory 201212 kb
Host smart-f096a326-9ba2-4103-a454-030fa5e43c76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214479473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.3214479473
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.992848155
Short name T903
Test name
Test status
Simulation time 67753502 ps
CPU time 0.96 seconds
Started Jul 26 05:37:57 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 201008 kb
Host smart-78f5699f-18b9-4477-b9e9-58eab782b51d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992848155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_hw_reset.992848155
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2429788925
Short name T927
Test name
Test status
Simulation time 103202785 ps
CPU time 1.87 seconds
Started Jul 26 05:38:02 PM PDT 24
Finished Jul 26 05:38:04 PM PDT 24
Peak memory 201140 kb
Host smart-71e316e9-223f-4145-8ee8-1da2b2111c1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429788925 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.2429788925
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.4020798589
Short name T843
Test name
Test status
Simulation time 17888972 ps
CPU time 0.82 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 200928 kb
Host smart-07c073e2-813a-4f05-b61c-841bdcb3a940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020798589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.4020798589
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3660891738
Short name T825
Test name
Test status
Simulation time 43566301 ps
CPU time 0.71 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 199496 kb
Host smart-0bf0d9ab-36f6-45fb-b626-ff5828c770b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660891738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.3660891738
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3602317987
Short name T840
Test name
Test status
Simulation time 32214259 ps
CPU time 1.17 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 201088 kb
Host smart-b5345627-1436-4634-9b7f-cc75dc00064c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602317987 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.3602317987
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2480635506
Short name T914
Test name
Test status
Simulation time 71840253 ps
CPU time 1.32 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 201156 kb
Host smart-6c2c45a9-1370-40c0-802b-2a784f4b7c82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480635506 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.2480635506
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1593242161
Short name T898
Test name
Test status
Simulation time 229172225 ps
CPU time 2.18 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 209600 kb
Host smart-c0a0a1f5-0a4f-49a3-8293-435261cdc186
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593242161 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1593242161
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2354316789
Short name T873
Test name
Test status
Simulation time 270393077 ps
CPU time 2.49 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 201068 kb
Host smart-ef9c7d82-9de5-4a4a-bdc8-b55b557c8a57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354316789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2354316789
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.4267579373
Short name T110
Test name
Test status
Simulation time 300350478 ps
CPU time 2.77 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:48 PM PDT 24
Peak memory 201248 kb
Host smart-b54bb3bc-69e4-45b6-b8d9-ee9d38e0944d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267579373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.4267579373
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3491319147
Short name T888
Test name
Test status
Simulation time 13204987 ps
CPU time 0.69 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199496 kb
Host smart-bcb0c7c4-dc08-4bef-91f0-df8c785782cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491319147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.3491319147
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3623445934
Short name T940
Test name
Test status
Simulation time 48553596 ps
CPU time 0.74 seconds
Started Jul 26 05:38:34 PM PDT 24
Finished Jul 26 05:38:35 PM PDT 24
Peak memory 199588 kb
Host smart-a58050dd-a471-4797-ba5b-aeebf5d2522e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623445934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.3623445934
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.510134923
Short name T826
Test name
Test status
Simulation time 27916814 ps
CPU time 0.67 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 199620 kb
Host smart-992a35a8-8a49-4b05-bff7-18483efd4d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510134923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk
mgr_intr_test.510134923
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2248869254
Short name T963
Test name
Test status
Simulation time 19200867 ps
CPU time 0.73 seconds
Started Jul 26 05:38:39 PM PDT 24
Finished Jul 26 05:38:40 PM PDT 24
Peak memory 199600 kb
Host smart-66d4dc4e-73e9-4cc3-abfe-fce5d174057d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248869254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.2248869254
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1537873325
Short name T896
Test name
Test status
Simulation time 25186057 ps
CPU time 0.67 seconds
Started Jul 26 05:38:34 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 199444 kb
Host smart-afa2d4ff-c7ec-4f80-a5c5-f69f774cd4ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537873325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.1537873325
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2647362859
Short name T948
Test name
Test status
Simulation time 40830051 ps
CPU time 0.71 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 199596 kb
Host smart-c2e3c167-5f17-431b-b55d-5b739f591616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647362859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.2647362859
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1811691405
Short name T912
Test name
Test status
Simulation time 33207689 ps
CPU time 0.72 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 199664 kb
Host smart-34224fba-b4f7-4c61-9b2d-b9683870f3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811691405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.1811691405
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.686914633
Short name T859
Test name
Test status
Simulation time 17509812 ps
CPU time 0.63 seconds
Started Jul 26 05:38:31 PM PDT 24
Finished Jul 26 05:38:32 PM PDT 24
Peak memory 199500 kb
Host smart-6962dfc6-4a05-4a94-9a46-59c20ef7a5d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686914633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk
mgr_intr_test.686914633
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1876551145
Short name T890
Test name
Test status
Simulation time 16120438 ps
CPU time 0.63 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199568 kb
Host smart-f17f9582-846b-4a8b-bf41-f4b936d55158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876551145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.1876551145
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.11445344
Short name T910
Test name
Test status
Simulation time 36264597 ps
CPU time 0.7 seconds
Started Jul 26 05:38:33 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199608 kb
Host smart-fd4e634c-9ad3-4a50-b46b-0ff268b3c839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11445344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkm
gr_intr_test.11445344
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1337051188
Short name T855
Test name
Test status
Simulation time 288530546 ps
CPU time 2.04 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 201208 kb
Host smart-3196ab59-53b6-4e6c-8b64-5ebb4216ffa3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337051188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.1337051188
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.185447310
Short name T885
Test name
Test status
Simulation time 736503662 ps
CPU time 7.95 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:38:03 PM PDT 24
Peak memory 201196 kb
Host smart-11fa078d-206f-4b36-8f3a-f9266319c443
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185447310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_bit_bash.185447310
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.218993948
Short name T845
Test name
Test status
Simulation time 27270201 ps
CPU time 0.91 seconds
Started Jul 26 05:38:01 PM PDT 24
Finished Jul 26 05:38:02 PM PDT 24
Peak memory 201220 kb
Host smart-e063a9a4-55dd-468c-81bb-bfe2aea4d842
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218993948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.218993948
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2023981728
Short name T926
Test name
Test status
Simulation time 49543945 ps
CPU time 1.42 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 201316 kb
Host smart-00caeace-137f-4922-ac59-568efbdb24d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023981728 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2023981728
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1919606877
Short name T83
Test name
Test status
Simulation time 36251434 ps
CPU time 0.77 seconds
Started Jul 26 05:38:03 PM PDT 24
Finished Jul 26 05:38:03 PM PDT 24
Peak memory 200896 kb
Host smart-f9f3d16a-c1b2-444b-b2be-4eb698ccdc28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919606877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.1919606877
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1727617400
Short name T916
Test name
Test status
Simulation time 15382582 ps
CPU time 0.66 seconds
Started Jul 26 05:37:56 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 199568 kb
Host smart-2a5c8c54-ba76-4e35-ab73-69b721def230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727617400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.1727617400
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3170683562
Short name T913
Test name
Test status
Simulation time 96628574 ps
CPU time 1.13 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 201004 kb
Host smart-b18fc548-bfd6-4714-93d3-3c221748174c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170683562 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.3170683562
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.341737645
Short name T124
Test name
Test status
Simulation time 75638047 ps
CPU time 1.38 seconds
Started Jul 26 05:37:53 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 201292 kb
Host smart-04e601c6-5b82-4bf7-aac0-049be42a7c3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341737645 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.clkmgr_shadow_reg_errors.341737645
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.207121848
Short name T66
Test name
Test status
Simulation time 262943158 ps
CPU time 2.2 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 217848 kb
Host smart-a9480396-7d83-40f6-876a-0f87bb19de99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207121848 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.207121848
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3277559283
Short name T830
Test name
Test status
Simulation time 257083253 ps
CPU time 3.66 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 201248 kb
Host smart-97c6fa06-1665-44a3-8c78-b65abded6aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277559283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.3277559283
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2916134787
Short name T113
Test name
Test status
Simulation time 464478971 ps
CPU time 3.61 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 201252 kb
Host smart-d43e88dd-30e7-4c73-882b-b26efa04fd06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916134787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.2916134787
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3358486931
Short name T958
Test name
Test status
Simulation time 20844103 ps
CPU time 0.68 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 199588 kb
Host smart-a501fd09-a3ca-48fd-b5b8-bdf5e56f56c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358486931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.3358486931
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2477390473
Short name T827
Test name
Test status
Simulation time 21633439 ps
CPU time 0.68 seconds
Started Jul 26 05:38:34 PM PDT 24
Finished Jul 26 05:38:35 PM PDT 24
Peak memory 199712 kb
Host smart-3eb6fb30-6e21-4058-8116-e42052230e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477390473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2477390473
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.632536059
Short name T908
Test name
Test status
Simulation time 11419665 ps
CPU time 0.65 seconds
Started Jul 26 05:38:34 PM PDT 24
Finished Jul 26 05:38:34 PM PDT 24
Peak memory 199468 kb
Host smart-b12e70b0-6f74-44c8-aa16-cbdc372b5b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632536059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clk
mgr_intr_test.632536059
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3567991035
Short name T957
Test name
Test status
Simulation time 13251295 ps
CPU time 0.67 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 199596 kb
Host smart-39fc8bbe-8ec0-4360-9ccd-d67d0bf58e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567991035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.3567991035
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.539463365
Short name T832
Test name
Test status
Simulation time 12555151 ps
CPU time 0.65 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 199620 kb
Host smart-1875b778-bfe5-4df1-a26f-35acdedf65dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539463365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clk
mgr_intr_test.539463365
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3332225365
Short name T973
Test name
Test status
Simulation time 32642720 ps
CPU time 0.68 seconds
Started Jul 26 05:38:32 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 199564 kb
Host smart-0371ed55-3d65-4faf-8099-cd9a3e29b9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332225365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.3332225365
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1946202067
Short name T880
Test name
Test status
Simulation time 13702908 ps
CPU time 0.71 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 199688 kb
Host smart-b0c30052-ab90-4b63-b8fc-eb993e086eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946202067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.1946202067
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3213158633
Short name T862
Test name
Test status
Simulation time 62434737 ps
CPU time 0.77 seconds
Started Jul 26 05:38:38 PM PDT 24
Finished Jul 26 05:38:39 PM PDT 24
Peak memory 199632 kb
Host smart-870fbe2c-18f0-465a-be25-b99c3f76ea6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213158633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.3213158633
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1686433599
Short name T850
Test name
Test status
Simulation time 14495000 ps
CPU time 0.68 seconds
Started Jul 26 05:38:35 PM PDT 24
Finished Jul 26 05:38:35 PM PDT 24
Peak memory 199608 kb
Host smart-4b67a776-14c4-489a-a613-953ab9316427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686433599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.1686433599
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1263692711
Short name T894
Test name
Test status
Simulation time 20901394 ps
CPU time 0.7 seconds
Started Jul 26 05:38:35 PM PDT 24
Finished Jul 26 05:38:36 PM PDT 24
Peak memory 199620 kb
Host smart-e6cd3052-b5db-4add-8a25-3a5e287107f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263692711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.1263692711
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1666619264
Short name T871
Test name
Test status
Simulation time 43289192 ps
CPU time 1.86 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:06 PM PDT 24
Peak memory 201252 kb
Host smart-79dc1824-2db6-4ebb-9be6-ef7f31d88400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666619264 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1666619264
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1475254289
Short name T852
Test name
Test status
Simulation time 26822189 ps
CPU time 0.77 seconds
Started Jul 26 05:38:03 PM PDT 24
Finished Jul 26 05:38:04 PM PDT 24
Peak memory 200876 kb
Host smart-e4bc8428-a8f9-4148-bc70-1999c2387fa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475254289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.1475254289
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4261492776
Short name T949
Test name
Test status
Simulation time 27853598 ps
CPU time 0.69 seconds
Started Jul 26 05:37:55 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 199512 kb
Host smart-57e1b076-4712-4868-8f1c-cbfc2381a17f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261492776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.4261492776
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2179660826
Short name T87
Test name
Test status
Simulation time 30489487 ps
CPU time 0.96 seconds
Started Jul 26 05:37:57 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 201032 kb
Host smart-c26f17c5-326b-4aaa-b80f-25c2133a84d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179660826 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.2179660826
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1757991409
Short name T954
Test name
Test status
Simulation time 99046983 ps
CPU time 1.94 seconds
Started Jul 26 05:37:56 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 209640 kb
Host smart-36c9b71b-70c8-406e-b2a4-ee897af23ee7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757991409 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1757991409
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.4199507605
Short name T127
Test name
Test status
Simulation time 115519482 ps
CPU time 2.62 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 209704 kb
Host smart-807235db-286c-4859-a278-a91462ac129e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199507605 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.4199507605
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3080917756
Short name T921
Test name
Test status
Simulation time 92392361 ps
CPU time 1.73 seconds
Started Jul 26 05:37:54 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 201124 kb
Host smart-b23a8220-1689-403d-9a56-adbabc28a10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080917756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.3080917756
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.4111608966
Short name T883
Test name
Test status
Simulation time 253250048 ps
CPU time 2.1 seconds
Started Jul 26 05:37:56 PM PDT 24
Finished Jul 26 05:37:59 PM PDT 24
Peak memory 201072 kb
Host smart-bfc881c2-d2ef-4ad6-a158-c10ae15cadfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111608966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.4111608966
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3054954980
Short name T846
Test name
Test status
Simulation time 36306979 ps
CPU time 1.01 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:05 PM PDT 24
Peak memory 201096 kb
Host smart-ae27db50-d1af-4d9f-9bb2-d6b11baf6554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054954980 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.3054954980
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1506948369
Short name T892
Test name
Test status
Simulation time 49361283 ps
CPU time 0.93 seconds
Started Jul 26 05:38:05 PM PDT 24
Finished Jul 26 05:38:06 PM PDT 24
Peak memory 200980 kb
Host smart-dfa9edb5-696b-4cda-9dd4-e6b5f0b33aa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506948369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.1506948369
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3761259867
Short name T824
Test name
Test status
Simulation time 14209198 ps
CPU time 0.7 seconds
Started Jul 26 05:38:09 PM PDT 24
Finished Jul 26 05:38:09 PM PDT 24
Peak memory 199664 kb
Host smart-f8151372-37f1-475c-861a-fbf838c921d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761259867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3761259867
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3041422217
Short name T970
Test name
Test status
Simulation time 26133958 ps
CPU time 0.97 seconds
Started Jul 26 05:38:08 PM PDT 24
Finished Jul 26 05:38:09 PM PDT 24
Peak memory 200956 kb
Host smart-53ebd23a-abf8-4c07-924e-e832b42cb1bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041422217 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.3041422217
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.4233290142
Short name T131
Test name
Test status
Simulation time 67181170 ps
CPU time 1.18 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:06 PM PDT 24
Peak memory 201232 kb
Host smart-4bcc5840-5aba-4b36-8f7e-6a50d3d09392
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233290142 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.4233290142
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.565032293
Short name T121
Test name
Test status
Simulation time 61713255 ps
CPU time 1.44 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:06 PM PDT 24
Peak memory 217408 kb
Host smart-e564bd5d-1cd0-4fde-beec-6e71f2a56552
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565032293 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.565032293
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3989913167
Short name T945
Test name
Test status
Simulation time 34003615 ps
CPU time 1.44 seconds
Started Jul 26 05:38:05 PM PDT 24
Finished Jul 26 05:38:07 PM PDT 24
Peak memory 201276 kb
Host smart-dcd588bd-f5a8-4987-96d2-55ed60f5fdd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989913167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.3989913167
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1273112018
Short name T105
Test name
Test status
Simulation time 139280303 ps
CPU time 2.92 seconds
Started Jul 26 05:38:06 PM PDT 24
Finished Jul 26 05:38:09 PM PDT 24
Peak memory 201176 kb
Host smart-074224e5-df31-4ba4-a59a-4a897c659daf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273112018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.1273112018
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1357217845
Short name T881
Test name
Test status
Simulation time 40216481 ps
CPU time 1.09 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:05 PM PDT 24
Peak memory 201084 kb
Host smart-d3f30e60-2544-4403-a691-c14418c18dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357217845 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1357217845
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3918780955
Short name T924
Test name
Test status
Simulation time 18780164 ps
CPU time 0.81 seconds
Started Jul 26 05:38:06 PM PDT 24
Finished Jul 26 05:38:07 PM PDT 24
Peak memory 200968 kb
Host smart-78dd94d6-1dc0-4c36-837d-4a90cf72edba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918780955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.3918780955
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3479409707
Short name T854
Test name
Test status
Simulation time 12110530 ps
CPU time 0.67 seconds
Started Jul 26 05:38:09 PM PDT 24
Finished Jul 26 05:38:10 PM PDT 24
Peak memory 199536 kb
Host smart-2a8b20cc-d067-41eb-aa77-8fb583eb9de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479409707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3479409707
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3376594818
Short name T85
Test name
Test status
Simulation time 27739814 ps
CPU time 1.03 seconds
Started Jul 26 05:38:07 PM PDT 24
Finished Jul 26 05:38:08 PM PDT 24
Peak memory 201096 kb
Host smart-01f556a7-e2b0-46c7-8a51-278d0c150f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376594818 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.3376594818
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.178792145
Short name T65
Test name
Test status
Simulation time 400363817 ps
CPU time 3.24 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:07 PM PDT 24
Peak memory 209704 kb
Host smart-5554c884-f3d9-4c94-a992-909d99b9007f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178792145 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.178792145
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1053747240
Short name T939
Test name
Test status
Simulation time 159638400 ps
CPU time 2.57 seconds
Started Jul 26 05:38:09 PM PDT 24
Finished Jul 26 05:38:12 PM PDT 24
Peak memory 201168 kb
Host smart-6631df5f-5976-470b-a2b8-6545ad0d522e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053747240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.1053747240
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3498285990
Short name T188
Test name
Test status
Simulation time 133995448 ps
CPU time 2.76 seconds
Started Jul 26 05:38:09 PM PDT 24
Finished Jul 26 05:38:12 PM PDT 24
Peak memory 201164 kb
Host smart-ec6a0d4c-7f7e-4fb0-a399-25f3a04fa557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498285990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3498285990
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2368788036
Short name T956
Test name
Test status
Simulation time 93715828 ps
CPU time 1.18 seconds
Started Jul 26 05:38:06 PM PDT 24
Finished Jul 26 05:38:07 PM PDT 24
Peak memory 201008 kb
Host smart-27b138b9-b62c-49ac-8621-65f80f588e04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368788036 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.2368788036
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3692699048
Short name T935
Test name
Test status
Simulation time 18343734 ps
CPU time 0.84 seconds
Started Jul 26 05:38:09 PM PDT 24
Finished Jul 26 05:38:10 PM PDT 24
Peak memory 200992 kb
Host smart-9862e889-ee75-447b-af38-500295a00b77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692699048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.3692699048
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.698157617
Short name T882
Test name
Test status
Simulation time 49701029 ps
CPU time 0.72 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:05 PM PDT 24
Peak memory 199592 kb
Host smart-4aeb09d4-127d-418e-a505-89694daa4066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698157617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_intr_test.698157617
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3116463924
Short name T931
Test name
Test status
Simulation time 30271878 ps
CPU time 0.93 seconds
Started Jul 26 05:38:03 PM PDT 24
Finished Jul 26 05:38:04 PM PDT 24
Peak memory 200992 kb
Host smart-e9b67d97-0734-47a7-baca-91cbcd16385e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116463924 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.3116463924
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1085497259
Short name T63
Test name
Test status
Simulation time 161713769 ps
CPU time 2.05 seconds
Started Jul 26 05:38:09 PM PDT 24
Finished Jul 26 05:38:11 PM PDT 24
Peak memory 201476 kb
Host smart-59a8b3c3-808e-4c15-9be3-33e76231a0c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085497259 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1085497259
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3244721868
Short name T904
Test name
Test status
Simulation time 162912227 ps
CPU time 3.03 seconds
Started Jul 26 05:38:08 PM PDT 24
Finished Jul 26 05:38:11 PM PDT 24
Peak memory 209652 kb
Host smart-44af0522-ae23-4002-a208-318f59c365ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244721868 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3244721868
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.644427780
Short name T943
Test name
Test status
Simulation time 38424775 ps
CPU time 2.29 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:07 PM PDT 24
Peak memory 201152 kb
Host smart-6b66ff6c-1458-4410-bcd9-2848ee7fc2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644427780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.644427780
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2602831407
Short name T101
Test name
Test status
Simulation time 296479341 ps
CPU time 2.57 seconds
Started Jul 26 05:38:06 PM PDT 24
Finished Jul 26 05:38:08 PM PDT 24
Peak memory 201228 kb
Host smart-7ab610bb-57f2-4ba1-adcc-aea6c96cd4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602831407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.2602831407
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1234074597
Short name T837
Test name
Test status
Simulation time 39994361 ps
CPU time 1.35 seconds
Started Jul 26 05:38:06 PM PDT 24
Finished Jul 26 05:38:08 PM PDT 24
Peak memory 201056 kb
Host smart-db05f990-4a75-4b29-89ab-9e238a3552bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234074597 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.1234074597
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.905220736
Short name T88
Test name
Test status
Simulation time 15808198 ps
CPU time 0.77 seconds
Started Jul 26 05:38:05 PM PDT 24
Finished Jul 26 05:38:06 PM PDT 24
Peak memory 200976 kb
Host smart-51c57ee7-13f8-484b-8fb1-156603649a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905220736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.c
lkmgr_csr_rw.905220736
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2095918591
Short name T831
Test name
Test status
Simulation time 16379545 ps
CPU time 0.73 seconds
Started Jul 26 05:38:07 PM PDT 24
Finished Jul 26 05:38:08 PM PDT 24
Peak memory 199672 kb
Host smart-ae6f9c17-0875-4d02-bc61-30308387a96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095918591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.2095918591
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1868310959
Short name T838
Test name
Test status
Simulation time 22033107 ps
CPU time 0.93 seconds
Started Jul 26 05:38:04 PM PDT 24
Finished Jul 26 05:38:05 PM PDT 24
Peak memory 200964 kb
Host smart-8fd369a6-b919-41e5-8349-ec77066abb1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868310959 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.1868310959
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.4109449939
Short name T120
Test name
Test status
Simulation time 358708066 ps
CPU time 2.33 seconds
Started Jul 26 05:38:07 PM PDT 24
Finished Jul 26 05:38:09 PM PDT 24
Peak memory 209936 kb
Host smart-26afd4a6-ca48-4f52-b764-93fe268b8883
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109449939 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.4109449939
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1347149282
Short name T130
Test name
Test status
Simulation time 428212715 ps
CPU time 3.29 seconds
Started Jul 26 05:38:07 PM PDT 24
Finished Jul 26 05:38:10 PM PDT 24
Peak memory 201644 kb
Host smart-c852a5bc-ee30-4c62-bd0a-37672f9ac619
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347149282 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.1347149282
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.442196485
Short name T866
Test name
Test status
Simulation time 571280642 ps
CPU time 4.08 seconds
Started Jul 26 05:38:08 PM PDT 24
Finished Jul 26 05:38:12 PM PDT 24
Peak memory 201196 kb
Host smart-170d2f7b-c80e-4318-9ced-7d9bbd54d396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442196485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm
gr_tl_errors.442196485
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2806575535
Short name T102
Test name
Test status
Simulation time 381222624 ps
CPU time 2.33 seconds
Started Jul 26 05:38:07 PM PDT 24
Finished Jul 26 05:38:09 PM PDT 24
Peak memory 201228 kb
Host smart-ae52b7a6-bd57-42b0-9829-1eadd0dd967d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806575535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2806575535
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.3171083502
Short name T741
Test name
Test status
Simulation time 47407156 ps
CPU time 0.85 seconds
Started Jul 26 06:31:58 PM PDT 24
Finished Jul 26 06:31:59 PM PDT 24
Peak memory 200440 kb
Host smart-b56a3122-f406-47a2-be74-51f4f3204320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171083502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.3171083502
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.905514404
Short name T92
Test name
Test status
Simulation time 15499413 ps
CPU time 0.75 seconds
Started Jul 26 06:31:50 PM PDT 24
Finished Jul 26 06:31:51 PM PDT 24
Peak memory 200392 kb
Host smart-fdfc8a2f-9240-4b1c-a30c-8daaa62144a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905514404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.905514404
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.1358888877
Short name T424
Test name
Test status
Simulation time 13727279 ps
CPU time 0.68 seconds
Started Jul 26 06:31:44 PM PDT 24
Finished Jul 26 06:31:45 PM PDT 24
Peak memory 200356 kb
Host smart-02bd0584-f1af-465b-9a71-ea2b66fef17e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358888877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1358888877
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.1033021536
Short name T637
Test name
Test status
Simulation time 30351157 ps
CPU time 0.95 seconds
Started Jul 26 06:31:49 PM PDT 24
Finished Jul 26 06:31:50 PM PDT 24
Peak memory 200472 kb
Host smart-80f8897b-420b-4a69-b150-790c0701f6b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033021536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.1033021536
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.2158839529
Short name T624
Test name
Test status
Simulation time 110571307 ps
CPU time 1.16 seconds
Started Jul 26 06:31:46 PM PDT 24
Finished Jul 26 06:31:47 PM PDT 24
Peak memory 200452 kb
Host smart-752c2ad8-d497-42fc-80fa-b0c43b815598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158839529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2158839529
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.1175696142
Short name T410
Test name
Test status
Simulation time 1883747648 ps
CPU time 10.42 seconds
Started Jul 26 06:31:46 PM PDT 24
Finished Jul 26 06:31:56 PM PDT 24
Peak memory 200696 kb
Host smart-55214d59-3eac-44d1-b660-f14ed678ce69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175696142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1175696142
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.1636463716
Short name T26
Test name
Test status
Simulation time 1217810308 ps
CPU time 8.86 seconds
Started Jul 26 06:31:44 PM PDT 24
Finished Jul 26 06:31:53 PM PDT 24
Peak memory 200536 kb
Host smart-2a07e5a3-dd17-445e-ae0d-2efa12d810e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636463716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.1636463716
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.1675076563
Short name T783
Test name
Test status
Simulation time 29310610 ps
CPU time 0.9 seconds
Started Jul 26 06:31:42 PM PDT 24
Finished Jul 26 06:31:43 PM PDT 24
Peak memory 200428 kb
Host smart-760b4ed9-5011-459f-96b8-a40ee2931881
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675076563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.1675076563
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1460999417
Short name T610
Test name
Test status
Simulation time 75756566 ps
CPU time 1.03 seconds
Started Jul 26 06:31:50 PM PDT 24
Finished Jul 26 06:31:51 PM PDT 24
Peak memory 200460 kb
Host smart-283f34a1-1d22-4ea7-b749-6c6bc32173e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460999417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.1460999417
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.879648107
Short name T441
Test name
Test status
Simulation time 26364576 ps
CPU time 0.92 seconds
Started Jul 26 06:31:43 PM PDT 24
Finished Jul 26 06:31:44 PM PDT 24
Peak memory 200468 kb
Host smart-4d4ae286-daeb-421b-ad22-c40b39b49364
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879648107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.879648107
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.2257297553
Short name T660
Test name
Test status
Simulation time 53400818 ps
CPU time 0.87 seconds
Started Jul 26 06:31:45 PM PDT 24
Finished Jul 26 06:31:46 PM PDT 24
Peak memory 200432 kb
Host smart-a139a36c-b9b7-4b96-8d12-2f308d13cc7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257297553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2257297553
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.604242120
Short name T45
Test name
Test status
Simulation time 150311900 ps
CPU time 1.93 seconds
Started Jul 26 06:31:49 PM PDT 24
Finished Jul 26 06:31:51 PM PDT 24
Peak memory 215920 kb
Host smart-52123eeb-b0dc-45b7-b50e-0549bb22cc38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604242120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_sec_cm.604242120
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.2697010549
Short name T715
Test name
Test status
Simulation time 63395720 ps
CPU time 0.96 seconds
Started Jul 26 06:31:43 PM PDT 24
Finished Jul 26 06:31:44 PM PDT 24
Peak memory 200468 kb
Host smart-2f28e255-c4c6-45f4-924d-0b8bb3cef7fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697010549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2697010549
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.4236532645
Short name T796
Test name
Test status
Simulation time 7340177807 ps
CPU time 40.91 seconds
Started Jul 26 06:31:58 PM PDT 24
Finished Jul 26 06:32:39 PM PDT 24
Peak memory 200796 kb
Host smart-62ab5175-90e2-4923-ae9a-659c349fe377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236532645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.4236532645
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.2304026709
Short name T73
Test name
Test status
Simulation time 36594523839 ps
CPU time 406.77 seconds
Started Jul 26 06:31:49 PM PDT 24
Finished Jul 26 06:38:36 PM PDT 24
Peak memory 217336 kb
Host smart-a80c91c8-eaa3-40b9-a151-4d089af5a220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2304026709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.2304026709
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_trans.18141210
Short name T651
Test name
Test status
Simulation time 29598206 ps
CPU time 0.93 seconds
Started Jul 26 06:31:45 PM PDT 24
Finished Jul 26 06:31:46 PM PDT 24
Peak memory 200444 kb
Host smart-3ee993c5-3585-4105-bc1a-62b310b5dff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18141210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.18141210
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.291442550
Short name T521
Test name
Test status
Simulation time 91856213 ps
CPU time 0.99 seconds
Started Jul 26 06:32:02 PM PDT 24
Finished Jul 26 06:32:03 PM PDT 24
Peak memory 200496 kb
Host smart-b30bfaa2-fbac-4cb3-b955-c4df0eae30b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291442550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_alert_test.291442550
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.4257286976
Short name T49
Test name
Test status
Simulation time 26516537 ps
CPU time 0.94 seconds
Started Jul 26 06:31:57 PM PDT 24
Finished Jul 26 06:31:58 PM PDT 24
Peak memory 200508 kb
Host smart-f0a888a0-6ce2-4ca5-930d-052f992fd79d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257286976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.4257286976
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.1070664199
Short name T556
Test name
Test status
Simulation time 24850852 ps
CPU time 0.74 seconds
Started Jul 26 06:31:58 PM PDT 24
Finished Jul 26 06:31:58 PM PDT 24
Peak memory 200340 kb
Host smart-0bb16e01-4a60-44a0-b6b6-96090e083c9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070664199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.1070664199
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.453307864
Short name T537
Test name
Test status
Simulation time 16242403 ps
CPU time 0.8 seconds
Started Jul 26 06:31:56 PM PDT 24
Finished Jul 26 06:31:57 PM PDT 24
Peak memory 200452 kb
Host smart-86e35aa1-928d-4975-8116-ce2e794c174c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453307864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.clkmgr_div_intersig_mubi.453307864
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.3843451241
Short name T351
Test name
Test status
Simulation time 15886794 ps
CPU time 0.79 seconds
Started Jul 26 06:31:56 PM PDT 24
Finished Jul 26 06:31:57 PM PDT 24
Peak memory 200436 kb
Host smart-55f37c10-c4db-47c6-8f28-867a46e9ec91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843451241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3843451241
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.1826360984
Short name T749
Test name
Test status
Simulation time 2362999124 ps
CPU time 18.32 seconds
Started Jul 26 06:31:54 PM PDT 24
Finished Jul 26 06:32:12 PM PDT 24
Peak memory 200756 kb
Host smart-60cfad28-a9c6-4151-a13e-73548ed75930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826360984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1826360984
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.1615394443
Short name T201
Test name
Test status
Simulation time 1220439438 ps
CPU time 6.57 seconds
Started Jul 26 06:31:56 PM PDT 24
Finished Jul 26 06:32:03 PM PDT 24
Peak memory 200588 kb
Host smart-93ece4de-1dcb-48f7-ae07-17b013c78a85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615394443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.1615394443
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.4124860100
Short name T710
Test name
Test status
Simulation time 72950167 ps
CPU time 0.91 seconds
Started Jul 26 06:31:55 PM PDT 24
Finished Jul 26 06:31:56 PM PDT 24
Peak memory 200460 kb
Host smart-c98b2a91-69a7-4041-adc2-f896e04ab4f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124860100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.4124860100
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.702504828
Short name T444
Test name
Test status
Simulation time 68294594 ps
CPU time 1.02 seconds
Started Jul 26 06:31:57 PM PDT 24
Finished Jul 26 06:31:58 PM PDT 24
Peak memory 200472 kb
Host smart-c56943f1-6277-4ad6-9cec-deb6ca87f83f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702504828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_clk_byp_req_intersig_mubi.702504828
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2437509508
Short name T470
Test name
Test status
Simulation time 18089032 ps
CPU time 0.78 seconds
Started Jul 26 06:31:56 PM PDT 24
Finished Jul 26 06:31:57 PM PDT 24
Peak memory 200468 kb
Host smart-2a523376-121a-4d7b-81a9-1a465786807e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437509508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.2437509508
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2793448450
Short name T668
Test name
Test status
Simulation time 22935559 ps
CPU time 0.77 seconds
Started Jul 26 06:31:59 PM PDT 24
Finished Jul 26 06:32:00 PM PDT 24
Peak memory 200428 kb
Host smart-047daea7-276f-448a-a5a3-52c6575f632d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793448450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2793448450
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.2574228205
Short name T566
Test name
Test status
Simulation time 371414348 ps
CPU time 2.62 seconds
Started Jul 26 06:31:56 PM PDT 24
Finished Jul 26 06:31:59 PM PDT 24
Peak memory 200640 kb
Host smart-6001d717-bd47-4c7f-84f8-630d735138c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574228205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2574228205
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.4150691664
Short name T46
Test name
Test status
Simulation time 148851325 ps
CPU time 2.06 seconds
Started Jul 26 06:31:55 PM PDT 24
Finished Jul 26 06:31:57 PM PDT 24
Peak memory 215920 kb
Host smart-1bc0d02d-3d9d-4e57-8176-c50308fb687e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150691664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.4150691664
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.1342970023
Short name T401
Test name
Test status
Simulation time 47813562 ps
CPU time 0.89 seconds
Started Jul 26 06:31:57 PM PDT 24
Finished Jul 26 06:31:58 PM PDT 24
Peak memory 200316 kb
Host smart-35f87b7a-ddb8-41d2-9555-db458b946227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342970023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1342970023
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.1271643961
Short name T221
Test name
Test status
Simulation time 5144072948 ps
CPU time 21.33 seconds
Started Jul 26 06:32:05 PM PDT 24
Finished Jul 26 06:32:26 PM PDT 24
Peak memory 200820 kb
Host smart-17eb4015-a3d3-4f5c-9133-6fb897d2be78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271643961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.1271643961
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.3604658567
Short name T79
Test name
Test status
Simulation time 180485657 ps
CPU time 1.38 seconds
Started Jul 26 06:31:56 PM PDT 24
Finished Jul 26 06:31:57 PM PDT 24
Peak memory 200412 kb
Host smart-ad70f093-5b45-47b3-a947-0df569e406a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604658567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3604658567
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.3490871788
Short name T727
Test name
Test status
Simulation time 35572172 ps
CPU time 0.81 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:01 PM PDT 24
Peak memory 200456 kb
Host smart-8ccfc625-7d8f-4650-bb5c-5c49b2eba620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490871788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.3490871788
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1302104989
Short name T95
Test name
Test status
Simulation time 21986313 ps
CPU time 0.91 seconds
Started Jul 26 06:33:01 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200492 kb
Host smart-2027d45d-a6ac-48b4-a1e1-b54d832ee8b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302104989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.1302104989
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.3813395102
Short name T426
Test name
Test status
Simulation time 15470586 ps
CPU time 0.8 seconds
Started Jul 26 06:33:01 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200264 kb
Host smart-17814a95-10df-4b5b-998b-24b96ef8ec89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813395102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3813395102
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.963544056
Short name T606
Test name
Test status
Simulation time 27686958 ps
CPU time 0.92 seconds
Started Jul 26 06:32:58 PM PDT 24
Finished Jul 26 06:32:59 PM PDT 24
Peak memory 200468 kb
Host smart-26bfd56a-caa1-482c-be50-20d199ea8184
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963544056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_div_intersig_mubi.963544056
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.859378570
Short name T583
Test name
Test status
Simulation time 147934565 ps
CPU time 1.23 seconds
Started Jul 26 06:32:55 PM PDT 24
Finished Jul 26 06:32:56 PM PDT 24
Peak memory 200464 kb
Host smart-18c7f76a-6e3a-4c77-9bb3-feb96c3c98ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859378570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.859378570
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.362359364
Short name T623
Test name
Test status
Simulation time 2477149490 ps
CPU time 18.65 seconds
Started Jul 26 06:32:53 PM PDT 24
Finished Jul 26 06:33:12 PM PDT 24
Peak memory 200756 kb
Host smart-5d5fbc71-b114-434e-a760-ab93152e760a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362359364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.362359364
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.1987407003
Short name T527
Test name
Test status
Simulation time 1469113851 ps
CPU time 8.25 seconds
Started Jul 26 06:32:55 PM PDT 24
Finished Jul 26 06:33:03 PM PDT 24
Peak memory 200560 kb
Host smart-0e4485ce-246c-4885-94bf-3f9cb8a2b2be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987407003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.1987407003
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.674198838
Short name T533
Test name
Test status
Simulation time 49725514 ps
CPU time 0.95 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:01 PM PDT 24
Peak memory 200424 kb
Host smart-e93c3d2e-a7fe-4b92-9f3a-27e57c3de449
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674198838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_idle_intersig_mubi.674198838
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3910300720
Short name T77
Test name
Test status
Simulation time 13192587 ps
CPU time 0.77 seconds
Started Jul 26 06:33:03 PM PDT 24
Finished Jul 26 06:33:03 PM PDT 24
Peak memory 200424 kb
Host smart-842158b0-16ae-4b08-85a8-3636fe345c81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910300720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.3910300720
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.977547336
Short name T530
Test name
Test status
Simulation time 24797368 ps
CPU time 0.93 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200468 kb
Host smart-1f5897e6-7822-4b91-969c-b1a747f02eea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977547336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.977547336
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.1451232493
Short name T577
Test name
Test status
Simulation time 19098729 ps
CPU time 0.77 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:01 PM PDT 24
Peak memory 200412 kb
Host smart-a5cfd8f5-0e45-45b9-bd23-873dfaad76b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451232493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.1451232493
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.2498445837
Short name T780
Test name
Test status
Simulation time 531855318 ps
CPU time 2.74 seconds
Started Jul 26 06:33:02 PM PDT 24
Finished Jul 26 06:33:04 PM PDT 24
Peak memory 200400 kb
Host smart-6955ca55-e558-4741-be12-d5897687aadb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498445837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2498445837
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.1542650935
Short name T216
Test name
Test status
Simulation time 115053941 ps
CPU time 1.13 seconds
Started Jul 26 06:32:55 PM PDT 24
Finished Jul 26 06:32:56 PM PDT 24
Peak memory 200424 kb
Host smart-9aa54b2c-5b90-4052-a457-5c3e8ccd2b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542650935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1542650935
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.3574843123
Short name T459
Test name
Test status
Simulation time 74843844 ps
CPU time 1.53 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200536 kb
Host smart-099fcba2-d3d2-4c4d-a465-6bde4f944633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574843123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.3574843123
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.1906805928
Short name T434
Test name
Test status
Simulation time 20020007 ps
CPU time 0.88 seconds
Started Jul 26 06:33:04 PM PDT 24
Finished Jul 26 06:33:05 PM PDT 24
Peak memory 200444 kb
Host smart-6f463604-258d-4b03-bb3a-d1ae6648b0da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906805928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.1906805928
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.3496269586
Short name T691
Test name
Test status
Simulation time 28026354 ps
CPU time 0.82 seconds
Started Jul 26 06:33:09 PM PDT 24
Finished Jul 26 06:33:10 PM PDT 24
Peak memory 200452 kb
Host smart-04252bb3-4342-402d-9dcb-447017b05348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496269586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.3496269586
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1891874242
Short name T99
Test name
Test status
Simulation time 83751567 ps
CPU time 1.12 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:01 PM PDT 24
Peak memory 200476 kb
Host smart-cf3c2ce0-86af-4c8e-83db-872de3806243
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891874242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1891874242
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.4277438766
Short name T703
Test name
Test status
Simulation time 12483732 ps
CPU time 0.7 seconds
Started Jul 26 06:33:03 PM PDT 24
Finished Jul 26 06:33:03 PM PDT 24
Peak memory 199936 kb
Host smart-fa7fb0b4-3f98-4026-9d04-cdd500a15b37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277438766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.4277438766
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.19094655
Short name T166
Test name
Test status
Simulation time 56553106 ps
CPU time 1.03 seconds
Started Jul 26 06:33:01 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200448 kb
Host smart-edb7c21a-5eba-4d34-a22e-718052bad919
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19094655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.clkmgr_div_intersig_mubi.19094655
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.729453049
Short name T477
Test name
Test status
Simulation time 57221576 ps
CPU time 0.95 seconds
Started Jul 26 06:33:01 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200500 kb
Host smart-ef006b50-6e82-4431-8069-8b305c855f5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729453049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.729453049
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.1072120841
Short name T22
Test name
Test status
Simulation time 2482510994 ps
CPU time 19.38 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:19 PM PDT 24
Peak memory 200804 kb
Host smart-f2d1f51e-1a99-4138-9256-bab60b1ada85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072120841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1072120841
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.3624029985
Short name T52
Test name
Test status
Simulation time 645114725 ps
CPU time 3.18 seconds
Started Jul 26 06:33:01 PM PDT 24
Finished Jul 26 06:33:04 PM PDT 24
Peak memory 200540 kb
Host smart-5bb073e2-e6af-4e8a-971f-480d2ed648ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624029985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.3624029985
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2275810988
Short name T492
Test name
Test status
Simulation time 138756795 ps
CPU time 1.38 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200372 kb
Host smart-c46917a7-50ad-4c7b-8a32-632738425282
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275810988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2275810988
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1698865686
Short name T276
Test name
Test status
Simulation time 43824480 ps
CPU time 0.84 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:01 PM PDT 24
Peak memory 200472 kb
Host smart-d48bfc80-7c0e-4ae3-a886-561af4f6fd3c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698865686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1698865686
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.3544392671
Short name T295
Test name
Test status
Simulation time 367117717 ps
CPU time 1.92 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200480 kb
Host smart-1b836d9c-94b2-4baf-a445-ea3f493325b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544392671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.3544392671
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.2496621427
Short name T41
Test name
Test status
Simulation time 15731456 ps
CPU time 0.78 seconds
Started Jul 26 06:33:04 PM PDT 24
Finished Jul 26 06:33:05 PM PDT 24
Peak memory 200440 kb
Host smart-c52ab090-a2c3-444c-9bda-9f1c4fa251af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496621427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2496621427
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.696700929
Short name T454
Test name
Test status
Simulation time 138081521 ps
CPU time 1.15 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 200428 kb
Host smart-f21840af-d02e-4fd4-95cf-4dbf4c8056fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696700929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.696700929
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.1905837805
Short name T453
Test name
Test status
Simulation time 19917176 ps
CPU time 0.85 seconds
Started Jul 26 06:33:00 PM PDT 24
Finished Jul 26 06:33:01 PM PDT 24
Peak memory 200380 kb
Host smart-d6d87ca3-dda9-4caa-baea-9945b4f5d3a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905837805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1905837805
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.3024949663
Short name T254
Test name
Test status
Simulation time 4935994350 ps
CPU time 26.7 seconds
Started Jul 26 06:33:06 PM PDT 24
Finished Jul 26 06:33:32 PM PDT 24
Peak memory 200856 kb
Host smart-d3558d98-b6a3-420a-addf-842b034f854e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024949663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.3024949663
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.1830577674
Short name T71
Test name
Test status
Simulation time 271664404064 ps
CPU time 1035.86 seconds
Started Jul 26 06:33:08 PM PDT 24
Finished Jul 26 06:50:24 PM PDT 24
Peak memory 217256 kb
Host smart-281ab3fc-1631-4988-8b4f-881e73f114e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1830577674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.1830577674
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_trans.906852748
Short name T289
Test name
Test status
Simulation time 41476092 ps
CPU time 0.91 seconds
Started Jul 26 06:33:03 PM PDT 24
Finished Jul 26 06:33:04 PM PDT 24
Peak memory 200732 kb
Host smart-baf76eab-753f-469c-a8ea-cadbf4fdc7c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906852748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.906852748
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.3498162702
Short name T396
Test name
Test status
Simulation time 18197927 ps
CPU time 0.8 seconds
Started Jul 26 06:33:08 PM PDT 24
Finished Jul 26 06:33:09 PM PDT 24
Peak memory 200476 kb
Host smart-eb85e392-5495-4f35-b601-095e22e620f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498162702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.3498162702
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3740671193
Short name T307
Test name
Test status
Simulation time 16469357 ps
CPU time 0.8 seconds
Started Jul 26 06:33:05 PM PDT 24
Finished Jul 26 06:33:06 PM PDT 24
Peak memory 200492 kb
Host smart-f27204cd-d86d-4520-b0d8-6d3c7730e1cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740671193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3740671193
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.588315517
Short name T595
Test name
Test status
Simulation time 32489271 ps
CPU time 0.78 seconds
Started Jul 26 06:33:07 PM PDT 24
Finished Jul 26 06:33:08 PM PDT 24
Peak memory 200380 kb
Host smart-705ecb90-39f9-4b02-a6f2-a57161bb5fee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588315517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.588315517
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.937272091
Short name T514
Test name
Test status
Simulation time 84857255 ps
CPU time 1.05 seconds
Started Jul 26 06:33:08 PM PDT 24
Finished Jul 26 06:33:10 PM PDT 24
Peak memory 200444 kb
Host smart-d1624836-6af8-450a-8c36-9ccb63fda413
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937272091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.clkmgr_div_intersig_mubi.937272091
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.166210501
Short name T416
Test name
Test status
Simulation time 210844105 ps
CPU time 1.4 seconds
Started Jul 26 06:33:09 PM PDT 24
Finished Jul 26 06:33:11 PM PDT 24
Peak memory 200476 kb
Host smart-46db2b4e-3fee-4729-b674-1296035b8ac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166210501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.166210501
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.2073906098
Short name T301
Test name
Test status
Simulation time 681894621 ps
CPU time 6.06 seconds
Started Jul 26 06:33:07 PM PDT 24
Finished Jul 26 06:33:13 PM PDT 24
Peak memory 200544 kb
Host smart-933a9126-4ef6-4ace-bbd4-524657e69877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073906098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.2073906098
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.4226137162
Short name T236
Test name
Test status
Simulation time 407499784 ps
CPU time 2.13 seconds
Started Jul 26 06:33:05 PM PDT 24
Finished Jul 26 06:33:07 PM PDT 24
Peak memory 200612 kb
Host smart-e6d865a6-7374-4990-b71a-ac37753d7ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226137162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.4226137162
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2164013664
Short name T814
Test name
Test status
Simulation time 206131843 ps
CPU time 1.36 seconds
Started Jul 26 06:33:07 PM PDT 24
Finished Jul 26 06:33:09 PM PDT 24
Peak memory 200432 kb
Host smart-b403e616-20eb-415d-b48a-fb5158d6b01c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164013664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.2164013664
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.863890517
Short name T149
Test name
Test status
Simulation time 88963965 ps
CPU time 1.09 seconds
Started Jul 26 06:33:09 PM PDT 24
Finished Jul 26 06:33:10 PM PDT 24
Peak memory 200472 kb
Host smart-d88afad5-4182-45b6-914b-0e638c06291f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863890517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.863890517
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3259276774
Short name T167
Test name
Test status
Simulation time 96434788 ps
CPU time 1.14 seconds
Started Jul 26 06:33:07 PM PDT 24
Finished Jul 26 06:33:08 PM PDT 24
Peak memory 200460 kb
Host smart-7347fde2-62ee-4aae-9b02-e9cb935bbac4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259276774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.3259276774
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.128431081
Short name T818
Test name
Test status
Simulation time 12473604 ps
CPU time 0.75 seconds
Started Jul 26 06:33:06 PM PDT 24
Finished Jul 26 06:33:07 PM PDT 24
Peak memory 200388 kb
Host smart-f10ff664-f318-49df-96cb-5352d78dad83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128431081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.128431081
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.3259919762
Short name T158
Test name
Test status
Simulation time 199578906 ps
CPU time 1.49 seconds
Started Jul 26 06:33:09 PM PDT 24
Finished Jul 26 06:33:11 PM PDT 24
Peak memory 200396 kb
Host smart-359a6dfd-5668-45e8-965a-c40002c35c8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259919762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3259919762
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.2830892930
Short name T233
Test name
Test status
Simulation time 21025706 ps
CPU time 0.88 seconds
Started Jul 26 06:33:06 PM PDT 24
Finished Jul 26 06:33:07 PM PDT 24
Peak memory 200384 kb
Host smart-c768f38d-379d-4acd-b42e-fd438fdab54a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830892930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2830892930
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.3588096191
Short name T140
Test name
Test status
Simulation time 2424664994 ps
CPU time 14.7 seconds
Started Jul 26 06:33:08 PM PDT 24
Finished Jul 26 06:33:22 PM PDT 24
Peak memory 200840 kb
Host smart-7489e476-077a-4ba5-9c4e-e9f37ff39a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588096191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.3588096191
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.2529924915
Short name T384
Test name
Test status
Simulation time 25839754 ps
CPU time 0.94 seconds
Started Jul 26 06:33:08 PM PDT 24
Finished Jul 26 06:33:09 PM PDT 24
Peak memory 200468 kb
Host smart-fb429706-d6be-4f0f-9b6a-d60ce63c3b63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529924915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2529924915
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.1449120514
Short name T747
Test name
Test status
Simulation time 106779695 ps
CPU time 1.02 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:15 PM PDT 24
Peak memory 200384 kb
Host smart-5d5cf63d-177f-4afd-99f5-b6670d134c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449120514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.1449120514
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.929162905
Short name T257
Test name
Test status
Simulation time 22243294 ps
CPU time 0.76 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:15 PM PDT 24
Peak memory 200420 kb
Host smart-73ac83de-4ed8-4b68-8e3a-e270d3f8a7e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929162905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.929162905
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.71509631
Short name T478
Test name
Test status
Simulation time 15174269 ps
CPU time 0.74 seconds
Started Jul 26 06:33:08 PM PDT 24
Finished Jul 26 06:33:09 PM PDT 24
Peak memory 200364 kb
Host smart-01925390-74c5-4ede-b03a-79776fec9d25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71509631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.71509631
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.565027008
Short name T417
Test name
Test status
Simulation time 118047219 ps
CPU time 1.13 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:15 PM PDT 24
Peak memory 200468 kb
Host smart-63cadce1-1e79-423c-862a-4493732ed5cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565027008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.clkmgr_div_intersig_mubi.565027008
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.1565659078
Short name T294
Test name
Test status
Simulation time 63373435 ps
CPU time 0.95 seconds
Started Jul 26 06:33:06 PM PDT 24
Finished Jul 26 06:33:07 PM PDT 24
Peak memory 200436 kb
Host smart-4858894a-835c-4858-9233-4321f5553d93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565659078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.1565659078
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.4273086993
Short name T449
Test name
Test status
Simulation time 1039017421 ps
CPU time 8.47 seconds
Started Jul 26 06:33:10 PM PDT 24
Finished Jul 26 06:33:19 PM PDT 24
Peak memory 200544 kb
Host smart-77dc1198-da56-4d26-b218-a3d3412761f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273086993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.4273086993
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.2262626231
Short name T174
Test name
Test status
Simulation time 2319822306 ps
CPU time 9.38 seconds
Started Jul 26 06:33:06 PM PDT 24
Finished Jul 26 06:33:16 PM PDT 24
Peak memory 200836 kb
Host smart-e0349e1e-c9b2-4018-a9a2-204215dc417e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262626231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.2262626231
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.1419035731
Short name T497
Test name
Test status
Simulation time 91036922 ps
CPU time 1.04 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:15 PM PDT 24
Peak memory 200500 kb
Host smart-463b1790-1588-48eb-aed0-c86a6a951715
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419035731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.1419035731
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1301119986
Short name T212
Test name
Test status
Simulation time 23792193 ps
CPU time 0.79 seconds
Started Jul 26 06:33:15 PM PDT 24
Finished Jul 26 06:33:16 PM PDT 24
Peak memory 200476 kb
Host smart-6ffddc7f-028f-44a3-8068-658d64003ef3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301119986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.1301119986
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.809850868
Short name T730
Test name
Test status
Simulation time 85078429 ps
CPU time 1.1 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:15 PM PDT 24
Peak memory 200484 kb
Host smart-9c14afcd-128e-465c-af61-5e0c83208148
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809850868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_ctrl_intersig_mubi.809850868
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.1582387913
Short name T235
Test name
Test status
Simulation time 19802695 ps
CPU time 0.74 seconds
Started Jul 26 06:33:09 PM PDT 24
Finished Jul 26 06:33:10 PM PDT 24
Peak memory 200424 kb
Host smart-ed74453f-e5d3-4164-b8e2-d351ce3c189f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582387913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1582387913
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.2698812740
Short name T711
Test name
Test status
Simulation time 474817099 ps
CPU time 2.49 seconds
Started Jul 26 06:33:13 PM PDT 24
Finished Jul 26 06:33:16 PM PDT 24
Peak memory 200384 kb
Host smart-eac4fb4e-03e7-45cd-96e6-8a8c3fe688c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698812740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.2698812740
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1970384574
Short name T142
Test name
Test status
Simulation time 37833831 ps
CPU time 0.91 seconds
Started Jul 26 06:33:06 PM PDT 24
Finished Jul 26 06:33:07 PM PDT 24
Peak memory 200412 kb
Host smart-6cb3b5bb-56cc-4b5d-91a1-76aaadc33d4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970384574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1970384574
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.460817437
Short name T594
Test name
Test status
Simulation time 2482541282 ps
CPU time 9.8 seconds
Started Jul 26 06:33:13 PM PDT 24
Finished Jul 26 06:33:23 PM PDT 24
Peak memory 200820 kb
Host smart-c2ac4d61-3c2d-46a9-9720-535d8828817a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460817437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.460817437
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1746435572
Short name T169
Test name
Test status
Simulation time 40996372920 ps
CPU time 230.82 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:37:05 PM PDT 24
Peak memory 215612 kb
Host smart-4e3bb550-28ff-4d0d-8471-702626078b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1746435572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1746435572
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_trans.3021195942
Short name T293
Test name
Test status
Simulation time 29352988 ps
CPU time 0.88 seconds
Started Jul 26 06:33:08 PM PDT 24
Finished Jul 26 06:33:09 PM PDT 24
Peak memory 200456 kb
Host smart-865896c2-8e5f-4bc3-92bd-897e8d4c1132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021195942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3021195942
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.1247803253
Short name T524
Test name
Test status
Simulation time 16709484 ps
CPU time 0.73 seconds
Started Jul 26 06:33:20 PM PDT 24
Finished Jul 26 06:33:21 PM PDT 24
Peak memory 200652 kb
Host smart-107d5771-162a-4c77-83f9-7dcb6025d378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247803253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.1247803253
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2396791570
Short name T246
Test name
Test status
Simulation time 34468562 ps
CPU time 0.79 seconds
Started Jul 26 06:33:20 PM PDT 24
Finished Jul 26 06:33:21 PM PDT 24
Peak memory 200528 kb
Host smart-216cf0a1-c7f6-4456-82c5-d9a06b65f386
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396791570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.2396791570
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.1961223370
Short name T183
Test name
Test status
Simulation time 12333463 ps
CPU time 0.69 seconds
Started Jul 26 06:33:13 PM PDT 24
Finished Jul 26 06:33:13 PM PDT 24
Peak memory 199668 kb
Host smart-ab6ecac5-3f4c-4f5a-8f9b-47cbc8599f4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961223370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1961223370
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.2131303406
Short name T507
Test name
Test status
Simulation time 18346415 ps
CPU time 0.82 seconds
Started Jul 26 06:33:18 PM PDT 24
Finished Jul 26 06:33:19 PM PDT 24
Peak memory 200460 kb
Host smart-fdd340b5-285b-4571-aeda-90e8ad9bf815
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131303406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.2131303406
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.26519948
Short name T198
Test name
Test status
Simulation time 65018397 ps
CPU time 0.98 seconds
Started Jul 26 06:33:13 PM PDT 24
Finished Jul 26 06:33:14 PM PDT 24
Peak memory 200412 kb
Host smart-1057fe73-0422-403a-82c4-723a790a2f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26519948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.26519948
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.457893957
Short name T2
Test name
Test status
Simulation time 572578826 ps
CPU time 3.26 seconds
Started Jul 26 06:33:13 PM PDT 24
Finished Jul 26 06:33:16 PM PDT 24
Peak memory 200564 kb
Host smart-8947d011-7f20-4561-aba6-d92df9a23e45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457893957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.457893957
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.1069557828
Short name T550
Test name
Test status
Simulation time 503069503 ps
CPU time 2.97 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:17 PM PDT 24
Peak memory 200588 kb
Host smart-8dce85a1-8ea3-4a11-bb6b-9657dafcd9cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069557828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.1069557828
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2322665888
Short name T466
Test name
Test status
Simulation time 135812796 ps
CPU time 1.43 seconds
Started Jul 26 06:33:22 PM PDT 24
Finished Jul 26 06:33:23 PM PDT 24
Peak memory 200416 kb
Host smart-f95baa93-b368-4029-944e-b8a7a7941a32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322665888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.2322665888
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1507907886
Short name T748
Test name
Test status
Simulation time 22872821 ps
CPU time 0.84 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200448 kb
Host smart-fecdf0f6-66f7-4fc4-ad4e-fb6cd3aaf0e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507907886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.1507907886
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3710442750
Short name T563
Test name
Test status
Simulation time 75911178 ps
CPU time 1.06 seconds
Started Jul 26 06:33:21 PM PDT 24
Finished Jul 26 06:33:22 PM PDT 24
Peak memory 200372 kb
Host smart-87745b8c-4101-4696-8cc3-53c1a596ddf2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710442750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3710442750
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.3678789253
Short name T185
Test name
Test status
Simulation time 13732020 ps
CPU time 0.74 seconds
Started Jul 26 06:33:12 PM PDT 24
Finished Jul 26 06:33:13 PM PDT 24
Peak memory 200420 kb
Host smart-ac686e62-5de7-431c-a0be-57966464beb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678789253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3678789253
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.1078490269
Short name T402
Test name
Test status
Simulation time 303848117 ps
CPU time 2.22 seconds
Started Jul 26 06:33:20 PM PDT 24
Finished Jul 26 06:33:22 PM PDT 24
Peak memory 200400 kb
Host smart-edf53721-cfeb-44c9-ac3d-8934939c364f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078490269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1078490269
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.3746334750
Short name T53
Test name
Test status
Simulation time 15605744 ps
CPU time 0.84 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:15 PM PDT 24
Peak memory 200400 kb
Host smart-9872c69d-f7c1-4acd-adba-4bbe57ff1cb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746334750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.3746334750
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.3126530636
Short name T766
Test name
Test status
Simulation time 3641197090 ps
CPU time 16.13 seconds
Started Jul 26 06:33:20 PM PDT 24
Finished Jul 26 06:33:36 PM PDT 24
Peak memory 200816 kb
Host smart-2c4c336c-9871-4da5-b2cf-bfa81ff8513c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126530636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.3126530636
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2177317700
Short name T418
Test name
Test status
Simulation time 105032589 ps
CPU time 1.16 seconds
Started Jul 26 06:33:14 PM PDT 24
Finished Jul 26 06:33:15 PM PDT 24
Peak memory 200480 kb
Host smart-79ae6942-7bb2-445b-9339-14c0b4ce23b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177317700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2177317700
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.4168554173
Short name T313
Test name
Test status
Simulation time 29390350 ps
CPU time 0.74 seconds
Started Jul 26 06:33:21 PM PDT 24
Finished Jul 26 06:33:22 PM PDT 24
Peak memory 199744 kb
Host smart-323a4f7f-8ed7-42e6-a798-dc165c8c47f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168554173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.4168554173
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1469042988
Short name T568
Test name
Test status
Simulation time 14335084 ps
CPU time 0.78 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200432 kb
Host smart-a9a7be3d-8a64-4604-8c65-6f32360ca5d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469042988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.1469042988
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.939046103
Short name T792
Test name
Test status
Simulation time 31158827 ps
CPU time 0.72 seconds
Started Jul 26 06:33:19 PM PDT 24
Finished Jul 26 06:33:20 PM PDT 24
Peak memory 199628 kb
Host smart-b99c7eae-9221-4490-b3f5-1a5c2fd454bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939046103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.939046103
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.226237344
Short name T728
Test name
Test status
Simulation time 65484911 ps
CPU time 1.03 seconds
Started Jul 26 06:33:22 PM PDT 24
Finished Jul 26 06:33:23 PM PDT 24
Peak memory 200424 kb
Host smart-151aa0e9-0d0a-41ef-a22d-6995bacb9192
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226237344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.226237344
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.1671511637
Short name T560
Test name
Test status
Simulation time 19485728 ps
CPU time 0.7 seconds
Started Jul 26 06:33:20 PM PDT 24
Finished Jul 26 06:33:21 PM PDT 24
Peak memory 200668 kb
Host smart-8e674479-a4b2-45cf-9890-21de9d2694a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671511637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.1671511637
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.1477611382
Short name T352
Test name
Test status
Simulation time 1998486991 ps
CPU time 12.72 seconds
Started Jul 26 06:33:19 PM PDT 24
Finished Jul 26 06:33:32 PM PDT 24
Peak memory 200704 kb
Host smart-ff5ca4b5-4e49-40d0-9c12-71632ea0ed05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477611382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1477611382
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.3618090460
Short name T820
Test name
Test status
Simulation time 1597055497 ps
CPU time 6.93 seconds
Started Jul 26 06:33:18 PM PDT 24
Finished Jul 26 06:33:25 PM PDT 24
Peak memory 200572 kb
Host smart-585574dc-d363-4c2e-b577-ad8e7d57a420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618090460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.3618090460
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1097688706
Short name T626
Test name
Test status
Simulation time 19791101 ps
CPU time 0.82 seconds
Started Jul 26 06:33:22 PM PDT 24
Finished Jul 26 06:33:23 PM PDT 24
Peak memory 200476 kb
Host smart-828d24e5-cb0b-4485-af8d-9a1b77569915
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097688706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.1097688706
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2285450879
Short name T620
Test name
Test status
Simulation time 21770729 ps
CPU time 0.92 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200440 kb
Host smart-aa881b17-ea1d-4c0c-8019-e1c991484064
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285450879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2285450879
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.512824695
Short name T736
Test name
Test status
Simulation time 54560450 ps
CPU time 0.85 seconds
Started Jul 26 06:33:19 PM PDT 24
Finished Jul 26 06:33:20 PM PDT 24
Peak memory 200324 kb
Host smart-246bc42a-e92d-4e8a-9df0-18e01dafa447
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512824695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.clkmgr_lc_ctrl_intersig_mubi.512824695
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.3235175763
Short name T347
Test name
Test status
Simulation time 17817204 ps
CPU time 0.8 seconds
Started Jul 26 06:33:20 PM PDT 24
Finished Jul 26 06:33:21 PM PDT 24
Peak memory 200380 kb
Host smart-82444e56-3844-4f36-9155-26cd20e07d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235175763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.3235175763
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.699134360
Short name T422
Test name
Test status
Simulation time 1193163170 ps
CPU time 4.65 seconds
Started Jul 26 06:33:19 PM PDT 24
Finished Jul 26 06:33:24 PM PDT 24
Peak memory 200660 kb
Host smart-ac526f01-46c1-4316-8afb-45f98f86bfd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699134360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.699134360
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.1689538116
Short name T740
Test name
Test status
Simulation time 17466786 ps
CPU time 0.81 seconds
Started Jul 26 06:33:21 PM PDT 24
Finished Jul 26 06:33:22 PM PDT 24
Peak memory 200428 kb
Host smart-8433e24b-6709-4ec5-8bcb-14624d60839f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689538116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1689538116
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.4025261891
Short name T499
Test name
Test status
Simulation time 3543555234 ps
CPU time 17.37 seconds
Started Jul 26 06:33:18 PM PDT 24
Finished Jul 26 06:33:36 PM PDT 24
Peak memory 200840 kb
Host smart-d445eacd-961c-4171-9ea7-0e72e847c1e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025261891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.4025261891
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1659222576
Short name T69
Test name
Test status
Simulation time 159232682897 ps
CPU time 1003.8 seconds
Started Jul 26 06:33:19 PM PDT 24
Finished Jul 26 06:50:03 PM PDT 24
Peak memory 209180 kb
Host smart-14bd3e6e-9532-49a1-9a10-ffb53a89f30e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1659222576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1659222576
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.2364825190
Short name T479
Test name
Test status
Simulation time 49155429 ps
CPU time 0.9 seconds
Started Jul 26 06:33:21 PM PDT 24
Finished Jul 26 06:33:22 PM PDT 24
Peak memory 199776 kb
Host smart-27cc5d97-c89a-48c2-955b-6ed0da8563d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364825190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2364825190
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.1036436789
Short name T381
Test name
Test status
Simulation time 40508318 ps
CPU time 0.84 seconds
Started Jul 26 06:33:25 PM PDT 24
Finished Jul 26 06:33:26 PM PDT 24
Peak memory 200488 kb
Host smart-06bfe921-9af8-471b-841f-8b6806234d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036436789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.1036436789
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.691365359
Short name T298
Test name
Test status
Simulation time 73250806 ps
CPU time 0.85 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 199652 kb
Host smart-c8265280-4b7b-476c-bd26-5a9dea55cff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691365359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.691365359
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3495232628
Short name T525
Test name
Test status
Simulation time 49008592 ps
CPU time 0.87 seconds
Started Jul 26 06:33:27 PM PDT 24
Finished Jul 26 06:33:28 PM PDT 24
Peak memory 200324 kb
Host smart-84fd3b3c-a976-411f-b5d3-c328feebe746
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495232628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.3495232628
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.1440856680
Short name T773
Test name
Test status
Simulation time 48180300 ps
CPU time 0.93 seconds
Started Jul 26 06:33:22 PM PDT 24
Finished Jul 26 06:33:23 PM PDT 24
Peak memory 200472 kb
Host smart-20fa893e-81d3-4aba-abc3-d5319bb66fb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440856680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.1440856680
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.1434140985
Short name T350
Test name
Test status
Simulation time 1287110849 ps
CPU time 7.31 seconds
Started Jul 26 06:33:17 PM PDT 24
Finished Jul 26 06:33:24 PM PDT 24
Peak memory 200536 kb
Host smart-9188a013-745d-4586-b417-ef2621499402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434140985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1434140985
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.3700807097
Short name T493
Test name
Test status
Simulation time 974638427 ps
CPU time 7.38 seconds
Started Jul 26 06:33:20 PM PDT 24
Finished Jul 26 06:33:28 PM PDT 24
Peak memory 200596 kb
Host smart-e94f1f07-2df2-42c4-a2fb-229c710f21ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700807097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.3700807097
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.1169013629
Short name T816
Test name
Test status
Simulation time 33416828 ps
CPU time 1 seconds
Started Jul 26 06:33:27 PM PDT 24
Finished Jul 26 06:33:28 PM PDT 24
Peak memory 200464 kb
Host smart-a09507f8-c0fb-4eff-aa5f-437c964a31fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169013629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.1169013629
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2249016418
Short name T584
Test name
Test status
Simulation time 22254767 ps
CPU time 0.87 seconds
Started Jul 26 06:33:27 PM PDT 24
Finished Jul 26 06:33:28 PM PDT 24
Peak memory 200460 kb
Host smart-654d0414-6c04-4220-860b-9439b2503a95
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249016418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.2249016418
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.565919719
Short name T176
Test name
Test status
Simulation time 136663547 ps
CPU time 1.23 seconds
Started Jul 26 06:33:27 PM PDT 24
Finished Jul 26 06:33:28 PM PDT 24
Peak memory 200484 kb
Host smart-e43ab033-6a17-451b-944a-407f94ca0499
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565919719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_ctrl_intersig_mubi.565919719
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.237398738
Short name T785
Test name
Test status
Simulation time 28415086 ps
CPU time 0.75 seconds
Started Jul 26 06:33:18 PM PDT 24
Finished Jul 26 06:33:19 PM PDT 24
Peak memory 200392 kb
Host smart-bcd99a61-9d09-4e2e-9ae6-9b6cd634233e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237398738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.237398738
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.3745973847
Short name T155
Test name
Test status
Simulation time 1071470843 ps
CPU time 6.26 seconds
Started Jul 26 06:33:28 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 200508 kb
Host smart-0693d71a-c951-4c7c-afc7-eb49ab1545fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745973847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3745973847
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.353731919
Short name T612
Test name
Test status
Simulation time 22207605 ps
CPU time 0.89 seconds
Started Jul 26 06:33:18 PM PDT 24
Finished Jul 26 06:33:19 PM PDT 24
Peak memory 200396 kb
Host smart-a547b7cf-05a5-4ab8-8327-b6bcee841c10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353731919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.353731919
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.3013602460
Short name T389
Test name
Test status
Simulation time 7041944883 ps
CPU time 38.46 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:34:05 PM PDT 24
Peak memory 200856 kb
Host smart-995f274a-4473-41bb-9aec-5410bf585bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013602460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.3013602460
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.1997382213
Short name T498
Test name
Test status
Simulation time 86727972 ps
CPU time 1.1 seconds
Started Jul 26 06:33:28 PM PDT 24
Finished Jul 26 06:33:29 PM PDT 24
Peak memory 200532 kb
Host smart-1a06ac8a-76d5-4a02-a81f-ee23d806fdfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997382213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1997382213
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.1778018184
Short name T765
Test name
Test status
Simulation time 21504959 ps
CPU time 0.77 seconds
Started Jul 26 06:33:34 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 200476 kb
Host smart-3c3d0911-0a02-473e-8f12-5b494210d333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778018184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.1778018184
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2639053392
Short name T768
Test name
Test status
Simulation time 28740270 ps
CPU time 0.87 seconds
Started Jul 26 06:33:37 PM PDT 24
Finished Jul 26 06:33:38 PM PDT 24
Peak memory 200444 kb
Host smart-5a5caa51-96a7-494f-911f-14d9aaa1e124
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639053392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.2639053392
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1743962229
Short name T367
Test name
Test status
Simulation time 13189832 ps
CPU time 0.72 seconds
Started Jul 26 06:33:27 PM PDT 24
Finished Jul 26 06:33:28 PM PDT 24
Peak memory 199672 kb
Host smart-fcab25d3-50c2-479a-973d-1cf0cfad3936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743962229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1743962229
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.1356582382
Short name T322
Test name
Test status
Simulation time 105327888 ps
CPU time 1.19 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 200420 kb
Host smart-a4571929-ef23-45b5-b295-13182b6e0438
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356582382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.1356582382
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.787728866
Short name T247
Test name
Test status
Simulation time 50372763 ps
CPU time 0.86 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200480 kb
Host smart-d8806f56-4704-412f-903d-99bc2c6444c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787728866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.787728866
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.736788450
Short name T621
Test name
Test status
Simulation time 438858631 ps
CPU time 2.21 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:29 PM PDT 24
Peak memory 200512 kb
Host smart-a0082af4-6316-4daa-8586-67af99854a03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736788450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.736788450
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.2190577003
Short name T687
Test name
Test status
Simulation time 1102200244 ps
CPU time 6.18 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:32 PM PDT 24
Peak memory 200568 kb
Host smart-a9dc281a-2f2a-41eb-942e-f3bac76aa8d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190577003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.2190577003
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2715127482
Short name T162
Test name
Test status
Simulation time 63559258 ps
CPU time 1.06 seconds
Started Jul 26 06:33:27 PM PDT 24
Finished Jul 26 06:33:29 PM PDT 24
Peak memory 200420 kb
Host smart-85373eff-9984-4d4a-bb6c-51f4a7ff5e43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715127482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2715127482
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.861503362
Short name T764
Test name
Test status
Simulation time 174251266 ps
CPU time 1.25 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200480 kb
Host smart-1672c9c9-5c69-44a3-b4a9-08be3eac9ff2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861503362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_clk_byp_req_intersig_mubi.861503362
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1752149304
Short name T231
Test name
Test status
Simulation time 52170082 ps
CPU time 0.89 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200464 kb
Host smart-2af8df99-7203-494b-8ad1-79c939390930
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752149304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.1752149304
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.4228144783
Short name T790
Test name
Test status
Simulation time 181218105 ps
CPU time 1.21 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200392 kb
Host smart-532f7969-32f2-49f7-9dd0-cd613c9337c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228144783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.4228144783
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.2821127338
Short name T151
Test name
Test status
Simulation time 1247626295 ps
CPU time 6.89 seconds
Started Jul 26 06:33:32 PM PDT 24
Finished Jul 26 06:33:39 PM PDT 24
Peak memory 200612 kb
Host smart-8934eb96-6874-4436-86b3-518636bea15f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821127338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2821127338
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.3944320174
Short name T548
Test name
Test status
Simulation time 21199352 ps
CPU time 0.87 seconds
Started Jul 26 06:33:24 PM PDT 24
Finished Jul 26 06:33:25 PM PDT 24
Peak memory 200404 kb
Host smart-c14faef4-8a08-46a4-a095-f68cc7a0bb9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944320174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3944320174
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.1404695556
Short name T139
Test name
Test status
Simulation time 10922144369 ps
CPU time 36.76 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:34:10 PM PDT 24
Peak memory 200732 kb
Host smart-c567eab6-c5ee-46ba-86b3-a5041fad7e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404695556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.1404695556
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.2392175970
Short name T744
Test name
Test status
Simulation time 23198387 ps
CPU time 0.93 seconds
Started Jul 26 06:33:26 PM PDT 24
Finished Jul 26 06:33:27 PM PDT 24
Peak memory 200468 kb
Host smart-cb85f23e-7323-4504-889b-effd550d2df5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392175970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2392175970
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.2601115177
Short name T806
Test name
Test status
Simulation time 32999814 ps
CPU time 0.85 seconds
Started Jul 26 06:33:32 PM PDT 24
Finished Jul 26 06:33:33 PM PDT 24
Peak memory 200424 kb
Host smart-da1cf2ac-5295-4f03-a60e-cfc55f529ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601115177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.2601115177
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1597801739
Short name T705
Test name
Test status
Simulation time 20061969 ps
CPU time 0.84 seconds
Started Jul 26 06:33:35 PM PDT 24
Finished Jul 26 06:33:36 PM PDT 24
Peak memory 200468 kb
Host smart-c131bef0-ba20-4dd8-87d7-c0efa5c6934f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597801739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.1597801739
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.216721926
Short name T512
Test name
Test status
Simulation time 23790340 ps
CPU time 0.72 seconds
Started Jul 26 06:33:34 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 199740 kb
Host smart-84d0f5b1-3577-4669-ae01-73ee3a0248a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216721926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.216721926
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.948152909
Short name T250
Test name
Test status
Simulation time 260103811 ps
CPU time 1.66 seconds
Started Jul 26 06:33:34 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 200472 kb
Host smart-e56c0e38-ef8e-407f-99e7-99b60caf7dbf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948152909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.clkmgr_div_intersig_mubi.948152909
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.2402705862
Short name T725
Test name
Test status
Simulation time 46935313 ps
CPU time 0.82 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:33:34 PM PDT 24
Peak memory 200452 kb
Host smart-13983567-ed9b-4fe8-ada7-4500072cf892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402705862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2402705862
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.3989416383
Short name T781
Test name
Test status
Simulation time 601261428 ps
CPU time 3.38 seconds
Started Jul 26 06:33:31 PM PDT 24
Finished Jul 26 06:33:34 PM PDT 24
Peak memory 200804 kb
Host smart-0fc09140-caed-42ec-851c-6d9c5a6f3dd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989416383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.3989416383
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.3936149922
Short name T496
Test name
Test status
Simulation time 262740461 ps
CPU time 1.91 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 200540 kb
Host smart-577c9c08-703d-48e3-a50e-2a7825554d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936149922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.3936149922
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2593446492
Short name T245
Test name
Test status
Simulation time 44416227 ps
CPU time 0.9 seconds
Started Jul 26 06:33:32 PM PDT 24
Finished Jul 26 06:33:33 PM PDT 24
Peak memory 200440 kb
Host smart-572601da-429e-4e7b-b1f4-b539682ed2c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593446492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.2593446492
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3269381035
Short name T445
Test name
Test status
Simulation time 42306575 ps
CPU time 0.91 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 200476 kb
Host smart-ed3c0f43-7918-48a6-8db7-4d7a7ce4d9e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269381035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3269381035
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.4000673098
Short name T475
Test name
Test status
Simulation time 72992202 ps
CPU time 1.04 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:33:34 PM PDT 24
Peak memory 200476 kb
Host smart-87e9ca3f-9b56-4b46-b043-3cfb7195606f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000673098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.4000673098
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2739223191
Short name T520
Test name
Test status
Simulation time 73290765 ps
CPU time 0.95 seconds
Started Jul 26 06:33:32 PM PDT 24
Finished Jul 26 06:33:33 PM PDT 24
Peak memory 200468 kb
Host smart-503d03c7-595a-404d-98e2-aa567c68dc4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739223191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2739223191
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.2141948591
Short name T267
Test name
Test status
Simulation time 833003950 ps
CPU time 4.81 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:33:38 PM PDT 24
Peak memory 200712 kb
Host smart-d1582d40-5adf-410d-8282-455a8dc51049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141948591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2141948591
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2922243521
Short name T354
Test name
Test status
Simulation time 57820555 ps
CPU time 0.96 seconds
Started Jul 26 06:33:32 PM PDT 24
Finished Jul 26 06:33:33 PM PDT 24
Peak memory 200444 kb
Host smart-137f16a1-7421-4a56-a548-911c76023402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922243521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2922243521
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.3257758506
Short name T242
Test name
Test status
Simulation time 2532458876 ps
CPU time 19.05 seconds
Started Jul 26 06:33:34 PM PDT 24
Finished Jul 26 06:33:53 PM PDT 24
Peak memory 200772 kb
Host smart-7f22cf79-dd6e-4caf-a56f-4158f1822c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257758506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.3257758506
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.1320169729
Short name T529
Test name
Test status
Simulation time 63131662 ps
CPU time 1.14 seconds
Started Jul 26 06:33:33 PM PDT 24
Finished Jul 26 06:33:35 PM PDT 24
Peak memory 200436 kb
Host smart-8458e223-4e34-473a-be77-8f023425c969
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320169729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1320169729
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2905564645
Short name T403
Test name
Test status
Simulation time 23464299 ps
CPU time 0.92 seconds
Started Jul 26 06:33:42 PM PDT 24
Finished Jul 26 06:33:43 PM PDT 24
Peak memory 200444 kb
Host smart-71cc6635-6351-4b3a-94b8-e540b3ee917a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905564645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.2905564645
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.4045750671
Short name T509
Test name
Test status
Simulation time 17259796 ps
CPU time 0.7 seconds
Started Jul 26 06:33:39 PM PDT 24
Finished Jul 26 06:33:40 PM PDT 24
Peak memory 200392 kb
Host smart-6a6a6e65-7650-44f6-8cb6-ea12db32ea81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045750671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.4045750671
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.3186300219
Short name T203
Test name
Test status
Simulation time 27865515 ps
CPU time 0.83 seconds
Started Jul 26 06:33:41 PM PDT 24
Finished Jul 26 06:33:42 PM PDT 24
Peak memory 200436 kb
Host smart-83931fcb-7b5f-40e3-9613-3e031a71ec80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186300219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.3186300219
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.1621572028
Short name T333
Test name
Test status
Simulation time 84369474 ps
CPU time 1.05 seconds
Started Jul 26 06:33:43 PM PDT 24
Finished Jul 26 06:33:44 PM PDT 24
Peak memory 200428 kb
Host smart-c9b2a643-cc58-4947-bd30-3da97d318a77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621572028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1621572028
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.994641743
Short name T9
Test name
Test status
Simulation time 1431218845 ps
CPU time 5.87 seconds
Started Jul 26 06:33:40 PM PDT 24
Finished Jul 26 06:33:46 PM PDT 24
Peak memory 200484 kb
Host smart-a2788cc0-0eef-4d52-aae1-40e9d3de053a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994641743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.994641743
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.2850810429
Short name T775
Test name
Test status
Simulation time 515031996 ps
CPU time 2.76 seconds
Started Jul 26 06:33:38 PM PDT 24
Finished Jul 26 06:33:41 PM PDT 24
Peak memory 200532 kb
Host smart-86067dc3-806e-444d-a71e-b97a6e0272d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850810429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.2850810429
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.4219374423
Short name T772
Test name
Test status
Simulation time 77201721 ps
CPU time 1.03 seconds
Started Jul 26 06:33:48 PM PDT 24
Finished Jul 26 06:33:49 PM PDT 24
Peak memory 200484 kb
Host smart-08e0cf7c-52ac-4846-884f-8201c970fd31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219374423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.4219374423
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.1172581452
Short name T412
Test name
Test status
Simulation time 20342305 ps
CPU time 0.76 seconds
Started Jul 26 06:33:40 PM PDT 24
Finished Jul 26 06:33:40 PM PDT 24
Peak memory 200448 kb
Host smart-5d6abc19-2312-42ce-b602-7d3c6019feb7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172581452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.1172581452
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.276044926
Short name T611
Test name
Test status
Simulation time 18767301 ps
CPU time 0.84 seconds
Started Jul 26 06:33:38 PM PDT 24
Finished Jul 26 06:33:39 PM PDT 24
Peak memory 200468 kb
Host smart-5d565a6e-1c53-4afd-8067-8adb5312e775
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276044926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.clkmgr_lc_ctrl_intersig_mubi.276044926
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.1966132756
Short name T801
Test name
Test status
Simulation time 20849784 ps
CPU time 0.78 seconds
Started Jul 26 06:33:39 PM PDT 24
Finished Jul 26 06:33:40 PM PDT 24
Peak memory 200404 kb
Host smart-1afb1e0c-0bf6-4d19-9357-c9de1f026a8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966132756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1966132756
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.1082751901
Short name T103
Test name
Test status
Simulation time 998536444 ps
CPU time 3.85 seconds
Started Jul 26 06:33:38 PM PDT 24
Finished Jul 26 06:33:42 PM PDT 24
Peak memory 200660 kb
Host smart-46f831a7-88ba-4f1e-b436-f5c3d401d578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082751901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1082751901
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.973045048
Short name T300
Test name
Test status
Simulation time 22195172 ps
CPU time 0.91 seconds
Started Jul 26 06:33:40 PM PDT 24
Finished Jul 26 06:33:41 PM PDT 24
Peak memory 200376 kb
Host smart-1677c408-4ff6-43b8-856e-1deae01d4967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973045048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.973045048
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.797742229
Short name T760
Test name
Test status
Simulation time 296900592 ps
CPU time 2.28 seconds
Started Jul 26 06:33:40 PM PDT 24
Finished Jul 26 06:33:42 PM PDT 24
Peak memory 200412 kb
Host smart-889a81d2-f742-42f8-bcc8-a6cfbd90200a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797742229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.797742229
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.810921442
Short name T554
Test name
Test status
Simulation time 95291520 ps
CPU time 1.12 seconds
Started Jul 26 06:33:42 PM PDT 24
Finished Jul 26 06:33:44 PM PDT 24
Peak memory 200388 kb
Host smart-5e22160f-625b-40b0-8deb-1664d19238b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810921442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.810921442
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.831699771
Short name T366
Test name
Test status
Simulation time 14177022 ps
CPU time 0.75 seconds
Started Jul 26 06:32:10 PM PDT 24
Finished Jul 26 06:32:10 PM PDT 24
Peak memory 200480 kb
Host smart-1f78e3c1-347e-4f9d-9d7a-82bfd6a521f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831699771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_alert_test.831699771
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.3008594202
Short name T93
Test name
Test status
Simulation time 53082598 ps
CPU time 0.95 seconds
Started Jul 26 06:32:10 PM PDT 24
Finished Jul 26 06:32:11 PM PDT 24
Peak memory 200496 kb
Host smart-df82d2c5-1a3e-43a3-8718-f5d48af45379
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008594202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.3008594202
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.1816710876
Short name T658
Test name
Test status
Simulation time 52335938 ps
CPU time 0.84 seconds
Started Jul 26 06:32:10 PM PDT 24
Finished Jul 26 06:32:11 PM PDT 24
Peak memory 199660 kb
Host smart-bf87716a-75ff-46bb-a0e3-6989df0c04aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816710876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1816710876
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.2766456595
Short name T75
Test name
Test status
Simulation time 19651274 ps
CPU time 0.76 seconds
Started Jul 26 06:32:10 PM PDT 24
Finished Jul 26 06:32:11 PM PDT 24
Peak memory 200468 kb
Host smart-fe978db1-e578-4754-8f51-8f374308bd03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766456595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.2766456595
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.2660540120
Short name T371
Test name
Test status
Simulation time 15754603 ps
CPU time 0.79 seconds
Started Jul 26 06:32:03 PM PDT 24
Finished Jul 26 06:32:04 PM PDT 24
Peak memory 200484 kb
Host smart-8407fc51-9e22-4e0e-a0b4-c163b03fdfa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660540120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2660540120
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.238741231
Short name T324
Test name
Test status
Simulation time 557704734 ps
CPU time 4.6 seconds
Started Jul 26 06:32:04 PM PDT 24
Finished Jul 26 06:32:09 PM PDT 24
Peak memory 200516 kb
Host smart-a8ec462f-d9ff-47b5-980a-46ba40e2c23d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238741231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.238741231
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.698074861
Short name T532
Test name
Test status
Simulation time 1186572341 ps
CPU time 5.19 seconds
Started Jul 26 06:32:03 PM PDT 24
Finished Jul 26 06:32:08 PM PDT 24
Peak memory 200580 kb
Host smart-27828841-514b-4eb4-9b5d-36858df09a26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698074861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_tim
eout.698074861
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2089866388
Short name T34
Test name
Test status
Simulation time 77359827 ps
CPU time 0.98 seconds
Started Jul 26 06:32:07 PM PDT 24
Finished Jul 26 06:32:08 PM PDT 24
Peak memory 200444 kb
Host smart-fc16eea0-b010-4b75-83e3-08df78a05cda
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089866388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.2089866388
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.314118050
Short name T608
Test name
Test status
Simulation time 46155500 ps
CPU time 0.9 seconds
Started Jul 26 06:32:11 PM PDT 24
Finished Jul 26 06:32:12 PM PDT 24
Peak memory 200460 kb
Host smart-8b54a6d6-a6c0-4b80-be7b-3532db9ae9fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314118050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_clk_byp_req_intersig_mubi.314118050
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.4128443378
Short name T312
Test name
Test status
Simulation time 49810066 ps
CPU time 1.02 seconds
Started Jul 26 06:32:08 PM PDT 24
Finished Jul 26 06:32:10 PM PDT 24
Peak memory 200484 kb
Host smart-766bf997-da35-4aff-b239-c5898cc8d8f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128443378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.4128443378
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2297513733
Short name T361
Test name
Test status
Simulation time 39788365 ps
CPU time 0.81 seconds
Started Jul 26 06:32:09 PM PDT 24
Finished Jul 26 06:32:10 PM PDT 24
Peak memory 200424 kb
Host smart-db09048c-27f3-49b0-b597-bfba0900fb84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297513733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2297513733
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.2261413799
Short name T159
Test name
Test status
Simulation time 1129977681 ps
CPU time 6.47 seconds
Started Jul 26 06:32:08 PM PDT 24
Finished Jul 26 06:32:15 PM PDT 24
Peak memory 200656 kb
Host smart-ab0c4aef-7213-4c70-bb13-fa3cdd5bd1f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261413799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.2261413799
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.3307180663
Short name T244
Test name
Test status
Simulation time 37244375 ps
CPU time 0.89 seconds
Started Jul 26 06:32:04 PM PDT 24
Finished Jul 26 06:32:05 PM PDT 24
Peak memory 200404 kb
Host smart-4ad78418-e7b3-4ca9-a8f9-2dbe0fdf2330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307180663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3307180663
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2420112791
Short name T309
Test name
Test status
Simulation time 3376612361 ps
CPU time 14.43 seconds
Started Jul 26 06:32:10 PM PDT 24
Finished Jul 26 06:32:24 PM PDT 24
Peak memory 200808 kb
Host smart-615fac45-ce0d-4e33-92bd-faf5b06409ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420112791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2420112791
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.3327964625
Short name T572
Test name
Test status
Simulation time 24784310 ps
CPU time 0.93 seconds
Started Jul 26 06:32:09 PM PDT 24
Finished Jul 26 06:32:10 PM PDT 24
Peak memory 200432 kb
Host smart-2a67816f-e72f-439d-a540-1b396d5a1984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327964625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.3327964625
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.1210990000
Short name T791
Test name
Test status
Simulation time 40627815 ps
CPU time 0.84 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:33:46 PM PDT 24
Peak memory 200504 kb
Host smart-22ff3866-dd2d-43fe-b221-c91973340d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210990000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.1210990000
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.4063263399
Short name T534
Test name
Test status
Simulation time 18605043 ps
CPU time 0.77 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:33:46 PM PDT 24
Peak memory 200532 kb
Host smart-c581e933-22c2-487d-9740-bb28c345bea6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063263399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.4063263399
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.987301717
Short name T690
Test name
Test status
Simulation time 17573404 ps
CPU time 0.73 seconds
Started Jul 26 06:33:40 PM PDT 24
Finished Jul 26 06:33:41 PM PDT 24
Peak memory 199656 kb
Host smart-7de4c5e4-080b-4e2d-bfdb-757183e98f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987301717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.987301717
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.967122230
Short name T787
Test name
Test status
Simulation time 72191420 ps
CPU time 0.91 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:33:46 PM PDT 24
Peak memory 200448 kb
Host smart-22427306-766c-4089-8f21-e20408ee436e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967122230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.967122230
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.529595134
Short name T194
Test name
Test status
Simulation time 18132910 ps
CPU time 0.75 seconds
Started Jul 26 06:33:36 PM PDT 24
Finished Jul 26 06:33:37 PM PDT 24
Peak memory 200480 kb
Host smart-fad541b2-eb2b-4082-a944-27577e39292e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529595134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.529595134
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.544909682
Short name T230
Test name
Test status
Simulation time 1880655121 ps
CPU time 15.41 seconds
Started Jul 26 06:33:39 PM PDT 24
Finished Jul 26 06:33:54 PM PDT 24
Peak memory 200732 kb
Host smart-9c1e0abf-d6d9-44e9-a84b-600792c6530a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544909682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.544909682
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.3453441835
Short name T271
Test name
Test status
Simulation time 857611764 ps
CPU time 6.52 seconds
Started Jul 26 06:33:38 PM PDT 24
Finished Jul 26 06:33:45 PM PDT 24
Peak memory 200560 kb
Host smart-23caab4a-d4c2-4dcb-8515-73c842484abe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453441835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.3453441835
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.923615352
Short name T353
Test name
Test status
Simulation time 48555096 ps
CPU time 0.87 seconds
Started Jul 26 06:33:39 PM PDT 24
Finished Jul 26 06:33:40 PM PDT 24
Peak memory 200416 kb
Host smart-47d2f06c-f35b-4fdd-8794-277b20571671
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923615352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_idle_intersig_mubi.923615352
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3659084849
Short name T287
Test name
Test status
Simulation time 102883881 ps
CPU time 1.13 seconds
Started Jul 26 06:33:43 PM PDT 24
Finished Jul 26 06:33:44 PM PDT 24
Peak memory 200460 kb
Host smart-e19afd48-6ada-44c2-acd3-a72d28f80289
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659084849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.3659084849
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1897160021
Short name T615
Test name
Test status
Simulation time 22931137 ps
CPU time 0.9 seconds
Started Jul 26 06:33:46 PM PDT 24
Finished Jul 26 06:33:47 PM PDT 24
Peak memory 200468 kb
Host smart-8b7ee06d-b1cf-4de7-990c-7f5322cd618e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897160021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.1897160021
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.4079847109
Short name T706
Test name
Test status
Simulation time 18961549 ps
CPU time 0.77 seconds
Started Jul 26 06:33:37 PM PDT 24
Finished Jul 26 06:33:38 PM PDT 24
Peak memory 200412 kb
Host smart-27b1e95e-6a2d-4b7a-bfc7-5eb8fd21b2ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079847109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.4079847109
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.2609323932
Short name T802
Test name
Test status
Simulation time 689627415 ps
CPU time 4.56 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:33:49 PM PDT 24
Peak memory 200656 kb
Host smart-b8bf958a-f6ea-44a7-863b-0616b674cb65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609323932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.2609323932
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.3131200258
Short name T511
Test name
Test status
Simulation time 112612136 ps
CPU time 1.09 seconds
Started Jul 26 06:33:39 PM PDT 24
Finished Jul 26 06:33:40 PM PDT 24
Peak memory 200420 kb
Host smart-9c8bcaca-22b1-4642-b0f0-02864a97e6e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131200258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3131200258
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.306887127
Short name T423
Test name
Test status
Simulation time 5243898358 ps
CPU time 39.8 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:34:25 PM PDT 24
Peak memory 201084 kb
Host smart-3d934822-9c7d-41ef-b64d-196826cfac50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306887127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.306887127
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.3079557401
Short name T646
Test name
Test status
Simulation time 98166208 ps
CPU time 1.09 seconds
Started Jul 26 06:33:42 PM PDT 24
Finished Jul 26 06:33:44 PM PDT 24
Peak memory 200436 kb
Host smart-8f5bce01-366d-4747-98f2-467a4c5350df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079557401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.3079557401
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.1906583069
Short name T5
Test name
Test status
Simulation time 50167088 ps
CPU time 0.81 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:33:52 PM PDT 24
Peak memory 200484 kb
Host smart-521352c3-5ed7-45d3-9091-a061068713bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906583069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.1906583069
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.166412214
Short name T308
Test name
Test status
Simulation time 22819871 ps
CPU time 0.76 seconds
Started Jul 26 06:33:52 PM PDT 24
Finished Jul 26 06:33:53 PM PDT 24
Peak memory 200472 kb
Host smart-15ae68c3-53da-4613-8e3e-4b02591e221a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166412214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.166412214
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.1629340823
Short name T714
Test name
Test status
Simulation time 50986845 ps
CPU time 0.81 seconds
Started Jul 26 06:33:44 PM PDT 24
Finished Jul 26 06:33:44 PM PDT 24
Peak memory 199676 kb
Host smart-c9303409-f8b8-48f0-aa3b-ea2675595775
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629340823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1629340823
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1774184584
Short name T340
Test name
Test status
Simulation time 43943223 ps
CPU time 0.93 seconds
Started Jul 26 06:33:52 PM PDT 24
Finished Jul 26 06:33:53 PM PDT 24
Peak memory 200456 kb
Host smart-4b1042df-3e79-4cac-bde6-88607d147aad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774184584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1774184584
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.2970119002
Short name T409
Test name
Test status
Simulation time 62994140 ps
CPU time 0.92 seconds
Started Jul 26 06:33:43 PM PDT 24
Finished Jul 26 06:33:44 PM PDT 24
Peak memory 200412 kb
Host smart-4aa17ba8-f4ed-4f02-bc8d-c043f146d680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970119002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2970119002
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.1729821056
Short name T588
Test name
Test status
Simulation time 439389596 ps
CPU time 3.89 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:33:49 PM PDT 24
Peak memory 200508 kb
Host smart-d66aa605-7a5f-4bb7-9e6d-4027abd1bbb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729821056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.1729821056
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.4093725867
Short name T704
Test name
Test status
Simulation time 1248432813 ps
CPU time 4.46 seconds
Started Jul 26 06:33:47 PM PDT 24
Finished Jul 26 06:33:51 PM PDT 24
Peak memory 200560 kb
Host smart-cac5eb12-ab67-437a-95a8-52157e55caea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093725867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.4093725867
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1986690941
Short name T745
Test name
Test status
Simulation time 475558445 ps
CPU time 2.24 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:33:48 PM PDT 24
Peak memory 200328 kb
Host smart-6fd954a4-64ee-4936-b6c0-7c6e511c142c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986690941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.1986690941
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1795980752
Short name T481
Test name
Test status
Simulation time 43340794 ps
CPU time 0.9 seconds
Started Jul 26 06:33:52 PM PDT 24
Finished Jul 26 06:33:53 PM PDT 24
Peak memory 200380 kb
Host smart-9eacfe12-4d0d-4004-8019-5290ebe146bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795980752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.1795980752
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2705935034
Short name T413
Test name
Test status
Simulation time 32195295 ps
CPU time 0.85 seconds
Started Jul 26 06:33:44 PM PDT 24
Finished Jul 26 06:33:45 PM PDT 24
Peak memory 200428 kb
Host smart-38ccb011-9c8d-41f3-ae30-79739b66a4b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705935034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.2705935034
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.3291605472
Short name T397
Test name
Test status
Simulation time 42550671 ps
CPU time 0.82 seconds
Started Jul 26 06:33:44 PM PDT 24
Finished Jul 26 06:33:45 PM PDT 24
Peak memory 200680 kb
Host smart-e7629006-5df4-4e65-b7d8-f93d656b68a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291605472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3291605472
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.1916082046
Short name T515
Test name
Test status
Simulation time 467668854 ps
CPU time 3.17 seconds
Started Jul 26 06:33:50 PM PDT 24
Finished Jul 26 06:33:53 PM PDT 24
Peak memory 200448 kb
Host smart-020dfa07-fa79-40ea-a21f-4f068e4b960b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916082046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1916082046
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.598334103
Short name T473
Test name
Test status
Simulation time 38827859 ps
CPU time 0.91 seconds
Started Jul 26 06:33:45 PM PDT 24
Finished Jul 26 06:33:46 PM PDT 24
Peak memory 200380 kb
Host smart-9e921400-e0ca-4451-a5fb-d9ba9f9e300a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598334103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.598334103
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.2551673221
Short name T647
Test name
Test status
Simulation time 8503825365 ps
CPU time 31.26 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200852 kb
Host smart-f02279cc-9e18-4b26-a764-b32e9e5ee1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551673221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.2551673221
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.1349966694
Short name T177
Test name
Test status
Simulation time 33311998 ps
CPU time 0.9 seconds
Started Jul 26 06:33:44 PM PDT 24
Finished Jul 26 06:33:45 PM PDT 24
Peak memory 200464 kb
Host smart-5c1ba5fd-f3b9-4ece-8b93-567a38a78732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349966694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.1349966694
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.1700258430
Short name T16
Test name
Test status
Simulation time 17424458 ps
CPU time 0.77 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:33:58 PM PDT 24
Peak memory 200412 kb
Host smart-4077482d-05af-440d-be3b-a1f573c739da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700258430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.1700258430
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1305282458
Short name T803
Test name
Test status
Simulation time 92514193 ps
CPU time 1.12 seconds
Started Jul 26 06:33:54 PM PDT 24
Finished Jul 26 06:33:55 PM PDT 24
Peak memory 200468 kb
Host smart-35f4f752-c1d5-4006-8f0e-8fb77da67076
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305282458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.1305282458
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.1778641956
Short name T672
Test name
Test status
Simulation time 52053417 ps
CPU time 0.85 seconds
Started Jul 26 06:33:54 PM PDT 24
Finished Jul 26 06:33:55 PM PDT 24
Peak memory 199688 kb
Host smart-e0faa811-002d-451b-a76a-8b8341a12d3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778641956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1778641956
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.2542262595
Short name T604
Test name
Test status
Simulation time 21573467 ps
CPU time 0.8 seconds
Started Jul 26 06:33:53 PM PDT 24
Finished Jul 26 06:33:54 PM PDT 24
Peak memory 200484 kb
Host smart-9ad65605-b991-4dc0-933f-fbb67ab5c319
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542262595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.2542262595
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.4118039839
Short name T455
Test name
Test status
Simulation time 103900297 ps
CPU time 1.12 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:33:52 PM PDT 24
Peak memory 200476 kb
Host smart-0312d501-db50-4905-bdbd-1a67d9b059e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118039839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.4118039839
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.1659646538
Short name T345
Test name
Test status
Simulation time 1756114473 ps
CPU time 14.42 seconds
Started Jul 26 06:33:54 PM PDT 24
Finished Jul 26 06:34:08 PM PDT 24
Peak memory 200496 kb
Host smart-a6608756-5a48-4172-8b28-f736b5702a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659646538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.1659646538
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.2202572023
Short name T483
Test name
Test status
Simulation time 140860105 ps
CPU time 1.72 seconds
Started Jul 26 06:33:52 PM PDT 24
Finished Jul 26 06:33:53 PM PDT 24
Peak memory 200544 kb
Host smart-a6ae0ca7-55f1-4c92-8171-f2a84356e32d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202572023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.2202572023
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.823492930
Short name T427
Test name
Test status
Simulation time 43614264 ps
CPU time 0.99 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:33:53 PM PDT 24
Peak memory 200440 kb
Host smart-d2d0d84f-b101-4607-b661-e22379868d1b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823492930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_idle_intersig_mubi.823492930
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3499378128
Short name T355
Test name
Test status
Simulation time 20369990 ps
CPU time 0.86 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:33:52 PM PDT 24
Peak memory 200476 kb
Host smart-91ded9db-3d36-4b32-9b4f-313ea4b0e1af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499378128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3499378128
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.4241984246
Short name T464
Test name
Test status
Simulation time 25134995 ps
CPU time 0.9 seconds
Started Jul 26 06:33:55 PM PDT 24
Finished Jul 26 06:33:56 PM PDT 24
Peak memory 200460 kb
Host smart-277798c7-a9ef-4050-8911-5d42cbf92814
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241984246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.4241984246
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.233113813
Short name T782
Test name
Test status
Simulation time 57825698 ps
CPU time 0.82 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:33:52 PM PDT 24
Peak memory 200472 kb
Host smart-9871ad6e-8294-4e51-bcd1-72aff9b37b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233113813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.233113813
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2550215501
Short name T591
Test name
Test status
Simulation time 739909317 ps
CPU time 3.63 seconds
Started Jul 26 06:33:54 PM PDT 24
Finished Jul 26 06:33:58 PM PDT 24
Peak memory 200648 kb
Host smart-147e0ad7-a5c0-44b9-b007-f34f7c19a5a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550215501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2550215501
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.665138792
Short name T363
Test name
Test status
Simulation time 78462514 ps
CPU time 1.01 seconds
Started Jul 26 06:33:53 PM PDT 24
Finished Jul 26 06:33:54 PM PDT 24
Peak memory 200424 kb
Host smart-dd6e8c02-4c1f-47cf-898f-07f447b6be85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665138792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.665138792
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.2968729739
Short name T805
Test name
Test status
Simulation time 4181782149 ps
CPU time 21.47 seconds
Started Jul 26 06:33:55 PM PDT 24
Finished Jul 26 06:34:16 PM PDT 24
Peak memory 200804 kb
Host smart-8f346cfc-7eb5-4f54-915d-879422b25505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968729739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.2968729739
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.43606643
Short name T689
Test name
Test status
Simulation time 24715777390 ps
CPU time 368.14 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:40:00 PM PDT 24
Peak memory 217340 kb
Host smart-883ff0d4-7edd-4535-aef1-a6adaf036b5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=43606643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.43606643
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.1139786352
Short name T540
Test name
Test status
Simulation time 21263145 ps
CPU time 0.85 seconds
Started Jul 26 06:33:51 PM PDT 24
Finished Jul 26 06:33:52 PM PDT 24
Peak memory 200464 kb
Host smart-03be823e-0ceb-4417-ad7e-20f29d4f7c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139786352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1139786352
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.1379987677
Short name T452
Test name
Test status
Simulation time 27838487 ps
CPU time 0.85 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:33:58 PM PDT 24
Peak memory 200456 kb
Host smart-f2ecd556-3ab7-4532-a13a-31530dce2974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379987677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.1379987677
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.718530353
Short name T694
Test name
Test status
Simulation time 105929304 ps
CPU time 1.08 seconds
Started Jul 26 06:33:58 PM PDT 24
Finished Jul 26 06:33:59 PM PDT 24
Peak memory 200428 kb
Host smart-a04fd561-5acf-4885-a1a0-2b2e98e4caca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718530353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.718530353
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.34429056
Short name T181
Test name
Test status
Simulation time 13816232 ps
CPU time 0.73 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:33:58 PM PDT 24
Peak memory 200388 kb
Host smart-945c754e-a55f-42c7-bcc0-66bbe5a0879c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34429056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.34429056
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2906243615
Short name T331
Test name
Test status
Simulation time 16270506 ps
CPU time 0.77 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:33:58 PM PDT 24
Peak memory 200412 kb
Host smart-7820f388-e8d4-4108-9d85-488461931c37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906243615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2906243615
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.3364943711
Short name T733
Test name
Test status
Simulation time 22701592 ps
CPU time 0.87 seconds
Started Jul 26 06:33:56 PM PDT 24
Finished Jul 26 06:33:57 PM PDT 24
Peak memory 200464 kb
Host smart-a2e8a927-0b74-418d-873c-f14bd72a311e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364943711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3364943711
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.3446326230
Short name T793
Test name
Test status
Simulation time 679335697 ps
CPU time 5.59 seconds
Started Jul 26 06:33:58 PM PDT 24
Finished Jul 26 06:34:03 PM PDT 24
Peak memory 200540 kb
Host smart-a7e00ff4-0fb5-4fd6-b25d-392d93eaee61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446326230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3446326230
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.2402263028
Short name T362
Test name
Test status
Simulation time 1945782018 ps
CPU time 9.66 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:34:07 PM PDT 24
Peak memory 200588 kb
Host smart-fe0ef8c9-7b01-46e2-8c42-9eaf8c5b3dc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402263028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.2402263028
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.208889632
Short name T290
Test name
Test status
Simulation time 21160258 ps
CPU time 0.81 seconds
Started Jul 26 06:34:00 PM PDT 24
Finished Jul 26 06:34:01 PM PDT 24
Peak memory 200460 kb
Host smart-52d5871f-1e8c-4215-a5d6-428a4207a3b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208889632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.clkmgr_idle_intersig_mubi.208889632
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.806945226
Short name T536
Test name
Test status
Simulation time 39944643 ps
CPU time 0.94 seconds
Started Jul 26 06:33:58 PM PDT 24
Finished Jul 26 06:33:59 PM PDT 24
Peak memory 200488 kb
Host smart-6d874869-85de-448d-9633-71b798aeed56
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806945226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.clkmgr_lc_clk_byp_req_intersig_mubi.806945226
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3754202972
Short name T755
Test name
Test status
Simulation time 17858762 ps
CPU time 0.8 seconds
Started Jul 26 06:33:59 PM PDT 24
Finished Jul 26 06:33:59 PM PDT 24
Peak memory 200444 kb
Host smart-209e2919-b02b-434b-8411-308d1d567191
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754202972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.3754202972
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.406007716
Short name T685
Test name
Test status
Simulation time 18403182 ps
CPU time 0.75 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:33:58 PM PDT 24
Peak memory 200428 kb
Host smart-a38c163f-de05-42aa-8c5b-b42880eb5c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406007716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.406007716
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.925607541
Short name T153
Test name
Test status
Simulation time 274370633 ps
CPU time 1.64 seconds
Started Jul 26 06:33:59 PM PDT 24
Finished Jul 26 06:34:00 PM PDT 24
Peak memory 200448 kb
Host smart-cb4c557c-046c-4773-9f89-f0edf37dd4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925607541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.925607541
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.1884414579
Short name T471
Test name
Test status
Simulation time 17886963 ps
CPU time 0.82 seconds
Started Jul 26 06:33:56 PM PDT 24
Finished Jul 26 06:33:57 PM PDT 24
Peak memory 200464 kb
Host smart-ec8f86b3-cc6b-49c8-8170-6a4766639bfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884414579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1884414579
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.3724322650
Short name T628
Test name
Test status
Simulation time 7041681212 ps
CPU time 53.07 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:34:51 PM PDT 24
Peak memory 200824 kb
Host smart-554b49f4-9396-4627-a070-6aaddb449f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724322650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.3724322650
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.690957312
Short name T463
Test name
Test status
Simulation time 34395577 ps
CPU time 0.98 seconds
Started Jul 26 06:33:57 PM PDT 24
Finished Jul 26 06:33:58 PM PDT 24
Peak memory 200380 kb
Host smart-5f91dce1-c093-435d-abdb-1433eae27826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690957312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.690957312
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.1428183247
Short name T742
Test name
Test status
Simulation time 34815399 ps
CPU time 0.86 seconds
Started Jul 26 06:34:11 PM PDT 24
Finished Jul 26 06:34:12 PM PDT 24
Peak memory 200428 kb
Host smart-a0196e61-3779-47c8-8009-bff36d1a4502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428183247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.1428183247
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.683879477
Short name T383
Test name
Test status
Simulation time 45285001 ps
CPU time 0.88 seconds
Started Jul 26 06:34:04 PM PDT 24
Finished Jul 26 06:34:05 PM PDT 24
Peak memory 200460 kb
Host smart-ca9c02b7-30ae-4e6d-bfed-c620262d746f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683879477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.683879477
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.236668811
Short name T336
Test name
Test status
Simulation time 15760745 ps
CPU time 0.73 seconds
Started Jul 26 06:34:03 PM PDT 24
Finished Jul 26 06:34:04 PM PDT 24
Peak memory 200248 kb
Host smart-6c19619c-2557-4dab-9182-859a67e36807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236668811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.236668811
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.3379805506
Short name T318
Test name
Test status
Simulation time 26178741 ps
CPU time 0.83 seconds
Started Jul 26 06:34:08 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 200408 kb
Host smart-8b2f4a0b-907f-4f20-95aa-fa8a0e255aa7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379805506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.3379805506
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.1488816915
Short name T561
Test name
Test status
Simulation time 261145233 ps
CPU time 1.54 seconds
Started Jul 26 06:34:02 PM PDT 24
Finished Jul 26 06:34:04 PM PDT 24
Peak memory 200440 kb
Host smart-ed96ffa1-2311-4676-a132-d732f991ceba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488816915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1488816915
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.1541605592
Short name T605
Test name
Test status
Simulation time 1910456993 ps
CPU time 9.23 seconds
Started Jul 26 06:34:04 PM PDT 24
Finished Jul 26 06:34:14 PM PDT 24
Peak memory 200756 kb
Host smart-f47f173f-6741-4229-946b-59c21c9d36c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541605592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1541605592
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.918479090
Short name T582
Test name
Test status
Simulation time 2423632097 ps
CPU time 12.38 seconds
Started Jul 26 06:34:04 PM PDT 24
Finished Jul 26 06:34:16 PM PDT 24
Peak memory 200852 kb
Host smart-24e4df10-63ba-495b-b881-9041b97df794
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918479090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_ti
meout.918479090
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.4230637396
Short name T598
Test name
Test status
Simulation time 79257128 ps
CPU time 1.07 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 200424 kb
Host smart-2443cb33-d144-4f69-b23a-f7395f5bd96d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230637396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.4230637396
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1729604452
Short name T480
Test name
Test status
Simulation time 16138030 ps
CPU time 0.77 seconds
Started Jul 26 06:34:04 PM PDT 24
Finished Jul 26 06:34:05 PM PDT 24
Peak memory 200496 kb
Host smart-1cb23796-30d7-4f00-96a0-1953bcffcf26
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729604452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1729604452
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.114550959
Short name T325
Test name
Test status
Simulation time 93267634 ps
CPU time 1.13 seconds
Started Jul 26 06:34:04 PM PDT 24
Finished Jul 26 06:34:05 PM PDT 24
Peak memory 200480 kb
Host smart-e7a3118d-63a1-4def-8559-777d789675d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114550959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_ctrl_intersig_mubi.114550959
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.3299068210
Short name T291
Test name
Test status
Simulation time 67279942 ps
CPU time 0.89 seconds
Started Jul 26 06:34:08 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 200380 kb
Host smart-c5d507c9-542e-44ee-b760-c90f5bd616f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299068210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3299068210
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.1742363283
Short name T414
Test name
Test status
Simulation time 1025771347 ps
CPU time 3.64 seconds
Started Jul 26 06:34:05 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 200620 kb
Host smart-bfcaf3ce-f7a1-469e-99c9-768cba40ba21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742363283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.1742363283
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.3005716432
Short name T168
Test name
Test status
Simulation time 61920108 ps
CPU time 1.03 seconds
Started Jul 26 06:34:03 PM PDT 24
Finished Jul 26 06:34:04 PM PDT 24
Peak memory 200324 kb
Host smart-2e5b1f32-7547-44c7-8fc2-f948bb7bf085
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005716432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3005716432
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.4216008239
Short name T373
Test name
Test status
Simulation time 3878201128 ps
CPU time 22.07 seconds
Started Jul 26 06:34:11 PM PDT 24
Finished Jul 26 06:34:33 PM PDT 24
Peak memory 200816 kb
Host smart-854c2dcb-0aef-4536-91e2-5286f4591704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216008239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.4216008239
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.939165503
Short name T50
Test name
Test status
Simulation time 35838865 ps
CPU time 0.89 seconds
Started Jul 26 06:34:04 PM PDT 24
Finished Jul 26 06:34:05 PM PDT 24
Peak memory 200492 kb
Host smart-e7c6e8c7-5814-475b-8386-5b335cb061e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939165503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.939165503
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.2386022272
Short name T408
Test name
Test status
Simulation time 42084649 ps
CPU time 0.85 seconds
Started Jul 26 06:34:11 PM PDT 24
Finished Jul 26 06:34:11 PM PDT 24
Peak memory 200428 kb
Host smart-c1ecfc9f-9ac0-4679-acf2-1839c01becfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386022272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.2386022272
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2018795624
Short name T15
Test name
Test status
Simulation time 53217637 ps
CPU time 0.91 seconds
Started Jul 26 06:34:11 PM PDT 24
Finished Jul 26 06:34:12 PM PDT 24
Peak memory 200424 kb
Host smart-18dd11d1-9425-42b3-9b52-aa9fc393391f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018795624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.2018795624
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.1394424404
Short name T184
Test name
Test status
Simulation time 62879903 ps
CPU time 0.84 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:08 PM PDT 24
Peak memory 200356 kb
Host smart-c507f364-0af6-47d3-8675-1f4936c5052d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394424404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.1394424404
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.669681419
Short name T589
Test name
Test status
Simulation time 43239050 ps
CPU time 0.96 seconds
Started Jul 26 06:34:10 PM PDT 24
Finished Jul 26 06:34:11 PM PDT 24
Peak memory 200456 kb
Host smart-8388ea4e-a961-481a-9595-f08de73bea0f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669681419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.669681419
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3818473196
Short name T227
Test name
Test status
Simulation time 34122260 ps
CPU time 0.86 seconds
Started Jul 26 06:34:04 PM PDT 24
Finished Jul 26 06:34:05 PM PDT 24
Peak memory 200452 kb
Host smart-5f3cde2e-b44b-4620-a44a-1e880686fd4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818473196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3818473196
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.1394148496
Short name T596
Test name
Test status
Simulation time 802361261 ps
CPU time 6.88 seconds
Started Jul 26 06:34:09 PM PDT 24
Finished Jul 26 06:34:16 PM PDT 24
Peak memory 200508 kb
Host smart-c99e4ac2-c14a-4a8d-b49b-a4ab4a88e720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394148496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.1394148496
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.2040628309
Short name T442
Test name
Test status
Simulation time 1246760051 ps
CPU time 4.87 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:12 PM PDT 24
Peak memory 200564 kb
Host smart-10f16b72-148c-427b-9a75-732a5f6f5c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040628309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.2040628309
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3733699965
Short name T206
Test name
Test status
Simulation time 47144882 ps
CPU time 1.01 seconds
Started Jul 26 06:34:05 PM PDT 24
Finished Jul 26 06:34:06 PM PDT 24
Peak memory 200452 kb
Host smart-5d5c1ccf-64bd-4b00-91dc-c95c09934937
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733699965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3733699965
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.3029030783
Short name T458
Test name
Test status
Simulation time 39236421 ps
CPU time 0.85 seconds
Started Jul 26 06:34:09 PM PDT 24
Finished Jul 26 06:34:10 PM PDT 24
Peak memory 200440 kb
Host smart-144f96ca-a963-4ac0-89a9-ecf21c47c127
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029030783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.3029030783
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2129906570
Short name T639
Test name
Test status
Simulation time 201918185 ps
CPU time 1.42 seconds
Started Jul 26 06:34:03 PM PDT 24
Finished Jul 26 06:34:05 PM PDT 24
Peak memory 200476 kb
Host smart-a06b71a9-0110-4252-9f11-6e8d8e2ac74e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129906570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.2129906570
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.3248986363
Short name T717
Test name
Test status
Simulation time 17958917 ps
CPU time 0.79 seconds
Started Jul 26 06:34:01 PM PDT 24
Finished Jul 26 06:34:02 PM PDT 24
Peak memory 200448 kb
Host smart-10aa1f04-017a-4fa1-baa7-5f3bff382883
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248986363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3248986363
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.1618714499
Short name T757
Test name
Test status
Simulation time 1254216479 ps
CPU time 6.01 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:13 PM PDT 24
Peak memory 200620 kb
Host smart-906e5555-cc05-48de-abb6-004de1148b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618714499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.1618714499
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2016814307
Short name T341
Test name
Test status
Simulation time 43341277 ps
CPU time 0.9 seconds
Started Jul 26 06:34:09 PM PDT 24
Finished Jul 26 06:34:10 PM PDT 24
Peak memory 200392 kb
Host smart-f5ec4b4f-c891-4ab6-88c2-8378b43e4627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016814307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2016814307
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.2813844838
Short name T375
Test name
Test status
Simulation time 132026605 ps
CPU time 1.19 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:08 PM PDT 24
Peak memory 200456 kb
Host smart-095c7450-16aa-4d18-af09-493ed7208d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813844838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.2813844838
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.2474258738
Short name T315
Test name
Test status
Simulation time 61219791 ps
CPU time 0.96 seconds
Started Jul 26 06:34:05 PM PDT 24
Finished Jul 26 06:34:06 PM PDT 24
Peak memory 200436 kb
Host smart-b6f806cd-1884-42c7-8ccc-a6d42414f571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474258738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2474258738
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.3450213365
Short name T795
Test name
Test status
Simulation time 26315674 ps
CPU time 0.9 seconds
Started Jul 26 06:34:09 PM PDT 24
Finished Jul 26 06:34:10 PM PDT 24
Peak memory 200480 kb
Host smart-7837a06b-a35e-42b1-94b3-fb1f3f847902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450213365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.3450213365
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.269320386
Short name T505
Test name
Test status
Simulation time 38171235 ps
CPU time 0.87 seconds
Started Jul 26 06:34:09 PM PDT 24
Finished Jul 26 06:34:10 PM PDT 24
Peak memory 200468 kb
Host smart-4af47af8-3103-4ef1-a9b6-cab3e3d34867
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269320386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.269320386
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.964482938
Short name T182
Test name
Test status
Simulation time 16050443 ps
CPU time 0.75 seconds
Started Jul 26 06:34:08 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 199672 kb
Host smart-fd998f93-9914-49ff-ada8-a0550ee7737e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964482938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.964482938
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.3312382031
Short name T559
Test name
Test status
Simulation time 48699841 ps
CPU time 1.04 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:08 PM PDT 24
Peak memory 200464 kb
Host smart-33344292-7827-4f1e-90fc-fff25c9e02b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312382031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.3312382031
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.1776560161
Short name T661
Test name
Test status
Simulation time 138497733 ps
CPU time 1.19 seconds
Started Jul 26 06:34:06 PM PDT 24
Finished Jul 26 06:34:07 PM PDT 24
Peak memory 200416 kb
Host smart-35b4c9f4-37d2-40f8-a5f3-40870a97cc29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776560161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1776560161
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.2152094537
Short name T377
Test name
Test status
Simulation time 2235166099 ps
CPU time 16.51 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200780 kb
Host smart-ab80232c-fade-4889-9983-be1af59d32e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152094537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.2152094537
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.4206344783
Short name T729
Test name
Test status
Simulation time 310426318 ps
CPU time 1.67 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 200540 kb
Host smart-5f7619fa-ce6b-4af5-8ec2-ee1fa890cfbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206344783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.4206344783
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.441475853
Short name T202
Test name
Test status
Simulation time 18456797 ps
CPU time 0.8 seconds
Started Jul 26 06:34:07 PM PDT 24
Finished Jul 26 06:34:08 PM PDT 24
Peak memory 200440 kb
Host smart-a031016c-d977-4846-b495-158d52f0c520
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441475853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_idle_intersig_mubi.441475853
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3856001557
Short name T579
Test name
Test status
Simulation time 17505062 ps
CPU time 0.81 seconds
Started Jul 26 06:34:09 PM PDT 24
Finished Jul 26 06:34:10 PM PDT 24
Peak memory 200484 kb
Host smart-c33c064b-215f-4cf1-b227-b5bd75339159
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856001557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3856001557
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.3277821423
Short name T406
Test name
Test status
Simulation time 13204664 ps
CPU time 0.81 seconds
Started Jul 26 06:34:08 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 200464 kb
Host smart-ee0d2528-2c8e-4a4c-bdba-79c158293058
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277821423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.3277821423
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.312723667
Short name T636
Test name
Test status
Simulation time 34628897 ps
CPU time 0.76 seconds
Started Jul 26 06:34:10 PM PDT 24
Finished Jul 26 06:34:11 PM PDT 24
Peak memory 200424 kb
Host smart-d8768740-9a4f-4ee0-bb33-8a3f206d9e2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312723667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.312723667
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.4031947430
Short name T164
Test name
Test status
Simulation time 552520612 ps
CPU time 3.57 seconds
Started Jul 26 06:34:11 PM PDT 24
Finished Jul 26 06:34:14 PM PDT 24
Peak memory 200624 kb
Host smart-81b6385e-fd09-467a-8241-155661d3906a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031947430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.4031947430
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.346437679
Short name T719
Test name
Test status
Simulation time 21013680 ps
CPU time 0.92 seconds
Started Jul 26 06:34:06 PM PDT 24
Finished Jul 26 06:34:07 PM PDT 24
Peak memory 200384 kb
Host smart-263ccd79-9238-4968-9c60-b35ff1e65a86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346437679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.346437679
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.592933146
Short name T12
Test name
Test status
Simulation time 8856143453 ps
CPU time 67.63 seconds
Started Jul 26 06:34:08 PM PDT 24
Finished Jul 26 06:35:16 PM PDT 24
Peak memory 200784 kb
Host smart-2b38aafb-399e-41a8-bf19-d8cb2e719203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592933146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.592933146
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1371003067
Short name T718
Test name
Test status
Simulation time 26554717 ps
CPU time 0.81 seconds
Started Jul 26 06:34:08 PM PDT 24
Finished Jul 26 06:34:09 PM PDT 24
Peak memory 200444 kb
Host smart-1a65b64d-5bb1-4bca-b4f7-99bcbabff317
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371003067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1371003067
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.2423735311
Short name T465
Test name
Test status
Simulation time 26907213 ps
CPU time 0.79 seconds
Started Jul 26 06:34:15 PM PDT 24
Finished Jul 26 06:34:16 PM PDT 24
Peak memory 200476 kb
Host smart-8db2ebf0-dde6-4c2f-9174-4c76d52d6c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423735311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.2423735311
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1847686629
Short name T248
Test name
Test status
Simulation time 15472624 ps
CPU time 0.73 seconds
Started Jul 26 06:34:13 PM PDT 24
Finished Jul 26 06:34:14 PM PDT 24
Peak memory 200492 kb
Host smart-56dff472-c60c-4205-aad9-cbc1283402b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847686629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.1847686629
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.539533902
Short name T358
Test name
Test status
Simulation time 18082584 ps
CPU time 0.73 seconds
Started Jul 26 06:34:14 PM PDT 24
Finished Jul 26 06:34:15 PM PDT 24
Peak memory 200652 kb
Host smart-90202b69-528b-45c9-b709-5478b1033dd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539533902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.539533902
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3059498439
Short name T292
Test name
Test status
Simulation time 12088408 ps
CPU time 0.74 seconds
Started Jul 26 06:34:15 PM PDT 24
Finished Jul 26 06:34:16 PM PDT 24
Peak memory 200432 kb
Host smart-e5280d78-eebe-4506-8ef3-5c32bfd19193
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059498439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3059498439
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.2148199661
Short name T191
Test name
Test status
Simulation time 21082137 ps
CPU time 0.87 seconds
Started Jul 26 06:34:15 PM PDT 24
Finished Jul 26 06:34:16 PM PDT 24
Peak memory 200424 kb
Host smart-40390157-a766-49a5-bcfb-33a570d82a7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148199661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2148199661
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.2668682533
Short name T567
Test name
Test status
Simulation time 1162057361 ps
CPU time 9.02 seconds
Started Jul 26 06:34:16 PM PDT 24
Finished Jul 26 06:34:25 PM PDT 24
Peak memory 200544 kb
Host smart-5778337c-851c-46cc-b330-1e07d6a37e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668682533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.2668682533
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.1463309528
Short name T506
Test name
Test status
Simulation time 275806217 ps
CPU time 1.71 seconds
Started Jul 26 06:34:16 PM PDT 24
Finished Jul 26 06:34:18 PM PDT 24
Peak memory 200568 kb
Host smart-83e27eb3-a624-4715-b916-7472ebb48e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463309528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.1463309528
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.1338080814
Short name T447
Test name
Test status
Simulation time 13863764 ps
CPU time 0.76 seconds
Started Jul 26 06:34:13 PM PDT 24
Finished Jul 26 06:34:14 PM PDT 24
Peak memory 200484 kb
Host smart-db922605-781d-4fa5-bb93-9c58c6ca5acc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338080814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.1338080814
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3954114266
Short name T581
Test name
Test status
Simulation time 40452112 ps
CPU time 0.84 seconds
Started Jul 26 06:34:16 PM PDT 24
Finished Jul 26 06:34:17 PM PDT 24
Peak memory 200328 kb
Host smart-a8ad7f64-ce48-4920-ba8d-61d493367e02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954114266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3954114266
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2129516814
Short name T784
Test name
Test status
Simulation time 23977290 ps
CPU time 0.9 seconds
Started Jul 26 06:34:15 PM PDT 24
Finished Jul 26 06:34:16 PM PDT 24
Peak memory 200464 kb
Host smart-72e6925d-b56f-4a2d-9736-dc6ac4ef859c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129516814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.2129516814
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.1910267403
Short name T239
Test name
Test status
Simulation time 14917674 ps
CPU time 0.75 seconds
Started Jul 26 06:34:16 PM PDT 24
Finished Jul 26 06:34:17 PM PDT 24
Peak memory 200408 kb
Host smart-1c00afe4-79d2-4873-b63f-9d96112e44a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910267403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1910267403
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.457665014
Short name T157
Test name
Test status
Simulation time 206318661 ps
CPU time 1.39 seconds
Started Jul 26 06:34:15 PM PDT 24
Finished Jul 26 06:34:17 PM PDT 24
Peak memory 200400 kb
Host smart-aa2ba0d1-34c9-4cdd-b923-09bac5012c44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457665014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.457665014
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.1681855353
Short name T141
Test name
Test status
Simulation time 22800621 ps
CPU time 0.84 seconds
Started Jul 26 06:34:17 PM PDT 24
Finished Jul 26 06:34:18 PM PDT 24
Peak memory 200380 kb
Host smart-d94b59b9-21d8-442b-9a1f-fdf3e670eae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681855353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.1681855353
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.3397155361
Short name T446
Test name
Test status
Simulation time 23196324 ps
CPU time 0.9 seconds
Started Jul 26 06:34:16 PM PDT 24
Finished Jul 26 06:34:17 PM PDT 24
Peak memory 200480 kb
Host smart-a9d36902-ded5-43ca-9c41-3f7894c1e2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397155361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.3397155361
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.4248981915
Short name T40
Test name
Test status
Simulation time 213735349795 ps
CPU time 1199.69 seconds
Started Jul 26 06:34:17 PM PDT 24
Finished Jul 26 06:54:17 PM PDT 24
Peak memory 209120 kb
Host smart-a8ba336e-bd82-4f9d-be4b-00b73cf1338b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4248981915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.4248981915
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.4186299652
Short name T226
Test name
Test status
Simulation time 31160667 ps
CPU time 0.99 seconds
Started Jul 26 06:34:14 PM PDT 24
Finished Jul 26 06:34:15 PM PDT 24
Peak memory 200432 kb
Host smart-3358dd6b-8477-45a8-8f16-0a7406d8e69b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186299652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.4186299652
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.65080679
Short name T251
Test name
Test status
Simulation time 42195975 ps
CPU time 0.83 seconds
Started Jul 26 06:34:23 PM PDT 24
Finished Jul 26 06:34:24 PM PDT 24
Peak memory 200472 kb
Host smart-499e1965-c28e-4420-8efe-5ee418ef4a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65080679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmg
r_alert_test.65080679
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.2809390607
Short name T215
Test name
Test status
Simulation time 39088330 ps
CPU time 0.85 seconds
Started Jul 26 06:34:24 PM PDT 24
Finished Jul 26 06:34:25 PM PDT 24
Peak memory 200504 kb
Host smart-0820f33c-52cf-4e12-96d2-7387ff66427f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809390607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.2809390607
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.915776849
Short name T546
Test name
Test status
Simulation time 65288661 ps
CPU time 0.85 seconds
Started Jul 26 06:34:21 PM PDT 24
Finished Jul 26 06:34:22 PM PDT 24
Peak memory 200408 kb
Host smart-6c8b50a0-79c4-4a07-ba15-71c815a4e536
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915776849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.915776849
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.773078868
Short name T681
Test name
Test status
Simulation time 56945561 ps
CPU time 1.06 seconds
Started Jul 26 06:34:24 PM PDT 24
Finished Jul 26 06:34:26 PM PDT 24
Peak memory 200412 kb
Host smart-9f1846bd-1286-4f1e-9fb2-8e0458bd6a01
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773078868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_div_intersig_mubi.773078868
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.1816190530
Short name T365
Test name
Test status
Simulation time 19974824 ps
CPU time 0.8 seconds
Started Jul 26 06:34:16 PM PDT 24
Finished Jul 26 06:34:17 PM PDT 24
Peak memory 200464 kb
Host smart-4ca3fe35-8c6e-4691-9e70-02173a43fbfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816190530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1816190530
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.4288122693
Short name T27
Test name
Test status
Simulation time 2120522997 ps
CPU time 17.44 seconds
Started Jul 26 06:34:16 PM PDT 24
Finished Jul 26 06:34:33 PM PDT 24
Peak memory 200756 kb
Host smart-0c0d6fb2-895d-4745-b575-ab8f106f4588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288122693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.4288122693
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.2495191903
Short name T431
Test name
Test status
Simulation time 2211431553 ps
CPU time 9.12 seconds
Started Jul 26 06:34:14 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200844 kb
Host smart-f0c158e5-2393-4c1a-949e-3087aa7cd76c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495191903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.2495191903
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.3910797351
Short name T260
Test name
Test status
Simulation time 15965404 ps
CPU time 0.76 seconds
Started Jul 26 06:34:23 PM PDT 24
Finished Jul 26 06:34:24 PM PDT 24
Peak memory 200468 kb
Host smart-a3d837ea-191b-4972-8021-1ade8fb66c9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910797351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.3910797351
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1880999815
Short name T143
Test name
Test status
Simulation time 15733981 ps
CPU time 0.76 seconds
Started Jul 26 06:34:20 PM PDT 24
Finished Jul 26 06:34:21 PM PDT 24
Peak memory 200488 kb
Host smart-4f5d73d1-7177-4ae1-8579-40073e0da116
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880999815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.1880999815
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.4144004442
Short name T800
Test name
Test status
Simulation time 39483008 ps
CPU time 0.86 seconds
Started Jul 26 06:34:24 PM PDT 24
Finished Jul 26 06:34:25 PM PDT 24
Peak memory 200456 kb
Host smart-bcd24152-d1a1-4cb0-983a-e2693d6f00b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144004442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.4144004442
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.1809591279
Short name T544
Test name
Test status
Simulation time 36290549 ps
CPU time 0.84 seconds
Started Jul 26 06:34:22 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200396 kb
Host smart-fa806e24-2647-44b3-86ee-986f8202a731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809591279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.1809591279
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.1801541855
Short name T311
Test name
Test status
Simulation time 104464970 ps
CPU time 1.2 seconds
Started Jul 26 06:34:26 PM PDT 24
Finished Jul 26 06:34:27 PM PDT 24
Peak memory 200368 kb
Host smart-b4cb47a6-1985-48b0-b749-5df0466352a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801541855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1801541855
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.3524786540
Short name T116
Test name
Test status
Simulation time 44743557 ps
CPU time 0.88 seconds
Started Jul 26 06:34:17 PM PDT 24
Finished Jul 26 06:34:18 PM PDT 24
Peak memory 200428 kb
Host smart-3cb5aacb-4f14-4c25-9aec-852a6cbeb128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524786540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3524786540
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.2200545497
Short name T489
Test name
Test status
Simulation time 4538204009 ps
CPU time 19.44 seconds
Started Jul 26 06:34:22 PM PDT 24
Finished Jul 26 06:34:42 PM PDT 24
Peak memory 200824 kb
Host smart-b21020e5-8c2d-4713-a352-da136256534a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200545497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.2200545497
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.1997088062
Short name T734
Test name
Test status
Simulation time 95382580 ps
CPU time 0.93 seconds
Started Jul 26 06:34:21 PM PDT 24
Finished Jul 26 06:34:22 PM PDT 24
Peak memory 200444 kb
Host smart-594a1707-8a26-4813-b12f-b92d9c02cadd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997088062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1997088062
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.1320217541
Short name T549
Test name
Test status
Simulation time 22960469 ps
CPU time 0.84 seconds
Started Jul 26 06:34:23 PM PDT 24
Finished Jul 26 06:34:24 PM PDT 24
Peak memory 200476 kb
Host smart-cc1f6e17-d47f-4b6f-8655-bbc1064c0941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320217541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.1320217541
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.630390074
Short name T80
Test name
Test status
Simulation time 60535373 ps
CPU time 0.9 seconds
Started Jul 26 06:34:24 PM PDT 24
Finished Jul 26 06:34:25 PM PDT 24
Peak memory 200504 kb
Host smart-e31b71f0-3131-4886-813c-1a16d49fb55f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630390074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.630390074
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.3371742622
Short name T528
Test name
Test status
Simulation time 22412165 ps
CPU time 0.76 seconds
Started Jul 26 06:34:23 PM PDT 24
Finished Jul 26 06:34:24 PM PDT 24
Peak memory 200352 kb
Host smart-44d41531-96b8-49dd-a622-41fd3e076397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371742622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.3371742622
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.1654643251
Short name T218
Test name
Test status
Simulation time 12018581 ps
CPU time 0.74 seconds
Started Jul 26 06:34:22 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200476 kb
Host smart-76ba8ce3-1f0a-4499-bebc-de8fe902a061
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654643251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.1654643251
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1007158137
Short name T443
Test name
Test status
Simulation time 25922888 ps
CPU time 0.8 seconds
Started Jul 26 06:34:22 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200456 kb
Host smart-193e2b8a-058c-422f-8740-8dfdb95ff883
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007158137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1007158137
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.3801481994
Short name T223
Test name
Test status
Simulation time 195536517 ps
CPU time 2.06 seconds
Started Jul 26 06:34:25 PM PDT 24
Finished Jul 26 06:34:27 PM PDT 24
Peak memory 200500 kb
Host smart-aeaecd6c-9ae9-482c-8f95-72908502742b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801481994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3801481994
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.3398767551
Short name T18
Test name
Test status
Simulation time 506226409 ps
CPU time 3.17 seconds
Started Jul 26 06:34:24 PM PDT 24
Finished Jul 26 06:34:27 PM PDT 24
Peak memory 200584 kb
Host smart-8a9f75e0-6a04-4669-9c9c-9503d8f35fe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398767551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.3398767551
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.2408986635
Short name T541
Test name
Test status
Simulation time 41722822 ps
CPU time 0.95 seconds
Started Jul 26 06:34:26 PM PDT 24
Finished Jul 26 06:34:27 PM PDT 24
Peak memory 200428 kb
Host smart-9e2982ef-6737-4e5e-8e37-48eeb8394f31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408986635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.2408986635
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1073294191
Short name T565
Test name
Test status
Simulation time 50147324 ps
CPU time 0.99 seconds
Started Jul 26 06:34:22 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200472 kb
Host smart-28637173-41ec-4049-ba92-56b54a683fde
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073294191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1073294191
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3141614595
Short name T531
Test name
Test status
Simulation time 19366836 ps
CPU time 0.81 seconds
Started Jul 26 06:34:22 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200428 kb
Host smart-c6909952-2146-4b84-9010-7740fb9aeda7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141614595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.3141614595
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.1700939137
Short name T468
Test name
Test status
Simulation time 30805802 ps
CPU time 0.8 seconds
Started Jul 26 06:34:26 PM PDT 24
Finished Jul 26 06:34:27 PM PDT 24
Peak memory 200416 kb
Host smart-fa4002bd-8636-4626-bd43-58fd4533ee97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700939137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.1700939137
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.906289420
Short name T461
Test name
Test status
Simulation time 1231207599 ps
CPU time 7.38 seconds
Started Jul 26 06:34:25 PM PDT 24
Finished Jul 26 06:34:32 PM PDT 24
Peak memory 200616 kb
Host smart-5c5bfe3b-1ab4-46e1-9e64-c9a703c45efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906289420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.906289420
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.1789632780
Short name T462
Test name
Test status
Simulation time 21617153 ps
CPU time 0.85 seconds
Started Jul 26 06:34:24 PM PDT 24
Finished Jul 26 06:34:25 PM PDT 24
Peak memory 200396 kb
Host smart-3fc34b93-a876-4367-9433-bea6a46f405e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789632780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1789632780
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.3249787753
Short name T641
Test name
Test status
Simulation time 4023838138 ps
CPU time 18.3 seconds
Started Jul 26 06:34:24 PM PDT 24
Finished Jul 26 06:34:42 PM PDT 24
Peak memory 200832 kb
Host smart-044b750d-2809-48f2-9d81-9ead0f7cc151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249787753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.3249787753
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.3824136236
Short name T173
Test name
Test status
Simulation time 40607567 ps
CPU time 1.15 seconds
Started Jul 26 06:34:21 PM PDT 24
Finished Jul 26 06:34:23 PM PDT 24
Peak memory 200456 kb
Host smart-9aeedf5e-8ed9-4d98-b0f4-706d65666701
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824136236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3824136236
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.1405169490
Short name T368
Test name
Test status
Simulation time 37498826 ps
CPU time 0.88 seconds
Started Jul 26 06:32:22 PM PDT 24
Finished Jul 26 06:32:23 PM PDT 24
Peak memory 200728 kb
Host smart-ac487b29-f64b-42e2-aaf9-001b08f288bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405169490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.1405169490
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1794712614
Short name T96
Test name
Test status
Simulation time 16475383 ps
CPU time 0.77 seconds
Started Jul 26 06:32:17 PM PDT 24
Finished Jul 26 06:32:18 PM PDT 24
Peak memory 200444 kb
Host smart-762fa845-1760-4203-9b97-39ff42a8f3de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794712614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1794712614
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.1807983151
Short name T821
Test name
Test status
Simulation time 21974874 ps
CPU time 0.75 seconds
Started Jul 26 06:32:18 PM PDT 24
Finished Jul 26 06:32:18 PM PDT 24
Peak memory 200392 kb
Host smart-735e501f-6fdf-4b9a-94cb-dec50011c1de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807983151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.1807983151
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.130427791
Short name T229
Test name
Test status
Simulation time 42978548 ps
CPU time 0.97 seconds
Started Jul 26 06:32:25 PM PDT 24
Finished Jul 26 06:32:26 PM PDT 24
Peak memory 200472 kb
Host smart-81f910e0-1666-4f66-bb49-f97cf7dc3fe7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130427791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.clkmgr_div_intersig_mubi.130427791
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.1732403227
Short name T296
Test name
Test status
Simulation time 24072701 ps
CPU time 0.81 seconds
Started Jul 26 06:32:17 PM PDT 24
Finished Jul 26 06:32:18 PM PDT 24
Peak memory 200452 kb
Host smart-1a6f9fee-ae74-4670-a44c-8dc833921e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732403227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1732403227
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.1907733512
Short name T25
Test name
Test status
Simulation time 2363017787 ps
CPU time 13.43 seconds
Started Jul 26 06:32:18 PM PDT 24
Finished Jul 26 06:32:32 PM PDT 24
Peak memory 200788 kb
Host smart-cbc82b48-47ce-4c44-ba4a-003a01438738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907733512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.1907733512
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.4111547663
Short name T823
Test name
Test status
Simulation time 1941359255 ps
CPU time 13.77 seconds
Started Jul 26 06:32:17 PM PDT 24
Finished Jul 26 06:32:31 PM PDT 24
Peak memory 200556 kb
Host smart-646bc4d0-6ffb-4419-a87c-3538b514815e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111547663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.4111547663
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.2535395081
Short name T510
Test name
Test status
Simulation time 51116913 ps
CPU time 0.85 seconds
Started Jul 26 06:32:17 PM PDT 24
Finished Jul 26 06:32:18 PM PDT 24
Peak memory 200428 kb
Host smart-1ea6376e-1ee8-4d1e-8657-8be64dc3eaaf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535395081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.2535395081
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.393883483
Short name T392
Test name
Test status
Simulation time 11850786 ps
CPU time 0.71 seconds
Started Jul 26 06:32:17 PM PDT 24
Finished Jul 26 06:32:18 PM PDT 24
Peak memory 200488 kb
Host smart-b5854849-6ad0-4a81-8e11-d60d4f1145c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393883483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_clk_byp_req_intersig_mubi.393883483
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.2182054453
Short name T665
Test name
Test status
Simulation time 21809424 ps
CPU time 0.87 seconds
Started Jul 26 06:32:18 PM PDT 24
Finished Jul 26 06:32:19 PM PDT 24
Peak memory 200440 kb
Host smart-72e6369f-f647-4e18-80e7-956b12b93f6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182054453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.2182054453
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.3853127005
Short name T205
Test name
Test status
Simulation time 16144202 ps
CPU time 0.74 seconds
Started Jul 26 06:32:17 PM PDT 24
Finished Jul 26 06:32:18 PM PDT 24
Peak memory 200424 kb
Host smart-c8e0e35c-46d7-4b8c-a97b-43ee93c00300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853127005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3853127005
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.4227804489
Short name T769
Test name
Test status
Simulation time 1586028805 ps
CPU time 5.27 seconds
Started Jul 26 06:32:22 PM PDT 24
Finished Jul 26 06:32:28 PM PDT 24
Peak memory 200664 kb
Host smart-914d75c5-9ad6-4ac0-bce6-a3cc43b41b0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227804489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.4227804489
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.3980720733
Short name T42
Test name
Test status
Simulation time 393095771 ps
CPU time 3.15 seconds
Started Jul 26 06:32:23 PM PDT 24
Finished Jul 26 06:32:27 PM PDT 24
Peak memory 221448 kb
Host smart-bb60c880-2eea-4c87-9a0c-2877b6e6febb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980720733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.3980720733
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.2761138928
Short name T380
Test name
Test status
Simulation time 15231746 ps
CPU time 0.86 seconds
Started Jul 26 06:32:16 PM PDT 24
Finished Jul 26 06:32:17 PM PDT 24
Peak memory 200432 kb
Host smart-b4e1a8de-bd5d-4563-8282-33f31ea9c8bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761138928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2761138928
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.2158436656
Short name T547
Test name
Test status
Simulation time 3183151207 ps
CPU time 25.07 seconds
Started Jul 26 06:32:26 PM PDT 24
Finished Jul 26 06:32:51 PM PDT 24
Peak memory 200836 kb
Host smart-f9b27ee2-f1b6-4c6e-ae64-d5ce9f7bf1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158436656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.2158436656
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.2802952496
Short name T382
Test name
Test status
Simulation time 314679843 ps
CPU time 1.89 seconds
Started Jul 26 06:32:19 PM PDT 24
Finished Jul 26 06:32:21 PM PDT 24
Peak memory 200420 kb
Host smart-601a9f92-da84-4b90-b6da-c33c3275bcbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802952496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2802952496
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.817173560
Short name T305
Test name
Test status
Simulation time 24695419 ps
CPU time 0.79 seconds
Started Jul 26 06:34:36 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200484 kb
Host smart-6ed126d8-d7cd-4abd-994e-698041158a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817173560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkm
gr_alert_test.817173560
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.964324932
Short name T622
Test name
Test status
Simulation time 46836290 ps
CPU time 0.88 seconds
Started Jul 26 06:34:26 PM PDT 24
Finished Jul 26 06:34:28 PM PDT 24
Peak memory 200436 kb
Host smart-9b239523-ef02-4adf-b241-316a1a852614
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964324932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.964324932
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.3930418867
Short name T314
Test name
Test status
Simulation time 21824607 ps
CPU time 0.75 seconds
Started Jul 26 06:34:28 PM PDT 24
Finished Jul 26 06:34:29 PM PDT 24
Peak memory 200384 kb
Host smart-c909e437-ca92-4653-9c77-3fc6ee2c408a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930418867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.3930418867
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.2557026310
Short name T415
Test name
Test status
Simulation time 86227636 ps
CPU time 1.13 seconds
Started Jul 26 06:34:27 PM PDT 24
Finished Jul 26 06:34:29 PM PDT 24
Peak memory 200460 kb
Host smart-0be55662-028f-416d-aef6-e97f19439f65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557026310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.2557026310
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.4225114922
Short name T279
Test name
Test status
Simulation time 67846373 ps
CPU time 1.03 seconds
Started Jul 26 06:34:28 PM PDT 24
Finished Jul 26 06:34:30 PM PDT 24
Peak memory 200464 kb
Host smart-2d6fee7c-a6f9-485d-bd3f-57c22841f150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225114922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.4225114922
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.1599399872
Short name T557
Test name
Test status
Simulation time 1162324361 ps
CPU time 8.19 seconds
Started Jul 26 06:34:28 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200540 kb
Host smart-70de4c3a-c9b5-44c3-b4a9-561ab1d843e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599399872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.1599399872
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.3995119620
Short name T435
Test name
Test status
Simulation time 861820017 ps
CPU time 4.93 seconds
Started Jul 26 06:34:28 PM PDT 24
Finished Jul 26 06:34:33 PM PDT 24
Peak memory 200556 kb
Host smart-73d80f8e-b287-4ef5-bf65-39ce9365ddaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995119620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.3995119620
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.3829032546
Short name T763
Test name
Test status
Simulation time 38189434 ps
CPU time 0.89 seconds
Started Jul 26 06:34:26 PM PDT 24
Finished Jul 26 06:34:28 PM PDT 24
Peak memory 200440 kb
Host smart-ec2fd0f4-9c83-486d-abfa-88e31464b5bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829032546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.3829032546
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.949499269
Short name T372
Test name
Test status
Simulation time 33643650 ps
CPU time 0.95 seconds
Started Jul 26 06:34:26 PM PDT 24
Finished Jul 26 06:34:28 PM PDT 24
Peak memory 200440 kb
Host smart-4492dd41-519a-4edd-a724-9a340d1586d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949499269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_clk_byp_req_intersig_mubi.949499269
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3663394805
Short name T607
Test name
Test status
Simulation time 42567994 ps
CPU time 0.83 seconds
Started Jul 26 06:34:28 PM PDT 24
Finished Jul 26 06:34:29 PM PDT 24
Peak memory 200428 kb
Host smart-ee052698-af22-4454-9681-62aa27201b43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663394805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3663394805
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.1098034111
Short name T555
Test name
Test status
Simulation time 105981461 ps
CPU time 1.03 seconds
Started Jul 26 06:34:28 PM PDT 24
Finished Jul 26 06:34:30 PM PDT 24
Peak memory 200336 kb
Host smart-5152cf70-8fd6-47be-be8f-82c533cba16d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098034111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.1098034111
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.665231428
Short name T726
Test name
Test status
Simulation time 1273974561 ps
CPU time 5.18 seconds
Started Jul 26 06:34:35 PM PDT 24
Finished Jul 26 06:34:40 PM PDT 24
Peak memory 200664 kb
Host smart-8090ce7b-4664-425f-8195-9f47bea4b5cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665231428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.665231428
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.1967207638
Short name T135
Test name
Test status
Simulation time 27749914 ps
CPU time 0.88 seconds
Started Jul 26 06:34:20 PM PDT 24
Finished Jul 26 06:34:21 PM PDT 24
Peak memory 200404 kb
Host smart-4171f420-76d5-4072-8cc2-1e2ebaf30f4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967207638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.1967207638
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.4102081350
Short name T344
Test name
Test status
Simulation time 2601568916 ps
CPU time 19.8 seconds
Started Jul 26 06:34:35 PM PDT 24
Finished Jul 26 06:34:55 PM PDT 24
Peak memory 200876 kb
Host smart-55970123-e939-42b2-910c-c7ddf1256454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102081350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.4102081350
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.715126686
Short name T767
Test name
Test status
Simulation time 60462537 ps
CPU time 1.13 seconds
Started Jul 26 06:34:27 PM PDT 24
Finished Jul 26 06:34:28 PM PDT 24
Peak memory 200476 kb
Host smart-8a93cbbc-1703-461c-81ab-77b505ea7373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715126686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.715126686
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1710151495
Short name T751
Test name
Test status
Simulation time 21957203 ps
CPU time 0.85 seconds
Started Jul 26 06:34:37 PM PDT 24
Finished Jul 26 06:34:38 PM PDT 24
Peak memory 200480 kb
Host smart-653fa76f-0489-4808-becf-bbac5003ce9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710151495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1710151495
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1844513443
Short name T601
Test name
Test status
Simulation time 14821953 ps
CPU time 0.74 seconds
Started Jul 26 06:34:36 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200428 kb
Host smart-7b1ec8f4-be39-490b-8a03-2a1e3ef7cca0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844513443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.1844513443
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.1873343276
Short name T419
Test name
Test status
Simulation time 13976062 ps
CPU time 0.69 seconds
Started Jul 26 06:34:36 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 199644 kb
Host smart-40a6b1f7-5e69-4155-a4e4-23ae9528cdda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873343276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.1873343276
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.2284763374
Short name T317
Test name
Test status
Simulation time 73030208 ps
CPU time 1 seconds
Started Jul 26 06:34:36 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200472 kb
Host smart-41e604f9-e82d-466e-9ae1-fa80cad5fa66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284763374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.2284763374
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.4170639469
Short name T629
Test name
Test status
Simulation time 16784945 ps
CPU time 0.78 seconds
Started Jul 26 06:34:37 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200440 kb
Host smart-cef6b3aa-6e5e-4b8b-bb4c-dda39dae45b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170639469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.4170639469
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1846598099
Short name T815
Test name
Test status
Simulation time 558366967 ps
CPU time 4.85 seconds
Started Jul 26 06:34:34 PM PDT 24
Finished Jul 26 06:34:39 PM PDT 24
Peak memory 200472 kb
Host smart-58a38038-e5cb-4cdb-890a-694c8371b8fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846598099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1846598099
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.3780081465
Short name T695
Test name
Test status
Simulation time 160858479 ps
CPU time 1.25 seconds
Started Jul 26 06:34:37 PM PDT 24
Finished Jul 26 06:34:39 PM PDT 24
Peak memory 200596 kb
Host smart-30f7a3a7-24d6-4c40-a3a9-ba6706054b4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780081465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.3780081465
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.973049780
Short name T474
Test name
Test status
Simulation time 49839505 ps
CPU time 1.03 seconds
Started Jul 26 06:34:37 PM PDT 24
Finished Jul 26 06:34:38 PM PDT 24
Peak memory 200464 kb
Host smart-e6f48858-c7cf-428d-935e-73950e362dcd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973049780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_idle_intersig_mubi.973049780
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3704704188
Short name T762
Test name
Test status
Simulation time 15352417 ps
CPU time 0.8 seconds
Started Jul 26 06:34:35 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200480 kb
Host smart-17fc65e1-4373-4818-a945-61cec85791d7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704704188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3704704188
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.3067022954
Short name T346
Test name
Test status
Simulation time 14325157 ps
CPU time 0.74 seconds
Started Jul 26 06:34:38 PM PDT 24
Finished Jul 26 06:34:39 PM PDT 24
Peak memory 200356 kb
Host smart-887be1a2-2491-4602-8b2c-e9e8eaeda3a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067022954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.3067022954
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.1611932871
Short name T664
Test name
Test status
Simulation time 32297998 ps
CPU time 0.77 seconds
Started Jul 26 06:34:35 PM PDT 24
Finished Jul 26 06:34:36 PM PDT 24
Peak memory 200448 kb
Host smart-29689fbf-d139-4558-8b7a-921627d5b641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611932871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1611932871
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.944124046
Short name T425
Test name
Test status
Simulation time 986602974 ps
CPU time 5.46 seconds
Started Jul 26 06:34:38 PM PDT 24
Finished Jul 26 06:34:44 PM PDT 24
Peak memory 200664 kb
Host smart-4b1e051e-6df4-4688-9f59-db5ac29511d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944124046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.944124046
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.4158476649
Short name T138
Test name
Test status
Simulation time 91412795 ps
CPU time 1.12 seconds
Started Jul 26 06:34:37 PM PDT 24
Finished Jul 26 06:34:38 PM PDT 24
Peak memory 200696 kb
Host smart-512800c0-8093-4eaa-bc7f-236a0b04a242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158476649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.4158476649
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.3687534226
Short name T692
Test name
Test status
Simulation time 2421927010 ps
CPU time 9.3 seconds
Started Jul 26 06:34:36 PM PDT 24
Finished Jul 26 06:34:46 PM PDT 24
Peak memory 200832 kb
Host smart-21ed78f2-9628-412d-87fd-5c7a354ad51a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687534226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.3687534226
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.2796691652
Short name T682
Test name
Test status
Simulation time 27127071 ps
CPU time 0.92 seconds
Started Jul 26 06:34:33 PM PDT 24
Finished Jul 26 06:34:34 PM PDT 24
Peak memory 200480 kb
Host smart-f518cb65-bf87-4e1c-b393-ecfe192115b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796691652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.2796691652
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.2722319532
Short name T671
Test name
Test status
Simulation time 69190894 ps
CPU time 0.93 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:44 PM PDT 24
Peak memory 200520 kb
Host smart-ad0aaf7e-7b43-461f-8d9c-3a6a0dc493af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722319532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.2722319532
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.573121823
Short name T338
Test name
Test status
Simulation time 18189648 ps
CPU time 0.85 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:44 PM PDT 24
Peak memory 200500 kb
Host smart-20459b82-f3f3-4e4c-8fc3-e2d71078536b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573121823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.573121823
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.3668756897
Short name T48
Test name
Test status
Simulation time 13110909 ps
CPU time 0.72 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:44 PM PDT 24
Peak memory 199656 kb
Host smart-9530203a-83cc-44c3-a048-25a4fad159b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668756897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3668756897
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2074635569
Short name T635
Test name
Test status
Simulation time 24422196 ps
CPU time 0.92 seconds
Started Jul 26 06:34:44 PM PDT 24
Finished Jul 26 06:34:45 PM PDT 24
Peak memory 200488 kb
Host smart-0c311cf7-8dc6-4970-b821-b772af0d8e9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074635569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2074635569
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.1573521365
Short name T680
Test name
Test status
Simulation time 26020283 ps
CPU time 0.82 seconds
Started Jul 26 06:34:35 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200492 kb
Host smart-604dad4b-752e-4753-9d7e-32b52e799d08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573521365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1573521365
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.17885955
Short name T1
Test name
Test status
Simulation time 2361162272 ps
CPU time 17.74 seconds
Started Jul 26 06:34:36 PM PDT 24
Finished Jul 26 06:34:54 PM PDT 24
Peak memory 200692 kb
Host smart-921ad91d-a200-4970-b7a7-1baa95a549d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17885955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.17885955
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.3574895666
Short name T686
Test name
Test status
Simulation time 135941078 ps
CPU time 1.56 seconds
Started Jul 26 06:34:38 PM PDT 24
Finished Jul 26 06:34:40 PM PDT 24
Peak memory 200484 kb
Host smart-c646c1c9-222e-4f68-88d4-96bba3009a5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574895666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.3574895666
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.4225771125
Short name T273
Test name
Test status
Simulation time 41462962 ps
CPU time 0.89 seconds
Started Jul 26 06:34:47 PM PDT 24
Finished Jul 26 06:34:48 PM PDT 24
Peak memory 200464 kb
Host smart-7b9c313f-0a94-44f2-93f9-67888d2a0d0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225771125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.4225771125
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1501678489
Short name T678
Test name
Test status
Simulation time 53050851 ps
CPU time 0.9 seconds
Started Jul 26 06:34:40 PM PDT 24
Finished Jul 26 06:34:41 PM PDT 24
Peak memory 200456 kb
Host smart-5b2b326e-2236-42c5-a139-6eb57af01481
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501678489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.1501678489
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3178999982
Short name T370
Test name
Test status
Simulation time 47091638 ps
CPU time 0.87 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:44 PM PDT 24
Peak memory 200460 kb
Host smart-9919b429-1934-4066-8336-9be31ad8718f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178999982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.3178999982
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.2635421390
Short name T240
Test name
Test status
Simulation time 34868850 ps
CPU time 0.79 seconds
Started Jul 26 06:34:45 PM PDT 24
Finished Jul 26 06:34:46 PM PDT 24
Peak memory 200400 kb
Host smart-664ce705-2959-4e39-a147-853c013995f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635421390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.2635421390
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.1768345150
Short name T484
Test name
Test status
Simulation time 403134610 ps
CPU time 2.74 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:46 PM PDT 24
Peak memory 200464 kb
Host smart-7e895eda-68d5-4d01-95c1-f5aa37687b3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768345150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1768345150
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.3700591777
Short name T337
Test name
Test status
Simulation time 21963268 ps
CPU time 0.88 seconds
Started Jul 26 06:34:36 PM PDT 24
Finished Jul 26 06:34:37 PM PDT 24
Peak memory 200392 kb
Host smart-655c7010-100b-467c-81b9-14f8257efe56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700591777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3700591777
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.658080843
Short name T770
Test name
Test status
Simulation time 2522423657 ps
CPU time 10.57 seconds
Started Jul 26 06:34:46 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200828 kb
Host smart-f0838b9b-7f8c-42be-899e-49d09cde87ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658080843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.658080843
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.2882534156
Short name T516
Test name
Test status
Simulation time 229617642 ps
CPU time 1.54 seconds
Started Jul 26 06:34:41 PM PDT 24
Finished Jul 26 06:34:42 PM PDT 24
Peak memory 200456 kb
Host smart-19f98f17-ca7b-42dc-a146-e276bcf3ad81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882534156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2882534156
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1967875576
Short name T457
Test name
Test status
Simulation time 38666794 ps
CPU time 0.79 seconds
Started Jul 26 06:34:48 PM PDT 24
Finished Jul 26 06:34:49 PM PDT 24
Peak memory 200448 kb
Host smart-5e46eed7-5c03-495c-9222-82dedb72d7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967875576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1967875576
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3708800355
Short name T429
Test name
Test status
Simulation time 77259449 ps
CPU time 1.06 seconds
Started Jul 26 06:34:47 PM PDT 24
Finished Jul 26 06:34:48 PM PDT 24
Peak memory 200476 kb
Host smart-6b79b65b-51ac-4101-b14f-fb7e27b03cd4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708800355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.3708800355
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.1596984465
Short name T504
Test name
Test status
Simulation time 23088428 ps
CPU time 0.76 seconds
Started Jul 26 06:34:42 PM PDT 24
Finished Jul 26 06:34:43 PM PDT 24
Peak memory 199680 kb
Host smart-5f903bba-c5ec-4cc2-ac9b-f9dcbf4ae58d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596984465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1596984465
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.2584474399
Short name T393
Test name
Test status
Simulation time 58564696 ps
CPU time 1.04 seconds
Started Jul 26 06:34:52 PM PDT 24
Finished Jul 26 06:34:53 PM PDT 24
Peak memory 200484 kb
Host smart-11084796-ca62-4277-a41f-daefef0ee30b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584474399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.2584474399
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.1187392111
Short name T712
Test name
Test status
Simulation time 66539183 ps
CPU time 1.01 seconds
Started Jul 26 06:34:44 PM PDT 24
Finished Jul 26 06:34:46 PM PDT 24
Peak memory 200460 kb
Host smart-0b3bcb55-152e-4dca-be5a-ba8a59d14a68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187392111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1187392111
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.1419799765
Short name T269
Test name
Test status
Simulation time 1426534882 ps
CPU time 5.9 seconds
Started Jul 26 06:34:41 PM PDT 24
Finished Jul 26 06:34:47 PM PDT 24
Peak memory 200532 kb
Host smart-27c7ebee-a990-40ca-b4d6-47cf7f9bf721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419799765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.1419799765
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.1434747812
Short name T642
Test name
Test status
Simulation time 1942394697 ps
CPU time 10.02 seconds
Started Jul 26 06:34:47 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200588 kb
Host smart-58267f6b-7422-452c-8f2f-c3f76dbafd62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434747812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.1434747812
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2934777166
Short name T545
Test name
Test status
Simulation time 36581372 ps
CPU time 0.85 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:44 PM PDT 24
Peak memory 200460 kb
Host smart-2df362aa-88d9-4753-a859-377489300831
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934777166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.2934777166
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1316242195
Short name T569
Test name
Test status
Simulation time 208132737 ps
CPU time 1.43 seconds
Started Jul 26 06:34:44 PM PDT 24
Finished Jul 26 06:34:45 PM PDT 24
Peak memory 200484 kb
Host smart-ce244468-b83a-4701-94e0-3702ac4ab018
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316242195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1316242195
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.2162088137
Short name T186
Test name
Test status
Simulation time 26908747 ps
CPU time 0.83 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:44 PM PDT 24
Peak memory 200396 kb
Host smart-869ee8b8-4847-41fa-b736-578de1090a67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162088137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.2162088137
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.4004849378
Short name T494
Test name
Test status
Simulation time 44531731 ps
CPU time 0.91 seconds
Started Jul 26 06:34:44 PM PDT 24
Finished Jul 26 06:34:45 PM PDT 24
Peak memory 200428 kb
Host smart-a2d9cb41-7959-4827-a734-26b5bbc8e516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004849378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4004849378
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.294549479
Short name T385
Test name
Test status
Simulation time 6597793483 ps
CPU time 27.62 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:35:17 PM PDT 24
Peak memory 200836 kb
Host smart-00e95c20-4f65-44ff-bac6-22814c34ac1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294549479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.294549479
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.2504201907
Short name T724
Test name
Test status
Simulation time 17151667 ps
CPU time 0.74 seconds
Started Jul 26 06:34:43 PM PDT 24
Finished Jul 26 06:34:43 PM PDT 24
Peak memory 200440 kb
Host smart-6726792e-f16b-4724-8ee7-acf5c5756493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504201907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2504201907
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.952196805
Short name T789
Test name
Test status
Simulation time 46760595 ps
CPU time 0.83 seconds
Started Jul 26 06:34:48 PM PDT 24
Finished Jul 26 06:34:49 PM PDT 24
Peak memory 200480 kb
Host smart-187ec860-9695-45d5-88b2-04182a2f89d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952196805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkm
gr_alert_test.952196805
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.947992431
Short name T580
Test name
Test status
Simulation time 76564430 ps
CPU time 1.01 seconds
Started Jul 26 06:34:48 PM PDT 24
Finished Jul 26 06:34:49 PM PDT 24
Peak memory 200516 kb
Host smart-35e6c9e7-96b5-416a-8785-3b6cab6d3304
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947992431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.947992431
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.3289941759
Short name T430
Test name
Test status
Simulation time 42663914 ps
CPU time 0.83 seconds
Started Jul 26 06:34:50 PM PDT 24
Finished Jul 26 06:34:51 PM PDT 24
Peak memory 199644 kb
Host smart-26b7372c-7510-4dba-be8b-9f6eddc75967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289941759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.3289941759
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.3627417989
Short name T735
Test name
Test status
Simulation time 24157602 ps
CPU time 0.91 seconds
Started Jul 26 06:34:51 PM PDT 24
Finished Jul 26 06:34:52 PM PDT 24
Peak memory 200420 kb
Host smart-a0481ad6-fea4-4cb2-8e59-2a5e458457bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627417989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.3627417989
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.117954594
Short name T808
Test name
Test status
Simulation time 23416898 ps
CPU time 0.88 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:34:50 PM PDT 24
Peak memory 200440 kb
Host smart-8e3e3de4-6f77-4a6a-bd1d-a361ee923a4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117954594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.117954594
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.818133404
Short name T677
Test name
Test status
Simulation time 2002056142 ps
CPU time 8.23 seconds
Started Jul 26 06:34:51 PM PDT 24
Finished Jul 26 06:35:00 PM PDT 24
Peak memory 200696 kb
Host smart-dd75609c-5949-49de-943b-a92ab59d8991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818133404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.818133404
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.3789896492
Short name T648
Test name
Test status
Simulation time 1781547064 ps
CPU time 7.34 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200576 kb
Host smart-2bc6ebd1-0573-4d7c-a4cb-7aeff8e44799
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789896492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.3789896492
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.4287010902
Short name T543
Test name
Test status
Simulation time 43273145 ps
CPU time 1 seconds
Started Jul 26 06:34:53 PM PDT 24
Finished Jul 26 06:34:54 PM PDT 24
Peak memory 200452 kb
Host smart-d874057a-dd70-4d13-8a7a-bf3b66b5ea43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287010902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.4287010902
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.4157365273
Short name T491
Test name
Test status
Simulation time 17420939 ps
CPU time 0.78 seconds
Started Jul 26 06:34:51 PM PDT 24
Finished Jul 26 06:34:52 PM PDT 24
Peak memory 200324 kb
Host smart-7d239bfa-0e12-4ba0-ad45-58e17142ad90
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157365273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.4157365273
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1611773883
Short name T817
Test name
Test status
Simulation time 59048705 ps
CPU time 0.9 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:34:50 PM PDT 24
Peak memory 200440 kb
Host smart-5b914b2e-cc3d-4485-8791-36fd4bee32fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611773883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.1611773883
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.2455200707
Short name T438
Test name
Test status
Simulation time 24458768 ps
CPU time 0.78 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:34:50 PM PDT 24
Peak memory 200420 kb
Host smart-b6baf58a-64bc-427a-8875-8e3903d7a0a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455200707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2455200707
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.1629601555
Short name T161
Test name
Test status
Simulation time 1021206857 ps
CPU time 4.01 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:34:54 PM PDT 24
Peak memory 200648 kb
Host smart-39dd52cb-6934-44ea-860d-072504cf8b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629601555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1629601555
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.843280647
Short name T650
Test name
Test status
Simulation time 23407028 ps
CPU time 0.82 seconds
Started Jul 26 06:34:48 PM PDT 24
Finished Jul 26 06:34:49 PM PDT 24
Peak memory 200424 kb
Host smart-70e07a01-041f-4a6e-990c-cfdfc551b45c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843280647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.843280647
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.1537419396
Short name T137
Test name
Test status
Simulation time 11316064140 ps
CPU time 43.94 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:35:33 PM PDT 24
Peak memory 200840 kb
Host smart-78329280-89c1-4a1f-ad8f-50b2d708ee1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537419396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.1537419396
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.1310039737
Short name T70
Test name
Test status
Simulation time 47275786507 ps
CPU time 444.88 seconds
Started Jul 26 06:34:48 PM PDT 24
Finished Jul 26 06:42:13 PM PDT 24
Peak memory 209184 kb
Host smart-7b7c7dde-eb9d-460c-9463-30c77a57f3cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1310039737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.1310039737
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.clkmgr_trans.717777669
Short name T379
Test name
Test status
Simulation time 116500247 ps
CPU time 1.2 seconds
Started Jul 26 06:34:47 PM PDT 24
Finished Jul 26 06:34:49 PM PDT 24
Peak memory 200452 kb
Host smart-449d62be-f43f-478e-991c-de16df5f5ac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717777669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.717777669
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3286543354
Short name T654
Test name
Test status
Simulation time 21942257 ps
CPU time 0.84 seconds
Started Jul 26 06:34:57 PM PDT 24
Finished Jul 26 06:34:58 PM PDT 24
Peak memory 200472 kb
Host smart-513466db-aef7-448c-86dd-aa6623a2b5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286543354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3286543354
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.1334386414
Short name T404
Test name
Test status
Simulation time 49444375 ps
CPU time 0.89 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200428 kb
Host smart-13022f50-fcba-4fe4-87d1-9aab16a2de04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334386414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.1334386414
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.2602392511
Short name T450
Test name
Test status
Simulation time 40415562 ps
CPU time 0.75 seconds
Started Jul 26 06:34:50 PM PDT 24
Finished Jul 26 06:34:51 PM PDT 24
Peak memory 200352 kb
Host smart-c3a58007-d226-4c09-ac94-fe2cd21e830a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602392511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2602392511
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.2625666229
Short name T256
Test name
Test status
Simulation time 14529027 ps
CPU time 0.75 seconds
Started Jul 26 06:34:58 PM PDT 24
Finished Jul 26 06:34:59 PM PDT 24
Peak memory 200420 kb
Host smart-a413e7df-309c-4d27-b264-470c72255ff4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625666229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.2625666229
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3176205938
Short name T564
Test name
Test status
Simulation time 13513100 ps
CPU time 0.76 seconds
Started Jul 26 06:34:51 PM PDT 24
Finished Jul 26 06:34:52 PM PDT 24
Peak memory 200416 kb
Host smart-5eeb060d-7db4-4155-9cf1-678766fe5013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176205938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3176205938
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2759414937
Short name T11
Test name
Test status
Simulation time 2121090153 ps
CPU time 16.23 seconds
Started Jul 26 06:34:52 PM PDT 24
Finished Jul 26 06:35:08 PM PDT 24
Peak memory 200684 kb
Host smart-b23c46ab-6179-49b9-b2f9-958261fc06e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759414937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2759414937
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.3030000916
Short name T330
Test name
Test status
Simulation time 2509007371 ps
CPU time 9.06 seconds
Started Jul 26 06:34:49 PM PDT 24
Finished Jul 26 06:34:59 PM PDT 24
Peak memory 200824 kb
Host smart-dae24022-5d2e-4dbf-b434-f2c3c1054b16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030000916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.3030000916
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3401853711
Short name T263
Test name
Test status
Simulation time 23532774 ps
CPU time 0.9 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200484 kb
Host smart-bd157a1e-a199-4c1b-8448-81e9941fab15
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401853711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3401853711
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.1559479154
Short name T673
Test name
Test status
Simulation time 75790501 ps
CPU time 0.92 seconds
Started Jul 26 06:34:53 PM PDT 24
Finished Jul 26 06:34:54 PM PDT 24
Peak memory 200452 kb
Host smart-be3f3719-0ee9-40dc-a0ca-aee335814176
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559479154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.1559479154
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3298682031
Short name T788
Test name
Test status
Simulation time 20962248 ps
CPU time 0.81 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:56 PM PDT 24
Peak memory 200476 kb
Host smart-c0b6943f-d889-48ee-8759-ceace451fe23
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298682031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.3298682031
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.3612151158
Short name T266
Test name
Test status
Simulation time 12659595 ps
CPU time 0.78 seconds
Started Jul 26 06:34:51 PM PDT 24
Finished Jul 26 06:34:52 PM PDT 24
Peak memory 200376 kb
Host smart-ab170192-775d-4a0f-87f0-758bdc8959ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612151158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.3612151158
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.2464333243
Short name T30
Test name
Test status
Simulation time 829472888 ps
CPU time 3.05 seconds
Started Jul 26 06:34:55 PM PDT 24
Finished Jul 26 06:34:58 PM PDT 24
Peak memory 200640 kb
Host smart-4c9243ed-0a79-48b0-af4d-649eb53e1568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464333243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2464333243
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.3242011833
Short name T771
Test name
Test status
Simulation time 71954936 ps
CPU time 1.07 seconds
Started Jul 26 06:34:51 PM PDT 24
Finished Jul 26 06:34:52 PM PDT 24
Peak memory 200388 kb
Host smart-ad0453fc-f0a6-499f-879d-1f9ebc45d8f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242011833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.3242011833
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.4044328978
Short name T28
Test name
Test status
Simulation time 2653123177 ps
CPU time 13.99 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:35:10 PM PDT 24
Peak memory 200716 kb
Host smart-7e33feb4-69cb-49c1-a9c7-18fdaa52938b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044328978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.4044328978
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.1851829697
Short name T72
Test name
Test status
Simulation time 6713222782 ps
CPU time 101.71 seconds
Started Jul 26 06:34:55 PM PDT 24
Finished Jul 26 06:36:37 PM PDT 24
Peak memory 209172 kb
Host smart-822ebebb-54d9-42d9-a599-6e7a79387c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1851829697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.1851829697
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.2194492718
Short name T238
Test name
Test status
Simulation time 28413395 ps
CPU time 0.97 seconds
Started Jul 26 06:34:52 PM PDT 24
Finished Jul 26 06:34:53 PM PDT 24
Peak memory 200448 kb
Host smart-ae5ec5a3-bbbd-4d0f-956e-7be1c57095db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194492718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.2194492718
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3361469430
Short name T809
Test name
Test status
Simulation time 16266295 ps
CPU time 0.72 seconds
Started Jul 26 06:34:57 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200464 kb
Host smart-2044b0d6-ae5b-4f1a-ae32-d8c1dc076932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361469430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3361469430
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.2866925327
Short name T778
Test name
Test status
Simulation time 16178476 ps
CPU time 0.75 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200428 kb
Host smart-324a43f1-2dc2-4da8-8f9c-45787aae8a7b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866925327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.2866925327
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.630575228
Short name T54
Test name
Test status
Simulation time 75793967 ps
CPU time 0.92 seconds
Started Jul 26 06:34:55 PM PDT 24
Finished Jul 26 06:34:56 PM PDT 24
Peak memory 199688 kb
Host smart-c1031f2c-1582-4f0f-a242-ab76ab7dc425
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630575228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.630575228
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2181237495
Short name T761
Test name
Test status
Simulation time 24529459 ps
CPU time 0.9 seconds
Started Jul 26 06:34:55 PM PDT 24
Finished Jul 26 06:34:56 PM PDT 24
Peak memory 200488 kb
Host smart-82b2651c-2f71-4ae8-9c85-c21e7ee11e6d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181237495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.2181237495
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.1656215368
Short name T360
Test name
Test status
Simulation time 55353093 ps
CPU time 0.85 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200408 kb
Host smart-411c5830-f808-43b5-a09e-115fc9ff67af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656215368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1656215368
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.3893158918
Short name T253
Test name
Test status
Simulation time 232659994 ps
CPU time 1.66 seconds
Started Jul 26 06:35:01 PM PDT 24
Finished Jul 26 06:35:02 PM PDT 24
Peak memory 200448 kb
Host smart-67274b0f-b6b8-4b0a-bd4c-bf836e4b5d56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893158918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.3893158918
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.1430425373
Short name T633
Test name
Test status
Simulation time 146320562 ps
CPU time 1.4 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:58 PM PDT 24
Peak memory 200560 kb
Host smart-a46ecc21-a618-4620-bf24-cc4c4bd2d262
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430425373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.1430425373
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.2400675121
Short name T599
Test name
Test status
Simulation time 44957376 ps
CPU time 0.83 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200460 kb
Host smart-0fccd6db-355e-4643-81db-85209c5c95f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400675121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.2400675121
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.1877462234
Short name T306
Test name
Test status
Simulation time 23936769 ps
CPU time 0.87 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:34:57 PM PDT 24
Peak memory 200460 kb
Host smart-a3bfa662-c3a7-4984-a487-7d65116c2d3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877462234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.1877462234
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1158396182
Short name T148
Test name
Test status
Simulation time 18757769 ps
CPU time 0.78 seconds
Started Jul 26 06:34:55 PM PDT 24
Finished Jul 26 06:34:56 PM PDT 24
Peak memory 200428 kb
Host smart-7c280f24-1151-4236-8562-efbace778e83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158396182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.1158396182
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.529701886
Short name T299
Test name
Test status
Simulation time 14857279 ps
CPU time 0.75 seconds
Started Jul 26 06:34:57 PM PDT 24
Finished Jul 26 06:34:58 PM PDT 24
Peak memory 200424 kb
Host smart-2e50275f-af42-455b-b020-13e64fbd5070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529701886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.529701886
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.2609998536
Short name T721
Test name
Test status
Simulation time 106440993 ps
CPU time 1.17 seconds
Started Jul 26 06:34:54 PM PDT 24
Finished Jul 26 06:34:55 PM PDT 24
Peak memory 200696 kb
Host smart-53563c76-2b1a-4ddd-a29f-093b84dce383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609998536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2609998536
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.2220716859
Short name T754
Test name
Test status
Simulation time 21492448 ps
CPU time 0.84 seconds
Started Jul 26 06:35:00 PM PDT 24
Finished Jul 26 06:35:01 PM PDT 24
Peak memory 200380 kb
Host smart-4c2836ea-56cc-4035-8b46-11a83a6598dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220716859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.2220716859
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.2832359377
Short name T756
Test name
Test status
Simulation time 8211078168 ps
CPU time 61.63 seconds
Started Jul 26 06:34:56 PM PDT 24
Finished Jul 26 06:35:58 PM PDT 24
Peak memory 200876 kb
Host smart-7302bd19-d14f-4c03-95b4-97ae79b893f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832359377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.2832359377
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.3638128176
Short name T822
Test name
Test status
Simulation time 27059911623 ps
CPU time 270.42 seconds
Started Jul 26 06:34:55 PM PDT 24
Finished Jul 26 06:39:26 PM PDT 24
Peak memory 217256 kb
Host smart-c2a77d9c-12a2-474a-a556-010cc07c32a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3638128176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.3638128176
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1964117050
Short name T600
Test name
Test status
Simulation time 21999773 ps
CPU time 0.84 seconds
Started Jul 26 06:34:54 PM PDT 24
Finished Jul 26 06:34:55 PM PDT 24
Peak memory 200484 kb
Host smart-b1c6ca77-02bf-46a6-9d98-bd9537cf5ec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964117050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1964117050
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3384739327
Short name T197
Test name
Test status
Simulation time 50088974 ps
CPU time 0.83 seconds
Started Jul 26 06:35:06 PM PDT 24
Finished Jul 26 06:35:07 PM PDT 24
Peak memory 200428 kb
Host smart-b7598609-1cd2-4612-9b9f-04019dbfafd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384739327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3384739327
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.3448655059
Short name T713
Test name
Test status
Simulation time 19846212 ps
CPU time 0.74 seconds
Started Jul 26 06:35:04 PM PDT 24
Finished Jul 26 06:35:05 PM PDT 24
Peak memory 200460 kb
Host smart-be9bae33-5d47-4c21-a8cd-d9f88384e03b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448655059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.3448655059
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.3667137723
Short name T593
Test name
Test status
Simulation time 23949519 ps
CPU time 0.76 seconds
Started Jul 26 06:35:07 PM PDT 24
Finished Jul 26 06:35:08 PM PDT 24
Peak memory 199628 kb
Host smart-d675f624-3e60-438f-9d27-8f2ecc675888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667137723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3667137723
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.2417241879
Short name T683
Test name
Test status
Simulation time 30462257 ps
CPU time 0.79 seconds
Started Jul 26 06:35:03 PM PDT 24
Finished Jul 26 06:35:04 PM PDT 24
Peak memory 200476 kb
Host smart-baf8f3ff-fb7e-4ed4-abba-a9ff82690fb3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417241879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.2417241879
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.1825888715
Short name T652
Test name
Test status
Simulation time 26826864 ps
CPU time 0.91 seconds
Started Jul 26 06:35:03 PM PDT 24
Finished Jul 26 06:35:04 PM PDT 24
Peak memory 200456 kb
Host smart-36f70ba6-f1c6-47c5-a823-6f14a3be1ebc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825888715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1825888715
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.2648805683
Short name T262
Test name
Test status
Simulation time 562239401 ps
CPU time 3.68 seconds
Started Jul 26 06:35:07 PM PDT 24
Finished Jul 26 06:35:10 PM PDT 24
Peak memory 200496 kb
Host smart-7e8b9368-b1e2-4beb-a450-66f1c6ff8c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648805683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2648805683
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.3380566225
Short name T574
Test name
Test status
Simulation time 740332040 ps
CPU time 5.83 seconds
Started Jul 26 06:35:05 PM PDT 24
Finished Jul 26 06:35:10 PM PDT 24
Peak memory 200600 kb
Host smart-9737236f-2bd3-44b8-a84c-0185c22dd33c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380566225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.3380566225
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.885610795
Short name T517
Test name
Test status
Simulation time 40754621 ps
CPU time 0.87 seconds
Started Jul 26 06:35:01 PM PDT 24
Finished Jul 26 06:35:02 PM PDT 24
Peak memory 200488 kb
Host smart-86ec4a04-3e30-44f7-9430-fa54231aaf02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885610795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.clkmgr_idle_intersig_mubi.885610795
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.880530378
Short name T585
Test name
Test status
Simulation time 83581586 ps
CPU time 1.1 seconds
Started Jul 26 06:35:03 PM PDT 24
Finished Jul 26 06:35:04 PM PDT 24
Peak memory 200460 kb
Host smart-c8c0228c-9c7f-4b84-bf87-a3a6afed7e2a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880530378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.clkmgr_lc_clk_byp_req_intersig_mubi.880530378
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.3238239459
Short name T758
Test name
Test status
Simulation time 29214421 ps
CPU time 1 seconds
Started Jul 26 06:35:04 PM PDT 24
Finished Jul 26 06:35:05 PM PDT 24
Peak memory 200472 kb
Host smart-bef7538f-84ba-45c9-a572-c81589d7c797
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238239459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.3238239459
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.606995841
Short name T746
Test name
Test status
Simulation time 32148108 ps
CPU time 0.82 seconds
Started Jul 26 06:35:03 PM PDT 24
Finished Jul 26 06:35:04 PM PDT 24
Peak memory 200448 kb
Host smart-707c8f8b-5e80-49f5-b805-6090e0c4f271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606995841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.606995841
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1333037861
Short name T518
Test name
Test status
Simulation time 577480501 ps
CPU time 3.48 seconds
Started Jul 26 06:35:05 PM PDT 24
Finished Jul 26 06:35:09 PM PDT 24
Peak memory 200660 kb
Host smart-672421cd-49f1-455c-82e3-9edabcb3e334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333037861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1333037861
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.3996283843
Short name T609
Test name
Test status
Simulation time 26473341 ps
CPU time 0.88 seconds
Started Jul 26 06:35:02 PM PDT 24
Finished Jul 26 06:35:03 PM PDT 24
Peak memory 200436 kb
Host smart-c9f09039-9b88-4098-9387-d05100535f9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996283843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3996283843
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.515896694
Short name T460
Test name
Test status
Simulation time 3446724190 ps
CPU time 27.1 seconds
Started Jul 26 06:35:02 PM PDT 24
Finished Jul 26 06:35:29 PM PDT 24
Peak memory 201116 kb
Host smart-9aec23fd-c8df-4d5f-81d8-ffdf24d3f119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515896694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.515896694
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.1897365655
Short name T732
Test name
Test status
Simulation time 83249051 ps
CPU time 1.12 seconds
Started Jul 26 06:35:07 PM PDT 24
Finished Jul 26 06:35:08 PM PDT 24
Peak memory 200436 kb
Host smart-23df209a-92ae-40c5-a7fd-bf8dd6e54d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897365655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.1897365655
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.2683313489
Short name T738
Test name
Test status
Simulation time 16909968 ps
CPU time 0.78 seconds
Started Jul 26 06:35:08 PM PDT 24
Finished Jul 26 06:35:08 PM PDT 24
Peak memory 200420 kb
Host smart-f25cd0f2-6a9f-474a-b96a-88fe1232db3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683313489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.2683313489
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3561744487
Short name T644
Test name
Test status
Simulation time 38095879 ps
CPU time 0.98 seconds
Started Jul 26 06:35:02 PM PDT 24
Finished Jul 26 06:35:03 PM PDT 24
Peak memory 200456 kb
Host smart-ce5c9f52-fabf-4184-a606-dc0a50137bab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561744487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.3561744487
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.3780920140
Short name T570
Test name
Test status
Simulation time 35778419 ps
CPU time 0.8 seconds
Started Jul 26 06:35:06 PM PDT 24
Finished Jul 26 06:35:07 PM PDT 24
Peak memory 199640 kb
Host smart-9bd97a99-9227-4892-98d3-90b75f5984b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780920140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3780920140
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.112880355
Short name T147
Test name
Test status
Simulation time 22482808 ps
CPU time 0.84 seconds
Started Jul 26 06:35:03 PM PDT 24
Finished Jul 26 06:35:04 PM PDT 24
Peak memory 200476 kb
Host smart-a865988f-b557-45c0-a5d5-b76acfff54f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112880355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_div_intersig_mubi.112880355
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.3176715988
Short name T265
Test name
Test status
Simulation time 21829067 ps
CPU time 0.78 seconds
Started Jul 26 06:35:04 PM PDT 24
Finished Jul 26 06:35:05 PM PDT 24
Peak memory 200460 kb
Host smart-0ad79631-db6c-4bb8-a235-ede9b74a1454
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176715988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.3176715988
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.1709216045
Short name T179
Test name
Test status
Simulation time 830720013 ps
CPU time 4.11 seconds
Started Jul 26 06:35:06 PM PDT 24
Finished Jul 26 06:35:10 PM PDT 24
Peak memory 200500 kb
Host smart-700279ca-1bca-49e5-a66c-d236e5333abe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709216045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1709216045
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.3685453149
Short name T321
Test name
Test status
Simulation time 1217636020 ps
CPU time 9.21 seconds
Started Jul 26 06:35:02 PM PDT 24
Finished Jul 26 06:35:11 PM PDT 24
Peak memory 200556 kb
Host smart-25df668b-ec19-4ce6-b81d-7af889829cf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685453149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.3685453149
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.699460578
Short name T78
Test name
Test status
Simulation time 71697691 ps
CPU time 1.03 seconds
Started Jul 26 06:35:05 PM PDT 24
Finished Jul 26 06:35:06 PM PDT 24
Peak memory 200452 kb
Host smart-edda02d1-3530-41e2-955c-f3f3f4eb1efa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699460578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_idle_intersig_mubi.699460578
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.3968036935
Short name T220
Test name
Test status
Simulation time 40979031 ps
CPU time 0.84 seconds
Started Jul 26 06:35:05 PM PDT 24
Finished Jul 26 06:35:06 PM PDT 24
Peak memory 200412 kb
Host smart-b81f0677-11ce-457e-8024-5ac9b5b37c87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968036935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.3968036935
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.2245573549
Short name T214
Test name
Test status
Simulation time 25690858 ps
CPU time 0.81 seconds
Started Jul 26 06:35:03 PM PDT 24
Finished Jul 26 06:35:04 PM PDT 24
Peak memory 200488 kb
Host smart-3a7e7507-668f-4f5a-a633-56e2ce96d4f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245573549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.2245573549
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.4064194927
Short name T602
Test name
Test status
Simulation time 32547647 ps
CPU time 0.8 seconds
Started Jul 26 06:35:04 PM PDT 24
Finished Jul 26 06:35:05 PM PDT 24
Peak memory 200444 kb
Host smart-78409c5e-8a67-44bc-8333-26c0582a9369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064194927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.4064194927
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.3152782448
Short name T614
Test name
Test status
Simulation time 168447211 ps
CPU time 1.35 seconds
Started Jul 26 06:35:09 PM PDT 24
Finished Jul 26 06:35:10 PM PDT 24
Peak memory 200364 kb
Host smart-0732eff3-b6a0-43ec-96a0-a1817f4ec0e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152782448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.3152782448
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.667107548
Short name T195
Test name
Test status
Simulation time 55991824 ps
CPU time 0.91 seconds
Started Jul 26 06:35:04 PM PDT 24
Finished Jul 26 06:35:05 PM PDT 24
Peak memory 200416 kb
Host smart-d99b2a75-e8e9-4052-a535-b3b38910bac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667107548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.667107548
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.3746606469
Short name T10
Test name
Test status
Simulation time 544823603 ps
CPU time 3.77 seconds
Started Jul 26 06:35:09 PM PDT 24
Finished Jul 26 06:35:13 PM PDT 24
Peak memory 200532 kb
Host smart-103a6e31-7ca7-4964-a711-5b87bcd7dc96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746606469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.3746606469
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.3311630071
Short name T395
Test name
Test status
Simulation time 50176280 ps
CPU time 0.99 seconds
Started Jul 26 06:35:05 PM PDT 24
Finished Jul 26 06:35:07 PM PDT 24
Peak memory 200436 kb
Host smart-12abc684-5d4e-404f-9d20-6814495b6ef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311630071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3311630071
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.2495927156
Short name T657
Test name
Test status
Simulation time 15914764 ps
CPU time 0.75 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200520 kb
Host smart-3e2ea420-ea0d-4401-b0ac-243e109786a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495927156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.2495927156
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.3901277918
Short name T97
Test name
Test status
Simulation time 25693177 ps
CPU time 0.91 seconds
Started Jul 26 06:35:07 PM PDT 24
Finished Jul 26 06:35:08 PM PDT 24
Peak memory 200444 kb
Host smart-5e6e0077-03aa-4bf6-9a4d-39e0a0d1fdd0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901277918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.3901277918
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.2174499782
Short name T486
Test name
Test status
Simulation time 16987232 ps
CPU time 0.76 seconds
Started Jul 26 06:35:09 PM PDT 24
Finished Jul 26 06:35:10 PM PDT 24
Peak memory 200348 kb
Host smart-3d1c65cf-32dd-4945-b70a-2e1b36a1e7f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174499782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2174499782
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.3395941116
Short name T752
Test name
Test status
Simulation time 57603422 ps
CPU time 1.01 seconds
Started Jul 26 06:35:19 PM PDT 24
Finished Jul 26 06:35:20 PM PDT 24
Peak memory 200736 kb
Host smart-172fb316-db95-403a-a241-a8586150ad33
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395941116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.3395941116
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.3627701759
Short name T666
Test name
Test status
Simulation time 34884856 ps
CPU time 0.89 seconds
Started Jul 26 06:35:08 PM PDT 24
Finished Jul 26 06:35:09 PM PDT 24
Peak memory 200448 kb
Host smart-82acd2d1-4e1a-4e50-b564-165cf582782b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627701759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.3627701759
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.4097370965
Short name T709
Test name
Test status
Simulation time 2359575000 ps
CPU time 16.94 seconds
Started Jul 26 06:35:08 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200772 kb
Host smart-93cd5090-ca09-4f96-9204-cecc5880b410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097370965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.4097370965
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.3532460318
Short name T82
Test name
Test status
Simulation time 2409810516 ps
CPU time 10.16 seconds
Started Jul 26 06:35:07 PM PDT 24
Finished Jul 26 06:35:17 PM PDT 24
Peak memory 200824 kb
Host smart-20ae7760-c542-4d65-9201-a57fb88ad130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532460318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.3532460318
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1451732495
Short name T701
Test name
Test status
Simulation time 61412283 ps
CPU time 0.87 seconds
Started Jul 26 06:35:11 PM PDT 24
Finished Jul 26 06:35:12 PM PDT 24
Peak memory 200412 kb
Host smart-cfc941f4-140c-4ca2-8173-902aca653019
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451732495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.1451732495
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1512657398
Short name T739
Test name
Test status
Simulation time 23196226 ps
CPU time 0.81 seconds
Started Jul 26 06:35:07 PM PDT 24
Finished Jul 26 06:35:08 PM PDT 24
Peak memory 200444 kb
Host smart-13289e32-2083-4aab-9274-6af4b039784b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512657398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1512657398
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.567533555
Short name T172
Test name
Test status
Simulation time 116270559 ps
CPU time 1.24 seconds
Started Jul 26 06:35:09 PM PDT 24
Finished Jul 26 06:35:10 PM PDT 24
Peak memory 200472 kb
Host smart-1eef4843-05cd-4041-9652-d9e2c74b8bc8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567533555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_ctrl_intersig_mubi.567533555
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.4294367011
Short name T699
Test name
Test status
Simulation time 22595003 ps
CPU time 0.76 seconds
Started Jul 26 06:35:10 PM PDT 24
Finished Jul 26 06:35:11 PM PDT 24
Peak memory 200460 kb
Host smart-11935713-ff8d-4e1c-9458-6aa968d014d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294367011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.4294367011
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1878508948
Short name T523
Test name
Test status
Simulation time 681805958 ps
CPU time 2.8 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:27 PM PDT 24
Peak memory 200544 kb
Host smart-ed1e861b-a3ae-4634-a152-39403e60283d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878508948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1878508948
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.653987709
Short name T237
Test name
Test status
Simulation time 106839188 ps
CPU time 1.15 seconds
Started Jul 26 06:35:10 PM PDT 24
Finished Jul 26 06:35:11 PM PDT 24
Peak memory 200424 kb
Host smart-ffbf8a72-63a4-44d7-a42d-fbb0ce196279
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653987709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.653987709
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.4041431432
Short name T688
Test name
Test status
Simulation time 357187113 ps
CPU time 2.33 seconds
Started Jul 26 06:35:23 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200460 kb
Host smart-9bed9f84-8b07-43ce-8770-55323ae0a314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041431432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.4041431432
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.4112188197
Short name T208
Test name
Test status
Simulation time 22352574 ps
CPU time 0.75 seconds
Started Jul 26 06:35:09 PM PDT 24
Finished Jul 26 06:35:09 PM PDT 24
Peak memory 200344 kb
Host smart-1bdf1079-da35-4369-bb14-939395f21ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112188197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.4112188197
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.475814914
Short name T270
Test name
Test status
Simulation time 18031071 ps
CPU time 0.8 seconds
Started Jul 26 06:32:33 PM PDT 24
Finished Jul 26 06:32:34 PM PDT 24
Peak memory 200488 kb
Host smart-625b2419-2b5f-46f0-b280-5d6031f85ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475814914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_alert_test.475814914
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.3990349233
Short name T192
Test name
Test status
Simulation time 43789649 ps
CPU time 0.84 seconds
Started Jul 26 06:32:26 PM PDT 24
Finished Jul 26 06:32:27 PM PDT 24
Peak memory 200444 kb
Host smart-92e0a366-c662-43c4-8899-ffa87a91733d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990349233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.3990349233
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.3892744346
Short name T482
Test name
Test status
Simulation time 48783277 ps
CPU time 0.8 seconds
Started Jul 26 06:32:24 PM PDT 24
Finished Jul 26 06:32:25 PM PDT 24
Peak memory 199688 kb
Host smart-76f365c8-3639-443f-a380-e1596ddde9c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892744346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3892744346
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1958056156
Short name T538
Test name
Test status
Simulation time 18675011 ps
CPU time 0.82 seconds
Started Jul 26 06:32:24 PM PDT 24
Finished Jul 26 06:32:25 PM PDT 24
Peak memory 200460 kb
Host smart-7d04b2d5-ff9d-46b4-8d8e-fbf07789420d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958056156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1958056156
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.4120009990
Short name T625
Test name
Test status
Simulation time 16256466 ps
CPU time 0.75 seconds
Started Jul 26 06:32:25 PM PDT 24
Finished Jul 26 06:32:25 PM PDT 24
Peak memory 200408 kb
Host smart-60ab69b2-0542-423f-a84c-d40bc33d43f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120009990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.4120009990
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.288235458
Short name T456
Test name
Test status
Simulation time 1890554462 ps
CPU time 10.95 seconds
Started Jul 26 06:32:24 PM PDT 24
Finished Jul 26 06:32:36 PM PDT 24
Peak memory 200692 kb
Host smart-cdcc3d0b-eef4-4f43-a804-729abbed8ebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288235458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.288235458
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.656088453
Short name T743
Test name
Test status
Simulation time 1938073670 ps
CPU time 13.61 seconds
Started Jul 26 06:32:28 PM PDT 24
Finished Jul 26 06:32:41 PM PDT 24
Peak memory 200564 kb
Host smart-4ebd919a-9893-487a-a036-e6b16388a4e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656088453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim
eout.656088453
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.3677468245
Short name T513
Test name
Test status
Simulation time 29933105 ps
CPU time 0.95 seconds
Started Jul 26 06:32:24 PM PDT 24
Finished Jul 26 06:32:25 PM PDT 24
Peak memory 200444 kb
Host smart-88b8f80b-4d82-4594-a76c-9e0aac3a330b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677468245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.3677468245
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2768040848
Short name T219
Test name
Test status
Simulation time 135622626 ps
CPU time 1.16 seconds
Started Jul 26 06:32:24 PM PDT 24
Finished Jul 26 06:32:25 PM PDT 24
Peak memory 200460 kb
Host smart-b632094f-7430-4420-a2c8-b3c952384d02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768040848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.2768040848
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1327004328
Short name T630
Test name
Test status
Simulation time 16271818 ps
CPU time 0.81 seconds
Started Jul 26 06:32:21 PM PDT 24
Finished Jul 26 06:32:22 PM PDT 24
Peak memory 200492 kb
Host smart-e57bd70b-1127-4789-ac1c-f4727e927222
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327004328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.1327004328
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.3152567184
Short name T420
Test name
Test status
Simulation time 37726649 ps
CPU time 0.83 seconds
Started Jul 26 06:32:25 PM PDT 24
Finished Jul 26 06:32:26 PM PDT 24
Peak memory 200416 kb
Host smart-ccd8b6b9-8617-4043-8e36-de8a6211bb72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152567184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3152567184
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.1976741857
Short name T343
Test name
Test status
Simulation time 160063454 ps
CPU time 1.24 seconds
Started Jul 26 06:32:25 PM PDT 24
Finished Jul 26 06:32:26 PM PDT 24
Peak memory 200396 kb
Host smart-e15046f6-ba67-40a2-8301-5a301b44408b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976741857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1976741857
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.1891671115
Short name T44
Test name
Test status
Simulation time 442264288 ps
CPU time 3.55 seconds
Started Jul 26 06:32:27 PM PDT 24
Finished Jul 26 06:32:31 PM PDT 24
Peak memory 221528 kb
Host smart-48c04042-dfc4-43ef-a7ce-1a18d1ade962
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891671115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.1891671115
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.81243651
Short name T603
Test name
Test status
Simulation time 22777681 ps
CPU time 0.91 seconds
Started Jul 26 06:32:27 PM PDT 24
Finished Jul 26 06:32:28 PM PDT 24
Peak memory 200428 kb
Host smart-54a4345c-31d7-4791-933d-a92ec69577cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81243651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.81243651
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.1039418633
Short name T675
Test name
Test status
Simulation time 369195710 ps
CPU time 3.6 seconds
Started Jul 26 06:32:26 PM PDT 24
Finished Jul 26 06:32:30 PM PDT 24
Peak memory 200536 kb
Host smart-fe313a09-de24-45c9-8260-4d83cd8ffaf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039418633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.1039418633
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.686695592
Short name T667
Test name
Test status
Simulation time 26486806 ps
CPU time 0.91 seconds
Started Jul 26 06:32:25 PM PDT 24
Finished Jul 26 06:32:26 PM PDT 24
Peak memory 200436 kb
Host smart-0e2ca390-75d7-46f0-8ac5-2e74de4f6748
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686695592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.686695592
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1850780946
Short name T649
Test name
Test status
Simulation time 49882364 ps
CPU time 0.88 seconds
Started Jul 26 06:35:22 PM PDT 24
Finished Jul 26 06:35:23 PM PDT 24
Peak memory 200480 kb
Host smart-cbaa6b26-f169-40c7-8a41-b06563bcc20d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850780946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1850780946
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1748987153
Short name T328
Test name
Test status
Simulation time 19692358 ps
CPU time 0.83 seconds
Started Jul 26 06:35:18 PM PDT 24
Finished Jul 26 06:35:19 PM PDT 24
Peak memory 200340 kb
Host smart-a058470c-6edb-4a0e-84c8-bfafa7a78a98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748987153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.1748987153
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1304064276
Short name T819
Test name
Test status
Simulation time 41738578 ps
CPU time 0.78 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:21 PM PDT 24
Peak memory 200352 kb
Host smart-aa42f549-db6d-4d55-b3c1-8b3f9a9c18fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304064276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1304064276
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.1989986193
Short name T391
Test name
Test status
Simulation time 49474946 ps
CPU time 0.89 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:21 PM PDT 24
Peak memory 200448 kb
Host smart-be16f2cc-8a78-451a-922b-abac603b9b52
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989986193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.1989986193
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.1766288804
Short name T302
Test name
Test status
Simulation time 134510700 ps
CPU time 1.23 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:23 PM PDT 24
Peak memory 200460 kb
Host smart-1a446230-c73a-445b-a9ca-f2153f649e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766288804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1766288804
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.1520888714
Short name T674
Test name
Test status
Simulation time 558491193 ps
CPU time 4.88 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200524 kb
Host smart-66b42f6d-e688-4e2c-93fe-7ddde3d7f8d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520888714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1520888714
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.4275705809
Short name T587
Test name
Test status
Simulation time 796405763 ps
CPU time 3.44 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:24 PM PDT 24
Peak memory 200548 kb
Host smart-4a68ac71-bb22-4097-b24b-8a2b331c5900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275705809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.4275705809
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1266604346
Short name T472
Test name
Test status
Simulation time 59864369 ps
CPU time 0.96 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200500 kb
Host smart-fd1ea7db-554d-486d-84b3-d79416d72b65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266604346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1266604346
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.895019850
Short name T437
Test name
Test status
Simulation time 73387547 ps
CPU time 0.96 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200472 kb
Host smart-278cdc62-2ada-41f8-ae3f-f0ea532bea64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895019850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.clkmgr_lc_clk_byp_req_intersig_mubi.895019850
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3165048004
Short name T332
Test name
Test status
Simulation time 50626346 ps
CPU time 0.91 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:21 PM PDT 24
Peak memory 200472 kb
Host smart-e474f53e-2ed5-4b12-96d5-d21f750aab62
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165048004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.3165048004
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.1683483443
Short name T670
Test name
Test status
Simulation time 18282646 ps
CPU time 0.74 seconds
Started Jul 26 06:35:19 PM PDT 24
Finished Jul 26 06:35:20 PM PDT 24
Peak memory 200356 kb
Host smart-810df9e8-7bfb-4cd3-92fa-bb44f8fd0ae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683483443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1683483443
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.1444753100
Short name T156
Test name
Test status
Simulation time 158202926 ps
CPU time 1.56 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200428 kb
Host smart-ea177449-a21a-4fd2-92bc-a12f3e223895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444753100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.1444753100
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.1936109890
Short name T136
Test name
Test status
Simulation time 23851702 ps
CPU time 0.88 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200396 kb
Host smart-bab3d54a-9522-4b6a-92e5-323e3446de27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936109890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.1936109890
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.2458615274
Short name T655
Test name
Test status
Simulation time 10115927652 ps
CPU time 41.85 seconds
Started Jul 26 06:35:17 PM PDT 24
Finished Jul 26 06:35:59 PM PDT 24
Peak memory 200860 kb
Host smart-7c079475-4496-415a-88df-ab216b8dbb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458615274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.2458615274
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2477439975
Short name T503
Test name
Test status
Simulation time 39614153 ps
CPU time 0.8 seconds
Started Jul 26 06:35:22 PM PDT 24
Finished Jul 26 06:35:23 PM PDT 24
Peak memory 200444 kb
Host smart-ac147bb3-d079-414e-a9ce-a03aef647f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477439975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2477439975
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.3121581180
Short name T619
Test name
Test status
Simulation time 27159959 ps
CPU time 0.78 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200496 kb
Host smart-cf9e4b64-255b-45ba-8fce-413757a1eee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121581180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.3121581180
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.3114205266
Short name T98
Test name
Test status
Simulation time 20281332 ps
CPU time 0.83 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200468 kb
Host smart-6a3eab53-885f-4d08-a703-fcb10001263c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114205266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.3114205266
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.767841169
Short name T35
Test name
Test status
Simulation time 32781066 ps
CPU time 0.75 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 199644 kb
Host smart-20ae91af-9fdc-4cf9-bba5-914a710261d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767841169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.767841169
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.2509520260
Short name T207
Test name
Test status
Simulation time 44108604 ps
CPU time 0.83 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200472 kb
Host smart-54e7b9c5-242a-460c-a15d-00b3af6fb208
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509520260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.2509520260
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.512757483
Short name T145
Test name
Test status
Simulation time 29037837 ps
CPU time 0.93 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200476 kb
Host smart-7f21091d-ea6d-407a-952d-1d49c971914f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512757483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.512757483
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.167652702
Short name T542
Test name
Test status
Simulation time 1275572055 ps
CPU time 9.35 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:34 PM PDT 24
Peak memory 200592 kb
Host smart-99e767e7-05ee-4e4c-8d1f-05828f76b8df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167652702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.167652702
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.1451492381
Short name T669
Test name
Test status
Simulation time 2184936283 ps
CPU time 10.51 seconds
Started Jul 26 06:35:18 PM PDT 24
Finished Jul 26 06:35:29 PM PDT 24
Peak memory 200800 kb
Host smart-54bd74b8-586f-4d16-a78a-c6984889367d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451492381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.1451492381
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1067268566
Short name T502
Test name
Test status
Simulation time 121247747 ps
CPU time 1.26 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200468 kb
Host smart-b4c5ca96-dca5-4e03-99c2-27e36766dabe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067268566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.1067268566
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3068317339
Short name T676
Test name
Test status
Simulation time 61130804 ps
CPU time 0.93 seconds
Started Jul 26 06:35:23 PM PDT 24
Finished Jul 26 06:35:24 PM PDT 24
Peak memory 200464 kb
Host smart-f8dad8a8-be60-4f12-9389-3f0a3ad06809
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068317339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3068317339
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.4217981300
Short name T684
Test name
Test status
Simulation time 20184935 ps
CPU time 0.82 seconds
Started Jul 26 06:35:22 PM PDT 24
Finished Jul 26 06:35:23 PM PDT 24
Peak memory 200372 kb
Host smart-5fd06403-6ead-4ab5-a2da-e2c339decff9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217981300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.4217981300
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.67922272
Short name T319
Test name
Test status
Simulation time 17308887 ps
CPU time 0.74 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200476 kb
Host smart-0653b367-1769-41e8-8875-307549a9ca6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67922272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.67922272
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.1157402295
Short name T241
Test name
Test status
Simulation time 702454400 ps
CPU time 3.53 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200660 kb
Host smart-0000a592-a13c-4b93-9107-2cd7063a4e75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157402295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1157402295
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.2597869100
Short name T282
Test name
Test status
Simulation time 40173385 ps
CPU time 0.91 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200404 kb
Host smart-35df2872-6266-4adf-a8ae-1b9be872de16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597869100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2597869100
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.3734057739
Short name T386
Test name
Test status
Simulation time 3650334729 ps
CPU time 11.89 seconds
Started Jul 26 06:35:25 PM PDT 24
Finished Jul 26 06:35:37 PM PDT 24
Peak memory 200752 kb
Host smart-7cd4d60e-646c-4314-a974-1e064107ee6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734057739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.3734057739
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.132755366
Short name T522
Test name
Test status
Simulation time 41788577 ps
CPU time 0.8 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:21 PM PDT 24
Peak memory 200472 kb
Host smart-39bda255-2868-4069-aa3b-508fe319a0db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132755366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.132755366
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.4015321081
Short name T617
Test name
Test status
Simulation time 14274983 ps
CPU time 0.74 seconds
Started Jul 26 06:35:26 PM PDT 24
Finished Jul 26 06:35:27 PM PDT 24
Peak memory 200488 kb
Host smart-f5a8b7f2-590f-4fa2-ac4d-8659cdcddc62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015321081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.4015321081
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.107645972
Short name T334
Test name
Test status
Simulation time 113138460 ps
CPU time 1.26 seconds
Started Jul 26 06:35:30 PM PDT 24
Finished Jul 26 06:35:31 PM PDT 24
Peak memory 200488 kb
Host smart-41ffac55-1218-43a7-87b3-23019487e476
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107645972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.107645972
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.3835971640
Short name T679
Test name
Test status
Simulation time 23826806 ps
CPU time 0.74 seconds
Started Jul 26 06:35:29 PM PDT 24
Finished Jul 26 06:35:30 PM PDT 24
Peak memory 199680 kb
Host smart-b3df07fe-201c-4d4d-879c-91858a7c1e43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835971640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.3835971640
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.2490825979
Short name T199
Test name
Test status
Simulation time 28508300 ps
CPU time 0.84 seconds
Started Jul 26 06:35:28 PM PDT 24
Finished Jul 26 06:35:28 PM PDT 24
Peak memory 200452 kb
Host smart-dd0a8a26-e5bd-4684-8243-431d6ea5fbd5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490825979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.2490825979
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.664746555
Short name T258
Test name
Test status
Simulation time 23080674 ps
CPU time 0.82 seconds
Started Jul 26 06:35:21 PM PDT 24
Finished Jul 26 06:35:22 PM PDT 24
Peak memory 200444 kb
Host smart-0fd661cb-ad40-48b8-be8f-d75c8b2df802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664746555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.664746555
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.1017169598
Short name T13
Test name
Test status
Simulation time 434699350 ps
CPU time 3.93 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:28 PM PDT 24
Peak memory 200596 kb
Host smart-a69b247f-6736-48cf-891b-2ff49ba7de4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017169598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1017169598
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.2577812200
Short name T348
Test name
Test status
Simulation time 505134584 ps
CPU time 3.07 seconds
Started Jul 26 06:35:20 PM PDT 24
Finished Jul 26 06:35:23 PM PDT 24
Peak memory 200548 kb
Host smart-23ed0913-f56b-46e7-be38-a4580ed17055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577812200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.2577812200
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2800632166
Short name T222
Test name
Test status
Simulation time 30297492 ps
CPU time 1 seconds
Started Jul 26 06:35:27 PM PDT 24
Finished Jul 26 06:35:28 PM PDT 24
Peak memory 200484 kb
Host smart-0e04e2d0-c608-43b5-85e2-ace6622b4dd9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800632166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.2800632166
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3815408245
Short name T335
Test name
Test status
Simulation time 44479487 ps
CPU time 0.91 seconds
Started Jul 26 06:35:27 PM PDT 24
Finished Jul 26 06:35:28 PM PDT 24
Peak memory 200424 kb
Host smart-4b593213-b1e1-4096-98f1-8395f5e0ea3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815408245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3815408245
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2553471964
Short name T421
Test name
Test status
Simulation time 43819430 ps
CPU time 0.93 seconds
Started Jul 26 06:35:27 PM PDT 24
Finished Jul 26 06:35:28 PM PDT 24
Peak memory 200440 kb
Host smart-787b2df7-d2c5-4453-a652-aba4d52612ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553471964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.2553471964
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.3593750195
Short name T750
Test name
Test status
Simulation time 34585160 ps
CPU time 0.84 seconds
Started Jul 26 06:35:19 PM PDT 24
Finished Jul 26 06:35:20 PM PDT 24
Peak memory 200424 kb
Host smart-033c4e35-b49a-4fe1-a7a8-61bb585f2c2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593750195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3593750195
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.2257434988
Short name T794
Test name
Test status
Simulation time 1145173336 ps
CPU time 6.63 seconds
Started Jul 26 06:35:27 PM PDT 24
Finished Jul 26 06:35:33 PM PDT 24
Peak memory 200656 kb
Host smart-7637a296-f9e0-4835-b6be-f2b9af1f171a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257434988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2257434988
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.1585259744
Short name T779
Test name
Test status
Simulation time 82092858 ps
CPU time 1.03 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200400 kb
Host smart-c0bdbda7-56e0-44bf-90bf-743f3223d35c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585259744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1585259744
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.268931846
Short name T180
Test name
Test status
Simulation time 63380339 ps
CPU time 1.3 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:25 PM PDT 24
Peak memory 200508 kb
Host smart-ae6909bf-b25f-4728-9570-ad38fc7552d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268931846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.268931846
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_trans.267504397
Short name T485
Test name
Test status
Simulation time 16169391 ps
CPU time 0.76 seconds
Started Jul 26 06:35:22 PM PDT 24
Finished Jul 26 06:35:23 PM PDT 24
Peak memory 200512 kb
Host smart-fec250fa-64a9-4100-9b8e-341cf027c798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267504397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.267504397
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.3100467446
Short name T32
Test name
Test status
Simulation time 15018293 ps
CPU time 0.75 seconds
Started Jul 26 06:35:32 PM PDT 24
Finished Jul 26 06:35:33 PM PDT 24
Peak memory 200488 kb
Host smart-08bbe0a2-baf9-4929-95c4-36f99ad39928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100467446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.3100467446
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.471910669
Short name T387
Test name
Test status
Simulation time 60403116 ps
CPU time 0.9 seconds
Started Jul 26 06:35:30 PM PDT 24
Finished Jul 26 06:35:31 PM PDT 24
Peak memory 200452 kb
Host smart-c7c98a2f-a38e-45c5-81b1-d5aab1fdd4da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471910669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.471910669
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.1211400313
Short name T804
Test name
Test status
Simulation time 16774419 ps
CPU time 0.83 seconds
Started Jul 26 06:35:31 PM PDT 24
Finished Jul 26 06:35:32 PM PDT 24
Peak memory 200400 kb
Host smart-7d9213b8-6a3b-4076-bfd2-18796f10c042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211400313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1211400313
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.3116470573
Short name T304
Test name
Test status
Simulation time 53766649 ps
CPU time 0.93 seconds
Started Jul 26 06:35:29 PM PDT 24
Finished Jul 26 06:35:30 PM PDT 24
Peak memory 200468 kb
Host smart-2945b1f8-1ae2-4a24-b2d1-6fbed245278b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116470573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.3116470573
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.4207604182
Short name T364
Test name
Test status
Simulation time 27385762 ps
CPU time 0.92 seconds
Started Jul 26 06:35:30 PM PDT 24
Finished Jul 26 06:35:31 PM PDT 24
Peak memory 200424 kb
Host smart-dca05717-93a7-4915-919a-61e31ba5d327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207604182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.4207604182
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.1427211677
Short name T47
Test name
Test status
Simulation time 1543600346 ps
CPU time 7.1 seconds
Started Jul 26 06:35:26 PM PDT 24
Finished Jul 26 06:35:34 PM PDT 24
Peak memory 200524 kb
Host smart-d1edc031-b94d-4026-8f65-64680a34e10d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427211677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1427211677
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.464138891
Short name T249
Test name
Test status
Simulation time 1581312831 ps
CPU time 9.8 seconds
Started Jul 26 06:35:29 PM PDT 24
Finished Jul 26 06:35:39 PM PDT 24
Peak memory 200516 kb
Host smart-5a04256a-9ebc-4d17-8b7f-30909d0faff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464138891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_ti
meout.464138891
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.3290404506
Short name T117
Test name
Test status
Simulation time 98248751 ps
CPU time 1.17 seconds
Started Jul 26 06:35:24 PM PDT 24
Finished Jul 26 06:35:26 PM PDT 24
Peak memory 200452 kb
Host smart-e2ebaa54-35ae-4b4a-8d82-e2c1c33b0a87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290404506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.3290404506
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3630673189
Short name T495
Test name
Test status
Simulation time 32198337 ps
CPU time 0.85 seconds
Started Jul 26 06:35:26 PM PDT 24
Finished Jul 26 06:35:27 PM PDT 24
Peak memory 200460 kb
Host smart-8578a864-a920-44d4-a31b-6a7d47bbb7ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630673189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.3630673189
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.2650728237
Short name T189
Test name
Test status
Simulation time 76323421 ps
CPU time 1.06 seconds
Started Jul 26 06:35:29 PM PDT 24
Finished Jul 26 06:35:30 PM PDT 24
Peak memory 200488 kb
Host smart-eeaea3de-1485-437c-bc2e-0f916d7f2a76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650728237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.2650728237
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.885281656
Short name T187
Test name
Test status
Simulation time 18028641 ps
CPU time 0.75 seconds
Started Jul 26 06:35:29 PM PDT 24
Finished Jul 26 06:35:30 PM PDT 24
Peak memory 200368 kb
Host smart-32c5765c-a7e0-42cd-aca0-d21a464d3e10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885281656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.885281656
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.1651733920
Short name T553
Test name
Test status
Simulation time 347897901 ps
CPU time 2.03 seconds
Started Jul 26 06:35:30 PM PDT 24
Finished Jul 26 06:35:32 PM PDT 24
Peak memory 200376 kb
Host smart-0d763b75-20b7-4582-97f6-8f24e89b4afa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651733920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1651733920
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.512231726
Short name T662
Test name
Test status
Simulation time 22633294 ps
CPU time 0.87 seconds
Started Jul 26 06:35:27 PM PDT 24
Finished Jul 26 06:35:28 PM PDT 24
Peak memory 200412 kb
Host smart-313ea6bf-3ed0-4eea-84a2-59d7e8d46eb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512231726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.512231726
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.4085424751
Short name T349
Test name
Test status
Simulation time 8154224692 ps
CPU time 30.3 seconds
Started Jul 26 06:35:32 PM PDT 24
Finished Jul 26 06:36:02 PM PDT 24
Peak memory 200892 kb
Host smart-8cf5a216-605b-4b5b-a20b-b0ce244b4d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085424751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.4085424751
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.2598578056
Short name T210
Test name
Test status
Simulation time 28699777 ps
CPU time 0.8 seconds
Started Jul 26 06:35:26 PM PDT 24
Finished Jul 26 06:35:27 PM PDT 24
Peak memory 200456 kb
Host smart-92f3b5d9-daf0-44a3-8c90-df9d9af0a91e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598578056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2598578056
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1240210361
Short name T288
Test name
Test status
Simulation time 27606232 ps
CPU time 0.83 seconds
Started Jul 26 06:35:32 PM PDT 24
Finished Jul 26 06:35:33 PM PDT 24
Peak memory 200484 kb
Host smart-8aaa7b32-041b-4a0b-a38a-d2c9d30e555f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240210361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1240210361
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.3560593196
Short name T278
Test name
Test status
Simulation time 85095111 ps
CPU time 1.15 seconds
Started Jul 26 06:35:35 PM PDT 24
Finished Jul 26 06:35:36 PM PDT 24
Peak memory 200464 kb
Host smart-f5ad4d09-c600-4ab5-b51b-5b2258d52cf2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560593196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.3560593196
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.2529357713
Short name T663
Test name
Test status
Simulation time 33199205 ps
CPU time 0.75 seconds
Started Jul 26 06:35:34 PM PDT 24
Finished Jul 26 06:35:35 PM PDT 24
Peak memory 199668 kb
Host smart-f4ab9ca1-f04d-4ffa-aeba-7b23f352757f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529357713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2529357713
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.2342000712
Short name T204
Test name
Test status
Simulation time 19403922 ps
CPU time 0.83 seconds
Started Jul 26 06:35:31 PM PDT 24
Finished Jul 26 06:35:32 PM PDT 24
Peak memory 200728 kb
Host smart-f968a13b-debf-41ae-8103-e97736ce9640
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342000712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.2342000712
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.746205084
Short name T190
Test name
Test status
Simulation time 71479242 ps
CPU time 1.07 seconds
Started Jul 26 06:35:40 PM PDT 24
Finished Jul 26 06:35:41 PM PDT 24
Peak memory 200444 kb
Host smart-aa3bd95d-be8f-4386-a143-0f0977902356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746205084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.746205084
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2479250418
Short name T7
Test name
Test status
Simulation time 2416696663 ps
CPU time 10.81 seconds
Started Jul 26 06:35:36 PM PDT 24
Finished Jul 26 06:35:47 PM PDT 24
Peak memory 200784 kb
Host smart-cf418e28-6bc0-4ee8-bbcf-580e5970cfc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479250418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2479250418
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.2792423835
Short name T759
Test name
Test status
Simulation time 1113196275 ps
CPU time 5.19 seconds
Started Jul 26 06:35:34 PM PDT 24
Finished Jul 26 06:35:40 PM PDT 24
Peak memory 200564 kb
Host smart-40703cc9-6d14-46b1-9897-b2504f725009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792423835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.2792423835
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.224186182
Short name T399
Test name
Test status
Simulation time 34436272 ps
CPU time 1.02 seconds
Started Jul 26 06:35:34 PM PDT 24
Finished Jul 26 06:35:35 PM PDT 24
Peak memory 200420 kb
Host smart-6007d623-749d-41b8-933c-b0333f35df64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224186182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_idle_intersig_mubi.224186182
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.160844340
Short name T535
Test name
Test status
Simulation time 44336589 ps
CPU time 0.95 seconds
Started Jul 26 06:35:40 PM PDT 24
Finished Jul 26 06:35:41 PM PDT 24
Peak memory 200452 kb
Host smart-b5154e06-cb88-43e7-b7c7-55d4d6cbde61
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160844340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_clk_byp_req_intersig_mubi.160844340
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2456217427
Short name T280
Test name
Test status
Simulation time 68508897 ps
CPU time 0.95 seconds
Started Jul 26 06:35:32 PM PDT 24
Finished Jul 26 06:35:33 PM PDT 24
Peak memory 200492 kb
Host smart-43ba3573-3f6f-49da-bb1a-6a8155f863a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456217427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.2456217427
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.4122501711
Short name T405
Test name
Test status
Simulation time 34798145 ps
CPU time 0.83 seconds
Started Jul 26 06:35:40 PM PDT 24
Finished Jul 26 06:35:41 PM PDT 24
Peak memory 200388 kb
Host smart-ae199c4b-ac9e-446b-b6e3-9ac478719339
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122501711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.4122501711
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.84163222
Short name T411
Test name
Test status
Simulation time 1089102626 ps
CPU time 5.81 seconds
Started Jul 26 06:35:36 PM PDT 24
Finished Jul 26 06:35:42 PM PDT 24
Peak memory 200628 kb
Host smart-c26fa4c2-c830-41de-aa10-5ef681f6ddb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84163222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.84163222
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.2129748326
Short name T716
Test name
Test status
Simulation time 50414903 ps
CPU time 0.9 seconds
Started Jul 26 06:35:34 PM PDT 24
Finished Jul 26 06:35:35 PM PDT 24
Peak memory 200372 kb
Host smart-9cf73ea4-3a2f-41c5-9ac5-42d7112af650
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129748326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.2129748326
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3117545028
Short name T23
Test name
Test status
Simulation time 3728165385 ps
CPU time 16.96 seconds
Started Jul 26 06:35:33 PM PDT 24
Finished Jul 26 06:35:50 PM PDT 24
Peak memory 200844 kb
Host smart-9e7c719e-2880-41ec-9008-4be57d1e7e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117545028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3117545028
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.622263257
Short name T562
Test name
Test status
Simulation time 111567893 ps
CPU time 1.21 seconds
Started Jul 26 06:35:33 PM PDT 24
Finished Jul 26 06:35:35 PM PDT 24
Peak memory 200432 kb
Host smart-dbd5f6bf-dff6-48e5-8b75-60de6e91cbc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622263257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.622263257
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.2079794944
Short name T632
Test name
Test status
Simulation time 27182473 ps
CPU time 0.79 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:40 PM PDT 24
Peak memory 200488 kb
Host smart-40791254-0e0d-485a-80a9-e970d7494ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079794944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.2079794944
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2873459970
Short name T643
Test name
Test status
Simulation time 32238328 ps
CPU time 0.95 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:40 PM PDT 24
Peak memory 200484 kb
Host smart-b2355112-264a-4964-9f4c-13ca40cc0a2a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873459970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.2873459970
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.1293283461
Short name T490
Test name
Test status
Simulation time 17925343 ps
CPU time 0.75 seconds
Started Jul 26 06:35:33 PM PDT 24
Finished Jul 26 06:35:34 PM PDT 24
Peak memory 200384 kb
Host smart-d5d86598-1f68-4e5e-97f9-ae6b93050574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293283461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1293283461
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2950818508
Short name T165
Test name
Test status
Simulation time 21339466 ps
CPU time 0.9 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:40 PM PDT 24
Peak memory 200448 kb
Host smart-d92f4c0f-3156-430d-88de-48dd64de6e1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950818508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2950818508
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.2260566246
Short name T104
Test name
Test status
Simulation time 15558889 ps
CPU time 0.74 seconds
Started Jul 26 06:35:31 PM PDT 24
Finished Jul 26 06:35:32 PM PDT 24
Peak memory 200464 kb
Host smart-bad2e24a-771a-4e3a-af46-2611f19caaf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260566246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2260566246
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3739395462
Short name T631
Test name
Test status
Simulation time 1876375393 ps
CPU time 14.89 seconds
Started Jul 26 06:35:40 PM PDT 24
Finished Jul 26 06:35:55 PM PDT 24
Peak memory 200704 kb
Host smart-9ee3810d-5ff8-4a7f-ad6b-5f9addf15777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739395462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3739395462
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.617267129
Short name T81
Test name
Test status
Simulation time 2192733710 ps
CPU time 9.12 seconds
Started Jul 26 06:35:33 PM PDT 24
Finished Jul 26 06:35:43 PM PDT 24
Peak memory 200824 kb
Host smart-87347ffc-7816-4c8f-b0fa-56267b0a9ebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617267129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_ti
meout.617267129
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2477499367
Short name T737
Test name
Test status
Simulation time 12161029 ps
CPU time 0.73 seconds
Started Jul 26 06:35:32 PM PDT 24
Finished Jul 26 06:35:32 PM PDT 24
Peak memory 200328 kb
Host smart-5241efca-81ec-4478-9e93-38f2a6e4cc47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477499367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2477499367
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1066268937
Short name T150
Test name
Test status
Simulation time 43305314 ps
CPU time 0.94 seconds
Started Jul 26 06:35:42 PM PDT 24
Finished Jul 26 06:35:43 PM PDT 24
Peak memory 200436 kb
Host smart-95bc33ad-aef3-4e74-9154-1830637b4ad2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066268937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1066268937
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3872464494
Short name T160
Test name
Test status
Simulation time 19506812 ps
CPU time 0.76 seconds
Started Jul 26 06:35:33 PM PDT 24
Finished Jul 26 06:35:34 PM PDT 24
Peak memory 200424 kb
Host smart-22fda700-bb91-4d39-8bca-9220a53abf89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872464494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.3872464494
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.2752036003
Short name T797
Test name
Test status
Simulation time 22039300 ps
CPU time 0.73 seconds
Started Jul 26 06:35:34 PM PDT 24
Finished Jul 26 06:35:34 PM PDT 24
Peak memory 200380 kb
Host smart-aec68dc4-1ea1-49b2-9b64-3e315f3e025f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752036003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2752036003
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2580619297
Short name T433
Test name
Test status
Simulation time 1729837732 ps
CPU time 6.02 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:45 PM PDT 24
Peak memory 200648 kb
Host smart-0c65ba67-1099-40ff-bcbb-ec30d40965fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580619297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2580619297
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.1384048581
Short name T316
Test name
Test status
Simulation time 15630203 ps
CPU time 0.82 seconds
Started Jul 26 06:35:34 PM PDT 24
Finished Jul 26 06:35:35 PM PDT 24
Peak memory 200380 kb
Host smart-bfa32c33-d3a5-477c-833e-7604fb0e7896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384048581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1384048581
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.3970558493
Short name T118
Test name
Test status
Simulation time 78344497 ps
CPU time 1.18 seconds
Started Jul 26 06:35:40 PM PDT 24
Finished Jul 26 06:35:41 PM PDT 24
Peak memory 200444 kb
Host smart-c13c55f4-f095-464f-9f54-ab4cad7fba80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970558493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.3970558493
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.3428003709
Short name T627
Test name
Test status
Simulation time 27180009 ps
CPU time 0.92 seconds
Started Jul 26 06:35:35 PM PDT 24
Finished Jul 26 06:35:36 PM PDT 24
Peak memory 200432 kb
Host smart-51fa3d4b-4cc2-45b2-8b9f-7e0b4deeca49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428003709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3428003709
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3877145121
Short name T693
Test name
Test status
Simulation time 46711209 ps
CPU time 0.88 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:35:47 PM PDT 24
Peak memory 200488 kb
Host smart-5359ca7c-9449-4eb3-8b69-fe04f072073a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877145121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3877145121
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1538779750
Short name T812
Test name
Test status
Simulation time 17400787 ps
CPU time 0.8 seconds
Started Jul 26 06:35:45 PM PDT 24
Finished Jul 26 06:35:46 PM PDT 24
Peak memory 200488 kb
Host smart-d0d26dd6-24f3-43ed-8a1a-8fa31eeb781f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538779750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.1538779750
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.3674954233
Short name T653
Test name
Test status
Simulation time 16765418 ps
CPU time 0.74 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:40 PM PDT 24
Peak memory 199676 kb
Host smart-2faa65fb-243c-4f01-b328-a7636af1a772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674954233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3674954233
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.694407807
Short name T469
Test name
Test status
Simulation time 25728065 ps
CPU time 0.97 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:35:48 PM PDT 24
Peak memory 200508 kb
Host smart-804fd629-c67c-486d-b35b-d5345e6ef81d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694407807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_div_intersig_mubi.694407807
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.1236282466
Short name T217
Test name
Test status
Simulation time 86045868 ps
CPU time 1.08 seconds
Started Jul 26 06:35:41 PM PDT 24
Finished Jul 26 06:35:42 PM PDT 24
Peak memory 200464 kb
Host smart-17cac1c1-252d-4e69-add4-60365d3d2ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236282466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1236282466
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.205902876
Short name T284
Test name
Test status
Simulation time 452532881 ps
CPU time 2.47 seconds
Started Jul 26 06:35:42 PM PDT 24
Finished Jul 26 06:35:45 PM PDT 24
Peak memory 200512 kb
Host smart-2b7331a5-310f-4020-a179-7c8a377135c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205902876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.205902876
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.1299589118
Short name T234
Test name
Test status
Simulation time 2552746654 ps
CPU time 8.37 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:48 PM PDT 24
Peak memory 200604 kb
Host smart-d9cb1e24-1078-45b8-b998-6666f0ef88cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299589118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.1299589118
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1630413303
Short name T720
Test name
Test status
Simulation time 25800322 ps
CPU time 0.93 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:40 PM PDT 24
Peak memory 200456 kb
Host smart-cf6ae171-4a32-43f1-8508-56ad0c8d8ada
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630413303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1630413303
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.398607693
Short name T281
Test name
Test status
Simulation time 22468736 ps
CPU time 0.76 seconds
Started Jul 26 06:35:44 PM PDT 24
Finished Jul 26 06:35:45 PM PDT 24
Peak memory 200460 kb
Host smart-f001278d-4dfc-4d3c-b79b-ecec1979b756
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398607693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_clk_byp_req_intersig_mubi.398607693
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2889203862
Short name T707
Test name
Test status
Simulation time 19830719 ps
CPU time 0.82 seconds
Started Jul 26 06:35:48 PM PDT 24
Finished Jul 26 06:35:49 PM PDT 24
Peak memory 200444 kb
Host smart-d94ca6e5-b75f-4031-9806-c98b90bedc74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889203862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.2889203862
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.1903620773
Short name T178
Test name
Test status
Simulation time 41331392 ps
CPU time 0.8 seconds
Started Jul 26 06:35:39 PM PDT 24
Finished Jul 26 06:35:39 PM PDT 24
Peak memory 200376 kb
Host smart-5f8546f3-aca2-4b49-9114-b58dc8254629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903620773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.1903620773
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.2173529380
Short name T586
Test name
Test status
Simulation time 1451219308 ps
CPU time 5.17 seconds
Started Jul 26 06:35:44 PM PDT 24
Finished Jul 26 06:35:49 PM PDT 24
Peak memory 200628 kb
Host smart-843ee5a4-3aa0-4450-a2fd-5eef1f0fab1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173529380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2173529380
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.2606326344
Short name T264
Test name
Test status
Simulation time 27216501 ps
CPU time 0.81 seconds
Started Jul 26 06:35:48 PM PDT 24
Finished Jul 26 06:35:49 PM PDT 24
Peak memory 200432 kb
Host smart-10250c53-fb0f-43ee-9730-80740a3e170d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606326344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2606326344
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.1732100287
Short name T467
Test name
Test status
Simulation time 9134641757 ps
CPU time 39.31 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:36:26 PM PDT 24
Peak memory 200840 kb
Host smart-0db8bfba-8a64-496f-8d33-d744cd088d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732100287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.1732100287
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.3447429037
Short name T640
Test name
Test status
Simulation time 38222603 ps
CPU time 0.84 seconds
Started Jul 26 06:35:44 PM PDT 24
Finished Jul 26 06:35:44 PM PDT 24
Peak memory 200480 kb
Host smart-62792200-b751-4e9e-abed-b0ad70e88109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447429037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3447429037
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.3759665898
Short name T702
Test name
Test status
Simulation time 18237110 ps
CPU time 0.84 seconds
Started Jul 26 06:35:45 PM PDT 24
Finished Jul 26 06:35:46 PM PDT 24
Peak memory 200480 kb
Host smart-0385ccae-3891-4596-a8fc-ab5429a45dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759665898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.3759665898
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.4072744279
Short name T274
Test name
Test status
Simulation time 67141242 ps
CPU time 0.96 seconds
Started Jul 26 06:35:49 PM PDT 24
Finished Jul 26 06:35:50 PM PDT 24
Peak memory 200448 kb
Host smart-dd8fa64e-0c31-4c88-943e-532e2abaa220
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072744279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.4072744279
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.1140860495
Short name T342
Test name
Test status
Simulation time 36971521 ps
CPU time 0.77 seconds
Started Jul 26 06:35:45 PM PDT 24
Finished Jul 26 06:35:46 PM PDT 24
Peak memory 200396 kb
Host smart-0b1e854c-4b1d-4997-9661-81aff3809b75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140860495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1140860495
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.3012399892
Short name T659
Test name
Test status
Simulation time 30448688 ps
CPU time 0.93 seconds
Started Jul 26 06:35:49 PM PDT 24
Finished Jul 26 06:35:50 PM PDT 24
Peak memory 200484 kb
Host smart-1ace7d0a-778a-4e4c-930e-ff82f477065c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012399892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.3012399892
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.3285843548
Short name T329
Test name
Test status
Simulation time 33668065 ps
CPU time 0.96 seconds
Started Jul 26 06:35:48 PM PDT 24
Finished Jul 26 06:35:49 PM PDT 24
Peak memory 200444 kb
Host smart-f32163a0-ae4f-47a7-bc99-7e6a32c62145
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285843548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3285843548
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.1499329780
Short name T813
Test name
Test status
Simulation time 675665167 ps
CPU time 5.49 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:35:52 PM PDT 24
Peak memory 200540 kb
Host smart-4a1cb422-4c6a-43a0-991a-6fdc6d140130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499329780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1499329780
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.2821125478
Short name T774
Test name
Test status
Simulation time 744727096 ps
CPU time 4.48 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:35:51 PM PDT 24
Peak memory 200532 kb
Host smart-cd55b9a1-855f-44d9-8e45-e8c37f7cac64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821125478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.2821125478
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3773696697
Short name T753
Test name
Test status
Simulation time 18611048 ps
CPU time 0.8 seconds
Started Jul 26 06:35:45 PM PDT 24
Finished Jul 26 06:35:46 PM PDT 24
Peak memory 200440 kb
Host smart-6ab65a3a-4051-4d3b-8d0c-bcbfaa05af3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773696697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.3773696697
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1854432219
Short name T224
Test name
Test status
Simulation time 22703911 ps
CPU time 0.82 seconds
Started Jul 26 06:35:47 PM PDT 24
Finished Jul 26 06:35:48 PM PDT 24
Peak memory 200416 kb
Host smart-a0712874-20c3-46fa-a576-bd1905e17275
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854432219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.1854432219
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.3805378476
Short name T357
Test name
Test status
Simulation time 48986818 ps
CPU time 0.89 seconds
Started Jul 26 06:35:49 PM PDT 24
Finished Jul 26 06:35:50 PM PDT 24
Peak memory 200440 kb
Host smart-b574a66e-82f2-4f5d-b534-2ce2ed1f864d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805378476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.3805378476
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.2130569430
Short name T310
Test name
Test status
Simulation time 36910797 ps
CPU time 0.83 seconds
Started Jul 26 06:35:47 PM PDT 24
Finished Jul 26 06:35:48 PM PDT 24
Peak memory 200404 kb
Host smart-96759a8e-eed4-42b6-9910-08a3a46a630b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130569430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2130569430
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.3598893347
Short name T439
Test name
Test status
Simulation time 1105348713 ps
CPU time 6.07 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:35:52 PM PDT 24
Peak memory 200640 kb
Host smart-72265a05-cce9-439d-96dd-817a1f9c2772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598893347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.3598893347
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.1201703170
Short name T777
Test name
Test status
Simulation time 18050030 ps
CPU time 0.85 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:35:47 PM PDT 24
Peak memory 200440 kb
Host smart-5c87833e-8712-4a08-8651-fd9c3136f967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201703170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1201703170
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.3103140361
Short name T810
Test name
Test status
Simulation time 1771518083 ps
CPU time 14.18 seconds
Started Jul 26 06:35:48 PM PDT 24
Finished Jul 26 06:36:03 PM PDT 24
Peak memory 200780 kb
Host smart-cb05f941-9b02-43de-a38a-5dae564a74ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103140361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.3103140361
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.1448054211
Short name T696
Test name
Test status
Simulation time 12810295542 ps
CPU time 233.53 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:39:40 PM PDT 24
Peak memory 215500 kb
Host smart-c3b42eb3-1cbd-4719-9c60-b95120a86f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1448054211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.1448054211
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.3355986175
Short name T638
Test name
Test status
Simulation time 59512055 ps
CPU time 0.92 seconds
Started Jul 26 06:35:49 PM PDT 24
Finished Jul 26 06:35:50 PM PDT 24
Peak memory 200440 kb
Host smart-cc0898f2-6c3a-44c2-bb2f-50065e5945c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355986175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3355986175
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.4047351125
Short name T558
Test name
Test status
Simulation time 58470134 ps
CPU time 0.92 seconds
Started Jul 26 06:36:00 PM PDT 24
Finished Jul 26 06:36:01 PM PDT 24
Peak memory 200488 kb
Host smart-67c772a2-6e17-4340-b35f-e7c254cf5079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047351125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.4047351125
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3782436234
Short name T374
Test name
Test status
Simulation time 23635731 ps
CPU time 0.88 seconds
Started Jul 26 06:35:51 PM PDT 24
Finished Jul 26 06:35:52 PM PDT 24
Peak memory 200460 kb
Host smart-945dba22-9001-4e90-9a0a-74bb67ff67d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782436234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.3782436234
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.168249184
Short name T268
Test name
Test status
Simulation time 89841504 ps
CPU time 1.13 seconds
Started Jul 26 06:35:53 PM PDT 24
Finished Jul 26 06:35:54 PM PDT 24
Peak memory 200476 kb
Host smart-57850a03-cacf-42eb-bed9-67fb8cb6f25f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168249184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.168249184
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.2322861155
Short name T323
Test name
Test status
Simulation time 15802915 ps
CPU time 0.76 seconds
Started Jul 26 06:35:46 PM PDT 24
Finished Jul 26 06:35:47 PM PDT 24
Peak memory 200424 kb
Host smart-cfebd046-406d-4c9b-90c9-45ef615e52ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322861155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2322861155
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.1627627677
Short name T3
Test name
Test status
Simulation time 1523813014 ps
CPU time 10.8 seconds
Started Jul 26 06:35:44 PM PDT 24
Finished Jul 26 06:35:55 PM PDT 24
Peak memory 200556 kb
Host smart-bf3b888d-cb39-47e5-8ace-9aac113d5a4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627627677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1627627677
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.2814281083
Short name T700
Test name
Test status
Simulation time 736242004 ps
CPU time 5.24 seconds
Started Jul 26 06:35:45 PM PDT 24
Finished Jul 26 06:35:51 PM PDT 24
Peak memory 200572 kb
Host smart-e36341d9-25f7-4c01-ab8f-e2f96b4fe8b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814281083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.2814281083
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.4187441266
Short name T407
Test name
Test status
Simulation time 29229156 ps
CPU time 0.99 seconds
Started Jul 26 06:35:56 PM PDT 24
Finished Jul 26 06:35:57 PM PDT 24
Peak memory 200452 kb
Host smart-c936b5f4-92e7-4eb4-a2dd-25c61130e5e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187441266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.4187441266
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.4223992137
Short name T390
Test name
Test status
Simulation time 63190516 ps
CPU time 0.89 seconds
Started Jul 26 06:35:54 PM PDT 24
Finished Jul 26 06:35:55 PM PDT 24
Peak memory 200412 kb
Host smart-0f8410f2-47d5-4402-91c7-3d7cb37b4edf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223992137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.4223992137
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.931130451
Short name T776
Test name
Test status
Simulation time 26450188 ps
CPU time 0.81 seconds
Started Jul 26 06:35:51 PM PDT 24
Finished Jul 26 06:35:52 PM PDT 24
Peak memory 200428 kb
Host smart-da0b2826-6712-4e31-a5ab-9504c80c5090
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931130451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.931130451
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.2476852604
Short name T327
Test name
Test status
Simulation time 763942568 ps
CPU time 2.98 seconds
Started Jul 26 06:35:53 PM PDT 24
Finished Jul 26 06:35:56 PM PDT 24
Peak memory 200588 kb
Host smart-512b98d2-2207-45b6-92c3-d7ac268b37f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476852604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2476852604
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2226912727
Short name T303
Test name
Test status
Simulation time 56902269 ps
CPU time 0.94 seconds
Started Jul 26 06:35:47 PM PDT 24
Finished Jul 26 06:35:48 PM PDT 24
Peak memory 200408 kb
Host smart-6ab2e139-ba86-4cb8-b396-0ee000c8f38e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226912727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2226912727
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.74208880
Short name T786
Test name
Test status
Simulation time 1338353239 ps
CPU time 6.35 seconds
Started Jul 26 06:36:00 PM PDT 24
Finished Jul 26 06:36:06 PM PDT 24
Peak memory 200416 kb
Host smart-9cf01e1d-0ead-4338-8774-790ec9dd93b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74208880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_stress_all.74208880
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.914764835
Short name T211
Test name
Test status
Simulation time 65781894 ps
CPU time 1.14 seconds
Started Jul 26 06:35:51 PM PDT 24
Finished Jul 26 06:35:53 PM PDT 24
Peak memory 200440 kb
Host smart-87df9290-5345-48fe-8aa6-f18dce540023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914764835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.914764835
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.957878522
Short name T487
Test name
Test status
Simulation time 157058605 ps
CPU time 1.17 seconds
Started Jul 26 06:36:00 PM PDT 24
Finished Jul 26 06:36:02 PM PDT 24
Peak memory 200488 kb
Host smart-b1c5d4fc-9927-46a7-87cb-6b0bb6ba13d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957878522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkm
gr_alert_test.957878522
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1708345709
Short name T590
Test name
Test status
Simulation time 49390028 ps
CPU time 0.89 seconds
Started Jul 26 06:35:58 PM PDT 24
Finished Jul 26 06:35:59 PM PDT 24
Peak memory 200472 kb
Host smart-7b69bfd8-1fdb-428a-b431-fd8295c2ec5c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708345709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1708345709
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.1267426200
Short name T36
Test name
Test status
Simulation time 22000680 ps
CPU time 0.78 seconds
Started Jul 26 06:35:55 PM PDT 24
Finished Jul 26 06:35:56 PM PDT 24
Peak memory 199936 kb
Host smart-bbb75361-7c69-4387-9717-b2f501ddf60f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267426200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.1267426200
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2068878395
Short name T807
Test name
Test status
Simulation time 20600589 ps
CPU time 0.84 seconds
Started Jul 26 06:35:54 PM PDT 24
Finished Jul 26 06:35:55 PM PDT 24
Peak memory 200416 kb
Host smart-8ee9efec-b3ae-43ea-96ee-50173a94cbfb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068878395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2068878395
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.3498758397
Short name T722
Test name
Test status
Simulation time 112806920 ps
CPU time 1.1 seconds
Started Jul 26 06:36:00 PM PDT 24
Finished Jul 26 06:36:01 PM PDT 24
Peak memory 200312 kb
Host smart-081709a1-f8d3-4e4b-8118-515dff100b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498758397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3498758397
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.2890713942
Short name T21
Test name
Test status
Simulation time 1343261229 ps
CPU time 5.52 seconds
Started Jul 26 06:35:56 PM PDT 24
Finished Jul 26 06:36:02 PM PDT 24
Peak memory 200392 kb
Host smart-d0fc098d-6311-428c-8322-4723484ae7f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890713942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2890713942
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.2867073389
Short name T394
Test name
Test status
Simulation time 1469048844 ps
CPU time 8.28 seconds
Started Jul 26 06:35:56 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 200556 kb
Host smart-4644b7a3-03bb-4c2c-833b-ba1dc44a0ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867073389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.2867073389
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.1206801132
Short name T326
Test name
Test status
Simulation time 61373292 ps
CPU time 1.04 seconds
Started Jul 26 06:36:00 PM PDT 24
Finished Jul 26 06:36:02 PM PDT 24
Peak memory 200476 kb
Host smart-b8ab9401-1696-4a79-a750-48bd1b379c5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206801132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.1206801132
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.908986213
Short name T17
Test name
Test status
Simulation time 21406772 ps
CPU time 0.75 seconds
Started Jul 26 06:35:57 PM PDT 24
Finished Jul 26 06:35:58 PM PDT 24
Peak memory 200484 kb
Host smart-3b8360b0-886b-443c-b7d7-aa07cb70a752
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908986213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.clkmgr_lc_clk_byp_req_intersig_mubi.908986213
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3709807219
Short name T731
Test name
Test status
Simulation time 51475026 ps
CPU time 0.89 seconds
Started Jul 26 06:35:57 PM PDT 24
Finished Jul 26 06:35:58 PM PDT 24
Peak memory 200328 kb
Host smart-c2df0f31-a547-47e8-9837-d0459919d0f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709807219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3709807219
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.908366951
Short name T618
Test name
Test status
Simulation time 17073005 ps
CPU time 0.76 seconds
Started Jul 26 06:36:00 PM PDT 24
Finished Jul 26 06:36:01 PM PDT 24
Peak memory 200424 kb
Host smart-c53ef366-2941-452a-b04c-ca20b883f0dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908366951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.908366951
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.4032340754
Short name T261
Test name
Test status
Simulation time 553845058 ps
CPU time 2.41 seconds
Started Jul 26 06:35:57 PM PDT 24
Finished Jul 26 06:36:00 PM PDT 24
Peak memory 200328 kb
Host smart-2bfdd9e7-2115-40d4-b175-6a0626d8a643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032340754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.4032340754
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.3866298479
Short name T283
Test name
Test status
Simulation time 43351685 ps
CPU time 0.95 seconds
Started Jul 26 06:35:58 PM PDT 24
Finished Jul 26 06:35:59 PM PDT 24
Peak memory 200420 kb
Host smart-aae3e1cf-e393-49df-b86a-bcfdfffa2feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866298479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3866298479
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_trans.4026564096
Short name T811
Test name
Test status
Simulation time 29738064 ps
CPU time 0.95 seconds
Started Jul 26 06:35:59 PM PDT 24
Finished Jul 26 06:36:00 PM PDT 24
Peak memory 200464 kb
Host smart-1615a230-bf81-4686-b0ed-95fdd155f258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026564096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.4026564096
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.3231998302
Short name T200
Test name
Test status
Simulation time 131707117 ps
CPU time 1.09 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:42 PM PDT 24
Peak memory 200464 kb
Host smart-67dca718-157b-46c4-a2f2-abbd9c8656d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231998302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.3231998302
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3147127135
Short name T193
Test name
Test status
Simulation time 63931950 ps
CPU time 0.96 seconds
Started Jul 26 06:32:40 PM PDT 24
Finished Jul 26 06:32:41 PM PDT 24
Peak memory 200484 kb
Host smart-433878e8-6fe4-4f3f-a93b-5f7f31ff97f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147127135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.3147127135
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.1294876364
Short name T369
Test name
Test status
Simulation time 18513677 ps
CPU time 0.75 seconds
Started Jul 26 06:32:31 PM PDT 24
Finished Jul 26 06:32:32 PM PDT 24
Peak memory 199644 kb
Host smart-2821728f-7bbb-4880-bfbb-6c4805b2d694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294876364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1294876364
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.1733147764
Short name T213
Test name
Test status
Simulation time 57281979 ps
CPU time 0.99 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:42 PM PDT 24
Peak memory 200456 kb
Host smart-6bda956b-040d-4d8a-9c9e-cf9a8c912bd4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733147764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.1733147764
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.3839694084
Short name T551
Test name
Test status
Simulation time 22228566 ps
CPU time 0.86 seconds
Started Jul 26 06:32:33 PM PDT 24
Finished Jul 26 06:32:34 PM PDT 24
Peak memory 200468 kb
Host smart-33bdad0d-a777-46a8-97ec-c4e4300edd33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839694084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.3839694084
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2109441696
Short name T508
Test name
Test status
Simulation time 920876134 ps
CPU time 7.33 seconds
Started Jul 26 06:32:32 PM PDT 24
Finished Jul 26 06:32:40 PM PDT 24
Peak memory 200524 kb
Host smart-15ab0e39-5d20-47ff-9a07-b98e2114679e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109441696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2109441696
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.3385511126
Short name T356
Test name
Test status
Simulation time 860340587 ps
CPU time 4.89 seconds
Started Jul 26 06:32:32 PM PDT 24
Finished Jul 26 06:32:37 PM PDT 24
Peak memory 200456 kb
Host smart-488a39d6-1dcb-4d8d-b441-6f69558398b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385511126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.3385511126
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1675786787
Short name T592
Test name
Test status
Simulation time 180685360 ps
CPU time 1.22 seconds
Started Jul 26 06:32:32 PM PDT 24
Finished Jul 26 06:32:33 PM PDT 24
Peak memory 200452 kb
Host smart-354d2d29-e052-4f1d-940e-e374901166d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675786787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.1675786787
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2007903597
Short name T359
Test name
Test status
Simulation time 15618862 ps
CPU time 0.79 seconds
Started Jul 26 06:32:43 PM PDT 24
Finished Jul 26 06:32:43 PM PDT 24
Peak memory 200436 kb
Host smart-6d938cae-7fec-498c-8661-cad3d50d1649
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007903597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.2007903597
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2353123629
Short name T6
Test name
Test status
Simulation time 84442025 ps
CPU time 1.13 seconds
Started Jul 26 06:32:31 PM PDT 24
Finished Jul 26 06:32:32 PM PDT 24
Peak memory 200468 kb
Host smart-35e26ff9-4368-4078-a822-652d976d653f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353123629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.2353123629
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3658007128
Short name T476
Test name
Test status
Simulation time 15709019 ps
CPU time 0.75 seconds
Started Jul 26 06:32:32 PM PDT 24
Finished Jul 26 06:32:33 PM PDT 24
Peak memory 200440 kb
Host smart-f62392f5-67e8-42a1-a89d-b47dca97de42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658007128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3658007128
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.144883036
Short name T698
Test name
Test status
Simulation time 1398541888 ps
CPU time 5.2 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:47 PM PDT 24
Peak memory 200632 kb
Host smart-c7816c28-456a-4107-9ff6-4be9321783f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144883036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.144883036
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.2870183181
Short name T19
Test name
Test status
Simulation time 47374375 ps
CPU time 0.89 seconds
Started Jul 26 06:32:32 PM PDT 24
Finished Jul 26 06:32:33 PM PDT 24
Peak memory 200420 kb
Host smart-35efd762-8528-4c68-a57e-7fac87446fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870183181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2870183181
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.941947410
Short name T616
Test name
Test status
Simulation time 3546258232 ps
CPU time 13.16 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:54 PM PDT 24
Peak memory 200696 kb
Host smart-0e9bb383-204b-4035-a9c2-f69c45c93e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941947410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.941947410
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.1531616690
Short name T196
Test name
Test status
Simulation time 44299282 ps
CPU time 0.94 seconds
Started Jul 26 06:32:31 PM PDT 24
Finished Jul 26 06:32:32 PM PDT 24
Peak memory 200416 kb
Host smart-b1b31b08-7658-489c-880b-39686eabe220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531616690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.1531616690
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.604436592
Short name T209
Test name
Test status
Simulation time 13461276 ps
CPU time 0.74 seconds
Started Jul 26 06:32:43 PM PDT 24
Finished Jul 26 06:32:44 PM PDT 24
Peak memory 200436 kb
Host smart-f8e2bbbd-71ec-4c32-a6dc-da24ee622b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604436592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg
r_alert_test.604436592
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.289734882
Short name T501
Test name
Test status
Simulation time 26613513 ps
CPU time 0.94 seconds
Started Jul 26 06:32:40 PM PDT 24
Finished Jul 26 06:32:41 PM PDT 24
Peak memory 200460 kb
Host smart-69d9e775-0522-4a0d-b49a-d8e556f7d28b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289734882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.289734882
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.3566249561
Short name T175
Test name
Test status
Simulation time 48948691 ps
CPU time 0.77 seconds
Started Jul 26 06:32:43 PM PDT 24
Finished Jul 26 06:32:44 PM PDT 24
Peak memory 199700 kb
Host smart-e884c9a3-cf55-45ed-947d-5c611d9241e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566249561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3566249561
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.2179762452
Short name T576
Test name
Test status
Simulation time 20802990 ps
CPU time 0.85 seconds
Started Jul 26 06:32:44 PM PDT 24
Finished Jul 26 06:32:45 PM PDT 24
Peak memory 200420 kb
Host smart-16d97624-dbdc-4feb-b046-bfd5216e603b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179762452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.2179762452
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.2252226657
Short name T723
Test name
Test status
Simulation time 240437333 ps
CPU time 1.46 seconds
Started Jul 26 06:32:44 PM PDT 24
Finished Jul 26 06:32:46 PM PDT 24
Peak memory 200484 kb
Host smart-55d6d81c-5a94-4353-8e69-389975b7ab84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252226657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2252226657
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.939268305
Short name T376
Test name
Test status
Simulation time 1829088983 ps
CPU time 8.74 seconds
Started Jul 26 06:32:42 PM PDT 24
Finished Jul 26 06:32:51 PM PDT 24
Peak memory 200544 kb
Host smart-614a32ae-b808-4602-b1df-8aa87a9261af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939268305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_tim
eout.939268305
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3955707180
Short name T277
Test name
Test status
Simulation time 20052153 ps
CPU time 0.87 seconds
Started Jul 26 06:32:44 PM PDT 24
Finished Jul 26 06:32:45 PM PDT 24
Peak memory 200484 kb
Host smart-cdb61323-ac82-40a4-877b-b7a5ed74d612
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955707180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.3955707180
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.4259667408
Short name T428
Test name
Test status
Simulation time 37869132 ps
CPU time 0.81 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:42 PM PDT 24
Peak memory 200480 kb
Host smart-f5f77427-9a46-4409-a981-9e2de395013f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259667408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.4259667408
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1282135528
Short name T597
Test name
Test status
Simulation time 20423300 ps
CPU time 0.82 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:42 PM PDT 24
Peak memory 200356 kb
Host smart-4fdf81fe-9d93-4a57-b647-a1990c0ada1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282135528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.1282135528
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.2898276466
Short name T225
Test name
Test status
Simulation time 45066096 ps
CPU time 0.82 seconds
Started Jul 26 06:32:39 PM PDT 24
Finished Jul 26 06:32:40 PM PDT 24
Peak memory 200404 kb
Host smart-45aa2c4e-baae-4603-93e6-7259e39b7039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898276466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2898276466
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.1792971533
Short name T656
Test name
Test status
Simulation time 419301825 ps
CPU time 2.68 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:44 PM PDT 24
Peak memory 200480 kb
Host smart-491bb0fe-3985-4383-8851-6b4f3433ba4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792971533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.1792971533
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1202265930
Short name T146
Test name
Test status
Simulation time 23087498 ps
CPU time 0.83 seconds
Started Jul 26 06:32:43 PM PDT 24
Finished Jul 26 06:32:44 PM PDT 24
Peak memory 200380 kb
Host smart-152b5606-aec9-4dfd-9938-0f8cfe52ed6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202265930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1202265930
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.343316376
Short name T539
Test name
Test status
Simulation time 6647911622 ps
CPU time 49.61 seconds
Started Jul 26 06:32:44 PM PDT 24
Finished Jul 26 06:33:33 PM PDT 24
Peak memory 200848 kb
Host smart-2c83c9a9-558c-46c9-ae82-3ea625eff11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343316376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.343316376
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.1242118161
Short name T339
Test name
Test status
Simulation time 64993304 ps
CPU time 0.97 seconds
Started Jul 26 06:32:39 PM PDT 24
Finished Jul 26 06:32:40 PM PDT 24
Peak memory 200456 kb
Host smart-539c8102-b916-48c5-aade-9999bbba354b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242118161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1242118161
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.319427630
Short name T488
Test name
Test status
Simulation time 38159578 ps
CPU time 0.82 seconds
Started Jul 26 06:32:47 PM PDT 24
Finished Jul 26 06:32:48 PM PDT 24
Peak memory 200336 kb
Host smart-ce3519ef-d845-4fd2-9e30-12473ef80fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319427630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg
r_alert_test.319427630
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1684070641
Short name T94
Test name
Test status
Simulation time 90405763 ps
CPU time 1.13 seconds
Started Jul 26 06:32:39 PM PDT 24
Finished Jul 26 06:32:41 PM PDT 24
Peak memory 200480 kb
Host smart-750238f9-e91b-46b8-8973-16721b8b2b4e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684070641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1684070641
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.704374883
Short name T400
Test name
Test status
Simulation time 14786510 ps
CPU time 0.72 seconds
Started Jul 26 06:32:43 PM PDT 24
Finished Jul 26 06:32:43 PM PDT 24
Peak memory 199668 kb
Host smart-57576d0c-6095-4cc4-891e-51c0f247b552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704374883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.704374883
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3453505147
Short name T398
Test name
Test status
Simulation time 46517725 ps
CPU time 0.91 seconds
Started Jul 26 06:32:47 PM PDT 24
Finished Jul 26 06:32:48 PM PDT 24
Peak memory 200752 kb
Host smart-73b3b23b-baae-4dc0-88d0-cbe0e3788e01
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453505147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.3453505147
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.620643482
Short name T451
Test name
Test status
Simulation time 15296052 ps
CPU time 0.81 seconds
Started Jul 26 06:32:40 PM PDT 24
Finished Jul 26 06:32:41 PM PDT 24
Peak memory 200436 kb
Host smart-05d1a75a-d923-49a6-8f0d-6ef5ba6b8ad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620643482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.620643482
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.4011506391
Short name T252
Test name
Test status
Simulation time 688701597 ps
CPU time 4.33 seconds
Started Jul 26 06:32:39 PM PDT 24
Finished Jul 26 06:32:43 PM PDT 24
Peak memory 200472 kb
Host smart-854ebdef-b342-4994-b06b-09e8cfd5def0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011506391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.4011506391
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.3945814698
Short name T286
Test name
Test status
Simulation time 1338981726 ps
CPU time 9.43 seconds
Started Jul 26 06:32:39 PM PDT 24
Finished Jul 26 06:32:49 PM PDT 24
Peak memory 200576 kb
Host smart-2c1f3f32-3478-416d-9957-3508786d6cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945814698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.3945814698
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1749255526
Short name T259
Test name
Test status
Simulation time 40361856 ps
CPU time 0.93 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:42 PM PDT 24
Peak memory 200428 kb
Host smart-2accbd4c-7b07-4737-8fba-a8090e6643bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749255526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.1749255526
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1045937413
Short name T76
Test name
Test status
Simulation time 70050943 ps
CPU time 0.89 seconds
Started Jul 26 06:32:39 PM PDT 24
Finished Jul 26 06:32:40 PM PDT 24
Peak memory 200340 kb
Host smart-3c7704ab-46a6-4ed0-aaa2-a16f186baa77
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045937413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.1045937413
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3360305431
Short name T275
Test name
Test status
Simulation time 93142972 ps
CPU time 1.11 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:42 PM PDT 24
Peak memory 200452 kb
Host smart-1eab18bf-3211-4c03-b9a3-e8c7fd26329a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360305431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3360305431
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.1035795316
Short name T526
Test name
Test status
Simulation time 14297190 ps
CPU time 0.76 seconds
Started Jul 26 06:32:42 PM PDT 24
Finished Jul 26 06:32:43 PM PDT 24
Peak memory 200480 kb
Host smart-c25ba415-d25c-48ff-baf8-58dad4974396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035795316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1035795316
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.3088901736
Short name T575
Test name
Test status
Simulation time 2046210922 ps
CPU time 7.1 seconds
Started Jul 26 06:32:50 PM PDT 24
Finished Jul 26 06:32:57 PM PDT 24
Peak memory 200616 kb
Host smart-74e9b4c2-8d5d-4f57-83dc-2e41be655b7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088901736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3088901736
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.279067467
Short name T552
Test name
Test status
Simulation time 40528847 ps
CPU time 0.96 seconds
Started Jul 26 06:32:41 PM PDT 24
Finished Jul 26 06:32:42 PM PDT 24
Peak memory 200424 kb
Host smart-a45dbc3e-1209-499e-88fc-4463e4aead3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279067467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.279067467
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.3797954311
Short name T645
Test name
Test status
Simulation time 7090855254 ps
CPU time 29.49 seconds
Started Jul 26 06:32:53 PM PDT 24
Finished Jul 26 06:33:23 PM PDT 24
Peak memory 200808 kb
Host smart-c24643ec-7f7d-4e7a-aaeb-882cc5822356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797954311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.3797954311
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.3361099015
Short name T388
Test name
Test status
Simulation time 47771253 ps
CPU time 0.88 seconds
Started Jul 26 06:32:40 PM PDT 24
Finished Jul 26 06:32:41 PM PDT 24
Peak memory 200468 kb
Host smart-9607d4b7-fe75-433f-b10b-e37948dea046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361099015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.3361099015
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.719294770
Short name T243
Test name
Test status
Simulation time 32021225 ps
CPU time 0.84 seconds
Started Jul 26 06:32:48 PM PDT 24
Finished Jul 26 06:32:49 PM PDT 24
Peak memory 200456 kb
Host smart-38840b69-4d99-414f-a4fd-062f5f3a05dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719294770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg
r_alert_test.719294770
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2107160267
Short name T571
Test name
Test status
Simulation time 81896254 ps
CPU time 1.11 seconds
Started Jul 26 06:32:45 PM PDT 24
Finished Jul 26 06:32:46 PM PDT 24
Peak memory 200472 kb
Host smart-c58f2efb-dda7-410f-bedc-4ee147ecfb47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107160267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.2107160267
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.282770253
Short name T51
Test name
Test status
Simulation time 17281555 ps
CPU time 0.71 seconds
Started Jul 26 06:32:47 PM PDT 24
Finished Jul 26 06:32:48 PM PDT 24
Peak memory 199684 kb
Host smart-f67342e1-84b3-48ff-a0b6-107fe0f80db9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282770253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.282770253
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.2501031654
Short name T38
Test name
Test status
Simulation time 31664761 ps
CPU time 0.9 seconds
Started Jul 26 06:32:46 PM PDT 24
Finished Jul 26 06:32:47 PM PDT 24
Peak memory 200496 kb
Host smart-99624f16-1d9b-4014-8280-83145bb13173
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501031654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.2501031654
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.224316590
Short name T573
Test name
Test status
Simulation time 25052207 ps
CPU time 0.75 seconds
Started Jul 26 06:32:45 PM PDT 24
Finished Jul 26 06:32:45 PM PDT 24
Peak memory 200476 kb
Host smart-a90df3ba-f054-400c-a62e-18a67a2a0eba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224316590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.224316590
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.3447984433
Short name T613
Test name
Test status
Simulation time 1397532130 ps
CPU time 11.01 seconds
Started Jul 26 06:32:47 PM PDT 24
Finished Jul 26 06:32:58 PM PDT 24
Peak memory 200508 kb
Host smart-b9d2dde0-e0e2-4b7d-b7e9-9ed325d53707
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447984433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.3447984433
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.667510246
Short name T232
Test name
Test status
Simulation time 2034274177 ps
CPU time 8.12 seconds
Started Jul 26 06:32:48 PM PDT 24
Finished Jul 26 06:32:56 PM PDT 24
Peak memory 200580 kb
Host smart-5a0cdf8b-9eef-4b7a-8536-2858266d19ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667510246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_tim
eout.667510246
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.2951489884
Short name T436
Test name
Test status
Simulation time 19564048 ps
CPU time 0.86 seconds
Started Jul 26 06:32:47 PM PDT 24
Finished Jul 26 06:32:48 PM PDT 24
Peak memory 200364 kb
Host smart-e16586b2-b013-4c26-801f-9f60895bcb3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951489884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.2951489884
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.3974123256
Short name T500
Test name
Test status
Simulation time 138135269 ps
CPU time 1.17 seconds
Started Jul 26 06:32:49 PM PDT 24
Finished Jul 26 06:32:51 PM PDT 24
Peak memory 200472 kb
Host smart-d12d861a-634c-4c55-bb11-2295317c0df4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974123256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.3974123256
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1172811856
Short name T320
Test name
Test status
Simulation time 24396907 ps
CPU time 0.89 seconds
Started Jul 26 06:32:47 PM PDT 24
Finished Jul 26 06:32:48 PM PDT 24
Peak memory 200352 kb
Host smart-9abe7cb9-7bc7-44d3-9269-92e91198cd32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172811856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.1172811856
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.2307539361
Short name T519
Test name
Test status
Simulation time 46861211 ps
CPU time 0.86 seconds
Started Jul 26 06:32:49 PM PDT 24
Finished Jul 26 06:32:50 PM PDT 24
Peak memory 200404 kb
Host smart-8333923b-d06b-4e7d-a310-38ca15406e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307539361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2307539361
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.3472558469
Short name T799
Test name
Test status
Simulation time 271264488 ps
CPU time 1.74 seconds
Started Jul 26 06:32:48 PM PDT 24
Finished Jul 26 06:32:50 PM PDT 24
Peak memory 200400 kb
Host smart-75c4ddae-df6a-4883-9dd1-7b63b5667831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472558469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.3472558469
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.1310817189
Short name T285
Test name
Test status
Simulation time 14323594 ps
CPU time 0.84 seconds
Started Jul 26 06:32:50 PM PDT 24
Finished Jul 26 06:32:51 PM PDT 24
Peak memory 200396 kb
Host smart-5ac9f1e7-a9e6-41c7-aa3d-461c564a8147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310817189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.1310817189
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.2475139048
Short name T37
Test name
Test status
Simulation time 183584938 ps
CPU time 1.38 seconds
Started Jul 26 06:32:48 PM PDT 24
Finished Jul 26 06:32:49 PM PDT 24
Peak memory 200468 kb
Host smart-e6ba5814-7239-4983-8487-35c1a6e1bd6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475139048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.2475139048
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.973257437
Short name T228
Test name
Test status
Simulation time 44398514 ps
CPU time 0.98 seconds
Started Jul 26 06:32:51 PM PDT 24
Finished Jul 26 06:32:52 PM PDT 24
Peak memory 200528 kb
Host smart-844f4b33-55b6-4355-9c81-6f1f1b6a2cbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973257437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.973257437
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.4031921146
Short name T31
Test name
Test status
Simulation time 30912843 ps
CPU time 0.82 seconds
Started Jul 26 06:32:53 PM PDT 24
Finished Jul 26 06:32:54 PM PDT 24
Peak memory 200476 kb
Host smart-fad1deae-a1d4-483a-a4f4-59b277c8725a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031921146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.4031921146
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3380734633
Short name T297
Test name
Test status
Simulation time 32302725 ps
CPU time 0.84 seconds
Started Jul 26 06:32:52 PM PDT 24
Finished Jul 26 06:32:53 PM PDT 24
Peak memory 200468 kb
Host smart-a891dbaa-2f75-4edc-93c4-5ab9b21cecc4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380734633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.3380734633
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.1863201836
Short name T634
Test name
Test status
Simulation time 13168487 ps
CPU time 0.72 seconds
Started Jul 26 06:32:54 PM PDT 24
Finished Jul 26 06:32:55 PM PDT 24
Peak memory 199684 kb
Host smart-98974625-0b4e-4ed5-af4a-5d6091ff766f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863201836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1863201836
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.3610608873
Short name T55
Test name
Test status
Simulation time 40641467 ps
CPU time 0.8 seconds
Started Jul 26 06:32:56 PM PDT 24
Finished Jul 26 06:32:57 PM PDT 24
Peak memory 200412 kb
Host smart-38b0ffc6-3883-45a9-96ff-f5649701ee88
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610608873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.3610608873
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1834927978
Short name T798
Test name
Test status
Simulation time 14772921 ps
CPU time 0.75 seconds
Started Jul 26 06:32:50 PM PDT 24
Finished Jul 26 06:32:51 PM PDT 24
Peak memory 200532 kb
Host smart-e44a2151-6487-4d6b-b6e8-5743722de094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834927978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1834927978
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.1698191779
Short name T272
Test name
Test status
Simulation time 681477671 ps
CPU time 5.78 seconds
Started Jul 26 06:32:47 PM PDT 24
Finished Jul 26 06:32:53 PM PDT 24
Peak memory 200528 kb
Host smart-772011bd-f3ed-4d15-900f-75402be3cc8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698191779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1698191779
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.283408799
Short name T697
Test name
Test status
Simulation time 2175034675 ps
CPU time 15.89 seconds
Started Jul 26 06:32:55 PM PDT 24
Finished Jul 26 06:33:11 PM PDT 24
Peak memory 200840 kb
Host smart-1fcb741e-bc73-4831-9ec7-36d1cc0c9204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283408799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim
eout.283408799
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.1618086028
Short name T578
Test name
Test status
Simulation time 183709629 ps
CPU time 1.55 seconds
Started Jul 26 06:32:53 PM PDT 24
Finished Jul 26 06:32:55 PM PDT 24
Peak memory 200444 kb
Host smart-85d7df61-9d5e-431f-b62c-d87a1d448b22
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618086028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.1618086028
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.703403270
Short name T708
Test name
Test status
Simulation time 17297744 ps
CPU time 0.82 seconds
Started Jul 26 06:32:55 PM PDT 24
Finished Jul 26 06:32:56 PM PDT 24
Peak memory 200452 kb
Host smart-149bfd2a-ab4e-4f83-bfa7-40157afd7a60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703403270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_clk_byp_req_intersig_mubi.703403270
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.516646602
Short name T255
Test name
Test status
Simulation time 16837838 ps
CPU time 0.79 seconds
Started Jul 26 06:32:54 PM PDT 24
Finished Jul 26 06:32:55 PM PDT 24
Peak memory 200436 kb
Host smart-ddcae859-c856-4182-9239-baeca4f35ca2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516646602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_ctrl_intersig_mubi.516646602
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.1722187697
Short name T378
Test name
Test status
Simulation time 23260263 ps
CPU time 0.76 seconds
Started Jul 26 06:32:54 PM PDT 24
Finished Jul 26 06:32:55 PM PDT 24
Peak memory 200420 kb
Host smart-ec84f707-99f8-4dfe-9dcf-7d6752182bcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722187697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1722187697
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1969504044
Short name T154
Test name
Test status
Simulation time 432717060 ps
CPU time 2.88 seconds
Started Jul 26 06:32:52 PM PDT 24
Finished Jul 26 06:32:55 PM PDT 24
Peak memory 200484 kb
Host smart-ac199e70-4aa6-4d81-b4f3-e06bcee8356e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969504044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1969504044
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.1133912771
Short name T440
Test name
Test status
Simulation time 20800695 ps
CPU time 0.86 seconds
Started Jul 26 06:32:50 PM PDT 24
Finished Jul 26 06:32:51 PM PDT 24
Peak memory 200380 kb
Host smart-03b04e55-a499-4ad9-8194-45d840d41833
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133912771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1133912771
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.1933093142
Short name T432
Test name
Test status
Simulation time 3031834783 ps
CPU time 12.58 seconds
Started Jul 26 06:32:55 PM PDT 24
Finished Jul 26 06:33:08 PM PDT 24
Peak memory 200804 kb
Host smart-3bef54f9-ea87-4a94-b252-4973bd7cbdcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933093142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.1933093142
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.3398728565
Short name T170
Test name
Test status
Simulation time 357926381951 ps
CPU time 1303.69 seconds
Started Jul 26 06:32:54 PM PDT 24
Finished Jul 26 06:54:38 PM PDT 24
Peak memory 209196 kb
Host smart-5eef9319-8510-4fc6-844c-0430b821f78e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3398728565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3398728565
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.3670893345
Short name T448
Test name
Test status
Simulation time 72691718 ps
CPU time 1.04 seconds
Started Jul 26 06:32:54 PM PDT 24
Finished Jul 26 06:32:55 PM PDT 24
Peak memory 200480 kb
Host smart-4f9124c1-8d82-4b18-91fd-b8cf22d45028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670893345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3670893345
Directory /workspace/9.clkmgr_trans/latest
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