Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 143233090 1 T1 469572 T5 3404 T2 141246
auto[1] 267112 1 T1 11072 T15 224 T20 446


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 143202414 1 T1 469939 T5 3404 T2 141246
auto[1] 297788 1 T1 7402 T15 100 T16 256


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 143158082 1 T1 469673 T5 3404 T2 141246
auto[1] 342120 1 T1 10064 T15 164 T16 292


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 136020584 1 T1 450622 T5 3404 T2 141246
auto[1] 7479618 1 T1 200572 T15 260 T16 3232


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 83663842 1 T1 329974 T5 2216 T2 141228
auto[1] 59836360 1 T1 140705 T5 1188 T2 18


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 76131956 1 T1 310215 T5 2216 T2 141228
auto[0] auto[0] auto[0] auto[0] auto[1] 59612390 1 T1 139966 T5 1188 T2 18
auto[0] auto[0] auto[0] auto[1] auto[0] 19018 1 T1 578 T15 106 T20 32
auto[0] auto[0] auto[0] auto[1] auto[1] 5194 1 T1 104 T20 98 T101 72
auto[0] auto[0] auto[1] auto[0] auto[0] 7105132 1 T1 186498 T15 134 T16 532
auto[0] auto[0] auto[1] auto[0] auto[1] 148702 1 T1 5038 T16 2440 T20 74
auto[0] auto[0] auto[1] auto[1] auto[0] 30266 1 T1 1082 T15 26 T20 28
auto[0] auto[0] auto[1] auto[1] auto[1] 7056 1 T1 286 T11 74 T87 14
auto[0] auto[1] auto[0] auto[0] auto[0] 64048 1 T1 114 T16 38 T4 2452
auto[0] auto[1] auto[0] auto[0] auto[1] 1006 1 T11 14 T12 22 T14 16
auto[0] auto[1] auto[0] auto[1] auto[0] 7162 1 T1 290 T98 112 T11 84
auto[0] auto[1] auto[0] auto[1] auto[1] 1814 1 T11 90 T12 60 T14 74
auto[0] auto[1] auto[1] auto[0] auto[0] 6674 1 T1 184 T15 32 T16 32
auto[0] auto[1] auto[1] auto[0] auto[1] 1370 1 T1 52 T16 10 T111 2
auto[0] auto[1] auto[1] auto[1] auto[0] 13402 1 T1 598 T11 92 T12 110
auto[0] auto[1] auto[1] auto[1] auto[1] 2892 1 T1 98 T111 68 T13 48
auto[1] auto[0] auto[0] auto[0] auto[0] 47984 1 T1 238 T15 26 T16 42
auto[1] auto[0] auto[0] auto[0] auto[1] 2696 1 T1 110 T15 26 T20 14
auto[1] auto[0] auto[0] auto[1] auto[0] 21316 1 T1 1086 T15 44 T20 42
auto[1] auto[0] auto[0] auto[1] auto[1] 5492 1 T1 188 T20 50 T97 40
auto[1] auto[0] auto[1] auto[0] auto[0] 17144 1 T1 380 T16 40 T20 6
auto[1] auto[0] auto[1] auto[0] auto[1] 4464 1 T1 34 T16 34 T20 8
auto[1] auto[0] auto[1] auto[1] auto[0] 34644 1 T1 1616 T20 98 T97 344
auto[1] auto[0] auto[1] auto[1] auto[1] 8960 1 T1 346 T87 106 T163 66
auto[1] auto[1] auto[0] auto[0] auto[0] 51468 1 T1 328 T16 24 T20 16
auto[1] auto[1] auto[0] auto[0] auto[1] 4138 1 T1 60 T16 8 T97 8
auto[1] auto[1] auto[0] auto[1] auto[0] 35062 1 T1 1028 T20 46 T97 102
auto[1] auto[1] auto[0] auto[1] auto[1] 9840 1 T1 290 T97 48 T98 46
auto[1] auto[1] auto[1] auto[0] auto[0] 26882 1 T1 730 T15 20 T16 76
auto[1] auto[1] auto[1] auto[0] auto[1] 7036 1 T1 148 T16 68 T11 374
auto[1] auto[1] auto[1] auto[1] auto[0] 51684 1 T1 2846 T15 48 T20 52
auto[1] auto[1] auto[1] auto[1] auto[1] 13310 1 T1 636 T11 218 T12 130

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