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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 979
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T793 /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1867545311 Jul 27 05:39:34 PM PDT 24 Jul 27 05:39:35 PM PDT 24 20740349 ps
T794 /workspace/coverage/default/19.clkmgr_smoke.3792039827 Jul 27 05:38:23 PM PDT 24 Jul 27 05:38:23 PM PDT 24 24398611 ps
T795 /workspace/coverage/default/24.clkmgr_peri.2726231736 Jul 27 05:38:28 PM PDT 24 Jul 27 05:38:29 PM PDT 24 20200702 ps
T796 /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.459871729 Jul 27 05:38:41 PM PDT 24 Jul 27 05:38:42 PM PDT 24 142648148 ps
T797 /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2605570606 Jul 27 05:37:43 PM PDT 24 Jul 27 05:37:43 PM PDT 24 16349616 ps
T798 /workspace/coverage/default/29.clkmgr_extclk.446332181 Jul 27 05:38:37 PM PDT 24 Jul 27 05:38:38 PM PDT 24 47271222 ps
T799 /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1634045465 Jul 27 05:39:23 PM PDT 24 Jul 27 05:39:24 PM PDT 24 32824422 ps
T800 /workspace/coverage/default/45.clkmgr_extclk.3709692698 Jul 27 05:39:20 PM PDT 24 Jul 27 05:39:21 PM PDT 24 26225725 ps
T801 /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2835322765 Jul 27 05:39:37 PM PDT 24 Jul 27 05:39:38 PM PDT 24 32115866 ps
T802 /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3014747493 Jul 27 05:38:10 PM PDT 24 Jul 27 05:38:11 PM PDT 24 127019979 ps
T803 /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.486407205 Jul 27 05:38:52 PM PDT 24 Jul 27 05:38:53 PM PDT 24 62307448 ps
T804 /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2797913895 Jul 27 05:39:14 PM PDT 24 Jul 27 05:39:15 PM PDT 24 72985356 ps
T805 /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2448090887 Jul 27 05:38:55 PM PDT 24 Jul 27 05:38:56 PM PDT 24 91702477 ps
T806 /workspace/coverage/default/25.clkmgr_frequency_timeout.3739659510 Jul 27 05:38:29 PM PDT 24 Jul 27 05:38:39 PM PDT 24 2544008481 ps
T807 /workspace/coverage/default/5.clkmgr_frequency_timeout.1138770490 Jul 27 05:37:39 PM PDT 24 Jul 27 05:37:52 PM PDT 24 1820076625 ps
T808 /workspace/coverage/default/4.clkmgr_alert_test.2561268792 Jul 27 05:37:35 PM PDT 24 Jul 27 05:37:36 PM PDT 24 39512800 ps
T809 /workspace/coverage/default/29.clkmgr_clk_status.1558209035 Jul 27 05:38:40 PM PDT 24 Jul 27 05:38:41 PM PDT 24 96292706 ps
T810 /workspace/coverage/default/26.clkmgr_trans.3615767609 Jul 27 05:38:30 PM PDT 24 Jul 27 05:38:33 PM PDT 24 352272073 ps
T811 /workspace/coverage/default/2.clkmgr_clk_status.2167362214 Jul 27 05:37:25 PM PDT 24 Jul 27 05:37:26 PM PDT 24 74025752 ps
T812 /workspace/coverage/default/25.clkmgr_trans.4068530491 Jul 27 05:38:30 PM PDT 24 Jul 27 05:38:31 PM PDT 24 16401865 ps
T813 /workspace/coverage/default/34.clkmgr_frequency_timeout.507789710 Jul 27 05:38:55 PM PDT 24 Jul 27 05:39:00 PM PDT 24 1000698853 ps
T814 /workspace/coverage/default/1.clkmgr_trans.3096517956 Jul 27 05:37:26 PM PDT 24 Jul 27 05:37:27 PM PDT 24 18772078 ps
T815 /workspace/coverage/default/16.clkmgr_smoke.1016575018 Jul 27 05:38:10 PM PDT 24 Jul 27 05:38:11 PM PDT 24 45962308 ps
T816 /workspace/coverage/default/41.clkmgr_div_intersig_mubi.3408801859 Jul 27 05:39:14 PM PDT 24 Jul 27 05:39:15 PM PDT 24 36106159 ps
T64 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2152544372 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 34579006 ps
T46 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3774990799 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:52 PM PDT 24 604606951 ps
T65 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2179191105 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:09 PM PDT 24 16396165 ps
T66 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.890264868 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:09 PM PDT 24 151621021 ps
T47 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.496137102 Jul 27 05:35:14 PM PDT 24 Jul 27 05:35:17 PM PDT 24 100092960 ps
T48 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2351001664 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:21 PM PDT 24 173064602 ps
T80 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2257140386 Jul 27 05:34:40 PM PDT 24 Jul 27 05:34:43 PM PDT 24 459227112 ps
T817 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.301852279 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:51 PM PDT 24 20008169 ps
T818 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.87127638 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:02 PM PDT 24 225471144 ps
T819 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.693895857 Jul 27 05:35:30 PM PDT 24 Jul 27 05:35:30 PM PDT 24 27357419 ps
T150 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.957199007 Jul 27 05:34:53 PM PDT 24 Jul 27 05:35:02 PM PDT 24 580704677 ps
T49 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1190728984 Jul 27 05:35:16 PM PDT 24 Jul 27 05:35:19 PM PDT 24 139512738 ps
T51 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1275444815 Jul 27 05:35:15 PM PDT 24 Jul 27 05:35:17 PM PDT 24 113531070 ps
T81 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.225526742 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:04 PM PDT 24 764840999 ps
T67 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3899323334 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:01 PM PDT 24 93507174 ps
T820 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.867560501 Jul 27 05:34:39 PM PDT 24 Jul 27 05:34:54 PM PDT 24 3627905580 ps
T50 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2366846351 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:21 PM PDT 24 66274622 ps
T82 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3861184337 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:20 PM PDT 24 237315304 ps
T821 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.2101222786 Jul 27 05:35:17 PM PDT 24 Jul 27 05:35:18 PM PDT 24 53790921 ps
T822 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3071528720 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:09 PM PDT 24 21771042 ps
T823 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1977186582 Jul 27 05:35:29 PM PDT 24 Jul 27 05:35:30 PM PDT 24 26183082 ps
T151 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.4194719089 Jul 27 05:34:38 PM PDT 24 Jul 27 05:34:45 PM PDT 24 1194804353 ps
T824 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3539707363 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:12 PM PDT 24 14958796 ps
T93 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.4254716964 Jul 27 05:34:48 PM PDT 24 Jul 27 05:34:51 PM PDT 24 300635975 ps
T825 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.697712622 Jul 27 05:35:28 PM PDT 24 Jul 27 05:35:29 PM PDT 24 19815632 ps
T68 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3526052668 Jul 27 05:35:13 PM PDT 24 Jul 27 05:35:16 PM PDT 24 165525235 ps
T826 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1665939941 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:02 PM PDT 24 23621293 ps
T96 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2705068107 Jul 27 05:35:13 PM PDT 24 Jul 27 05:35:15 PM PDT 24 76525345 ps
T54 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3959128908 Jul 27 05:34:41 PM PDT 24 Jul 27 05:34:43 PM PDT 24 401636722 ps
T827 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.921254415 Jul 27 05:34:48 PM PDT 24 Jul 27 05:34:50 PM PDT 24 26083643 ps
T69 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.898344798 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:02 PM PDT 24 103160114 ps
T112 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3084504358 Jul 27 05:35:15 PM PDT 24 Jul 27 05:35:17 PM PDT 24 147167394 ps
T828 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1824205092 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:11 PM PDT 24 436104939 ps
T829 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1127779722 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 15332526 ps
T830 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1126114909 Jul 27 05:34:48 PM PDT 24 Jul 27 05:34:49 PM PDT 24 32572130 ps
T113 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2754389626 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:02 PM PDT 24 153375383 ps
T831 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2837111978 Jul 27 05:35:20 PM PDT 24 Jul 27 05:35:24 PM PDT 24 489626645 ps
T832 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2550015235 Jul 27 05:34:47 PM PDT 24 Jul 27 05:34:59 PM PDT 24 1994514505 ps
T52 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.272312807 Jul 27 05:35:13 PM PDT 24 Jul 27 05:35:15 PM PDT 24 274564788 ps
T833 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3891211122 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:13 PM PDT 24 102761672 ps
T115 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2497021596 Jul 27 05:35:22 PM PDT 24 Jul 27 05:35:24 PM PDT 24 201004815 ps
T834 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2723027778 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:20 PM PDT 24 11009268 ps
T114 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.4288798169 Jul 27 05:35:02 PM PDT 24 Jul 27 05:35:04 PM PDT 24 121916508 ps
T53 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1362752286 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:52 PM PDT 24 126292393 ps
T116 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.4080458392 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:14 PM PDT 24 105875194 ps
T835 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1847063642 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 53329341 ps
T119 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.602301679 Jul 27 05:35:09 PM PDT 24 Jul 27 05:35:11 PM PDT 24 233639147 ps
T836 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2165638480 Jul 27 05:35:20 PM PDT 24 Jul 27 05:35:21 PM PDT 24 12735663 ps
T837 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2052875626 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:03 PM PDT 24 128516349 ps
T838 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1522657098 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 10376609 ps
T118 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2566801174 Jul 27 05:35:14 PM PDT 24 Jul 27 05:35:16 PM PDT 24 81640999 ps
T839 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2018415640 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:50 PM PDT 24 18999616 ps
T840 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2545509533 Jul 27 05:35:15 PM PDT 24 Jul 27 05:35:16 PM PDT 24 267394128 ps
T117 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2631546627 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:03 PM PDT 24 118662303 ps
T841 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.887892724 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:13 PM PDT 24 34257798 ps
T842 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1316250154 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:10 PM PDT 24 67357333 ps
T843 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3554291901 Jul 27 05:35:02 PM PDT 24 Jul 27 05:35:03 PM PDT 24 12274947 ps
T844 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2114391119 Jul 27 05:35:31 PM PDT 24 Jul 27 05:35:31 PM PDT 24 12688936 ps
T845 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.791933350 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:18 PM PDT 24 13613855 ps
T846 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1219483964 Jul 27 05:34:52 PM PDT 24 Jul 27 05:34:54 PM PDT 24 67615823 ps
T847 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2192589505 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:09 PM PDT 24 18028912 ps
T121 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.451446666 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:03 PM PDT 24 127494519 ps
T848 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4160155509 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:19 PM PDT 24 37925984 ps
T85 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3043087177 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:01 PM PDT 24 241257165 ps
T849 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.979053606 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:20 PM PDT 24 14607522 ps
T850 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1014443949 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:19 PM PDT 24 17600845 ps
T851 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3180879974 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:20 PM PDT 24 55849882 ps
T852 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1625719064 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:21 PM PDT 24 176735751 ps
T853 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2753688820 Jul 27 05:35:27 PM PDT 24 Jul 27 05:35:28 PM PDT 24 15881827 ps
T854 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3064908583 Jul 27 05:35:15 PM PDT 24 Jul 27 05:35:15 PM PDT 24 15674005 ps
T855 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3052703372 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:14 PM PDT 24 92159325 ps
T856 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3480196245 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:19 PM PDT 24 145990945 ps
T857 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1132506470 Jul 27 05:35:14 PM PDT 24 Jul 27 05:35:15 PM PDT 24 25559995 ps
T858 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4056930667 Jul 27 05:35:15 PM PDT 24 Jul 27 05:35:17 PM PDT 24 204657366 ps
T859 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3675046316 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:02 PM PDT 24 15865676 ps
T860 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1992743450 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:50 PM PDT 24 21117282 ps
T861 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2712206235 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:20 PM PDT 24 22475412 ps
T862 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2174111881 Jul 27 05:35:27 PM PDT 24 Jul 27 05:35:27 PM PDT 24 31219445 ps
T863 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.4063759981 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:09 PM PDT 24 28489093 ps
T864 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1375647159 Jul 27 05:34:44 PM PDT 24 Jul 27 05:34:46 PM PDT 24 36447632 ps
T94 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3300253411 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:12 PM PDT 24 888155298 ps
T865 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3988926663 Jul 27 05:35:07 PM PDT 24 Jul 27 05:35:08 PM PDT 24 67851181 ps
T866 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1704740473 Jul 27 05:35:14 PM PDT 24 Jul 27 05:35:17 PM PDT 24 341414439 ps
T867 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2924665442 Jul 27 05:34:39 PM PDT 24 Jul 27 05:34:42 PM PDT 24 185733444 ps
T868 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1455260171 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:02 PM PDT 24 95736215 ps
T869 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1619871449 Jul 27 05:34:48 PM PDT 24 Jul 27 05:34:50 PM PDT 24 97277425 ps
T870 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2381507047 Jul 27 05:35:09 PM PDT 24 Jul 27 05:35:12 PM PDT 24 149301928 ps
T86 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.983837125 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:01 PM PDT 24 74820823 ps
T871 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2296858184 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:10 PM PDT 24 56216297 ps
T872 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2338007538 Jul 27 05:35:29 PM PDT 24 Jul 27 05:35:29 PM PDT 24 26257563 ps
T873 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2405406705 Jul 27 05:35:17 PM PDT 24 Jul 27 05:35:17 PM PDT 24 13424774 ps
T874 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.690985263 Jul 27 05:35:22 PM PDT 24 Jul 27 05:35:22 PM PDT 24 14375500 ps
T875 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3477887876 Jul 27 05:34:58 PM PDT 24 Jul 27 05:34:59 PM PDT 24 19428466 ps
T876 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3019519904 Jul 27 05:35:28 PM PDT 24 Jul 27 05:35:29 PM PDT 24 29717238 ps
T877 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3282123642 Jul 27 05:35:16 PM PDT 24 Jul 27 05:35:18 PM PDT 24 173188772 ps
T878 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1625668521 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:14 PM PDT 24 48953170 ps
T879 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.654944381 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:00 PM PDT 24 12337022 ps
T880 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2509449194 Jul 27 05:35:08 PM PDT 24 Jul 27 05:35:09 PM PDT 24 54902535 ps
T881 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3428283193 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:04 PM PDT 24 93080979 ps
T120 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1432480928 Jul 27 05:35:11 PM PDT 24 Jul 27 05:35:14 PM PDT 24 506021040 ps
T882 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.829871392 Jul 27 05:35:23 PM PDT 24 Jul 27 05:35:24 PM PDT 24 35298582 ps
T883 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3472346143 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:02 PM PDT 24 78129665 ps
T884 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1754165363 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:20 PM PDT 24 79459282 ps
T885 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2335407460 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:00 PM PDT 24 76798928 ps
T886 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1048084533 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 49155962 ps
T887 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.382628128 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:51 PM PDT 24 35218373 ps
T888 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.4223238328 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:50 PM PDT 24 99034174 ps
T889 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1569120677 Jul 27 05:35:17 PM PDT 24 Jul 27 05:35:18 PM PDT 24 73604592 ps
T890 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2915312486 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:52 PM PDT 24 52827704 ps
T891 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.592398806 Jul 27 05:35:14 PM PDT 24 Jul 27 05:35:15 PM PDT 24 53468858 ps
T892 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3109502375 Jul 27 05:35:30 PM PDT 24 Jul 27 05:35:30 PM PDT 24 27836004 ps
T893 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.1701216220 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:18 PM PDT 24 19047903 ps
T894 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1571702252 Jul 27 05:35:03 PM PDT 24 Jul 27 05:35:04 PM PDT 24 52400365 ps
T895 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.905975389 Jul 27 05:35:27 PM PDT 24 Jul 27 05:35:28 PM PDT 24 15924868 ps
T896 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.68182118 Jul 27 05:34:47 PM PDT 24 Jul 27 05:34:48 PM PDT 24 17538445 ps
T897 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.897340703 Jul 27 05:34:42 PM PDT 24 Jul 27 05:34:43 PM PDT 24 33666515 ps
T898 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1553755998 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:19 PM PDT 24 36305960 ps
T899 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1959844719 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:02 PM PDT 24 57198985 ps
T900 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2434506537 Jul 27 05:34:40 PM PDT 24 Jul 27 05:34:42 PM PDT 24 96167081 ps
T901 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3120173108 Jul 27 05:34:51 PM PDT 24 Jul 27 05:34:52 PM PDT 24 115513661 ps
T902 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.744388859 Jul 27 05:35:27 PM PDT 24 Jul 27 05:35:28 PM PDT 24 24519328 ps
T903 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.192956564 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:20 PM PDT 24 159978938 ps
T95 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1029991865 Jul 27 05:35:11 PM PDT 24 Jul 27 05:35:14 PM PDT 24 139484574 ps
T904 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4272655096 Jul 27 05:35:03 PM PDT 24 Jul 27 05:35:04 PM PDT 24 100582333 ps
T905 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3539605596 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 45557179 ps
T906 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2781452801 Jul 27 05:34:42 PM PDT 24 Jul 27 05:34:43 PM PDT 24 19119910 ps
T907 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.610287017 Jul 27 05:35:02 PM PDT 24 Jul 27 05:35:05 PM PDT 24 207109076 ps
T161 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.762827600 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:05 PM PDT 24 669603598 ps
T162 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3998491417 Jul 27 05:35:20 PM PDT 24 Jul 27 05:35:23 PM PDT 24 98853822 ps
T908 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.892411060 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:00 PM PDT 24 23494076 ps
T909 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.868699017 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:13 PM PDT 24 24212906 ps
T910 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.539775164 Jul 27 05:35:09 PM PDT 24 Jul 27 05:35:10 PM PDT 24 55878417 ps
T911 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1804734480 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:12 PM PDT 24 16182298 ps
T912 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3157347077 Jul 27 05:34:39 PM PDT 24 Jul 27 05:34:40 PM PDT 24 37754421 ps
T913 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3151992198 Jul 27 05:35:15 PM PDT 24 Jul 27 05:35:20 PM PDT 24 841053306 ps
T914 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.4237645589 Jul 27 05:34:58 PM PDT 24 Jul 27 05:35:01 PM PDT 24 337464606 ps
T915 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2475330851 Jul 27 05:35:16 PM PDT 24 Jul 27 05:35:18 PM PDT 24 183686179 ps
T916 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.401946965 Jul 27 05:34:51 PM PDT 24 Jul 27 05:34:52 PM PDT 24 79131645 ps
T917 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2533201108 Jul 27 05:34:40 PM PDT 24 Jul 27 05:34:41 PM PDT 24 85278247 ps
T918 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2802159950 Jul 27 05:35:03 PM PDT 24 Jul 27 05:35:04 PM PDT 24 45063009 ps
T919 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1137739392 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:50 PM PDT 24 18138101 ps
T920 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3040187791 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:04 PM PDT 24 872722602 ps
T921 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.652210091 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:51 PM PDT 24 22917813 ps
T922 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1855216567 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:01 PM PDT 24 68672323 ps
T923 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2518969888 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:14 PM PDT 24 56713019 ps
T924 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.513515617 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:00 PM PDT 24 38476733 ps
T925 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1444735739 Jul 27 05:35:16 PM PDT 24 Jul 27 05:35:17 PM PDT 24 41445862 ps
T926 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2899829604 Jul 27 05:35:13 PM PDT 24 Jul 27 05:35:15 PM PDT 24 54002977 ps
T927 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1314423774 Jul 27 05:35:28 PM PDT 24 Jul 27 05:35:29 PM PDT 24 11548905 ps
T928 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2305040877 Jul 27 05:35:29 PM PDT 24 Jul 27 05:35:30 PM PDT 24 13837412 ps
T929 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2974292174 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 83358587 ps
T930 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.4027654408 Jul 27 05:34:41 PM PDT 24 Jul 27 05:34:42 PM PDT 24 79885744 ps
T931 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.226559289 Jul 27 05:34:39 PM PDT 24 Jul 27 05:34:40 PM PDT 24 33189893 ps
T89 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1290696771 Jul 27 05:34:38 PM PDT 24 Jul 27 05:34:41 PM PDT 24 95342557 ps
T932 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1354983982 Jul 27 05:35:27 PM PDT 24 Jul 27 05:35:27 PM PDT 24 28634322 ps
T933 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1954623235 Jul 27 05:35:28 PM PDT 24 Jul 27 05:35:29 PM PDT 24 35457420 ps
T934 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1708418062 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:50 PM PDT 24 16004118 ps
T935 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1249290413 Jul 27 05:34:58 PM PDT 24 Jul 27 05:34:59 PM PDT 24 23403310 ps
T936 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2314308846 Jul 27 05:34:40 PM PDT 24 Jul 27 05:34:43 PM PDT 24 353354066 ps
T937 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3712215889 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:53 PM PDT 24 148183405 ps
T938 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1245494801 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:05 PM PDT 24 993078298 ps
T939 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.829574875 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:52 PM PDT 24 51528178 ps
T940 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2570940875 Jul 27 05:35:09 PM PDT 24 Jul 27 05:35:11 PM PDT 24 140300399 ps
T941 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2337530559 Jul 27 05:35:23 PM PDT 24 Jul 27 05:35:25 PM PDT 24 60779682 ps
T942 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.680071839 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:06 PM PDT 24 969051297 ps
T943 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1772212525 Jul 27 05:35:10 PM PDT 24 Jul 27 05:35:12 PM PDT 24 140060869 ps
T944 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.580617465 Jul 27 05:35:28 PM PDT 24 Jul 27 05:35:29 PM PDT 24 118842765 ps
T945 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.1528895571 Jul 27 05:35:15 PM PDT 24 Jul 27 05:35:17 PM PDT 24 33500539 ps
T946 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2905419936 Jul 27 05:35:31 PM PDT 24 Jul 27 05:35:32 PM PDT 24 40629726 ps
T91 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.3624585508 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:21 PM PDT 24 136352411 ps
T947 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.140719499 Jul 27 05:35:04 PM PDT 24 Jul 27 05:35:06 PM PDT 24 80169606 ps
T90 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2027504268 Jul 27 05:35:13 PM PDT 24 Jul 27 05:35:16 PM PDT 24 399701763 ps
T948 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1136634149 Jul 27 05:34:58 PM PDT 24 Jul 27 05:35:00 PM PDT 24 325260388 ps
T949 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.361670363 Jul 27 05:35:26 PM PDT 24 Jul 27 05:35:26 PM PDT 24 12479164 ps
T950 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1708447362 Jul 27 05:35:12 PM PDT 24 Jul 27 05:35:14 PM PDT 24 29206908 ps
T951 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.962794450 Jul 27 05:35:10 PM PDT 24 Jul 27 05:35:11 PM PDT 24 67256208 ps
T952 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2248745663 Jul 27 05:35:09 PM PDT 24 Jul 27 05:35:10 PM PDT 24 15027408 ps
T953 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3753474831 Jul 27 05:35:22 PM PDT 24 Jul 27 05:35:25 PM PDT 24 43220526 ps
T954 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3625259469 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:02 PM PDT 24 18944431 ps
T955 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.151859772 Jul 27 05:35:25 PM PDT 24 Jul 27 05:35:26 PM PDT 24 29952855 ps
T956 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1366701885 Jul 27 05:35:02 PM PDT 24 Jul 27 05:35:03 PM PDT 24 30263561 ps
T957 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.2003478657 Jul 27 05:35:13 PM PDT 24 Jul 27 05:35:15 PM PDT 24 161251382 ps
T958 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2074352659 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:20 PM PDT 24 90942736 ps
T959 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1458701054 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:03 PM PDT 24 293946193 ps
T960 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1446751077 Jul 27 05:35:04 PM PDT 24 Jul 27 05:35:05 PM PDT 24 49048826 ps
T961 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3447966543 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:56 PM PDT 24 271110931 ps
T962 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.4070252264 Jul 27 05:35:23 PM PDT 24 Jul 27 05:35:24 PM PDT 24 108159325 ps
T963 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.422520737 Jul 27 05:35:14 PM PDT 24 Jul 27 05:35:16 PM PDT 24 76791093 ps
T964 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3347391329 Jul 27 05:34:59 PM PDT 24 Jul 27 05:35:01 PM PDT 24 19819909 ps
T965 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1691894354 Jul 27 05:35:17 PM PDT 24 Jul 27 05:35:18 PM PDT 24 29270876 ps
T966 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2937735744 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:50 PM PDT 24 14331621 ps
T967 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1226298174 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:51 PM PDT 24 67237511 ps
T968 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2632491360 Jul 27 05:35:10 PM PDT 24 Jul 27 05:35:12 PM PDT 24 92212127 ps
T92 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4218976299 Jul 27 05:35:01 PM PDT 24 Jul 27 05:35:03 PM PDT 24 92836856 ps
T969 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.4248719795 Jul 27 05:35:19 PM PDT 24 Jul 27 05:35:20 PM PDT 24 25347647 ps
T970 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3333422762 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:04 PM PDT 24 591885646 ps
T971 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1594791612 Jul 27 05:34:50 PM PDT 24 Jul 27 05:34:53 PM PDT 24 144322594 ps
T972 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3066389942 Jul 27 05:35:00 PM PDT 24 Jul 27 05:35:01 PM PDT 24 29635069 ps
T973 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.579322956 Jul 27 05:35:29 PM PDT 24 Jul 27 05:35:29 PM PDT 24 13765143 ps
T974 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2891131014 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:20 PM PDT 24 39226487 ps
T975 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1135032468 Jul 27 05:34:52 PM PDT 24 Jul 27 05:34:54 PM PDT 24 30076777 ps
T976 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.873260015 Jul 27 05:35:18 PM PDT 24 Jul 27 05:35:19 PM PDT 24 40887607 ps
T977 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2600669867 Jul 27 05:35:28 PM PDT 24 Jul 27 05:35:29 PM PDT 24 15300991 ps
T978 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.4274112461 Jul 27 05:34:49 PM PDT 24 Jul 27 05:34:52 PM PDT 24 426772729 ps
T979 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2506835946 Jul 27 05:34:48 PM PDT 24 Jul 27 05:34:50 PM PDT 24 181712710 ps

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2234155705
Short name T1
Test name
Test status
Simulation time 213999416951 ps
CPU time 1011.79 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:55:00 PM PDT 24
Peak memory 216904 kb
Host smart-2c46bbca-ee7f-4ff7-8822-f87fa4152b1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2234155705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2234155705
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.2841023783
Short name T4
Test name
Test status
Simulation time 1293180683 ps
CPU time 6.74 seconds
Started Jul 27 05:39:31 PM PDT 24
Finished Jul 27 05:39:38 PM PDT 24
Peak memory 200572 kb
Host smart-18d90743-abbd-4b8a-b428-115285c9483e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841023783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2841023783
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3774990799
Short name T46
Test name
Test status
Simulation time 604606951 ps
CPU time 3.03 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 217840 kb
Host smart-8d500c40-f5a7-4fed-b910-a8c34b0e683d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774990799 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.3774990799
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.598754164
Short name T33
Test name
Test status
Simulation time 298173376 ps
CPU time 3.01 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 217296 kb
Host smart-806a80d2-70f1-442f-8c8f-edf966473812
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598754164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr
_sec_cm.598754164
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.1624559875
Short name T30
Test name
Test status
Simulation time 26177855 ps
CPU time 0.74 seconds
Started Jul 27 05:38:12 PM PDT 24
Finished Jul 27 05:38:13 PM PDT 24
Peak memory 199676 kb
Host smart-d544cf8c-d742-43ff-a69e-f13581e4f9cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624559875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.1624559875
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.930616657
Short name T12
Test name
Test status
Simulation time 6823790261 ps
CPU time 49.65 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:38:33 PM PDT 24
Peak memory 200780 kb
Host smart-fdc66b52-43a7-4c51-b930-7dd8e09ae9fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930616657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.930616657
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1869200585
Short name T19
Test name
Test status
Simulation time 76119677 ps
CPU time 0.99 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:39 PM PDT 24
Peak memory 200460 kb
Host smart-1a64feca-8993-4461-8212-5566406f0d2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869200585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.1869200585
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2257140386
Short name T80
Test name
Test status
Simulation time 459227112 ps
CPU time 3.17 seconds
Started Jul 27 05:34:40 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 201184 kb
Host smart-33c5cca5-29f0-4b35-8c9e-d472c3d1ba16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257140386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.2257140386
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.496137102
Short name T47
Test name
Test status
Simulation time 100092960 ps
CPU time 2.78 seconds
Started Jul 27 05:35:14 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 201688 kb
Host smart-72fd1357-2920-4f81-a094-e2e656232043
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496137102 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.496137102
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.1456123929
Short name T58
Test name
Test status
Simulation time 77668543736 ps
CPU time 550.65 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:46:45 PM PDT 24
Peak memory 209168 kb
Host smart-baae5160-8be4-4b2d-b0e6-28afcbdd3340
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1456123929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.1456123929
Directory /workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.3082005682
Short name T27
Test name
Test status
Simulation time 19880548 ps
CPU time 0.82 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200468 kb
Host smart-2fad680a-f7fc-4b80-95ea-e670aca54073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082005682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.3082005682
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.1156159481
Short name T20
Test name
Test status
Simulation time 23871720 ps
CPU time 0.9 seconds
Started Jul 27 05:37:52 PM PDT 24
Finished Jul 27 05:37:53 PM PDT 24
Peak memory 200464 kb
Host smart-b82a83b6-eae8-44f1-8b09-f7c51ee351e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156159481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.1156159481
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2027504268
Short name T90
Test name
Test status
Simulation time 399701763 ps
CPU time 3.71 seconds
Started Jul 27 05:35:13 PM PDT 24
Finished Jul 27 05:35:16 PM PDT 24
Peak memory 201124 kb
Host smart-ea5ce7b5-5f14-43bf-9c0d-dd2cbfbab1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027504268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.2027504268
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.4080458392
Short name T116
Test name
Test status
Simulation time 105875194 ps
CPU time 1.81 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:14 PM PDT 24
Peak memory 201504 kb
Host smart-a8d20295-e6f8-41c4-ba65-3c935a3b155a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080458392 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.4080458392
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.3620387445
Short name T24
Test name
Test status
Simulation time 781112364 ps
CPU time 4.79 seconds
Started Jul 27 05:38:36 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200904 kb
Host smart-69890a08-e720-4f7e-98c5-cafa513b16be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620387445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3620387445
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3959128908
Short name T54
Test name
Test status
Simulation time 401636722 ps
CPU time 2.45 seconds
Started Jul 27 05:34:41 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 209576 kb
Host smart-1313c89c-0d79-4e66-a26f-549358fb9d48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959128908 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.3959128908
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.3173512208
Short name T41
Test name
Test status
Simulation time 228781469 ps
CPU time 1.65 seconds
Started Jul 27 05:37:28 PM PDT 24
Finished Jul 27 05:37:29 PM PDT 24
Peak memory 200400 kb
Host smart-52a3e6b9-db00-4450-a46b-9161c8553807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173512208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.3173512208
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3186559046
Short name T73
Test name
Test status
Simulation time 47907047 ps
CPU time 0.93 seconds
Started Jul 27 05:37:59 PM PDT 24
Finished Jul 27 05:38:00 PM PDT 24
Peak memory 200468 kb
Host smart-5a54b0f7-1b29-4153-a8f1-f9404effe9ca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186559046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.3186559046
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2632491360
Short name T968
Test name
Test status
Simulation time 92212127 ps
CPU time 1.61 seconds
Started Jul 27 05:35:10 PM PDT 24
Finished Jul 27 05:35:12 PM PDT 24
Peak memory 201172 kb
Host smart-d0a02f6b-9323-4968-b45c-28d28674146f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632491360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.2632491360
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.2162400139
Short name T11
Test name
Test status
Simulation time 74087456434 ps
CPU time 487.45 seconds
Started Jul 27 05:39:36 PM PDT 24
Finished Jul 27 05:47:43 PM PDT 24
Peak memory 209120 kb
Host smart-cafe4e63-e4dc-4116-a3f1-157deca3ed59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2162400139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.2162400139
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1375647159
Short name T864
Test name
Test status
Simulation time 36447632 ps
CPU time 1.51 seconds
Started Jul 27 05:34:44 PM PDT 24
Finished Jul 27 05:34:46 PM PDT 24
Peak memory 201184 kb
Host smart-35d09c19-2e09-48b0-89eb-77c697d99bd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375647159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.1375647159
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.867560501
Short name T820
Test name
Test status
Simulation time 3627905580 ps
CPU time 15.05 seconds
Started Jul 27 05:34:39 PM PDT 24
Finished Jul 27 05:34:54 PM PDT 24
Peak memory 201224 kb
Host smart-a23e3016-dfc2-4964-baad-624e30cc7053
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867560501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.867560501
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3157347077
Short name T912
Test name
Test status
Simulation time 37754421 ps
CPU time 0.8 seconds
Started Jul 27 05:34:39 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 200924 kb
Host smart-e955b60b-c89d-4a0c-b1cd-b7f52a97d74a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157347077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.3157347077
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.4223238328
Short name T888
Test name
Test status
Simulation time 99034174 ps
CPU time 1.47 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 201132 kb
Host smart-1782826d-a068-4bfc-a101-b8221dd7e678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223238328 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.4223238328
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2781452801
Short name T906
Test name
Test status
Simulation time 19119910 ps
CPU time 0.77 seconds
Started Jul 27 05:34:42 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 200932 kb
Host smart-1fd7f4fa-8530-4aed-a347-ba472d37dc8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781452801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.2781452801
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1137739392
Short name T919
Test name
Test status
Simulation time 18138101 ps
CPU time 0.67 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 199580 kb
Host smart-a1e7ecab-9968-4638-8bcd-8207cacff3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137739392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1137739392
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.897340703
Short name T897
Test name
Test status
Simulation time 33666515 ps
CPU time 1.41 seconds
Started Jul 27 05:34:42 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 201116 kb
Host smart-c004d484-64e8-4764-bfbd-ddf7a82c4896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897340703 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.clkmgr_same_csr_outstanding.897340703
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.4027654408
Short name T930
Test name
Test status
Simulation time 79885744 ps
CPU time 1.36 seconds
Started Jul 27 05:34:41 PM PDT 24
Finished Jul 27 05:34:42 PM PDT 24
Peak memory 201276 kb
Host smart-d321966e-5e99-424e-8b98-b9e315e58686
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027654408 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.4027654408
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3712215889
Short name T937
Test name
Test status
Simulation time 148183405 ps
CPU time 2.9 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:53 PM PDT 24
Peak memory 209596 kb
Host smart-f8ee75f0-eb11-4ac0-b932-9f078b895c54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712215889 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3712215889
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2924665442
Short name T867
Test name
Test status
Simulation time 185733444 ps
CPU time 3.47 seconds
Started Jul 27 05:34:39 PM PDT 24
Finished Jul 27 05:34:42 PM PDT 24
Peak memory 201120 kb
Host smart-ff86bb0e-df71-417f-aede-3c8acc41b2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924665442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.2924665442
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1290696771
Short name T89
Test name
Test status
Simulation time 95342557 ps
CPU time 2.41 seconds
Started Jul 27 05:34:38 PM PDT 24
Finished Jul 27 05:34:41 PM PDT 24
Peak memory 201196 kb
Host smart-3a6cca62-9fbd-4596-9964-9b1c418236f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290696771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.1290696771
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2314308846
Short name T936
Test name
Test status
Simulation time 353354066 ps
CPU time 2.61 seconds
Started Jul 27 05:34:40 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 201188 kb
Host smart-5c15c733-f8f9-4484-8901-d6808b4ac24b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314308846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.2314308846
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3447966543
Short name T961
Test name
Test status
Simulation time 271110931 ps
CPU time 6.65 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:56 PM PDT 24
Peak memory 201096 kb
Host smart-778889da-ca54-4742-beaf-076bdcef412c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447966543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.3447966543
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1992743450
Short name T860
Test name
Test status
Simulation time 21117282 ps
CPU time 0.83 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 200880 kb
Host smart-9d1f150f-7081-4475-af5a-cc19f585c0dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992743450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.1992743450
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.401946965
Short name T916
Test name
Test status
Simulation time 79131645 ps
CPU time 1.05 seconds
Started Jul 27 05:34:51 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 201000 kb
Host smart-e61499ab-179a-48a1-844f-bff792d17c60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401946965 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.401946965
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2533201108
Short name T917
Test name
Test status
Simulation time 85278247 ps
CPU time 0.97 seconds
Started Jul 27 05:34:40 PM PDT 24
Finished Jul 27 05:34:41 PM PDT 24
Peak memory 200936 kb
Host smart-eb37b632-c885-429a-a13f-6fe8ceedb974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533201108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.2533201108
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.226559289
Short name T931
Test name
Test status
Simulation time 33189893 ps
CPU time 0.76 seconds
Started Jul 27 05:34:39 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 199544 kb
Host smart-faeb9dc2-cccf-45f8-85f7-59e8dff4e6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226559289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkm
gr_intr_test.226559289
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2434506537
Short name T900
Test name
Test status
Simulation time 96167081 ps
CPU time 1.2 seconds
Started Jul 27 05:34:40 PM PDT 24
Finished Jul 27 05:34:42 PM PDT 24
Peak memory 200996 kb
Host smart-5afc6d23-0fcb-4534-a8c1-170d80530037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434506537 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.2434506537
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1275444815
Short name T51
Test name
Test status
Simulation time 113531070 ps
CPU time 2.59 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 209608 kb
Host smart-dc625c3c-0ff5-4751-bc30-d42784abe19a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275444815 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.1275444815
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.4194719089
Short name T151
Test name
Test status
Simulation time 1194804353 ps
CPU time 6.79 seconds
Started Jul 27 05:34:38 PM PDT 24
Finished Jul 27 05:34:45 PM PDT 24
Peak memory 201164 kb
Host smart-4b81314d-b89f-44fc-903e-33c6b257026c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194719089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.4194719089
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3988926663
Short name T865
Test name
Test status
Simulation time 67851181 ps
CPU time 1.01 seconds
Started Jul 27 05:35:07 PM PDT 24
Finished Jul 27 05:35:08 PM PDT 24
Peak memory 201080 kb
Host smart-20686a7f-32b1-4e3c-9e57-61cc1fce370d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988926663 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.3988926663
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1249290413
Short name T935
Test name
Test status
Simulation time 23403310 ps
CPU time 0.77 seconds
Started Jul 27 05:34:58 PM PDT 24
Finished Jul 27 05:34:59 PM PDT 24
Peak memory 201028 kb
Host smart-c255812b-2f07-4eae-9cd7-e68c47716f78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249290413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.1249290413
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3554291901
Short name T843
Test name
Test status
Simulation time 12274947 ps
CPU time 0.67 seconds
Started Jul 27 05:35:02 PM PDT 24
Finished Jul 27 05:35:03 PM PDT 24
Peak memory 199668 kb
Host smart-4aa2f5eb-c1d3-45bd-a6bd-1a23b98c0608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554291901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.3554291901
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2899829604
Short name T926
Test name
Test status
Simulation time 54002977 ps
CPU time 1.41 seconds
Started Jul 27 05:35:13 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 201220 kb
Host smart-99730b0d-c00e-4283-b124-0aba808be807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899829604 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.2899829604
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.4288798169
Short name T114
Test name
Test status
Simulation time 121916508 ps
CPU time 2.1 seconds
Started Jul 27 05:35:02 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 209628 kb
Host smart-f8c11fb4-5ad9-445d-b73f-309901bab35b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288798169 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.4288798169
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2052875626
Short name T837
Test name
Test status
Simulation time 128516349 ps
CPU time 2.7 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:03 PM PDT 24
Peak memory 209692 kb
Host smart-6d10d82f-6c80-440e-b4c3-56d466c8f9fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052875626 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2052875626
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1704740473
Short name T866
Test name
Test status
Simulation time 341414439 ps
CPU time 3.49 seconds
Started Jul 27 05:35:14 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 201216 kb
Host smart-186b14d3-a39f-4418-a290-2552d6a6c85d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704740473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.1704740473
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.225526742
Short name T81
Test name
Test status
Simulation time 764840999 ps
CPU time 4.21 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 201244 kb
Host smart-e8134d91-5278-47e0-9fbc-a8934d6dd95c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225526742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_tl_intg_err.225526742
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2192589505
Short name T847
Test name
Test status
Simulation time 18028912 ps
CPU time 0.88 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:09 PM PDT 24
Peak memory 201108 kb
Host smart-022589a9-aa1a-4607-a6a4-48ee745e433c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192589505 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.2192589505
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.592398806
Short name T891
Test name
Test status
Simulation time 53468858 ps
CPU time 0.96 seconds
Started Jul 27 05:35:14 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 200284 kb
Host smart-18c4a046-bb24-46d0-a2d4-65952002354f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592398806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
clkmgr_csr_rw.592398806
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3539707363
Short name T824
Test name
Test status
Simulation time 14958796 ps
CPU time 0.67 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:12 PM PDT 24
Peak memory 199608 kb
Host smart-ca6092f0-d991-40d6-9190-b747a4beb75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539707363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.3539707363
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.890264868
Short name T66
Test name
Test status
Simulation time 151621021 ps
CPU time 1.32 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:09 PM PDT 24
Peak memory 201064 kb
Host smart-fca223a5-1e03-42fe-91c5-684bde3b1b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890264868 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 11.clkmgr_same_csr_outstanding.890264868
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4056930667
Short name T858
Test name
Test status
Simulation time 204657366 ps
CPU time 2.06 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 209680 kb
Host smart-d65979a7-aed5-4711-8df5-5476497f5c8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056930667 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.4056930667
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1772212525
Short name T943
Test name
Test status
Simulation time 140060869 ps
CPU time 1.8 seconds
Started Jul 27 05:35:10 PM PDT 24
Finished Jul 27 05:35:12 PM PDT 24
Peak memory 201524 kb
Host smart-de503fa1-35f3-43cc-9426-5513ace537f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772212525 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.1772212525
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1824205092
Short name T828
Test name
Test status
Simulation time 436104939 ps
CPU time 3.58 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:11 PM PDT 24
Peak memory 201184 kb
Host smart-7a9c9139-9136-42bd-96c0-3820c102918b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824205092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.1824205092
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1708447362
Short name T950
Test name
Test status
Simulation time 29206908 ps
CPU time 1.44 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:14 PM PDT 24
Peak memory 201148 kb
Host smart-07c0acb4-6b0c-494e-a7ae-5d1db60be8a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708447362 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.1708447362
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2179191105
Short name T65
Test name
Test status
Simulation time 16396165 ps
CPU time 0.83 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:09 PM PDT 24
Peak memory 200992 kb
Host smart-41bfac3c-6ef0-4cd2-80f0-6ea522dcfeca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179191105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.2179191105
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3071528720
Short name T822
Test name
Test status
Simulation time 21771042 ps
CPU time 0.66 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:09 PM PDT 24
Peak memory 199620 kb
Host smart-4db69efe-ea30-4a0d-b424-dae59dacdcd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071528720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.3071528720
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1316250154
Short name T842
Test name
Test status
Simulation time 67357333 ps
CPU time 1.1 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:10 PM PDT 24
Peak memory 201072 kb
Host smart-56899890-f3e0-4e30-85b0-5cb33c466363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316250154 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1316250154
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.962794450
Short name T951
Test name
Test status
Simulation time 67256208 ps
CPU time 1.5 seconds
Started Jul 27 05:35:10 PM PDT 24
Finished Jul 27 05:35:11 PM PDT 24
Peak memory 201152 kb
Host smart-8d7e84d1-0b5b-4863-ac03-9ec0aa6973f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962794450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_tl_errors.962794450
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1029991865
Short name T95
Test name
Test status
Simulation time 139484574 ps
CPU time 3.03 seconds
Started Jul 27 05:35:11 PM PDT 24
Finished Jul 27 05:35:14 PM PDT 24
Peak memory 201248 kb
Host smart-f90aee86-6f27-423a-ac42-d6da41d1fdcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029991865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1029991865
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2545509533
Short name T840
Test name
Test status
Simulation time 267394128 ps
CPU time 1.79 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:16 PM PDT 24
Peak memory 201044 kb
Host smart-942f904b-ee37-4d3d-b944-f841416e427e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545509533 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.2545509533
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2509449194
Short name T880
Test name
Test status
Simulation time 54902535 ps
CPU time 0.83 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:09 PM PDT 24
Peak memory 200848 kb
Host smart-692127f7-ca04-412f-9aee-e71dd8889439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509449194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.2509449194
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1804734480
Short name T911
Test name
Test status
Simulation time 16182298 ps
CPU time 0.68 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:12 PM PDT 24
Peak memory 199608 kb
Host smart-f67b1040-54b2-4434-afbd-a40eb92bbe16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804734480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.1804734480
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3891211122
Short name T833
Test name
Test status
Simulation time 102761672 ps
CPU time 1.17 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:13 PM PDT 24
Peak memory 200900 kb
Host smart-76a028a1-a11d-49ff-a0ac-376960329d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891211122 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.3891211122
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1432480928
Short name T120
Test name
Test status
Simulation time 506021040 ps
CPU time 2.45 seconds
Started Jul 27 05:35:11 PM PDT 24
Finished Jul 27 05:35:14 PM PDT 24
Peak memory 201276 kb
Host smart-5ec8e469-f266-4bf4-b7ef-3448b8f443b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432480928 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.1432480928
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2381507047
Short name T870
Test name
Test status
Simulation time 149301928 ps
CPU time 2.82 seconds
Started Jul 27 05:35:09 PM PDT 24
Finished Jul 27 05:35:12 PM PDT 24
Peak memory 201504 kb
Host smart-59175051-8762-4663-b211-6a24f88728cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381507047 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.2381507047
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3052703372
Short name T855
Test name
Test status
Simulation time 92159325 ps
CPU time 1.87 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:14 PM PDT 24
Peak memory 201048 kb
Host smart-131f7ecf-9c6c-4a47-857c-deff78bd1299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052703372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.3052703372
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2570940875
Short name T940
Test name
Test status
Simulation time 140300399 ps
CPU time 1.49 seconds
Started Jul 27 05:35:09 PM PDT 24
Finished Jul 27 05:35:11 PM PDT 24
Peak memory 201080 kb
Host smart-d87697ea-5143-4496-8935-6b6f10c70537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570940875 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.2570940875
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1132506470
Short name T857
Test name
Test status
Simulation time 25559995 ps
CPU time 0.9 seconds
Started Jul 27 05:35:14 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 201208 kb
Host smart-fea0a8ea-c746-4c1f-8759-8d745edc72c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132506470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.1132506470
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.4063759981
Short name T863
Test name
Test status
Simulation time 28489093 ps
CPU time 0.68 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:09 PM PDT 24
Peak memory 199584 kb
Host smart-af7830b0-80af-42d8-b017-b1df7479599b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063759981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.4063759981
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.422520737
Short name T963
Test name
Test status
Simulation time 76791093 ps
CPU time 1.53 seconds
Started Jul 27 05:35:14 PM PDT 24
Finished Jul 27 05:35:16 PM PDT 24
Peak memory 200516 kb
Host smart-de8faec4-7299-4b88-9ee1-824837cb3bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422520737 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 14.clkmgr_same_csr_outstanding.422520737
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.602301679
Short name T119
Test name
Test status
Simulation time 233639147 ps
CPU time 2.08 seconds
Started Jul 27 05:35:09 PM PDT 24
Finished Jul 27 05:35:11 PM PDT 24
Peak memory 217788 kb
Host smart-dbd7f537-1077-44e7-b7fc-9d179c2ee5dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602301679 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.clkmgr_shadow_reg_errors.602301679
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.2003478657
Short name T957
Test name
Test status
Simulation time 161251382 ps
CPU time 2.17 seconds
Started Jul 27 05:35:13 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 201484 kb
Host smart-3cb3bb9a-f452-41e5-ad52-12a0b0fa0343
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003478657 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.2003478657
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.539775164
Short name T910
Test name
Test status
Simulation time 55878417 ps
CPU time 1.19 seconds
Started Jul 27 05:35:09 PM PDT 24
Finished Jul 27 05:35:10 PM PDT 24
Peak memory 200908 kb
Host smart-1e6299ba-4934-4f76-8c2a-955b232b8425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539775164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_tl_errors.539775164
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3300253411
Short name T94
Test name
Test status
Simulation time 888155298 ps
CPU time 4.14 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:12 PM PDT 24
Peak memory 201156 kb
Host smart-39c1adfc-d733-458a-acd5-d5ace0dcebea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300253411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.3300253411
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.887892724
Short name T841
Test name
Test status
Simulation time 34257798 ps
CPU time 1.1 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:13 PM PDT 24
Peak memory 200984 kb
Host smart-85dba829-3f26-44d4-a27c-34bf3ba3aff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887892724 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.887892724
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1444735739
Short name T925
Test name
Test status
Simulation time 41445862 ps
CPU time 0.78 seconds
Started Jul 27 05:35:16 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 200892 kb
Host smart-9d99815c-bebb-44ba-9d4b-3e672ac206ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444735739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.1444735739
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2248745663
Short name T952
Test name
Test status
Simulation time 15027408 ps
CPU time 0.67 seconds
Started Jul 27 05:35:09 PM PDT 24
Finished Jul 27 05:35:10 PM PDT 24
Peak memory 199524 kb
Host smart-358225c9-2daf-4dc8-94f2-1d26e66e9f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248745663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2248745663
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.868699017
Short name T909
Test name
Test status
Simulation time 24212906 ps
CPU time 1.06 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:13 PM PDT 24
Peak memory 201000 kb
Host smart-2fec888e-d6b1-4459-8fcc-1cc497e76108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868699017 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 15.clkmgr_same_csr_outstanding.868699017
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2566801174
Short name T118
Test name
Test status
Simulation time 81640999 ps
CPU time 1.8 seconds
Started Jul 27 05:35:14 PM PDT 24
Finished Jul 27 05:35:16 PM PDT 24
Peak memory 218024 kb
Host smart-9ef54900-b846-4010-b794-9e09b58ca7b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566801174 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.2566801174
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3084504358
Short name T112
Test name
Test status
Simulation time 147167394 ps
CPU time 1.93 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 201784 kb
Host smart-f2f0a4e5-bc6b-4e99-96df-7429e6e68704
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084504358 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3084504358
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2296858184
Short name T871
Test name
Test status
Simulation time 56216297 ps
CPU time 1.66 seconds
Started Jul 27 05:35:08 PM PDT 24
Finished Jul 27 05:35:10 PM PDT 24
Peak memory 201204 kb
Host smart-9b235d6e-6e03-4613-9877-1663bdf13693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296858184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.2296858184
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2705068107
Short name T96
Test name
Test status
Simulation time 76525345 ps
CPU time 1.81 seconds
Started Jul 27 05:35:13 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 201128 kb
Host smart-2d0dc9dc-3cb5-4005-a378-12a34bb990a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705068107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.2705068107
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4160155509
Short name T848
Test name
Test status
Simulation time 37925984 ps
CPU time 1.59 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:19 PM PDT 24
Peak memory 201236 kb
Host smart-28d63b1e-252a-483a-b240-89835918e1c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160155509 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.4160155509
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1014443949
Short name T850
Test name
Test status
Simulation time 17600845 ps
CPU time 0.87 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:19 PM PDT 24
Peak memory 200956 kb
Host smart-53cd1f66-273d-44ab-a51c-00d64a102f5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014443949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.1014443949
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.829871392
Short name T882
Test name
Test status
Simulation time 35298582 ps
CPU time 0.71 seconds
Started Jul 27 05:35:23 PM PDT 24
Finished Jul 27 05:35:24 PM PDT 24
Peak memory 199548 kb
Host smart-73af03af-eaf6-4d56-a29a-7511583029ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829871392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk
mgr_intr_test.829871392
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.192956564
Short name T903
Test name
Test status
Simulation time 159978938 ps
CPU time 1.55 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 201064 kb
Host smart-90b61e97-87b4-4d68-8b5c-a7ffda4508c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192956564 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 16.clkmgr_same_csr_outstanding.192956564
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.272312807
Short name T52
Test name
Test status
Simulation time 274564788 ps
CPU time 2.19 seconds
Started Jul 27 05:35:13 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 201420 kb
Host smart-0a2320c4-a771-4cc5-acbb-00e46951ae40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272312807 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.clkmgr_shadow_reg_errors.272312807
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3526052668
Short name T68
Test name
Test status
Simulation time 165525235 ps
CPU time 3.05 seconds
Started Jul 27 05:35:13 PM PDT 24
Finished Jul 27 05:35:16 PM PDT 24
Peak memory 209708 kb
Host smart-e81b0a2d-9c9a-4657-8322-f7f2bd5e2d46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526052668 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.3526052668
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1625668521
Short name T878
Test name
Test status
Simulation time 48953170 ps
CPU time 1.73 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:14 PM PDT 24
Peak memory 201092 kb
Host smart-5057697f-7c1a-45ca-8fa8-a73f789e9876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625668521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.1625668521
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2518969888
Short name T923
Test name
Test status
Simulation time 56713019 ps
CPU time 1.56 seconds
Started Jul 27 05:35:12 PM PDT 24
Finished Jul 27 05:35:14 PM PDT 24
Peak memory 201232 kb
Host smart-57dc4a03-1eb0-45a6-9254-15aed4b27e50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518969888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.2518969888
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1569120677
Short name T889
Test name
Test status
Simulation time 73604592 ps
CPU time 1.01 seconds
Started Jul 27 05:35:17 PM PDT 24
Finished Jul 27 05:35:18 PM PDT 24
Peak memory 201080 kb
Host smart-3f333e23-30dd-4afe-9b96-e6e0cd4a68b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569120677 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.1569120677
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2074352659
Short name T958
Test name
Test status
Simulation time 90942736 ps
CPU time 0.95 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 200996 kb
Host smart-c716318b-a314-4e2e-a1da-ceba83c73a95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074352659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.2074352659
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2723027778
Short name T834
Test name
Test status
Simulation time 11009268 ps
CPU time 0.73 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 199684 kb
Host smart-2b4153c6-0a31-4d82-ac83-8e1fe5228905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723027778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2723027778
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.4070252264
Short name T962
Test name
Test status
Simulation time 108159325 ps
CPU time 1.41 seconds
Started Jul 27 05:35:23 PM PDT 24
Finished Jul 27 05:35:24 PM PDT 24
Peak memory 201216 kb
Host smart-720f571e-b993-43b0-919c-bb520c756fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070252264 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.4070252264
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3282123642
Short name T877
Test name
Test status
Simulation time 173188772 ps
CPU time 1.68 seconds
Started Jul 27 05:35:16 PM PDT 24
Finished Jul 27 05:35:18 PM PDT 24
Peak memory 201168 kb
Host smart-10cea95d-7dc2-44b4-99fc-423007a673d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282123642 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3282123642
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1190728984
Short name T49
Test name
Test status
Simulation time 139512738 ps
CPU time 2.85 seconds
Started Jul 27 05:35:16 PM PDT 24
Finished Jul 27 05:35:19 PM PDT 24
Peak memory 209692 kb
Host smart-65ec3096-4128-4a6c-aad3-e47934c12d54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190728984 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1190728984
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3753474831
Short name T953
Test name
Test status
Simulation time 43220526 ps
CPU time 2.82 seconds
Started Jul 27 05:35:22 PM PDT 24
Finished Jul 27 05:35:25 PM PDT 24
Peak memory 201124 kb
Host smart-5f5140d5-b6a9-4aeb-a43b-5083a6eca0da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753474831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3753474831
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.3624585508
Short name T91
Test name
Test status
Simulation time 136352411 ps
CPU time 2.78 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 201200 kb
Host smart-7087fdff-fb75-463e-b068-e581242c3d29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624585508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.3624585508
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1691894354
Short name T965
Test name
Test status
Simulation time 29270876 ps
CPU time 1.53 seconds
Started Jul 27 05:35:17 PM PDT 24
Finished Jul 27 05:35:18 PM PDT 24
Peak memory 201236 kb
Host smart-bd69f154-38af-4659-ad26-315aa2670098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691894354 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.1691894354
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1625719064
Short name T852
Test name
Test status
Simulation time 176735751 ps
CPU time 1.17 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 201188 kb
Host smart-d2df5a81-89c0-401b-ae0c-91045facad85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625719064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.1625719064
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1754165363
Short name T884
Test name
Test status
Simulation time 79459282 ps
CPU time 0.82 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 199576 kb
Host smart-60c890cc-7ff8-4a9d-90c6-ee3349551c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754165363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.1754165363
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.873260015
Short name T976
Test name
Test status
Simulation time 40887607 ps
CPU time 1.12 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:19 PM PDT 24
Peak memory 200912 kb
Host smart-29062aed-775d-407b-858a-c8eecc65dec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873260015 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 18.clkmgr_same_csr_outstanding.873260015
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2475330851
Short name T915
Test name
Test status
Simulation time 183686179 ps
CPU time 1.59 seconds
Started Jul 27 05:35:16 PM PDT 24
Finished Jul 27 05:35:18 PM PDT 24
Peak memory 201216 kb
Host smart-be49a5f7-816e-498c-a6e6-6bc270556b9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475330851 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.2475330851
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2351001664
Short name T48
Test name
Test status
Simulation time 173064602 ps
CPU time 3.03 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 209836 kb
Host smart-5a8be77d-e646-4e87-907d-6ddde3902602
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351001664 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.2351001664
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2837111978
Short name T831
Test name
Test status
Simulation time 489626645 ps
CPU time 4.03 seconds
Started Jul 27 05:35:20 PM PDT 24
Finished Jul 27 05:35:24 PM PDT 24
Peak memory 201200 kb
Host smart-7500083f-94ae-4d5a-9030-fd67152451c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837111978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.2837111978
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3998491417
Short name T162
Test name
Test status
Simulation time 98853822 ps
CPU time 2.39 seconds
Started Jul 27 05:35:20 PM PDT 24
Finished Jul 27 05:35:23 PM PDT 24
Peak memory 201252 kb
Host smart-bb812b6a-1d52-4801-92c5-d2788cc4ebcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998491417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.3998491417
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2891131014
Short name T974
Test name
Test status
Simulation time 39226487 ps
CPU time 1.31 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 201048 kb
Host smart-9eb91275-bbfd-45c8-b840-607032338ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891131014 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.2891131014
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.4248719795
Short name T969
Test name
Test status
Simulation time 25347647 ps
CPU time 0.8 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 200932 kb
Host smart-0b40c76e-da33-4dd5-ab77-6f5822c85501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248719795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.4248719795
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.1701216220
Short name T893
Test name
Test status
Simulation time 19047903 ps
CPU time 0.65 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:18 PM PDT 24
Peak memory 199608 kb
Host smart-401f86b7-256f-4082-a503-737296b322ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701216220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.1701216220
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3180879974
Short name T851
Test name
Test status
Simulation time 55849882 ps
CPU time 1.26 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 201116 kb
Host smart-5396a310-c5c2-490a-8ce4-642932c15b13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180879974 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.3180879974
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2366846351
Short name T50
Test name
Test status
Simulation time 66274622 ps
CPU time 1.36 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 201196 kb
Host smart-49ef8383-e33c-4b81-8407-58d763e26975
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366846351 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.2366846351
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2497021596
Short name T115
Test name
Test status
Simulation time 201004815 ps
CPU time 1.91 seconds
Started Jul 27 05:35:22 PM PDT 24
Finished Jul 27 05:35:24 PM PDT 24
Peak memory 217776 kb
Host smart-dd8c9874-04c1-4490-9e38-6e21208b3b8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497021596 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2497021596
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2337530559
Short name T941
Test name
Test status
Simulation time 60779682 ps
CPU time 1.95 seconds
Started Jul 27 05:35:23 PM PDT 24
Finished Jul 27 05:35:25 PM PDT 24
Peak memory 201112 kb
Host smart-fde07f0d-5561-496c-b05e-cfe040dacaff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337530559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.2337530559
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3861184337
Short name T82
Test name
Test status
Simulation time 237315304 ps
CPU time 2.09 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 201112 kb
Host smart-caa4dbea-507a-4d11-a1ea-6bc0f14e1ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861184337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.3861184337
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1135032468
Short name T975
Test name
Test status
Simulation time 30076777 ps
CPU time 1.47 seconds
Started Jul 27 05:34:52 PM PDT 24
Finished Jul 27 05:34:54 PM PDT 24
Peak memory 201196 kb
Host smart-082e5b54-5c97-47b8-a999-0fedcf0e8bb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135032468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1135032468
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.957199007
Short name T150
Test name
Test status
Simulation time 580704677 ps
CPU time 8.57 seconds
Started Jul 27 05:34:53 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 201196 kb
Host smart-cd815ab1-c194-4124-8cef-54dc7f88e9ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957199007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_bit_bash.957199007
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2018415640
Short name T839
Test name
Test status
Simulation time 18999616 ps
CPU time 0.83 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 201012 kb
Host smart-b5941531-5807-4497-9fb5-1142ef4209e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018415640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.2018415640
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.921254415
Short name T827
Test name
Test status
Simulation time 26083643 ps
CPU time 1.33 seconds
Started Jul 27 05:34:48 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 200992 kb
Host smart-da7c2d6f-deba-4c11-b3c8-573469f698f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921254415 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.921254415
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1708418062
Short name T934
Test name
Test status
Simulation time 16004118 ps
CPU time 0.79 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 200836 kb
Host smart-7b6c246c-de96-44a0-85ef-399eb87e5332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708418062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.1708418062
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1126114909
Short name T830
Test name
Test status
Simulation time 32572130 ps
CPU time 0.72 seconds
Started Jul 27 05:34:48 PM PDT 24
Finished Jul 27 05:34:49 PM PDT 24
Peak memory 199492 kb
Host smart-b34912e1-aa86-4e99-ae7e-8926147fd6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126114909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.1126114909
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.829574875
Short name T939
Test name
Test status
Simulation time 51528178 ps
CPU time 1.15 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 201024 kb
Host smart-6f4292c5-d064-4ce4-9c3f-43534c79dfe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829574875 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.clkmgr_same_csr_outstanding.829574875
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1219483964
Short name T846
Test name
Test status
Simulation time 67615823 ps
CPU time 1.23 seconds
Started Jul 27 05:34:52 PM PDT 24
Finished Jul 27 05:34:54 PM PDT 24
Peak memory 201264 kb
Host smart-3f9248ea-4356-463c-ab64-a2276079768d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219483964 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.1219483964
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1594791612
Short name T971
Test name
Test status
Simulation time 144322594 ps
CPU time 2.81 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:53 PM PDT 24
Peak memory 217828 kb
Host smart-a525e41a-41d4-472b-82cb-ddc214cda810
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594791612 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.1594791612
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.1528895571
Short name T945
Test name
Test status
Simulation time 33500539 ps
CPU time 1.87 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 201072 kb
Host smart-8cfeeaf9-ca90-4de0-ae03-dd3050f39a73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528895571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.1528895571
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1226298174
Short name T967
Test name
Test status
Simulation time 67237511 ps
CPU time 1.66 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:51 PM PDT 24
Peak memory 201196 kb
Host smart-762c4d6b-215a-4246-8b0d-0d9c62a4b2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226298174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.1226298174
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2405406705
Short name T873
Test name
Test status
Simulation time 13424774 ps
CPU time 0.69 seconds
Started Jul 27 05:35:17 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 199648 kb
Host smart-b9aba748-cbd6-4cb5-b270-3f052fe0010e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405406705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2405406705
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2712206235
Short name T861
Test name
Test status
Simulation time 22475412 ps
CPU time 0.69 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 199632 kb
Host smart-25cef69e-2e1a-44fd-bb19-c75ed8cb7bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712206235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.2712206235
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.2101222786
Short name T821
Test name
Test status
Simulation time 53790921 ps
CPU time 0.74 seconds
Started Jul 27 05:35:17 PM PDT 24
Finished Jul 27 05:35:18 PM PDT 24
Peak memory 199692 kb
Host smart-2ef72320-d57a-42a7-96dd-09e25a29d38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101222786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.2101222786
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.979053606
Short name T849
Test name
Test status
Simulation time 14607522 ps
CPU time 0.72 seconds
Started Jul 27 05:35:19 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 199616 kb
Host smart-608fd3ba-9cc6-4240-92de-2355bef8804b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979053606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clk
mgr_intr_test.979053606
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.690985263
Short name T874
Test name
Test status
Simulation time 14375500 ps
CPU time 0.7 seconds
Started Jul 27 05:35:22 PM PDT 24
Finished Jul 27 05:35:22 PM PDT 24
Peak memory 199608 kb
Host smart-744cbda7-d3c9-43f3-8091-09b14d45f2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690985263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk
mgr_intr_test.690985263
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.791933350
Short name T845
Test name
Test status
Simulation time 13613855 ps
CPU time 0.65 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:18 PM PDT 24
Peak memory 199784 kb
Host smart-33a6e677-e8da-4dad-8baf-ec2cdc948578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791933350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk
mgr_intr_test.791933350
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2165638480
Short name T836
Test name
Test status
Simulation time 12735663 ps
CPU time 0.66 seconds
Started Jul 27 05:35:20 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 199512 kb
Host smart-6ad93483-6de4-47ae-aa3d-328734df4bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165638480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.2165638480
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3480196245
Short name T856
Test name
Test status
Simulation time 145990945 ps
CPU time 0.97 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:19 PM PDT 24
Peak memory 199624 kb
Host smart-3c98e884-dee0-4aaf-90f8-417a80778b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480196245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.3480196245
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1553755998
Short name T898
Test name
Test status
Simulation time 36305960 ps
CPU time 0.73 seconds
Started Jul 27 05:35:18 PM PDT 24
Finished Jul 27 05:35:19 PM PDT 24
Peak memory 199596 kb
Host smart-d65b921b-832c-48ea-9021-6c92c4a5cd37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553755998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.1553755998
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.151859772
Short name T955
Test name
Test status
Simulation time 29952855 ps
CPU time 0.68 seconds
Started Jul 27 05:35:25 PM PDT 24
Finished Jul 27 05:35:26 PM PDT 24
Peak memory 199668 kb
Host smart-11aa02c5-f1d4-4a2d-bf24-bc8da9a0b340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151859772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk
mgr_intr_test.151859772
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3120173108
Short name T901
Test name
Test status
Simulation time 115513661 ps
CPU time 1.51 seconds
Started Jul 27 05:34:51 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 200920 kb
Host smart-908d6f85-ba35-42a5-b1a1-ad21a0e786e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120173108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3120173108
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2550015235
Short name T832
Test name
Test status
Simulation time 1994514505 ps
CPU time 11.96 seconds
Started Jul 27 05:34:47 PM PDT 24
Finished Jul 27 05:34:59 PM PDT 24
Peak memory 201192 kb
Host smart-aadae876-5e08-4e22-87e5-f800fba8c5f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550015235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.2550015235
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.68182118
Short name T896
Test name
Test status
Simulation time 17538445 ps
CPU time 0.78 seconds
Started Jul 27 05:34:47 PM PDT 24
Finished Jul 27 05:34:48 PM PDT 24
Peak memory 201004 kb
Host smart-b7d07bd1-2777-4c3c-ac61-df187de86cb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68182118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_csr_hw_reset.68182118
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.301852279
Short name T817
Test name
Test status
Simulation time 20008169 ps
CPU time 1.02 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:51 PM PDT 24
Peak memory 201076 kb
Host smart-1f466b1a-798b-4ee8-b106-793d1ff2631c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301852279 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.301852279
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.382628128
Short name T887
Test name
Test status
Simulation time 35218373 ps
CPU time 0.82 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:51 PM PDT 24
Peak memory 200888 kb
Host smart-b88f0753-3356-461e-8e67-62276ba10af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382628128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.c
lkmgr_csr_rw.382628128
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2937735744
Short name T966
Test name
Test status
Simulation time 14331621 ps
CPU time 0.7 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 199660 kb
Host smart-d2cac781-c5a6-478d-9bde-10fe8de9b76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937735744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.2937735744
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.652210091
Short name T921
Test name
Test status
Simulation time 22917813 ps
CPU time 0.98 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:51 PM PDT 24
Peak memory 200996 kb
Host smart-508a55b0-db59-45bf-a5c7-ddb218f36612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652210091 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.clkmgr_same_csr_outstanding.652210091
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3151992198
Short name T913
Test name
Test status
Simulation time 841053306 ps
CPU time 4.16 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 201616 kb
Host smart-4f4c908a-d116-4516-b87c-8095ff84beeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151992198 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.3151992198
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2506835946
Short name T979
Test name
Test status
Simulation time 181712710 ps
CPU time 2.29 seconds
Started Jul 27 05:34:48 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 201120 kb
Host smart-a3b95955-5fe6-4518-8c19-5c328fe748f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506835946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2506835946
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.4274112461
Short name T978
Test name
Test status
Simulation time 426772729 ps
CPU time 3.15 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 201196 kb
Host smart-e884b0f1-743e-4907-87df-acd22ea7c7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274112461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.4274112461
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2174111881
Short name T862
Test name
Test status
Simulation time 31219445 ps
CPU time 0.71 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:35:27 PM PDT 24
Peak memory 199612 kb
Host smart-0cb787a0-9c61-4c3b-a68f-81823dc52cc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174111881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.2174111881
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.579322956
Short name T973
Test name
Test status
Simulation time 13765143 ps
CPU time 0.7 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199576 kb
Host smart-5d8cf285-8cd6-4b53-a76d-280f070d63b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579322956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clk
mgr_intr_test.579322956
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.361670363
Short name T949
Test name
Test status
Simulation time 12479164 ps
CPU time 0.67 seconds
Started Jul 27 05:35:26 PM PDT 24
Finished Jul 27 05:35:26 PM PDT 24
Peak memory 199620 kb
Host smart-bee0d48f-2844-491e-b824-b8c7eaf9a708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361670363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk
mgr_intr_test.361670363
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1314423774
Short name T927
Test name
Test status
Simulation time 11548905 ps
CPU time 0.7 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199612 kb
Host smart-cbf03871-a6f8-413e-9084-aefaa600a507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314423774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.1314423774
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1354983982
Short name T932
Test name
Test status
Simulation time 28634322 ps
CPU time 0.69 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:35:27 PM PDT 24
Peak memory 199600 kb
Host smart-d6cee0bc-8e21-4018-9b4c-72fca883ee71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354983982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.1354983982
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1954623235
Short name T933
Test name
Test status
Simulation time 35457420 ps
CPU time 0.71 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199616 kb
Host smart-6e80f741-4b81-4583-b31f-7117318ebc11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954623235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.1954623235
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2114391119
Short name T844
Test name
Test status
Simulation time 12688936 ps
CPU time 0.68 seconds
Started Jul 27 05:35:31 PM PDT 24
Finished Jul 27 05:35:31 PM PDT 24
Peak memory 199524 kb
Host smart-c72271f8-9290-4d83-a97a-88ddbe1e3b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114391119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.2114391119
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2305040877
Short name T928
Test name
Test status
Simulation time 13837412 ps
CPU time 0.69 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:35:30 PM PDT 24
Peak memory 199616 kb
Host smart-b44caf4a-ed2d-455f-a58f-6372eea41b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305040877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.2305040877
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2753688820
Short name T853
Test name
Test status
Simulation time 15881827 ps
CPU time 0.69 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:35:28 PM PDT 24
Peak memory 199608 kb
Host smart-57e24808-ca60-492a-bed4-5466bbcc2488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753688820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2753688820
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.744388859
Short name T902
Test name
Test status
Simulation time 24519328 ps
CPU time 0.67 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:35:28 PM PDT 24
Peak memory 199608 kb
Host smart-43821a7a-69d8-4ff5-a9f5-deee1fe043e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744388859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk
mgr_intr_test.744388859
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3347391329
Short name T964
Test name
Test status
Simulation time 19819909 ps
CPU time 1.13 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 200900 kb
Host smart-c5813aa6-d62b-4d6e-8fe3-42f3b494b599
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347391329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3347391329
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.680071839
Short name T942
Test name
Test status
Simulation time 969051297 ps
CPU time 6.17 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:06 PM PDT 24
Peak memory 201180 kb
Host smart-7d744a63-e09a-422b-83c5-065207da7df4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680071839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_bit_bash.680071839
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3625259469
Short name T954
Test name
Test status
Simulation time 18944431 ps
CPU time 0.88 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 201004 kb
Host smart-409b7ffe-261d-49e3-aab4-03a7f5786af2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625259469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.3625259469
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3066389942
Short name T972
Test name
Test status
Simulation time 29635069 ps
CPU time 1.04 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 200960 kb
Host smart-75d3d522-cd65-4153-a358-ebfd4f7ed3ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066389942 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.3066389942
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3675046316
Short name T859
Test name
Test status
Simulation time 15865676 ps
CPU time 0.79 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 200908 kb
Host smart-4274fe52-9e2b-4ca5-8df5-92eccb258915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675046316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3675046316
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1522657098
Short name T838
Test name
Test status
Simulation time 10376609 ps
CPU time 0.66 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 199512 kb
Host smart-0637fd3f-f155-4081-9c75-0ede8ea7c116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522657098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.1522657098
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2335407460
Short name T885
Test name
Test status
Simulation time 76798928 ps
CPU time 1.33 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:00 PM PDT 24
Peak memory 201112 kb
Host smart-908e03b7-f857-40cf-acd6-c70997209fec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335407460 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.2335407460
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1362752286
Short name T53
Test name
Test status
Simulation time 126292393 ps
CPU time 2.01 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 201408 kb
Host smart-15e0a753-1187-45da-ad91-e2312efe6862
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362752286 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.1362752286
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1619871449
Short name T869
Test name
Test status
Simulation time 97277425 ps
CPU time 2.11 seconds
Started Jul 27 05:34:48 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 209616 kb
Host smart-845c4d10-6dab-47f3-9883-ce7ad30ba664
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619871449 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.1619871449
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2915312486
Short name T890
Test name
Test status
Simulation time 52827704 ps
CPU time 1.88 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 201164 kb
Host smart-085beddc-dcc3-4872-aeed-1db05b55e7b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915312486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.2915312486
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.4254716964
Short name T93
Test name
Test status
Simulation time 300635975 ps
CPU time 2.26 seconds
Started Jul 27 05:34:48 PM PDT 24
Finished Jul 27 05:34:51 PM PDT 24
Peak memory 201228 kb
Host smart-957cdab0-578d-4db7-a780-9579c2cafe60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254716964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.4254716964
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.697712622
Short name T825
Test name
Test status
Simulation time 19815632 ps
CPU time 0.67 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199612 kb
Host smart-becd095c-d6e9-4fc5-83ba-69ecb25024e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697712622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk
mgr_intr_test.697712622
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.905975389
Short name T895
Test name
Test status
Simulation time 15924868 ps
CPU time 0.66 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:35:28 PM PDT 24
Peak memory 199612 kb
Host smart-25309898-0182-4916-b28f-1392db9d24c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905975389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk
mgr_intr_test.905975389
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3109502375
Short name T892
Test name
Test status
Simulation time 27836004 ps
CPU time 0.7 seconds
Started Jul 27 05:35:30 PM PDT 24
Finished Jul 27 05:35:30 PM PDT 24
Peak memory 199828 kb
Host smart-2ddd7f84-ea8f-46ef-85a5-676e6fadedd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109502375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.3109502375
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1977186582
Short name T823
Test name
Test status
Simulation time 26183082 ps
CPU time 0.68 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:35:30 PM PDT 24
Peak memory 199580 kb
Host smart-f629888c-0942-4c58-97eb-ccf09dacc94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977186582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1977186582
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3019519904
Short name T876
Test name
Test status
Simulation time 29717238 ps
CPU time 0.71 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199596 kb
Host smart-d3c422a5-4e7e-423a-a638-4d9be802438f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019519904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.3019519904
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.580617465
Short name T944
Test name
Test status
Simulation time 118842765 ps
CPU time 0.9 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199684 kb
Host smart-e19a3441-3420-4dc7-8424-9017e1c0a900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580617465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clk
mgr_intr_test.580617465
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2905419936
Short name T946
Test name
Test status
Simulation time 40629726 ps
CPU time 0.74 seconds
Started Jul 27 05:35:31 PM PDT 24
Finished Jul 27 05:35:32 PM PDT 24
Peak memory 199524 kb
Host smart-155099fb-c4f1-4a9b-a90e-4b9743827c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905419936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.2905419936
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.693895857
Short name T819
Test name
Test status
Simulation time 27357419 ps
CPU time 0.73 seconds
Started Jul 27 05:35:30 PM PDT 24
Finished Jul 27 05:35:30 PM PDT 24
Peak memory 199904 kb
Host smart-08e176c1-0395-4401-9971-f3496e1cdbd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693895857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.693895857
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2600669867
Short name T977
Test name
Test status
Simulation time 15300991 ps
CPU time 0.69 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199480 kb
Host smart-46b63dd4-1033-490a-ab72-8e9f595c8695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600669867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.2600669867
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2338007538
Short name T872
Test name
Test status
Simulation time 26257563 ps
CPU time 0.75 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:35:29 PM PDT 24
Peak memory 199668 kb
Host smart-32cc7a36-2d63-456f-aad4-b27472d2daf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338007538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.2338007538
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.87127638
Short name T818
Test name
Test status
Simulation time 225471144 ps
CPU time 2.05 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 201240 kb
Host smart-576f4cc2-36be-485c-8c5c-ff084a7900f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87127638 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.87127638
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2152544372
Short name T64
Test name
Test status
Simulation time 34579006 ps
CPU time 0.93 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 200972 kb
Host smart-95e57b26-85f2-4526-9e4f-e546d9992b50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152544372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.2152544372
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.513515617
Short name T924
Test name
Test status
Simulation time 38476733 ps
CPU time 0.72 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:00 PM PDT 24
Peak memory 199620 kb
Host smart-21db7b14-5a50-49db-9142-0b6a8b0b3619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513515617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_intr_test.513515617
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.898344798
Short name T69
Test name
Test status
Simulation time 103160114 ps
CPU time 1.53 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 201152 kb
Host smart-0a389133-04a7-4631-bc45-3af5cff23eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898344798 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.clkmgr_same_csr_outstanding.898344798
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1455260171
Short name T868
Test name
Test status
Simulation time 95736215 ps
CPU time 1.88 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 201464 kb
Host smart-2f2c8e09-b3eb-4f91-a2b3-d4c9f982dd2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455260171 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1455260171
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3333422762
Short name T970
Test name
Test status
Simulation time 591885646 ps
CPU time 3.68 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 209684 kb
Host smart-8fafe0db-9c64-41e2-a84c-819553a946e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333422762 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3333422762
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.610287017
Short name T907
Test name
Test status
Simulation time 207109076 ps
CPU time 3.59 seconds
Started Jul 27 05:35:02 PM PDT 24
Finished Jul 27 05:35:05 PM PDT 24
Peak memory 201220 kb
Host smart-1bb9a39e-ac09-4ca2-8f9b-e37c7abe887a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610287017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_tl_errors.610287017
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.762827600
Short name T161
Test name
Test status
Simulation time 669603598 ps
CPU time 3.76 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:05 PM PDT 24
Peak memory 201224 kb
Host smart-8a3edb65-87bd-49b9-bf07-a52aeac1f3a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762827600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_tl_intg_err.762827600
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2974292174
Short name T929
Test name
Test status
Simulation time 83358587 ps
CPU time 1.42 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 200984 kb
Host smart-78558e01-49c3-4ef5-b81e-a0a43a47fd45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974292174 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2974292174
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3064908583
Short name T854
Test name
Test status
Simulation time 15674005 ps
CPU time 0.85 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 201000 kb
Host smart-c748e750-b56e-46b0-b22c-e0a74859e2f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064908583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.3064908583
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1446751077
Short name T960
Test name
Test status
Simulation time 49048826 ps
CPU time 0.77 seconds
Started Jul 27 05:35:04 PM PDT 24
Finished Jul 27 05:35:05 PM PDT 24
Peak memory 199680 kb
Host smart-72261ca8-7191-48b5-a74a-d44ab515db21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446751077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.1446751077
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2802159950
Short name T918
Test name
Test status
Simulation time 45063009 ps
CPU time 1.34 seconds
Started Jul 27 05:35:03 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 201124 kb
Host smart-8af83cc1-4f3c-4aeb-8abc-748f75168a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802159950 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.2802159950
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1136634149
Short name T948
Test name
Test status
Simulation time 325260388 ps
CPU time 2.34 seconds
Started Jul 27 05:34:58 PM PDT 24
Finished Jul 27 05:35:00 PM PDT 24
Peak memory 201492 kb
Host smart-7f32eb88-f5f0-43a0-99fb-ff24b03fba8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136634149 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.1136634149
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3899323334
Short name T67
Test name
Test status
Simulation time 93507174 ps
CPU time 1.8 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 209672 kb
Host smart-8ede1de6-c5ed-4ceb-83b2-f47102bcc6a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899323334 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.3899323334
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1855216567
Short name T922
Test name
Test status
Simulation time 68672323 ps
CPU time 2.13 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 201240 kb
Host smart-c30d36a2-35c2-4d2d-83e4-25b8bb883fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855216567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.1855216567
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3043087177
Short name T85
Test name
Test status
Simulation time 241257165 ps
CPU time 2.31 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 201212 kb
Host smart-334a0146-434a-4bac-81c0-295274fa6158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043087177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3043087177
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3472346143
Short name T883
Test name
Test status
Simulation time 78129665 ps
CPU time 1.43 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 200964 kb
Host smart-46cdaa22-2ff0-4e6a-8e48-577e9d248fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472346143 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.3472346143
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.892411060
Short name T908
Test name
Test status
Simulation time 23494076 ps
CPU time 0.8 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:00 PM PDT 24
Peak memory 200916 kb
Host smart-27ec6862-5aaa-43c2-848c-fe28b1e3e185
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892411060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.c
lkmgr_csr_rw.892411060
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3477887876
Short name T875
Test name
Test status
Simulation time 19428466 ps
CPU time 0.7 seconds
Started Jul 27 05:34:58 PM PDT 24
Finished Jul 27 05:34:59 PM PDT 24
Peak memory 199668 kb
Host smart-821a75ab-4e6c-4a9f-85b7-f14ef9f29e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477887876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3477887876
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1959844719
Short name T899
Test name
Test status
Simulation time 57198985 ps
CPU time 1.21 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 200980 kb
Host smart-2920dacc-9c66-4635-8d94-ce6629b1422c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959844719 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.1959844719
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2631546627
Short name T117
Test name
Test status
Simulation time 118662303 ps
CPU time 2.16 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:03 PM PDT 24
Peak memory 201448 kb
Host smart-aeb38813-2b20-4e7c-b14e-4d92cb704f52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631546627 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.2631546627
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1458701054
Short name T959
Test name
Test status
Simulation time 293946193 ps
CPU time 3.56 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:03 PM PDT 24
Peak memory 209668 kb
Host smart-5898bffa-aca6-40d9-92fb-96602051006e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458701054 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.1458701054
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1665939941
Short name T826
Test name
Test status
Simulation time 23621293 ps
CPU time 1.31 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 201124 kb
Host smart-ac0a4864-9a3a-4787-924e-331368224723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665939941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.1665939941
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4218976299
Short name T92
Test name
Test status
Simulation time 92836856 ps
CPU time 2.36 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:03 PM PDT 24
Peak memory 201140 kb
Host smart-a2aa59ac-0e76-4719-8edf-3d446295cf46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218976299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.4218976299
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3539605596
Short name T905
Test name
Test status
Simulation time 45557179 ps
CPU time 0.95 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 201008 kb
Host smart-7f04bd99-6ca6-4fcb-bfaf-538849b9e436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539605596 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.3539605596
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1048084533
Short name T886
Test name
Test status
Simulation time 49155962 ps
CPU time 0.88 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 200908 kb
Host smart-6180214f-93b3-4e8b-bc95-c5cf3cbafad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048084533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.1048084533
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1127779722
Short name T829
Test name
Test status
Simulation time 15332526 ps
CPU time 0.68 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 199680 kb
Host smart-9fb0c2c5-7e5c-4263-a5a8-44f75f8b2a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127779722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.1127779722
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1847063642
Short name T835
Test name
Test status
Simulation time 53329341 ps
CPU time 1.11 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 200968 kb
Host smart-17afc95f-f263-475e-9e28-8ce6b296de45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847063642 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.1847063642
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3040187791
Short name T920
Test name
Test status
Simulation time 872722602 ps
CPU time 3.95 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 201484 kb
Host smart-a4234c9d-8531-4540-8847-25f2cc7a042e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040187791 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.3040187791
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.4237645589
Short name T914
Test name
Test status
Simulation time 337464606 ps
CPU time 2.97 seconds
Started Jul 27 05:34:58 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 209604 kb
Host smart-1982bc0a-2682-4ccb-835c-841dfcf076e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237645589 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.4237645589
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3428283193
Short name T881
Test name
Test status
Simulation time 93080979 ps
CPU time 3.17 seconds
Started Jul 27 05:35:00 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 201124 kb
Host smart-663006ff-89e5-426d-8bea-6b595aca952d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428283193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.3428283193
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.140719499
Short name T947
Test name
Test status
Simulation time 80169606 ps
CPU time 1.86 seconds
Started Jul 27 05:35:04 PM PDT 24
Finished Jul 27 05:35:06 PM PDT 24
Peak memory 201152 kb
Host smart-3196c3fb-0113-4b96-a32c-60a60f695132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140719499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_tl_intg_err.140719499
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1366701885
Short name T956
Test name
Test status
Simulation time 30263561 ps
CPU time 1.06 seconds
Started Jul 27 05:35:02 PM PDT 24
Finished Jul 27 05:35:03 PM PDT 24
Peak memory 201012 kb
Host smart-fdad5c11-ada2-4717-82c3-a0708f6934cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366701885 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.1366701885
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.654944381
Short name T879
Test name
Test status
Simulation time 12337022 ps
CPU time 0.76 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:00 PM PDT 24
Peak memory 201000 kb
Host smart-3c37ca89-c62c-4926-90ee-216241036f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654944381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.c
lkmgr_csr_rw.654944381
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1571702252
Short name T894
Test name
Test status
Simulation time 52400365 ps
CPU time 0.74 seconds
Started Jul 27 05:35:03 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 199532 kb
Host smart-be54ada6-9281-4955-8b25-b5dc1ad4c73f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571702252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.1571702252
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4272655096
Short name T904
Test name
Test status
Simulation time 100582333 ps
CPU time 1.2 seconds
Started Jul 27 05:35:03 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 200972 kb
Host smart-2065da02-8ff6-455a-9874-1dc57ccba0da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272655096 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.4272655096
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.451446666
Short name T121
Test name
Test status
Simulation time 127494519 ps
CPU time 2.08 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:03 PM PDT 24
Peak memory 201488 kb
Host smart-260c3a51-b996-4818-89c0-de24e2110098
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451446666 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.clkmgr_shadow_reg_errors.451446666
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2754389626
Short name T113
Test name
Test status
Simulation time 153375383 ps
CPU time 2.86 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 217788 kb
Host smart-36c04398-9628-4930-afc9-bdad7ccfe71d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754389626 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.2754389626
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1245494801
Short name T938
Test name
Test status
Simulation time 993078298 ps
CPU time 5.93 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:05 PM PDT 24
Peak memory 201132 kb
Host smart-57768f74-7064-4181-bdba-e67d7a378915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245494801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.1245494801
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.983837125
Short name T86
Test name
Test status
Simulation time 74820823 ps
CPU time 1.58 seconds
Started Jul 27 05:34:59 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 201224 kb
Host smart-cd6d356c-972a-4db6-9577-d0063b079ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983837125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.clkmgr_tl_intg_err.983837125
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.1023040251
Short name T271
Test name
Test status
Simulation time 18403637 ps
CPU time 0.83 seconds
Started Jul 27 05:37:28 PM PDT 24
Finished Jul 27 05:37:29 PM PDT 24
Peak memory 200404 kb
Host smart-f91c97b2-5f34-4fd8-a7c6-624c3fca41ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023040251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.1023040251
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3029227714
Short name T176
Test name
Test status
Simulation time 15469519 ps
CPU time 0.81 seconds
Started Jul 27 05:37:22 PM PDT 24
Finished Jul 27 05:37:23 PM PDT 24
Peak memory 200476 kb
Host smart-df551480-0d08-478d-8b2d-3204991c04c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029227714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.3029227714
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2571070684
Short name T784
Test name
Test status
Simulation time 28642515 ps
CPU time 0.72 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 199668 kb
Host smart-3100f9da-7560-43d1-be72-b8d18e3bd164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571070684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2571070684
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.272140091
Short name T327
Test name
Test status
Simulation time 42964594 ps
CPU time 0.91 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 200464 kb
Host smart-dfa15f9a-5272-4880-9d9b-74333a008704
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272140091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_div_intersig_mubi.272140091
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.2400408371
Short name T180
Test name
Test status
Simulation time 24546250 ps
CPU time 0.89 seconds
Started Jul 27 05:37:24 PM PDT 24
Finished Jul 27 05:37:25 PM PDT 24
Peak memory 200468 kb
Host smart-99c79aa6-8cde-4b1c-9886-05ade4c26e12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400408371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2400408371
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.1950769745
Short name T723
Test name
Test status
Simulation time 1037727086 ps
CPU time 9.09 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:28 PM PDT 24
Peak memory 200540 kb
Host smart-ab2c943e-f81d-44c8-8479-9d17663c2ad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950769745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1950769745
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.2743630658
Short name T175
Test name
Test status
Simulation time 1217077949 ps
CPU time 9.14 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200560 kb
Host smart-848ce45c-f525-4402-9ed9-fad2cdab1c31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743630658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.2743630658
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.89277003
Short name T659
Test name
Test status
Simulation time 24111284 ps
CPU time 0.9 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 200452 kb
Host smart-f76b0b12-f33b-4ce0-9c80-3aec4c5a273d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89277003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
clkmgr_idle_intersig_mubi.89277003
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2679703833
Short name T465
Test name
Test status
Simulation time 47952141 ps
CPU time 0.86 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 200468 kb
Host smart-da172b8b-9230-4b17-b49c-a29ec36b0532
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679703833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.2679703833
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.155237296
Short name T273
Test name
Test status
Simulation time 24216633 ps
CPU time 0.75 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 200436 kb
Host smart-e87158bc-fdef-4dad-97e1-dad15b60f41f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155237296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.155237296
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.438943807
Short name T584
Test name
Test status
Simulation time 29695823 ps
CPU time 0.74 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 200424 kb
Host smart-1cbb1290-a679-47e8-9307-2f27da2b385b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438943807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.438943807
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.3139622456
Short name T310
Test name
Test status
Simulation time 967751719 ps
CPU time 4.62 seconds
Started Jul 27 05:37:24 PM PDT 24
Finished Jul 27 05:37:29 PM PDT 24
Peak memory 200560 kb
Host smart-6e08ca2b-9b40-4587-94bf-1ec6bdc3440b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139622456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3139622456
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.3360972795
Short name T35
Test name
Test status
Simulation time 762448555 ps
CPU time 4.31 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 217464 kb
Host smart-ddb14e2c-1ab2-4292-b636-9a79363a40f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360972795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.3360972795
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.3636659290
Short name T238
Test name
Test status
Simulation time 15571870 ps
CPU time 0.78 seconds
Started Jul 27 05:37:17 PM PDT 24
Finished Jul 27 05:37:18 PM PDT 24
Peak memory 200420 kb
Host smart-abd4fb91-aa2d-4886-b835-10322a7f3568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636659290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3636659290
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.2118811213
Short name T278
Test name
Test status
Simulation time 3669985995 ps
CPU time 25.08 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:43 PM PDT 24
Peak memory 200840 kb
Host smart-10a26491-d033-407c-8706-7a0c0344603f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118811213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.2118811213
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.1827608134
Short name T149
Test name
Test status
Simulation time 19189084351 ps
CPU time 246.32 seconds
Started Jul 27 05:37:22 PM PDT 24
Finished Jul 27 05:41:29 PM PDT 24
Peak memory 209124 kb
Host smart-ab0941f7-1b66-4d5e-a221-0cd604036d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1827608134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.1827608134
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_trans.2707643155
Short name T179
Test name
Test status
Simulation time 25564947 ps
CPU time 0.9 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 200424 kb
Host smart-ac1b9e25-c4ba-4777-acdf-40eda3b442c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707643155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2707643155
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.1153365788
Short name T735
Test name
Test status
Simulation time 15998773 ps
CPU time 0.72 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200412 kb
Host smart-4c6bc162-38fd-4bfe-b509-521373cbd4d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153365788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.1153365788
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3764194917
Short name T569
Test name
Test status
Simulation time 80767138 ps
CPU time 1.02 seconds
Started Jul 27 05:37:27 PM PDT 24
Finished Jul 27 05:37:28 PM PDT 24
Peak memory 200500 kb
Host smart-8b9629c9-e7ed-4cda-bf17-b3e48a7c96ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764194917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.3764194917
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.2377408929
Short name T328
Test name
Test status
Simulation time 31312370 ps
CPU time 0.75 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200324 kb
Host smart-06c6c99f-ae0e-419b-a64a-c65f727b8fdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377408929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2377408929
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.1348646047
Short name T776
Test name
Test status
Simulation time 79395413 ps
CPU time 1.03 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:28 PM PDT 24
Peak memory 200472 kb
Host smart-9f15e014-39d9-4412-956a-07b4b11507a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348646047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.1348646047
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.1591468113
Short name T292
Test name
Test status
Simulation time 27141261 ps
CPU time 0.88 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200472 kb
Host smart-ff2b121c-643e-4d23-bb2f-051bc65d8b38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591468113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1591468113
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.431115519
Short name T414
Test name
Test status
Simulation time 2475774445 ps
CPU time 19.35 seconds
Started Jul 27 05:37:28 PM PDT 24
Finished Jul 27 05:37:47 PM PDT 24
Peak memory 200704 kb
Host smart-486a5041-fc8c-405e-a0ac-db0011da09d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431115519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.431115519
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.3795931874
Short name T18
Test name
Test status
Simulation time 1459216376 ps
CPU time 11.12 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:37 PM PDT 24
Peak memory 200544 kb
Host smart-2862d8e5-ee59-4906-ac38-a99089688ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795931874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.3795931874
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.1530807774
Short name T609
Test name
Test status
Simulation time 22357975 ps
CPU time 0.84 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200452 kb
Host smart-fa561187-3132-4916-9eae-a6204ac78e40
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530807774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.1530807774
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1567256371
Short name T564
Test name
Test status
Simulation time 14157210 ps
CPU time 0.75 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200512 kb
Host smart-e88c5d96-5464-44cc-9a64-3a37d0d09c0f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567256371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.1567256371
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2068720293
Short name T412
Test name
Test status
Simulation time 15489953 ps
CPU time 0.79 seconds
Started Jul 27 05:37:27 PM PDT 24
Finished Jul 27 05:37:28 PM PDT 24
Peak memory 200476 kb
Host smart-5f5f66ec-a09a-4d9d-a6eb-fa921462056d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068720293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.2068720293
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2402569309
Short name T466
Test name
Test status
Simulation time 44099324 ps
CPU time 0.89 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200420 kb
Host smart-247489c1-795a-43bf-90b6-75fedafd9104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402569309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2402569309
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.1123719110
Short name T752
Test name
Test status
Simulation time 1025121371 ps
CPU time 4.46 seconds
Started Jul 27 05:37:27 PM PDT 24
Finished Jul 27 05:37:31 PM PDT 24
Peak memory 200644 kb
Host smart-5f29f8b9-49b6-48d8-8c22-e47f20e277b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123719110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1123719110
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.2509192041
Short name T45
Test name
Test status
Simulation time 647913164 ps
CPU time 3.85 seconds
Started Jul 27 05:37:27 PM PDT 24
Finished Jul 27 05:37:31 PM PDT 24
Peak memory 221544 kb
Host smart-38b9adbd-9d5b-4ac9-a1c5-de78d9e2f92d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509192041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.2509192041
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.4107082306
Short name T282
Test name
Test status
Simulation time 3514034930 ps
CPU time 17.42 seconds
Started Jul 27 05:37:27 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200840 kb
Host smart-79fd6b79-b694-4a36-a63c-45bb887e4aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107082306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.4107082306
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.3096517956
Short name T814
Test name
Test status
Simulation time 18772078 ps
CPU time 0.79 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200476 kb
Host smart-e0fd4b26-ff75-49cb-a4cb-73887295d293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096517956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3096517956
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.2579747685
Short name T627
Test name
Test status
Simulation time 35855322 ps
CPU time 0.88 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200416 kb
Host smart-1008a1c6-c20b-4b50-b83d-3d7ee4619db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579747685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.2579747685
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.3842327155
Short name T479
Test name
Test status
Simulation time 12020520 ps
CPU time 0.74 seconds
Started Jul 27 05:37:48 PM PDT 24
Finished Jul 27 05:37:49 PM PDT 24
Peak memory 200392 kb
Host smart-191402c4-56a3-4902-a905-468c0cb85f63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842327155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.3842327155
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.3341808521
Short name T555
Test name
Test status
Simulation time 18867086 ps
CPU time 0.73 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 199620 kb
Host smart-d43f0c2b-4a7a-4a69-a7b8-15cb47535d53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341808521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3341808521
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.4103807423
Short name T417
Test name
Test status
Simulation time 74409508 ps
CPU time 1.15 seconds
Started Jul 27 05:38:02 PM PDT 24
Finished Jul 27 05:38:03 PM PDT 24
Peak memory 200440 kb
Host smart-49ecf47b-d0df-4db0-8170-d71c5cd6b893
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103807423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.4103807423
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2513979552
Short name T182
Test name
Test status
Simulation time 34980257 ps
CPU time 0.86 seconds
Started Jul 27 05:37:53 PM PDT 24
Finished Jul 27 05:37:54 PM PDT 24
Peak memory 200464 kb
Host smart-451c9770-2cfb-4d0e-9783-429a59dd14f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513979552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2513979552
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.1394872571
Short name T765
Test name
Test status
Simulation time 1875320960 ps
CPU time 14.25 seconds
Started Jul 27 05:37:48 PM PDT 24
Finished Jul 27 05:38:02 PM PDT 24
Peak memory 200732 kb
Host smart-1028878f-760d-45c0-b259-fdad5cf1ec53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394872571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1394872571
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.2525978003
Short name T472
Test name
Test status
Simulation time 382849691 ps
CPU time 3.14 seconds
Started Jul 27 05:37:53 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200388 kb
Host smart-4b094de3-150b-4fc6-b5f2-129266e1f8bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525978003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.2525978003
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.2250009903
Short name T302
Test name
Test status
Simulation time 192706311 ps
CPU time 1.42 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200400 kb
Host smart-f811f89b-3f56-4650-9abe-f7c4a4de3c36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250009903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.2250009903
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1088841563
Short name T432
Test name
Test status
Simulation time 14595236 ps
CPU time 0.74 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200408 kb
Host smart-3ff2868c-4f8b-4585-aec0-ab90431f19c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088841563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.1088841563
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3412536005
Short name T634
Test name
Test status
Simulation time 28502797 ps
CPU time 0.96 seconds
Started Jul 27 05:37:50 PM PDT 24
Finished Jul 27 05:37:51 PM PDT 24
Peak memory 200472 kb
Host smart-50c9fd71-cd90-44c9-a9fd-dc7bd472941f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412536005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.3412536005
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.706311875
Short name T671
Test name
Test status
Simulation time 49127426 ps
CPU time 0.86 seconds
Started Jul 27 05:37:51 PM PDT 24
Finished Jul 27 05:37:52 PM PDT 24
Peak memory 200436 kb
Host smart-c77ec958-a4ea-447a-9d7c-d46db0fdd8d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706311875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.706311875
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.4106791727
Short name T6
Test name
Test status
Simulation time 258843045 ps
CPU time 2.04 seconds
Started Jul 27 05:37:49 PM PDT 24
Finished Jul 27 05:37:52 PM PDT 24
Peak memory 200464 kb
Host smart-7ef0439a-5db4-4e01-8adf-7aaac412a29e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106791727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.4106791727
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.3588854621
Short name T217
Test name
Test status
Simulation time 145502263 ps
CPU time 1.43 seconds
Started Jul 27 05:38:02 PM PDT 24
Finished Jul 27 05:38:04 PM PDT 24
Peak memory 200376 kb
Host smart-11c88086-1124-4220-b206-80bb12498830
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588854621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.3588854621
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.1762614373
Short name T509
Test name
Test status
Simulation time 2843675430 ps
CPU time 15.5 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:38:13 PM PDT 24
Peak memory 200576 kb
Host smart-1e692e78-60a0-4046-a888-ae8ce12d9d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762614373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.1762614373
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.1985421110
Short name T449
Test name
Test status
Simulation time 82766593684 ps
CPU time 557.65 seconds
Started Jul 27 05:37:49 PM PDT 24
Finished Jul 27 05:47:07 PM PDT 24
Peak memory 209164 kb
Host smart-f4526293-8ddd-4c85-a436-0b93b4d65829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1985421110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.1985421110
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_trans.4116722693
Short name T152
Test name
Test status
Simulation time 16020607 ps
CPU time 0.75 seconds
Started Jul 27 05:37:48 PM PDT 24
Finished Jul 27 05:37:49 PM PDT 24
Peak memory 200388 kb
Host smart-599f7e36-edcc-402d-a6d5-6000ed544843
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116722693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.4116722693
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.3698419162
Short name T558
Test name
Test status
Simulation time 26139886 ps
CPU time 0.85 seconds
Started Jul 27 05:38:03 PM PDT 24
Finished Jul 27 05:38:03 PM PDT 24
Peak memory 200476 kb
Host smart-9d742325-5d45-492a-a948-41edc9f6f10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698419162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.3698419162
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2968856923
Short name T373
Test name
Test status
Simulation time 16135297 ps
CPU time 0.76 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200252 kb
Host smart-ceec31f8-f73f-4163-b70d-b0eb84a4a28f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968856923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.2968856923
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.578497266
Short name T160
Test name
Test status
Simulation time 29329016 ps
CPU time 0.76 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 199616 kb
Host smart-0e25c080-9436-4ac9-b749-232f8e9c9823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578497266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.578497266
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.3283038440
Short name T533
Test name
Test status
Simulation time 21206233 ps
CPU time 0.98 seconds
Started Jul 27 05:38:02 PM PDT 24
Finished Jul 27 05:38:03 PM PDT 24
Peak memory 200432 kb
Host smart-2b4ec16d-aa0a-449c-843a-15db1d83cb9e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283038440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.3283038440
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.1717245881
Short name T746
Test name
Test status
Simulation time 1883770090 ps
CPU time 10.37 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:38:05 PM PDT 24
Peak memory 200656 kb
Host smart-fba890f1-dc2d-4054-9274-f4ebf717c653
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717245881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1717245881
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.1316736103
Short name T337
Test name
Test status
Simulation time 1950258987 ps
CPU time 9.9 seconds
Started Jul 27 05:37:50 PM PDT 24
Finished Jul 27 05:38:00 PM PDT 24
Peak memory 200580 kb
Host smart-b060ddd0-08af-4c90-b4b6-361944da62fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316736103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.1316736103
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.3882555920
Short name T55
Test name
Test status
Simulation time 53693733 ps
CPU time 0.84 seconds
Started Jul 27 05:37:51 PM PDT 24
Finished Jul 27 05:37:52 PM PDT 24
Peak memory 200480 kb
Host smart-cc8e6b44-6eac-4dbf-b1bc-a8084a985414
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882555920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.3882555920
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.3444429816
Short name T16
Test name
Test status
Simulation time 21859999 ps
CPU time 0.86 seconds
Started Jul 27 05:37:49 PM PDT 24
Finished Jul 27 05:37:49 PM PDT 24
Peak memory 200472 kb
Host smart-52212bfd-be40-4595-a4dd-8cb906c4f9c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444429816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.3444429816
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2911466751
Short name T433
Test name
Test status
Simulation time 66902866 ps
CPU time 0.88 seconds
Started Jul 27 05:37:53 PM PDT 24
Finished Jul 27 05:37:54 PM PDT 24
Peak memory 200464 kb
Host smart-4285f5d6-f101-4cb2-80a0-6527573c2d36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911466751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.2911466751
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.3933679726
Short name T407
Test name
Test status
Simulation time 30489924 ps
CPU time 0.78 seconds
Started Jul 27 05:37:49 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200416 kb
Host smart-dad49ce9-f53d-45c8-9b84-9a242f104af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933679726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.3933679726
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.1535918120
Short name T445
Test name
Test status
Simulation time 826501641 ps
CPU time 5.18 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:38:04 PM PDT 24
Peak memory 200608 kb
Host smart-8bfb9c1f-ca23-4608-a2d1-1b284e8b377f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535918120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1535918120
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.495438943
Short name T131
Test name
Test status
Simulation time 21948221 ps
CPU time 0.89 seconds
Started Jul 27 05:37:49 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200420 kb
Host smart-0964f15f-6290-44ff-813e-8acf49057374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495438943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.495438943
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.3459952371
Short name T135
Test name
Test status
Simulation time 32518003 ps
CPU time 0.91 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:37:59 PM PDT 24
Peak memory 200436 kb
Host smart-0d55a4b1-ed58-46b3-aec0-36cd50a9e379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459952371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.3459952371
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.3239499128
Short name T624
Test name
Test status
Simulation time 150762492 ps
CPU time 1.37 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200320 kb
Host smart-9cc923b4-7f07-4eb2-853f-7c028a2a6d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239499128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3239499128
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.3418353628
Short name T587
Test name
Test status
Simulation time 40104590 ps
CPU time 0.81 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200444 kb
Host smart-edd98912-bdf0-43c5-ab70-862d5c144f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418353628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.3418353628
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3739170185
Short name T405
Test name
Test status
Simulation time 25777884 ps
CPU time 0.8 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 200372 kb
Host smart-6599b6e6-75b3-4025-825a-a02209cb0d9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739170185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3739170185
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.58880669
Short name T400
Test name
Test status
Simulation time 17240200 ps
CPU time 0.71 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 199640 kb
Host smart-705c1570-c7f5-4efb-bf66-1d1486797888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58880669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.58880669
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.2603396902
Short name T792
Test name
Test status
Simulation time 50976030 ps
CPU time 0.98 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200472 kb
Host smart-04803bdc-60e5-45fc-8d8c-77f5c7403c90
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603396902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.2603396902
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.2797279187
Short name T787
Test name
Test status
Simulation time 81117388 ps
CPU time 1.04 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200424 kb
Host smart-8aa43499-cef0-4112-8dbd-1f1e2814219f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797279187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.2797279187
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.4033144537
Short name T332
Test name
Test status
Simulation time 2125160269 ps
CPU time 11.91 seconds
Started Jul 27 05:38:01 PM PDT 24
Finished Jul 27 05:38:13 PM PDT 24
Peak memory 200708 kb
Host smart-71399b4f-7c36-4fc2-96c8-4fe16f9b0ac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033144537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.4033144537
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2460448575
Short name T261
Test name
Test status
Simulation time 1370805777 ps
CPU time 5.29 seconds
Started Jul 27 05:37:54 PM PDT 24
Finished Jul 27 05:38:00 PM PDT 24
Peak memory 200584 kb
Host smart-453c43a2-fa9b-4121-9fdf-092589c4864d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460448575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2460448575
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2646699691
Short name T202
Test name
Test status
Simulation time 109289278 ps
CPU time 1.27 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:59 PM PDT 24
Peak memory 200472 kb
Host smart-e5865557-db88-422e-9238-b709028adbeb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646699691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.2646699691
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.355399970
Short name T226
Test name
Test status
Simulation time 63330316 ps
CPU time 0.97 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200476 kb
Host smart-9c23f52d-19ff-493b-8ba1-1c2275c6561b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355399970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.355399970
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2113169536
Short name T368
Test name
Test status
Simulation time 47565890 ps
CPU time 0.99 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 200436 kb
Host smart-5e0491c8-7c43-47d3-b048-e77971503f28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113169536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.2113169536
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.1633810130
Short name T451
Test name
Test status
Simulation time 23445320 ps
CPU time 0.73 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200468 kb
Host smart-2d975709-62a5-4d5e-97df-d9d97065b271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633810130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.1633810130
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.981750878
Short name T588
Test name
Test status
Simulation time 467086162 ps
CPU time 2.06 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200732 kb
Host smart-339c99a5-d534-461f-b099-617d65035661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981750878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.981750878
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.2358155120
Short name T346
Test name
Test status
Simulation time 42882022 ps
CPU time 0.94 seconds
Started Jul 27 05:38:01 PM PDT 24
Finished Jul 27 05:38:02 PM PDT 24
Peak memory 200412 kb
Host smart-37a3bd6d-e81b-46e6-8612-ae5588d91d1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358155120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2358155120
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.382528452
Short name T22
Test name
Test status
Simulation time 7363567659 ps
CPU time 32.46 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200856 kb
Host smart-d4b99b8b-b9f4-4ddd-a32b-c5a608275ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382528452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.382528452
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.2387030839
Short name T719
Test name
Test status
Simulation time 20802539 ps
CPU time 0.8 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 200464 kb
Host smart-c72aa983-3c8d-482c-a344-0556c9fca0ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387030839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2387030839
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.220940351
Short name T729
Test name
Test status
Simulation time 29959126 ps
CPU time 0.87 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:37:59 PM PDT 24
Peak memory 200464 kb
Host smart-3ea0b805-3b3d-4cb4-8453-db9893af54b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220940351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkm
gr_alert_test.220940351
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1908341198
Short name T397
Test name
Test status
Simulation time 331895849 ps
CPU time 1.83 seconds
Started Jul 27 05:37:59 PM PDT 24
Finished Jul 27 05:38:01 PM PDT 24
Peak memory 200424 kb
Host smart-f53ebf9c-1fa3-4c55-b69c-6a7aaa8e39a1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908341198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.1908341198
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.3881719913
Short name T459
Test name
Test status
Simulation time 15094982 ps
CPU time 0.74 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200388 kb
Host smart-2683502e-65d4-4c62-ba1e-839f75923de8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881719913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3881719913
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.1811861894
Short name T482
Test name
Test status
Simulation time 49389762 ps
CPU time 0.95 seconds
Started Jul 27 05:37:59 PM PDT 24
Finished Jul 27 05:38:00 PM PDT 24
Peak memory 200448 kb
Host smart-8e5a66cf-1204-4e81-9e06-e4ef6bc86527
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811861894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.1811861894
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.1063988538
Short name T582
Test name
Test status
Simulation time 47439966 ps
CPU time 1 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200460 kb
Host smart-06a5f74e-cc9b-42be-9869-127754f039af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063988538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.1063988538
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3711328629
Short name T366
Test name
Test status
Simulation time 2251938338 ps
CPU time 12.66 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200824 kb
Host smart-46bf6cec-7391-4d7b-a603-7b91e4722e5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711328629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3711328629
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.4230720350
Short name T284
Test name
Test status
Simulation time 1800115830 ps
CPU time 6.87 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:38:04 PM PDT 24
Peak memory 200564 kb
Host smart-84d6c194-c907-4255-8182-412646cc71a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230720350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.4230720350
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.1519210894
Short name T228
Test name
Test status
Simulation time 25177182 ps
CPU time 0.89 seconds
Started Jul 27 05:37:59 PM PDT 24
Finished Jul 27 05:38:00 PM PDT 24
Peak memory 200460 kb
Host smart-61502280-8a48-4229-a049-e17f5becb105
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519210894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.1519210894
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2150302481
Short name T626
Test name
Test status
Simulation time 40065746 ps
CPU time 0.95 seconds
Started Jul 27 05:38:01 PM PDT 24
Finished Jul 27 05:38:02 PM PDT 24
Peak memory 200480 kb
Host smart-4159b286-19f9-4c13-a952-6b33e59e6481
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150302481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2150302481
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1945956052
Short name T344
Test name
Test status
Simulation time 27905235 ps
CPU time 0.9 seconds
Started Jul 27 05:38:00 PM PDT 24
Finished Jul 27 05:38:01 PM PDT 24
Peak memory 200472 kb
Host smart-fc3a0304-61d6-4a2f-8639-ba98d68a83fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945956052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.1945956052
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.2841797157
Short name T567
Test name
Test status
Simulation time 16311287 ps
CPU time 0.77 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:37:59 PM PDT 24
Peak memory 200436 kb
Host smart-43ccd4fb-6f59-425e-a110-8f4200de2edd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841797157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.2841797157
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.4098260995
Short name T431
Test name
Test status
Simulation time 222646883 ps
CPU time 1.73 seconds
Started Jul 27 05:38:01 PM PDT 24
Finished Jul 27 05:38:03 PM PDT 24
Peak memory 200420 kb
Host smart-d141ff19-ef58-402a-91a6-0391982c17b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098260995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.4098260995
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1640569539
Short name T313
Test name
Test status
Simulation time 32362183 ps
CPU time 0.86 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 200324 kb
Host smart-0cff0c8b-23e2-42be-a649-876f8e3981a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640569539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1640569539
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.1934492379
Short name T640
Test name
Test status
Simulation time 9629186713 ps
CPU time 38.52 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:38:37 PM PDT 24
Peak memory 200832 kb
Host smart-f026a456-2977-4411-b501-6d350e391f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934492379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.1934492379
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.2528553372
Short name T200
Test name
Test status
Simulation time 29156072 ps
CPU time 0.98 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200468 kb
Host smart-f02246ec-3a8b-425b-914c-ef976c98c097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528553372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2528553372
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.736722029
Short name T580
Test name
Test status
Simulation time 49067143 ps
CPU time 0.99 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 200444 kb
Host smart-632bec11-5801-4ab6-a3b0-0805210e4f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736722029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkm
gr_alert_test.736722029
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.3593469699
Short name T404
Test name
Test status
Simulation time 79223959 ps
CPU time 0.85 seconds
Started Jul 27 05:38:01 PM PDT 24
Finished Jul 27 05:38:02 PM PDT 24
Peak memory 199620 kb
Host smart-3b1ac677-8d1e-4fc4-b1b1-96bea2919765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593469699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.3593469699
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.3604367960
Short name T750
Test name
Test status
Simulation time 23001721 ps
CPU time 0.87 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 200396 kb
Host smart-2de41039-c738-4718-a7e5-e7592f8ea55c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604367960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.3604367960
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.2805075103
Short name T629
Test name
Test status
Simulation time 28465561 ps
CPU time 0.98 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 200460 kb
Host smart-f22031f2-5975-4cf9-80ab-c6dd66d43b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805075103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.2805075103
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.1763933906
Short name T109
Test name
Test status
Simulation time 1614130689 ps
CPU time 5.77 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:38:01 PM PDT 24
Peak memory 200540 kb
Host smart-d1f140a7-b0fb-4d8c-8535-999ce39929ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763933906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1763933906
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.1099627517
Short name T205
Test name
Test status
Simulation time 495211445 ps
CPU time 4.24 seconds
Started Jul 27 05:38:00 PM PDT 24
Finished Jul 27 05:38:05 PM PDT 24
Peak memory 200552 kb
Host smart-764725b2-2c1b-413a-a9ee-99efbc4668fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099627517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.1099627517
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3526230898
Short name T595
Test name
Test status
Simulation time 50258722 ps
CPU time 1.02 seconds
Started Jul 27 05:38:01 PM PDT 24
Finished Jul 27 05:38:02 PM PDT 24
Peak memory 200416 kb
Host smart-7713442d-f04b-41ec-baa1-097399fa5f6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526230898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.3526230898
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1392238441
Short name T689
Test name
Test status
Simulation time 299120598 ps
CPU time 1.75 seconds
Started Jul 27 05:38:03 PM PDT 24
Finished Jul 27 05:38:05 PM PDT 24
Peak memory 200432 kb
Host smart-599835e4-d92e-4b88-b887-5d8bb99959ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392238441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.1392238441
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.510014626
Short name T543
Test name
Test status
Simulation time 16144871 ps
CPU time 0.78 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:37:59 PM PDT 24
Peak memory 200464 kb
Host smart-71efb42d-b1bc-4f47-afb5-943be576ea82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510014626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_ctrl_intersig_mubi.510014626
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.4015537325
Short name T272
Test name
Test status
Simulation time 44857473 ps
CPU time 0.82 seconds
Started Jul 27 05:37:56 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 200444 kb
Host smart-7a040ef0-ef36-4f63-aa8c-6c7df7942482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015537325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.4015537325
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.1288882038
Short name T516
Test name
Test status
Simulation time 455293810 ps
CPU time 2.04 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200468 kb
Host smart-e0db2728-09f2-40b7-9fcc-9852f571b996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288882038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1288882038
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.1856917000
Short name T663
Test name
Test status
Simulation time 24073977 ps
CPU time 0.88 seconds
Started Jul 27 05:37:59 PM PDT 24
Finished Jul 27 05:38:00 PM PDT 24
Peak memory 200388 kb
Host smart-29847116-b463-4b02-a5cf-49606d5e567e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856917000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1856917000
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.1901389201
Short name T351
Test name
Test status
Simulation time 9492255964 ps
CPU time 40.12 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:48 PM PDT 24
Peak memory 200776 kb
Host smart-10d501dc-cf7f-46dc-a3ce-ffbbc398c7e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901389201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.1901389201
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.2532692858
Short name T579
Test name
Test status
Simulation time 32547994831 ps
CPU time 592.03 seconds
Started Jul 27 05:38:06 PM PDT 24
Finished Jul 27 05:47:58 PM PDT 24
Peak memory 209160 kb
Host smart-a32bebcc-bd93-45d9-afde-8b221667e302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2532692858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.2532692858
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.3603456342
Short name T678
Test name
Test status
Simulation time 13737024 ps
CPU time 0.72 seconds
Started Jul 27 05:37:58 PM PDT 24
Finished Jul 27 05:37:59 PM PDT 24
Peak memory 200488 kb
Host smart-e9a0de1e-f933-478e-bfea-bada973454df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603456342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3603456342
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.405193445
Short name T715
Test name
Test status
Simulation time 13808688 ps
CPU time 0.71 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200432 kb
Host smart-f4cd32d4-22ea-40af-8d68-9c1b884eb4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405193445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkm
gr_alert_test.405193445
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1077434102
Short name T76
Test name
Test status
Simulation time 94360188 ps
CPU time 1.2 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200496 kb
Host smart-6bec2db4-8a5c-4592-9159-c1805cc0bdde
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077434102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.1077434102
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.3315022542
Short name T617
Test name
Test status
Simulation time 42896744 ps
CPU time 0.76 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:08 PM PDT 24
Peak memory 199664 kb
Host smart-0300de43-6fbf-4777-9dc5-2c4ff1e8d8c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315022542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3315022542
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.3078093792
Short name T576
Test name
Test status
Simulation time 20335835 ps
CPU time 0.84 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:10 PM PDT 24
Peak memory 200472 kb
Host smart-11c720d8-0e1b-4919-be87-ddd6b5b4c509
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078093792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.3078093792
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.3967046111
Short name T789
Test name
Test status
Simulation time 12910458 ps
CPU time 0.71 seconds
Started Jul 27 05:38:07 PM PDT 24
Finished Jul 27 05:38:08 PM PDT 24
Peak memory 200444 kb
Host smart-f1d62e55-ade1-4015-8d85-a836dfd235ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967046111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3967046111
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.1165760776
Short name T262
Test name
Test status
Simulation time 1160482450 ps
CPU time 9.4 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:18 PM PDT 24
Peak memory 200496 kb
Host smart-0c1a6b5d-908d-49c9-ae03-19ad1f6c824d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165760776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1165760776
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.2056977298
Short name T623
Test name
Test status
Simulation time 1461285311 ps
CPU time 9.08 seconds
Started Jul 27 05:38:06 PM PDT 24
Finished Jul 27 05:38:15 PM PDT 24
Peak memory 200596 kb
Host smart-b1841683-12ad-4743-9d3d-38fe8ed977cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056977298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.2056977298
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1940484427
Short name T755
Test name
Test status
Simulation time 30732855 ps
CPU time 0.94 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:10 PM PDT 24
Peak memory 200468 kb
Host smart-42435014-69f6-43bc-b261-0b587d5be6a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940484427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.1940484427
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3413693056
Short name T333
Test name
Test status
Simulation time 18377958 ps
CPU time 0.71 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200164 kb
Host smart-721c2d81-2065-4a97-97bd-0990c28738f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413693056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3413693056
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1549701460
Short name T283
Test name
Test status
Simulation time 26832770 ps
CPU time 0.82 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 200416 kb
Host smart-a48a68ff-5d17-490b-8d32-2351dfe74918
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549701460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1549701460
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.3232471217
Short name T655
Test name
Test status
Simulation time 45817637 ps
CPU time 0.84 seconds
Started Jul 27 05:38:06 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 200456 kb
Host smart-62a1eeac-a653-4246-b734-3fae244fb2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232471217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.3232471217
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.3332516525
Short name T462
Test name
Test status
Simulation time 243345913 ps
CPU time 1.7 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:10 PM PDT 24
Peak memory 200460 kb
Host smart-a660ea3a-a8f7-4101-a8a0-841d659c7d9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332516525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3332516525
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.356634283
Short name T531
Test name
Test status
Simulation time 51518993 ps
CPU time 0.91 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 200444 kb
Host smart-e537570f-1830-4f88-8437-825cfab58565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356634283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.356634283
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.1388925800
Short name T385
Test name
Test status
Simulation time 4493433111 ps
CPU time 31.75 seconds
Started Jul 27 05:38:07 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200784 kb
Host smart-1d7d35dc-b234-45d4-bf38-4b0adc24a576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388925800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.1388925800
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.2904948456
Short name T436
Test name
Test status
Simulation time 241110735 ps
CPU time 1.61 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200460 kb
Host smart-470f19c6-419f-4eda-bdc4-ef07f5a53d60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904948456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2904948456
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.930876397
Short name T444
Test name
Test status
Simulation time 13257193 ps
CPU time 0.74 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 200468 kb
Host smart-1a29115e-d7df-4db0-b2cf-1f78a573b5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930876397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkm
gr_alert_test.930876397
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.4263379268
Short name T677
Test name
Test status
Simulation time 14529820 ps
CPU time 0.79 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:10 PM PDT 24
Peak memory 200476 kb
Host smart-8f129a46-60ee-4aa1-ba40-f00f5826760e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263379268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.4263379268
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.1531207459
Short name T747
Test name
Test status
Simulation time 20763526 ps
CPU time 0.69 seconds
Started Jul 27 05:38:06 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 199676 kb
Host smart-0623ea38-7667-4b2a-b2ab-2bc2aaf1384e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531207459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1531207459
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.4181184483
Short name T402
Test name
Test status
Simulation time 41855310 ps
CPU time 0.8 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200172 kb
Host smart-4e303c87-7836-47c2-84d6-f883cab399c3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181184483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.4181184483
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.938082442
Short name T219
Test name
Test status
Simulation time 25692352 ps
CPU time 0.88 seconds
Started Jul 27 05:38:07 PM PDT 24
Finished Jul 27 05:38:08 PM PDT 24
Peak memory 200464 kb
Host smart-e1f5946c-5bf6-48f2-99dc-22d2ab3bafb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938082442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.938082442
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.1176570946
Short name T286
Test name
Test status
Simulation time 199173071 ps
CPU time 2.14 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:22 PM PDT 24
Peak memory 200488 kb
Host smart-ee6db88d-80ed-42f7-9cc9-ce970db8d459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176570946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1176570946
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.1460124301
Short name T319
Test name
Test status
Simulation time 379300829 ps
CPU time 3.52 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:13 PM PDT 24
Peak memory 200592 kb
Host smart-35fdd3e1-01b5-45f8-b008-27f18431ba14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460124301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.1460124301
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2584797007
Short name T463
Test name
Test status
Simulation time 254730660 ps
CPU time 1.65 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200464 kb
Host smart-aadde649-b839-4d8f-a986-991be332ab1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584797007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2584797007
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2812053444
Short name T100
Test name
Test status
Simulation time 28433150 ps
CPU time 0.84 seconds
Started Jul 27 05:38:06 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 200452 kb
Host smart-53d1bdd9-4c89-438e-812b-3da9dee10690
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812053444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.2812053444
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3743030175
Short name T547
Test name
Test status
Simulation time 194639894 ps
CPU time 1.29 seconds
Started Jul 27 05:38:07 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 200484 kb
Host smart-c6f89dc3-cef4-47f2-9680-c4db9ec869c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743030175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3743030175
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.3178401070
Short name T778
Test name
Test status
Simulation time 65541435 ps
CPU time 0.93 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:10 PM PDT 24
Peak memory 200404 kb
Host smart-f41869af-01a6-443b-a0e6-cda199c3a9e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178401070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3178401070
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.3190976088
Short name T788
Test name
Test status
Simulation time 587181952 ps
CPU time 2.96 seconds
Started Jul 27 05:38:10 PM PDT 24
Finished Jul 27 05:38:13 PM PDT 24
Peak memory 200648 kb
Host smart-590e4d4b-e1c0-4408-8150-7f786ff07dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190976088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3190976088
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.1016575018
Short name T815
Test name
Test status
Simulation time 45962308 ps
CPU time 0.9 seconds
Started Jul 27 05:38:10 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200412 kb
Host smart-d8872db1-1e19-4386-a523-a13409dfd62a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016575018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.1016575018
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.3911443539
Short name T775
Test name
Test status
Simulation time 8102211777 ps
CPU time 42.18 seconds
Started Jul 27 05:38:06 PM PDT 24
Finished Jul 27 05:38:49 PM PDT 24
Peak memory 200852 kb
Host smart-d602d59e-062d-4739-9bf0-e62776d9dadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911443539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.3911443539
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3709788795
Short name T727
Test name
Test status
Simulation time 76714015 ps
CPU time 0.97 seconds
Started Jul 27 05:38:06 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 200400 kb
Host smart-ab2eb8ee-b446-4285-b002-4b80d75bbd3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709788795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3709788795
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.3118928600
Short name T415
Test name
Test status
Simulation time 36129926 ps
CPU time 0.78 seconds
Started Jul 27 05:38:13 PM PDT 24
Finished Jul 27 05:38:14 PM PDT 24
Peak memory 200388 kb
Host smart-4a733f68-507b-44b0-868d-93e6c2a4d495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118928600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.3118928600
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.3575799461
Short name T37
Test name
Test status
Simulation time 42453143 ps
CPU time 0.95 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200436 kb
Host smart-5070dd80-6f29-49de-899c-e3b042bd3d56
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575799461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.3575799461
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1568392054
Short name T372
Test name
Test status
Simulation time 39334954 ps
CPU time 0.75 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 199664 kb
Host smart-d58d7cca-131d-4366-b5ec-7b912e29197b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568392054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1568392054
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.3214122101
Short name T203
Test name
Test status
Simulation time 23910389 ps
CPU time 0.89 seconds
Started Jul 27 05:38:05 PM PDT 24
Finished Jul 27 05:38:06 PM PDT 24
Peak memory 200452 kb
Host smart-c1b08fc8-0c25-4271-86f0-d20b3d441199
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214122101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.3214122101
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.1868873621
Short name T370
Test name
Test status
Simulation time 55161605 ps
CPU time 0.95 seconds
Started Jul 27 05:38:07 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 200460 kb
Host smart-c184065d-1b4a-42c8-957a-ba8bd7c0ff0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868873621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1868873621
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1172306093
Short name T597
Test name
Test status
Simulation time 1685928769 ps
CPU time 6.96 seconds
Started Jul 27 05:38:07 PM PDT 24
Finished Jul 27 05:38:14 PM PDT 24
Peak memory 200528 kb
Host smart-295ff2e5-c3ec-40c3-99de-8fb8e5085187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172306093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1172306093
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.1829693523
Short name T191
Test name
Test status
Simulation time 137851455 ps
CPU time 1.61 seconds
Started Jul 27 05:38:11 PM PDT 24
Finished Jul 27 05:38:13 PM PDT 24
Peak memory 200548 kb
Host smart-294b1989-eed1-4aab-be8f-1be45f3aa9e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829693523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.1829693523
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3589819924
Short name T505
Test name
Test status
Simulation time 29749954 ps
CPU time 0.87 seconds
Started Jul 27 05:38:10 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200380 kb
Host smart-86009a47-65df-44c6-9d55-54d7ccdc0ecf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589819924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.3589819924
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.787602475
Short name T422
Test name
Test status
Simulation time 136058545 ps
CPU time 1.16 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200444 kb
Host smart-3c67d472-0e43-4fa5-906d-c411af8e09fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787602475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_clk_byp_req_intersig_mubi.787602475
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3014747493
Short name T802
Test name
Test status
Simulation time 127019979 ps
CPU time 1.15 seconds
Started Jul 27 05:38:10 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200384 kb
Host smart-fe3ee378-79cd-44a7-9a28-275a5fa57ce2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014747493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.3014747493
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.308626682
Short name T690
Test name
Test status
Simulation time 21624073 ps
CPU time 0.78 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:08 PM PDT 24
Peak memory 200332 kb
Host smart-c40f499c-9c42-40cb-b030-1b3f99f4cb1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308626682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.308626682
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.1195610029
Short name T195
Test name
Test status
Simulation time 1047557309 ps
CPU time 4.81 seconds
Started Jul 27 05:38:14 PM PDT 24
Finished Jul 27 05:38:18 PM PDT 24
Peak memory 200596 kb
Host smart-dd1fc2fb-4afc-4b53-af4a-d70c99a680f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195610029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1195610029
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.2107336703
Short name T410
Test name
Test status
Simulation time 22274900 ps
CPU time 0.9 seconds
Started Jul 27 05:38:08 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 200352 kb
Host smart-863e0c78-0c56-4bd8-bf2c-bda33907627b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107336703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2107336703
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2539396260
Short name T123
Test name
Test status
Simulation time 4461220984 ps
CPU time 18.51 seconds
Started Jul 27 05:38:21 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200760 kb
Host smart-45ca0c68-3006-4f55-974e-653639b85bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539396260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2539396260
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.3672963842
Short name T603
Test name
Test status
Simulation time 141593914 ps
CPU time 1.36 seconds
Started Jul 27 05:38:09 PM PDT 24
Finished Jul 27 05:38:11 PM PDT 24
Peak memory 200496 kb
Host smart-226c3bf5-1adf-44e4-ac74-46c33070dff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672963842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.3672963842
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.1665101118
Short name T619
Test name
Test status
Simulation time 55455698 ps
CPU time 0.96 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200452 kb
Host smart-2df37b8e-9e05-4323-9590-defb760035f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665101118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.1665101118
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3594192125
Short name T87
Test name
Test status
Simulation time 19285188 ps
CPU time 0.83 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200488 kb
Host smart-60a76266-b2fb-4c83-926e-f0f99db8bff8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594192125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.3594192125
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1607896854
Short name T506
Test name
Test status
Simulation time 96888839 ps
CPU time 1.05 seconds
Started Jul 27 05:38:15 PM PDT 24
Finished Jul 27 05:38:16 PM PDT 24
Peak memory 200440 kb
Host smart-a7c8c5c4-a89f-419d-a4c4-7bdb1daa048b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607896854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1607896854
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.3771728871
Short name T369
Test name
Test status
Simulation time 17331055 ps
CPU time 0.78 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200464 kb
Host smart-2ec7ab2a-2c52-4d54-847e-611012b5e119
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771728871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3771728871
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.2880947543
Short name T252
Test name
Test status
Simulation time 1882155283 ps
CPU time 14.69 seconds
Started Jul 27 05:38:13 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 200772 kb
Host smart-9c08a82b-c176-4e2b-9c64-c776b78760aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880947543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.2880947543
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.3149913320
Short name T316
Test name
Test status
Simulation time 858849642 ps
CPU time 6.85 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200572 kb
Host smart-c25fd413-a550-4829-bab7-86ab8ef52ea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149913320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.3149913320
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3186830479
Short name T318
Test name
Test status
Simulation time 25540029 ps
CPU time 0.96 seconds
Started Jul 27 05:38:14 PM PDT 24
Finished Jul 27 05:38:15 PM PDT 24
Peak memory 200420 kb
Host smart-bbe85345-2026-4d42-8adb-a11e05141c57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186830479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.3186830479
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2857285912
Short name T464
Test name
Test status
Simulation time 15760224 ps
CPU time 0.73 seconds
Started Jul 27 05:38:14 PM PDT 24
Finished Jul 27 05:38:15 PM PDT 24
Peak memory 200488 kb
Host smart-4b1408b1-5533-4193-8a32-da9732cec00e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857285912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.2857285912
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3354911826
Short name T726
Test name
Test status
Simulation time 18734464 ps
CPU time 0.81 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200484 kb
Host smart-65312c7e-fec5-4f13-b026-bbab2887ecef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354911826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.3354911826
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2206278937
Short name T707
Test name
Test status
Simulation time 113437017 ps
CPU time 1.1 seconds
Started Jul 27 05:38:21 PM PDT 24
Finished Jul 27 05:38:22 PM PDT 24
Peak memory 200392 kb
Host smart-8c230f88-5b14-427b-a3b1-ec33e3b55233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206278937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2206278937
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3825159292
Short name T744
Test name
Test status
Simulation time 774361420 ps
CPU time 3.04 seconds
Started Jul 27 05:38:13 PM PDT 24
Finished Jul 27 05:38:16 PM PDT 24
Peak memory 200696 kb
Host smart-4df51785-6a6e-432b-b76a-ed6427677021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825159292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3825159292
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.1626664231
Short name T32
Test name
Test status
Simulation time 41688595 ps
CPU time 0.91 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200408 kb
Host smart-5a33a3a0-364d-438c-94a1-05ec98264be0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626664231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.1626664231
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.1847456952
Short name T382
Test name
Test status
Simulation time 2722031262 ps
CPU time 15.32 seconds
Started Jul 27 05:38:15 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200880 kb
Host smart-7d712074-3b8c-4979-ba89-4d2cf2fe2338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847456952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.1847456952
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.1344028408
Short name T767
Test name
Test status
Simulation time 188546089 ps
CPU time 1.46 seconds
Started Jul 27 05:38:13 PM PDT 24
Finished Jul 27 05:38:15 PM PDT 24
Peak memory 200408 kb
Host smart-59f25c20-f6ff-4635-b8b4-b4aecbdacb87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344028408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1344028408
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1281685861
Short name T742
Test name
Test status
Simulation time 32858632 ps
CPU time 0.78 seconds
Started Jul 27 05:38:13 PM PDT 24
Finished Jul 27 05:38:14 PM PDT 24
Peak memory 200472 kb
Host smart-c5a22d17-b38e-493c-bdbd-0dd2a65300ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281685861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.1281685861
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.3257928321
Short name T523
Test name
Test status
Simulation time 18554831 ps
CPU time 0.78 seconds
Started Jul 27 05:38:21 PM PDT 24
Finished Jul 27 05:38:22 PM PDT 24
Peak memory 199664 kb
Host smart-223a1b5e-750b-4c01-be6a-c0e6df4f7774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257928321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.3257928321
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.3355035961
Short name T396
Test name
Test status
Simulation time 27906707 ps
CPU time 0.92 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200444 kb
Host smart-b0c3aca5-191c-4440-bdd3-e9890afb5c55
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355035961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.3355035961
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.1049127380
Short name T419
Test name
Test status
Simulation time 17228774 ps
CPU time 0.77 seconds
Started Jul 27 05:38:20 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200472 kb
Host smart-8865b2a9-ea5c-4800-b017-c5573f80f316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049127380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1049127380
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.197918198
Short name T625
Test name
Test status
Simulation time 1395440713 ps
CPU time 11.14 seconds
Started Jul 27 05:38:13 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200512 kb
Host smart-696ee58d-f173-4032-a8f2-95041b3c2897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197918198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.197918198
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.1186805979
Short name T367
Test name
Test status
Simulation time 981592699 ps
CPU time 7.22 seconds
Started Jul 27 05:38:14 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 200556 kb
Host smart-9091536b-b6a8-48c2-8f6f-1d07be4febd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186805979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.1186805979
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1806637562
Short name T256
Test name
Test status
Simulation time 16590577 ps
CPU time 0.78 seconds
Started Jul 27 05:38:14 PM PDT 24
Finished Jul 27 05:38:15 PM PDT 24
Peak memory 200476 kb
Host smart-aa855c87-fcb9-4159-ac99-af646b0cdffc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806637562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.1806637562
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2388401243
Short name T783
Test name
Test status
Simulation time 37326906 ps
CPU time 0.9 seconds
Started Jul 27 05:38:12 PM PDT 24
Finished Jul 27 05:38:13 PM PDT 24
Peak memory 200456 kb
Host smart-7e8867d5-7594-49cc-be24-0cce1d659786
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388401243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2388401243
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.64033468
Short name T260
Test name
Test status
Simulation time 42218491 ps
CPU time 0.92 seconds
Started Jul 27 05:38:26 PM PDT 24
Finished Jul 27 05:38:27 PM PDT 24
Peak memory 200276 kb
Host smart-a2f7dc59-c9ec-45c3-89ab-414981658ac7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64033468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_lc_ctrl_intersig_mubi.64033468
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.2575906294
Short name T474
Test name
Test status
Simulation time 25849683 ps
CPU time 0.77 seconds
Started Jul 27 05:38:13 PM PDT 24
Finished Jul 27 05:38:14 PM PDT 24
Peak memory 200456 kb
Host smart-3c31c26a-3426-4ee9-9883-7e317f57b293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575906294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.2575906294
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.1827538081
Short name T295
Test name
Test status
Simulation time 917866017 ps
CPU time 5.31 seconds
Started Jul 27 05:38:19 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200588 kb
Host smart-5fd09f1c-8fc3-400a-bddb-56506393b859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827538081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1827538081
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.3792039827
Short name T794
Test name
Test status
Simulation time 24398611 ps
CPU time 0.8 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200332 kb
Host smart-0e5a13b0-a13f-4469-b8d0-529b5b8c78d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792039827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.3792039827
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.2290849417
Short name T285
Test name
Test status
Simulation time 3288134566 ps
CPU time 25.08 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:49 PM PDT 24
Peak memory 200836 kb
Host smart-6b1e4be0-09ae-4023-a208-c6787b9517ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290849417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.2290849417
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.3273123408
Short name T59
Test name
Test status
Simulation time 180472733265 ps
CPU time 875.23 seconds
Started Jul 27 05:38:18 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 217292 kb
Host smart-580950c6-45f2-4e07-993e-b2e2cbe80321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3273123408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.3273123408
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.3711182677
Short name T605
Test name
Test status
Simulation time 60567322 ps
CPU time 1.06 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200440 kb
Host smart-89026f3d-b8e2-4d0b-9587-341b43d7a28f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711182677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3711182677
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.97684325
Short name T586
Test name
Test status
Simulation time 15514903 ps
CPU time 0.74 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:37:35 PM PDT 24
Peak memory 200388 kb
Host smart-4d6361fe-b40b-450c-a1bc-814f52b08793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97684325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr
_alert_test.97684325
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.934030010
Short name T691
Test name
Test status
Simulation time 37168510 ps
CPU time 0.81 seconds
Started Jul 27 05:37:27 PM PDT 24
Finished Jul 27 05:37:28 PM PDT 24
Peak memory 200468 kb
Host smart-10b57f51-6701-4fa9-97c1-4d5a2d2c315a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934030010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.934030010
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.2167362214
Short name T811
Test name
Test status
Simulation time 74025752 ps
CPU time 0.87 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 199612 kb
Host smart-c77f470a-54af-42ef-8b7e-d0e6113d8f99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167362214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2167362214
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.328630935
Short name T377
Test name
Test status
Simulation time 22535837 ps
CPU time 0.87 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200400 kb
Host smart-22935c46-d0fb-467f-aa85-3b238005c787
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328630935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_div_intersig_mubi.328630935
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.1138332340
Short name T413
Test name
Test status
Simulation time 43791450 ps
CPU time 0.92 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200476 kb
Host smart-58f8b21d-6642-44d6-9902-528a3e87b6e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138332340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1138332340
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.2775778837
Short name T641
Test name
Test status
Simulation time 1280503102 ps
CPU time 10 seconds
Started Jul 27 05:37:27 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 200540 kb
Host smart-746b3082-bd3c-4c32-95ad-3666f5e47b66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775778837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2775778837
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.3363769487
Short name T515
Test name
Test status
Simulation time 138923544 ps
CPU time 1.27 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200552 kb
Host smart-26c89479-a0d4-4e10-ba03-654625f5105a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363769487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.3363769487
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.4283399281
Short name T754
Test name
Test status
Simulation time 33774918 ps
CPU time 0.99 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200396 kb
Host smart-a8bf2673-d696-483d-9423-9c1074b95698
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283399281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.4283399281
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.4204256930
Short name T99
Test name
Test status
Simulation time 35530054 ps
CPU time 0.82 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200472 kb
Host smart-5741e1ed-58b9-43dc-8a57-6d6c30f4fe96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204256930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.4204256930
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.882257393
Short name T470
Test name
Test status
Simulation time 44099647 ps
CPU time 0.84 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200460 kb
Host smart-7014e593-cee3-4e45-8944-748f638968e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882257393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_ctrl_intersig_mubi.882257393
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.175304148
Short name T443
Test name
Test status
Simulation time 14084905 ps
CPU time 0.8 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200472 kb
Host smart-d04cbec5-29de-40b4-a605-a0d7bea7ab31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175304148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.175304148
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.3050776838
Short name T423
Test name
Test status
Simulation time 226022637 ps
CPU time 1.36 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:37 PM PDT 24
Peak memory 200424 kb
Host smart-426daa83-fa26-4dfb-96e0-7b7def9bb939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050776838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3050776838
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.2115482890
Short name T34
Test name
Test status
Simulation time 320652912 ps
CPU time 3.35 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 221676 kb
Host smart-25236875-3cbd-4869-93b7-c089726cbd0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115482890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.2115482890
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.3382358603
Short name T571
Test name
Test status
Simulation time 17102110 ps
CPU time 0.82 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 200400 kb
Host smart-ce2fd532-c45c-42be-8161-44671e84abe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382358603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3382358603
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.330077918
Short name T488
Test name
Test status
Simulation time 4866568099 ps
CPU time 36.98 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:38:16 PM PDT 24
Peak memory 200800 kb
Host smart-28148027-b820-46fe-b711-7faee8cdfce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330077918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.330077918
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.794960319
Short name T264
Test name
Test status
Simulation time 52527213 ps
CPU time 1.07 seconds
Started Jul 27 05:37:26 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 200496 kb
Host smart-a6ad66fc-3a5a-43b5-8078-a7b8f893d6ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794960319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.794960319
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.3959900808
Short name T329
Test name
Test status
Simulation time 19699363 ps
CPU time 0.75 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200476 kb
Host smart-9fb888f1-55c7-44ef-b173-e3bdf8825880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959900808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.3959900808
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.1506619648
Short name T78
Test name
Test status
Simulation time 69110590 ps
CPU time 0.96 seconds
Started Jul 27 05:38:21 PM PDT 24
Finished Jul 27 05:38:22 PM PDT 24
Peak memory 200472 kb
Host smart-d2244d6b-f538-4be3-9671-01f6348a7f3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506619648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.1506619648
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1848328296
Short name T790
Test name
Test status
Simulation time 80212098 ps
CPU time 0.87 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200364 kb
Host smart-15d240eb-148b-411f-b5c8-a6ecedecee6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848328296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1848328296
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.892127088
Short name T225
Test name
Test status
Simulation time 18536219 ps
CPU time 0.79 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200468 kb
Host smart-32825d38-4716-4b86-b02b-a8cb88050c34
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892127088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.892127088
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.128143409
Short name T97
Test name
Test status
Simulation time 23646946 ps
CPU time 0.94 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200472 kb
Host smart-eed6dc19-6bc4-4d06-a49d-18e8a20bd851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128143409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.128143409
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1599854171
Short name T375
Test name
Test status
Simulation time 1762603525 ps
CPU time 10.53 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200668 kb
Host smart-ad79afd0-888e-4602-923c-bb46286002cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599854171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1599854171
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.709178981
Short name T38
Test name
Test status
Simulation time 374844524 ps
CPU time 3.12 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200556 kb
Host smart-8cc3855e-edde-4f02-8adf-5bb17e8c3a3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709178981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_ti
meout.709178981
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3136406487
Short name T391
Test name
Test status
Simulation time 49011465 ps
CPU time 1.02 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200428 kb
Host smart-21d873a9-2d3a-4018-9890-f2f2d4db8118
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136406487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.3136406487
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3883048260
Short name T233
Test name
Test status
Simulation time 54322496 ps
CPU time 0.92 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200448 kb
Host smart-429527d0-b886-47ea-972f-28383fafff4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883048260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.3883048260
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2021779870
Short name T209
Test name
Test status
Simulation time 41534945 ps
CPU time 0.87 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200452 kb
Host smart-5b616777-dd58-4bda-9f5f-487f4bf4c5f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021779870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.2021779870
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.1839898710
Short name T352
Test name
Test status
Simulation time 19786316 ps
CPU time 0.8 seconds
Started Jul 27 05:38:21 PM PDT 24
Finished Jul 27 05:38:22 PM PDT 24
Peak memory 200428 kb
Host smart-f9d1600d-5b29-4eb1-ad91-65633b55e8ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839898710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.1839898710
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.3395334932
Short name T637
Test name
Test status
Simulation time 1643253232 ps
CPU time 6.36 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200580 kb
Host smart-9e8ab83c-ae64-443c-a682-62150a6a82e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395334932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.3395334932
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.1424789254
Short name T540
Test name
Test status
Simulation time 22722654 ps
CPU time 0.92 seconds
Started Jul 27 05:38:26 PM PDT 24
Finished Jul 27 05:38:27 PM PDT 24
Peak memory 200324 kb
Host smart-49ba88c1-480e-44c9-8201-29d0b2e9e32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424789254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.1424789254
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1409344384
Short name T309
Test name
Test status
Simulation time 3956086658 ps
CPU time 22.31 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:47 PM PDT 24
Peak memory 200728 kb
Host smart-19cb3c90-7f4a-4279-b487-2be2b80a39e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409344384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1409344384
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.681592253
Short name T155
Test name
Test status
Simulation time 38458474 ps
CPU time 0.78 seconds
Started Jul 27 05:38:26 PM PDT 24
Finished Jul 27 05:38:27 PM PDT 24
Peak memory 200444 kb
Host smart-1e76e44f-4490-488e-960a-c0337d1f6557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681592253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.681592253
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.2791877083
Short name T435
Test name
Test status
Simulation time 16672644 ps
CPU time 0.81 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200444 kb
Host smart-5675f371-869e-4ca7-9ad5-c5d1c63a8ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791877083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.2791877083
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.955513666
Short name T650
Test name
Test status
Simulation time 38670411 ps
CPU time 0.81 seconds
Started Jul 27 05:38:27 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 200392 kb
Host smart-f68851ce-b9ed-40b1-9b45-c33673996172
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955513666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.955513666
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.1900417180
Short name T426
Test name
Test status
Simulation time 13445081 ps
CPU time 0.7 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 199736 kb
Host smart-7315cf3d-7c33-4154-af7d-71cf62f242e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900417180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1900417180
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.3306836366
Short name T549
Test name
Test status
Simulation time 84491075 ps
CPU time 1.1 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200484 kb
Host smart-e649e840-a809-404b-a348-a7b4b0a81f0c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306836366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.3306836366
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.4223432960
Short name T136
Test name
Test status
Simulation time 60722900 ps
CPU time 0.93 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200404 kb
Host smart-8a06ce02-35de-43a1-a07f-09424f119caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223432960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.4223432960
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.3362048349
Short name T632
Test name
Test status
Simulation time 2236374885 ps
CPU time 16.23 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200784 kb
Host smart-0fbde6d5-43be-46b3-ba62-fb69b86d7c08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362048349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3362048349
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3873183316
Short name T430
Test name
Test status
Simulation time 1934659482 ps
CPU time 14.85 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200624 kb
Host smart-49c8ca42-6467-480d-9b88-1af41330c6a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873183316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3873183316
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.2953938827
Short name T668
Test name
Test status
Simulation time 49048807 ps
CPU time 0.86 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200468 kb
Host smart-feaf7924-c221-4e1e-9864-5bdeca9af478
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953938827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.2953938827
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2765552515
Short name T356
Test name
Test status
Simulation time 46452199 ps
CPU time 0.97 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200724 kb
Host smart-e92fe624-a3c1-4aa8-abe4-05a84be92fc7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765552515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.2765552515
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3179257910
Short name T633
Test name
Test status
Simulation time 29419818 ps
CPU time 0.9 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200468 kb
Host smart-188d2606-0e10-45f6-85a7-ac2a4f3845a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179257910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.3179257910
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.1356612983
Short name T762
Test name
Test status
Simulation time 38757117 ps
CPU time 0.79 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200504 kb
Host smart-6cc552f3-09c9-4597-a26c-0e4ee53398d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356612983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.1356612983
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.473074122
Short name T62
Test name
Test status
Simulation time 422512212 ps
CPU time 2.97 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200468 kb
Host smart-d6f01866-4c81-4023-94e4-80c2e24c504f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473074122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.473074122
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.2372639189
Short name T695
Test name
Test status
Simulation time 46117230 ps
CPU time 0.91 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200388 kb
Host smart-43009f10-44cc-4d65-9721-44c99be4b921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372639189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.2372639189
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.2860953608
Short name T551
Test name
Test status
Simulation time 5595625525 ps
CPU time 41.94 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:39:05 PM PDT 24
Peak memory 200856 kb
Host smart-b9d832e7-9926-45c1-91dd-bb07b5dca4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860953608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.2860953608
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.3925219040
Short name T491
Test name
Test status
Simulation time 20203088 ps
CPU time 0.82 seconds
Started Jul 27 05:38:27 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 200460 kb
Host smart-5115d3be-e266-4b53-af6a-33cc2cd6e299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925219040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.3925219040
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.1318669975
Short name T771
Test name
Test status
Simulation time 41450088 ps
CPU time 0.82 seconds
Started Jul 27 05:38:27 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 200392 kb
Host smart-7c27ea2c-23eb-4cb1-b5e9-2263018d31f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318669975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.1318669975
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.3394909388
Short name T739
Test name
Test status
Simulation time 91318525 ps
CPU time 1.16 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200476 kb
Host smart-f5f4ec16-1fec-4f8f-ac88-6c6398f2449b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394909388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.3394909388
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.4146150128
Short name T740
Test name
Test status
Simulation time 15732504 ps
CPU time 0.73 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 199700 kb
Host smart-14bb75d5-b7b6-4bf3-a874-bb1e05164b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146150128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.4146150128
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.1314270617
Short name T682
Test name
Test status
Simulation time 65231215 ps
CPU time 0.98 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200356 kb
Host smart-4e5495d5-bc92-4e91-aacc-ccd9af286bfc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314270617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.1314270617
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.3258397883
Short name T399
Test name
Test status
Simulation time 49649255 ps
CPU time 0.92 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200308 kb
Host smart-9ad1a0f1-bad4-48e5-b7ce-83c2d35c1cbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258397883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.3258397883
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.999378670
Short name T777
Test name
Test status
Simulation time 676615180 ps
CPU time 6.07 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:35 PM PDT 24
Peak memory 200432 kb
Host smart-42f33bda-aea2-460f-b2ba-2c5a0c9b91c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999378670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.999378670
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.2150716766
Short name T607
Test name
Test status
Simulation time 2431069162 ps
CPU time 9.9 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:32 PM PDT 24
Peak memory 200824 kb
Host smart-cd7aa1f5-e260-4373-8916-58c44f781f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150716766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.2150716766
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1962284217
Short name T511
Test name
Test status
Simulation time 43640032 ps
CPU time 0.8 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200444 kb
Host smart-01b55a42-4a10-4e47-9817-3890a22f0de5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962284217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.1962284217
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3858787318
Short name T212
Test name
Test status
Simulation time 45538748 ps
CPU time 0.89 seconds
Started Jul 27 05:38:21 PM PDT 24
Finished Jul 27 05:38:22 PM PDT 24
Peak memory 200488 kb
Host smart-cde9306a-b36f-4ee3-9823-b2128b6459e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858787318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3858787318
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1352970011
Short name T425
Test name
Test status
Simulation time 53854121 ps
CPU time 0.88 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 200452 kb
Host smart-ca096d70-1a3a-4d85-a105-ae9a18bc7c0f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352970011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.1352970011
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3241721784
Short name T552
Test name
Test status
Simulation time 17241892 ps
CPU time 0.73 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200680 kb
Host smart-c0eefe11-85be-48ed-abeb-90e1706abb4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241721784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3241721784
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.1638695972
Short name T712
Test name
Test status
Simulation time 1351990989 ps
CPU time 4.74 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 200564 kb
Host smart-6f46da2e-52be-4112-9c3b-bba186af6455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638695972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.1638695972
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.770745518
Short name T148
Test name
Test status
Simulation time 23222711 ps
CPU time 0.95 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200384 kb
Host smart-564435a2-fb74-400c-bdf7-350239df3e77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770745518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.770745518
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.342549852
Short name T166
Test name
Test status
Simulation time 76626188 ps
CPU time 1.1 seconds
Started Jul 27 05:38:25 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200524 kb
Host smart-dc1100fc-7af9-4705-9ba6-b2b8b645610c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342549852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.342549852
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1112696122
Short name T14
Test name
Test status
Simulation time 499487670151 ps
CPU time 1920.85 seconds
Started Jul 27 05:38:26 PM PDT 24
Finished Jul 27 06:10:27 PM PDT 24
Peak memory 212900 kb
Host smart-ba005d83-9017-4d6a-9b9f-00cb031df757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1112696122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1112696122
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.2761653925
Short name T438
Test name
Test status
Simulation time 23637017 ps
CPU time 0.87 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200456 kb
Host smart-a189b79b-8fea-444d-9c6c-419cc79a60b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761653925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2761653925
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.1816242880
Short name T507
Test name
Test status
Simulation time 16002771 ps
CPU time 0.78 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200416 kb
Host smart-0e98d1a7-6020-4559-8a59-5d0f0313de56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816242880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.1816242880
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1873570657
Short name T72
Test name
Test status
Simulation time 75371752 ps
CPU time 1.04 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200416 kb
Host smart-7deb5ebc-7acb-43f0-b8e3-655ab8f9ab8f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873570657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.1873570657
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.4265736188
Short name T247
Test name
Test status
Simulation time 33932914 ps
CPU time 0.76 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200360 kb
Host smart-0f632f9e-0c02-4d33-a3ef-ed03bf814135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265736188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.4265736188
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2624759499
Short name T693
Test name
Test status
Simulation time 66252939 ps
CPU time 1.01 seconds
Started Jul 27 05:38:33 PM PDT 24
Finished Jul 27 05:38:34 PM PDT 24
Peak memory 198888 kb
Host smart-c2e407fb-f892-4924-9399-d5f117e4fe38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624759499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2624759499
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.3273186468
Short name T578
Test name
Test status
Simulation time 46923192 ps
CPU time 0.93 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200444 kb
Host smart-bb270ae0-61fd-4ab5-9690-df7b8a4d610f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273186468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3273186468
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.591240834
Short name T110
Test name
Test status
Simulation time 2491078032 ps
CPU time 13.85 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200672 kb
Host smart-d02c2180-d41c-48fe-9657-76985d3e1b64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591240834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.591240834
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.588435643
Short name T25
Test name
Test status
Simulation time 638840949 ps
CPU time 3.26 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:26 PM PDT 24
Peak memory 200596 kb
Host smart-3fd39f88-70c3-490f-b239-b7a4682eee49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588435643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti
meout.588435643
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2060225577
Short name T153
Test name
Test status
Simulation time 44250814 ps
CPU time 1.17 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200400 kb
Host smart-04d0c23e-0805-49a9-bae8-ddbcd9d98c71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060225577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.2060225577
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1293274358
Short name T133
Test name
Test status
Simulation time 15452880 ps
CPU time 0.77 seconds
Started Jul 27 05:38:26 PM PDT 24
Finished Jul 27 05:38:27 PM PDT 24
Peak memory 200328 kb
Host smart-71e3a707-1024-41d8-bf46-7422d93812c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293274358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.1293274358
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3988174213
Short name T781
Test name
Test status
Simulation time 87476557 ps
CPU time 1.08 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200432 kb
Host smart-1adcc0fe-d94c-43c2-af5b-47833bb165a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988174213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.3988174213
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.1191605640
Short name T602
Test name
Test status
Simulation time 18732079 ps
CPU time 0.75 seconds
Started Jul 27 05:38:23 PM PDT 24
Finished Jul 27 05:38:24 PM PDT 24
Peak memory 200504 kb
Host smart-49afd57e-ba99-4358-af91-07a3f2e54ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191605640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1191605640
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.1775771639
Short name T145
Test name
Test status
Simulation time 900721100 ps
CPU time 5.64 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:34 PM PDT 24
Peak memory 200644 kb
Host smart-eb2d3665-c6c6-4be4-b5c5-dcd72c1a6612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775771639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1775771639
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.1677087816
Short name T769
Test name
Test status
Simulation time 18117254 ps
CPU time 0.85 seconds
Started Jul 27 05:38:24 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 200352 kb
Host smart-aa977a92-dd27-49d5-bea5-aac952f9a6dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677087816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1677087816
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.2099621908
Short name T541
Test name
Test status
Simulation time 4852947732 ps
CPU time 32.8 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 200824 kb
Host smart-f0b261d7-d00d-4da7-aefe-3c4988f8fe40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099621908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.2099621908
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.1570105855
Short name T21
Test name
Test status
Simulation time 170004867817 ps
CPU time 673.42 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:49:43 PM PDT 24
Peak memory 217332 kb
Host smart-65017fc2-054f-4093-b126-78737d4f9d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1570105855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.1570105855
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.1477463288
Short name T355
Test name
Test status
Simulation time 37991705 ps
CPU time 0.78 seconds
Started Jul 27 05:38:22 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 200464 kb
Host smart-a45feb2a-914d-43a7-816b-15a4e675d64e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477463288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.1477463288
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.1516682901
Short name T17
Test name
Test status
Simulation time 23930449 ps
CPU time 0.79 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200468 kb
Host smart-1c70d8b4-609e-48bf-8143-621caed7c093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516682901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.1516682901
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3002614431
Short name T520
Test name
Test status
Simulation time 32560466 ps
CPU time 0.77 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200424 kb
Host smart-141f8ac0-7789-4643-bf10-7393c80ba0dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002614431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3002614431
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.2498341609
Short name T544
Test name
Test status
Simulation time 16780562 ps
CPU time 0.7 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200376 kb
Host smart-49a2461a-7cfb-49b1-80d1-a0f46e0d8fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498341609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2498341609
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1293018699
Short name T656
Test name
Test status
Simulation time 65696109 ps
CPU time 0.93 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200452 kb
Host smart-d75a089e-e572-449b-8267-e7008497b850
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293018699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1293018699
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2162863383
Short name T236
Test name
Test status
Simulation time 81326210 ps
CPU time 1.05 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200392 kb
Host smart-6ddb2bf6-4dcd-496f-9393-01d36962aa34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162863383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2162863383
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3513553154
Short name T2
Test name
Test status
Simulation time 919460501 ps
CPU time 6.7 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:35 PM PDT 24
Peak memory 200540 kb
Host smart-50b3ef4c-176b-4396-823f-13fc89e44032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513553154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3513553154
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.425858517
Short name T246
Test name
Test status
Simulation time 2057243269 ps
CPU time 14.58 seconds
Started Jul 27 05:38:27 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 200752 kb
Host smart-880e92b7-2171-48c4-8b67-47c3d9e16216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425858517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_ti
meout.425858517
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.1533495995
Short name T257
Test name
Test status
Simulation time 111229820 ps
CPU time 1.25 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200396 kb
Host smart-e39a0223-d7a6-4131-843e-63b87b77b1e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533495995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.1533495995
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1099069475
Short name T428
Test name
Test status
Simulation time 208869200 ps
CPU time 1.34 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:32 PM PDT 24
Peak memory 200396 kb
Host smart-3bdac627-3e6d-47e9-bb76-a539f4c14b25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099069475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1099069475
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.1567455712
Short name T468
Test name
Test status
Simulation time 40261816 ps
CPU time 0.83 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200468 kb
Host smart-13300c85-4397-44b6-90a2-922bc56927a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567455712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.1567455712
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.2726231736
Short name T795
Test name
Test status
Simulation time 20200702 ps
CPU time 0.71 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200436 kb
Host smart-c2efd7f4-acd0-486e-9b84-685aed1e1108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726231736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.2726231736
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.3950157848
Short name T141
Test name
Test status
Simulation time 392984280 ps
CPU time 2.77 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200332 kb
Host smart-3f14a908-8057-47aa-8370-8a5852b94ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950157848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3950157848
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.3618137050
Short name T359
Test name
Test status
Simulation time 17424279 ps
CPU time 0.8 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200344 kb
Host smart-f1a76d36-3d69-4584-b103-901aaee72d83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618137050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3618137050
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.2608148384
Short name T258
Test name
Test status
Simulation time 116746179 ps
CPU time 1.21 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200468 kb
Host smart-0414336d-08fb-49e5-86d6-cd664ff827db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608148384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.2608148384
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2878085852
Short name T184
Test name
Test status
Simulation time 60610603 ps
CPU time 0.96 seconds
Started Jul 27 05:38:33 PM PDT 24
Finished Jul 27 05:38:34 PM PDT 24
Peak memory 198832 kb
Host smart-3a501583-7314-441e-a85c-b17e61d9351e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878085852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2878085852
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.951577680
Short name T358
Test name
Test status
Simulation time 242557738 ps
CPU time 1.46 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200444 kb
Host smart-595d6349-4f26-4826-a22c-c7842fc9ce2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951577680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm
gr_alert_test.951577680
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2330680806
Short name T500
Test name
Test status
Simulation time 24159163 ps
CPU time 0.88 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:38:30 PM PDT 24
Peak memory 200432 kb
Host smart-cab354d5-4cdc-4dd7-b8df-e48363a9d23d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330680806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.2330680806
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.389668981
Short name T159
Test name
Test status
Simulation time 65441387 ps
CPU time 0.82 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 199668 kb
Host smart-af75b9b3-2dfa-4658-94bf-aaa407b52c8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389668981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.389668981
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.1773580145
Short name T169
Test name
Test status
Simulation time 38305989 ps
CPU time 0.82 seconds
Started Jul 27 05:38:33 PM PDT 24
Finished Jul 27 05:38:34 PM PDT 24
Peak memory 200468 kb
Host smart-44c5e785-5ca1-4dcc-9156-a2c937efa1bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773580145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.1773580145
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3718196716
Short name T163
Test name
Test status
Simulation time 90565839 ps
CPU time 1.13 seconds
Started Jul 27 05:38:33 PM PDT 24
Finished Jul 27 05:38:34 PM PDT 24
Peak memory 200224 kb
Host smart-d04812c7-0138-4544-abe8-361c471ce498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718196716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3718196716
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.2633708762
Short name T280
Test name
Test status
Simulation time 317200169 ps
CPU time 3.02 seconds
Started Jul 27 05:38:33 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200516 kb
Host smart-6d0a62e4-84ca-46c5-9ed2-b439fae9e927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633708762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2633708762
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.3739659510
Short name T806
Test name
Test status
Simulation time 2544008481 ps
CPU time 10.02 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:38:39 PM PDT 24
Peak memory 200816 kb
Host smart-586dcccf-7a9e-4764-b47e-04ae6a3da6a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739659510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.3739659510
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.2089517476
Short name T267
Test name
Test status
Simulation time 67002452 ps
CPU time 0.98 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200372 kb
Host smart-a000d39a-783b-42dc-9934-4273bbd8213e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089517476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.2089517476
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1861631185
Short name T608
Test name
Test status
Simulation time 33428199 ps
CPU time 0.78 seconds
Started Jul 27 05:38:27 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 200484 kb
Host smart-5e91ef66-ffd8-433b-ba20-211f520b1f28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861631185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1861631185
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.4104008957
Short name T590
Test name
Test status
Simulation time 15871892 ps
CPU time 0.77 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200416 kb
Host smart-4bbf85d3-6e2e-4eab-8e53-8e70bca5cd44
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104008957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.4104008957
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.2075842582
Short name T192
Test name
Test status
Simulation time 40835043 ps
CPU time 0.84 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200456 kb
Host smart-22a115b4-72d1-42c4-99d2-a9918bfd5fb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075842582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2075842582
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.4249487984
Short name T23
Test name
Test status
Simulation time 534501589 ps
CPU time 3.4 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 200572 kb
Host smart-f3a699c7-8e68-4e1d-9ce2-9db625d67a66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249487984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.4249487984
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.3331073233
Short name T562
Test name
Test status
Simulation time 25181051 ps
CPU time 0.82 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200416 kb
Host smart-9c82316b-1266-4f2e-8a75-b255376e7819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331073233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3331073233
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.3467520975
Short name T566
Test name
Test status
Simulation time 2665306509 ps
CPU time 14.66 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:43 PM PDT 24
Peak memory 200832 kb
Host smart-4b5c079c-9aea-4ca8-89ef-a78d66fdf49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467520975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.3467520975
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.4068530491
Short name T812
Test name
Test status
Simulation time 16401865 ps
CPU time 0.8 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200444 kb
Host smart-a0729238-ae6a-4662-a6ba-21eb5a595b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068530491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.4068530491
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.2945950272
Short name T645
Test name
Test status
Simulation time 16434336 ps
CPU time 0.8 seconds
Started Jul 27 05:38:36 PM PDT 24
Finished Jul 27 05:38:37 PM PDT 24
Peak memory 200468 kb
Host smart-6f64357d-eef1-42e4-abc3-5c5dd02ee9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945950272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.2945950272
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2263162779
Short name T748
Test name
Test status
Simulation time 24409881 ps
CPU time 0.76 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200464 kb
Host smart-38263775-b4fd-4640-8bb8-e74c18a28942
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263162779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.2263162779
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.2039956718
Short name T342
Test name
Test status
Simulation time 32863411 ps
CPU time 0.76 seconds
Started Jul 27 05:38:29 PM PDT 24
Finished Jul 27 05:38:29 PM PDT 24
Peak memory 200364 kb
Host smart-b169c804-7982-4cd7-ac2c-db22c5f180d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039956718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2039956718
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.435134261
Short name T199
Test name
Test status
Simulation time 37985265 ps
CPU time 0.96 seconds
Started Jul 27 05:38:40 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200424 kb
Host smart-c0130d54-e24d-4db5-9b79-016a960e2653
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435134261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_div_intersig_mubi.435134261
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.2313038507
Short name T768
Test name
Test status
Simulation time 118619511 ps
CPU time 1.23 seconds
Started Jul 27 05:38:31 PM PDT 24
Finished Jul 27 05:38:33 PM PDT 24
Peak memory 200472 kb
Host smart-e97342a5-c4d6-405d-86c8-72bb8aa49e86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313038507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.2313038507
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.1968744615
Short name T248
Test name
Test status
Simulation time 2034565536 ps
CPU time 7.41 seconds
Started Jul 27 05:38:28 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200540 kb
Host smart-401099f0-6b0a-43b0-8961-c1ca2f2b5f07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968744615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.1968744615
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.1080731156
Short name T439
Test name
Test status
Simulation time 787658739 ps
CPU time 3.77 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:33 PM PDT 24
Peak memory 200572 kb
Host smart-f2bc4fc6-691c-4d9b-b810-27398021db7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080731156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.1080731156
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.3961054934
Short name T766
Test name
Test status
Simulation time 28951796 ps
CPU time 0.84 seconds
Started Jul 27 05:38:31 PM PDT 24
Finished Jul 27 05:38:32 PM PDT 24
Peak memory 200452 kb
Host smart-53859393-98d2-4f85-b3d6-c85ee967d8aa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961054934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.3961054934
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.4215964357
Short name T532
Test name
Test status
Simulation time 42131742 ps
CPU time 0.94 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200460 kb
Host smart-b95d1cda-811a-41ed-9277-522765883662
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215964357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.4215964357
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2385496271
Short name T353
Test name
Test status
Simulation time 57273257 ps
CPU time 0.9 seconds
Started Jul 27 05:38:33 PM PDT 24
Finished Jul 27 05:38:34 PM PDT 24
Peak memory 200452 kb
Host smart-a1c6b56d-fd7b-47ad-9930-021bc8f8eb5f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385496271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.2385496271
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.1788849929
Short name T490
Test name
Test status
Simulation time 43920844 ps
CPU time 0.81 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200412 kb
Host smart-56d6f83e-5c8d-4791-a020-30336aa016a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788849929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1788849929
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.2651669545
Short name T447
Test name
Test status
Simulation time 16089595 ps
CPU time 0.83 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:31 PM PDT 24
Peak memory 200412 kb
Host smart-395e3efc-f824-4d01-8dd3-fbfee6839a36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651669545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2651669545
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.1857326727
Short name T581
Test name
Test status
Simulation time 5959924336 ps
CPU time 23.68 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200800 kb
Host smart-918cc4ce-d500-46bc-9dcb-00db1ca04177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857326727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.1857326727
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.3615767609
Short name T810
Test name
Test status
Simulation time 352272073 ps
CPU time 2.08 seconds
Started Jul 27 05:38:30 PM PDT 24
Finished Jul 27 05:38:33 PM PDT 24
Peak memory 200420 kb
Host smart-83722171-d669-44b4-8717-aca90a66f854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615767609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3615767609
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.3346200436
Short name T478
Test name
Test status
Simulation time 26559228 ps
CPU time 0.78 seconds
Started Jul 27 05:38:36 PM PDT 24
Finished Jul 27 05:38:37 PM PDT 24
Peak memory 200480 kb
Host smart-374f5210-c9ed-454e-8aa8-83251629ec2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346200436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.3346200436
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.4263805878
Short name T772
Test name
Test status
Simulation time 99557948 ps
CPU time 1.18 seconds
Started Jul 27 05:38:35 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200476 kb
Host smart-1dc2f640-3df0-4202-89aa-122b16bed192
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263805878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.4263805878
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.173542347
Short name T174
Test name
Test status
Simulation time 16155258 ps
CPU time 0.69 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:38:37 PM PDT 24
Peak memory 199672 kb
Host smart-9e8d884b-8881-41d6-871a-cb7c6fd8ec37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173542347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.173542347
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.724831750
Short name T711
Test name
Test status
Simulation time 23813419 ps
CPU time 0.86 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200448 kb
Host smart-37e1c5de-77e0-43d3-b512-3cfc0d259f79
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724831750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_div_intersig_mubi.724831750
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.3002718184
Short name T15
Test name
Test status
Simulation time 41706282 ps
CPU time 0.86 seconds
Started Jul 27 05:38:41 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 200368 kb
Host smart-691e7449-e59a-43a9-9880-1e4bc1035e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002718184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3002718184
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.1151314936
Short name T105
Test name
Test status
Simulation time 234287162 ps
CPU time 1.64 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200528 kb
Host smart-bc948c8e-f6b3-48d1-8c44-61d3c44cdff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151314936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1151314936
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.2355116196
Short name T704
Test name
Test status
Simulation time 417745269 ps
CPU time 2.52 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200596 kb
Host smart-f798bc3d-e19d-4b67-a005-d106db50d13f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355116196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.2355116196
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.459871729
Short name T796
Test name
Test status
Simulation time 142648148 ps
CPU time 1.27 seconds
Started Jul 27 05:38:41 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 200320 kb
Host smart-e31861cd-ff91-43c0-90d9-d4884a6fcf4e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459871729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_idle_intersig_mubi.459871729
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.1284074533
Short name T596
Test name
Test status
Simulation time 24742252 ps
CPU time 0.89 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200476 kb
Host smart-3cc7d40b-0923-474d-98d0-c0c5d1a1ee35
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284074533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.1284074533
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.250714606
Short name T508
Test name
Test status
Simulation time 24085290 ps
CPU time 0.92 seconds
Started Jul 27 05:38:40 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200456 kb
Host smart-b6b8ab60-e970-4026-a746-032674266aef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250714606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_ctrl_intersig_mubi.250714606
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.2731499302
Short name T575
Test name
Test status
Simulation time 24945030 ps
CPU time 0.79 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 200432 kb
Host smart-96c18b67-4b55-4585-84d7-876163726eaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731499302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2731499302
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.2640321105
Short name T460
Test name
Test status
Simulation time 64328677 ps
CPU time 0.92 seconds
Started Jul 27 05:38:36 PM PDT 24
Finished Jul 27 05:38:37 PM PDT 24
Peak memory 200428 kb
Host smart-0d53901f-804d-4229-bed1-da3076131b4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640321105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.2640321105
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.1432958496
Short name T548
Test name
Test status
Simulation time 20660934 ps
CPU time 0.83 seconds
Started Jul 27 05:38:35 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200412 kb
Host smart-821bc090-08dc-4a63-96b4-5579951ab4dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432958496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.1432958496
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.3529096565
Short name T125
Test name
Test status
Simulation time 12841736758 ps
CPU time 69.78 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:39:55 PM PDT 24
Peak memory 200516 kb
Host smart-3f4a3545-e474-499c-9e26-a344e21a2be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529096565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.3529096565
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.286490963
Short name T611
Test name
Test status
Simulation time 195594207306 ps
CPU time 1201.64 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:58:42 PM PDT 24
Peak memory 217276 kb
Host smart-9807bc4e-d65b-4abe-8b5b-15a03fe5d1bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=286490963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.286490963
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.3848884782
Short name T61
Test name
Test status
Simulation time 53757383 ps
CPU time 0.89 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200476 kb
Host smart-f0c5bef1-9246-49b6-aa1c-190e4e6fcdd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848884782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3848884782
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.1212939849
Short name T386
Test name
Test status
Simulation time 90336787 ps
CPU time 0.97 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:38:46 PM PDT 24
Peak memory 200380 kb
Host smart-bb6a0627-fc94-41fc-b643-7f2912e61163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212939849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.1212939849
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.408589190
Short name T572
Test name
Test status
Simulation time 51363501 ps
CPU time 0.97 seconds
Started Jul 27 05:38:35 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200424 kb
Host smart-e8d410a3-de8a-48c7-b603-80ea7b7694bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408589190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.408589190
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3239046080
Short name T785
Test name
Test status
Simulation time 46783023 ps
CPU time 0.82 seconds
Started Jul 27 05:38:41 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 199620 kb
Host smart-f0e28a2d-fd58-4846-8466-5bc77c4c2b88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239046080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3239046080
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.1229863433
Short name T231
Test name
Test status
Simulation time 55548724 ps
CPU time 0.89 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200460 kb
Host smart-3edde240-53fb-4fd4-ab85-ccaf593bae62
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229863433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.1229863433
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.804076895
Short name T556
Test name
Test status
Simulation time 14996555 ps
CPU time 0.77 seconds
Started Jul 27 05:38:35 PM PDT 24
Finished Jul 27 05:38:36 PM PDT 24
Peak memory 200440 kb
Host smart-b4bb7d31-d9eb-41b9-a5ca-4f4f7df0554f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804076895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.804076895
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.2854136110
Short name T652
Test name
Test status
Simulation time 2128815025 ps
CPU time 11.58 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:38:49 PM PDT 24
Peak memory 200716 kb
Host smart-dd79c31e-fb02-4951-9a7f-869679110b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854136110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2854136110
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.2315291041
Short name T222
Test name
Test status
Simulation time 895366761 ps
CPU time 3.44 seconds
Started Jul 27 05:38:40 PM PDT 24
Finished Jul 27 05:38:43 PM PDT 24
Peak memory 200576 kb
Host smart-ef888eb1-594d-4511-996a-1c68926d9fe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315291041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.2315291041
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.3766031150
Short name T791
Test name
Test status
Simulation time 19627932 ps
CPU time 0.8 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200484 kb
Host smart-03dc72ae-1d55-4158-b704-513db6f04c3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766031150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.3766031150
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1664649691
Short name T418
Test name
Test status
Simulation time 20815501 ps
CPU time 0.84 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:38:46 PM PDT 24
Peak memory 200392 kb
Host smart-5152ad23-476f-49fe-b709-5e02567f1e74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664649691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.1664649691
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2687132721
Short name T731
Test name
Test status
Simulation time 28866985 ps
CPU time 0.92 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200452 kb
Host smart-920a9713-ef58-44f9-9c71-53c15354a9c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687132721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.2687132721
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.3219599363
Short name T259
Test name
Test status
Simulation time 60814473 ps
CPU time 0.92 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:39 PM PDT 24
Peak memory 200404 kb
Host smart-ee8b3057-8ba7-4623-b17b-ad1f10780418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219599363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3219599363
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.2384497753
Short name T681
Test name
Test status
Simulation time 859321267 ps
CPU time 3.49 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200656 kb
Host smart-c5f6c969-9a04-42d2-af41-6381acaf877f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384497753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2384497753
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.2650518871
Short name T553
Test name
Test status
Simulation time 29478340 ps
CPU time 0.83 seconds
Started Jul 27 05:38:36 PM PDT 24
Finished Jul 27 05:38:37 PM PDT 24
Peak memory 200428 kb
Host smart-0ca865e6-69a7-4247-8c22-99125dbd6a32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650518871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.2650518871
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.2930862879
Short name T334
Test name
Test status
Simulation time 212166669 ps
CPU time 1.59 seconds
Started Jul 27 05:38:40 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 200464 kb
Host smart-a3efd703-cc66-4ea3-97dd-675c5b3c846d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930862879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.2930862879
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.2939219513
Short name T57
Test name
Test status
Simulation time 32796321831 ps
CPU time 494.08 seconds
Started Jul 27 05:38:35 PM PDT 24
Finished Jul 27 05:46:49 PM PDT 24
Peak memory 217320 kb
Host smart-1429114f-c0b4-4cd0-b8a6-cdd662f53e75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2939219513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.2939219513
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3227705948
Short name T5
Test name
Test status
Simulation time 73516298 ps
CPU time 1.05 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200456 kb
Host smart-98d92fdb-3fb0-4b7b-80c9-92716938e393
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227705948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3227705948
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.892117726
Short name T774
Test name
Test status
Simulation time 36794868 ps
CPU time 0.85 seconds
Started Jul 27 05:38:47 PM PDT 24
Finished Jul 27 05:38:48 PM PDT 24
Peak memory 200468 kb
Host smart-54b7e88b-6f57-4e46-ade6-58bb849bd482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892117726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkm
gr_alert_test.892117726
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.1565453099
Short name T518
Test name
Test status
Simulation time 50046426 ps
CPU time 0.94 seconds
Started Jul 27 05:38:34 PM PDT 24
Finished Jul 27 05:38:35 PM PDT 24
Peak memory 200464 kb
Host smart-9ce385d6-ca04-4adc-8ffb-ead2be87f2f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565453099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.1565453099
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.1558209035
Short name T809
Test name
Test status
Simulation time 96292706 ps
CPU time 0.98 seconds
Started Jul 27 05:38:40 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 199700 kb
Host smart-f8d76ca0-de16-4992-867e-3834ec5a148e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558209035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.1558209035
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.4180492503
Short name T281
Test name
Test status
Simulation time 28635605 ps
CPU time 0.93 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:38:39 PM PDT 24
Peak memory 200460 kb
Host smart-f1b0c8cc-b8fd-41dc-9f9f-9a75015c67b0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180492503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.4180492503
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.446332181
Short name T798
Test name
Test status
Simulation time 47271222 ps
CPU time 0.86 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200464 kb
Host smart-9d6dd06c-3a1a-4732-a2f1-f04819d3d3fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446332181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.446332181
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2293887349
Short name T570
Test name
Test status
Simulation time 2530784125 ps
CPU time 9.89 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:38:55 PM PDT 24
Peak memory 200680 kb
Host smart-e561ad8b-7110-44c8-b290-c222a2cd2982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293887349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2293887349
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.3821788234
Short name T381
Test name
Test status
Simulation time 2414560934 ps
CPU time 18.33 seconds
Started Jul 27 05:38:40 PM PDT 24
Finished Jul 27 05:38:59 PM PDT 24
Peak memory 200832 kb
Host smart-e0410836-f416-4f0b-95f0-c1a9a8998041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821788234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.3821788234
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.2303750283
Short name T676
Test name
Test status
Simulation time 48263550 ps
CPU time 0.84 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200476 kb
Host smart-0912608d-2f83-4334-8df3-20b11ad33c0c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303750283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.2303750283
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2478243452
Short name T573
Test name
Test status
Simulation time 31027034 ps
CPU time 0.76 seconds
Started Jul 27 05:38:41 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 200200 kb
Host smart-5e963a1b-7253-4f45-a143-d35884dd4c1c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478243452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2478243452
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.150766918
Short name T489
Test name
Test status
Simulation time 48663064 ps
CPU time 0.89 seconds
Started Jul 27 05:38:40 PM PDT 24
Finished Jul 27 05:38:41 PM PDT 24
Peak memory 200444 kb
Host smart-def288b4-5762-4328-9e62-a82657dd4fee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150766918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_ctrl_intersig_mubi.150766918
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.896666481
Short name T673
Test name
Test status
Simulation time 116520392 ps
CPU time 1.07 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:38:46 PM PDT 24
Peak memory 200108 kb
Host smart-57d514bd-042b-4c1f-98e6-7137b297f363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896666481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.896666481
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.2297819007
Short name T643
Test name
Test status
Simulation time 611527624 ps
CPU time 2.63 seconds
Started Jul 27 05:38:39 PM PDT 24
Finished Jul 27 05:38:42 PM PDT 24
Peak memory 200440 kb
Host smart-3f50ab15-028d-4237-8728-c49fc9823b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297819007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2297819007
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.662829809
Short name T102
Test name
Test status
Simulation time 63630104 ps
CPU time 0.96 seconds
Started Jul 27 05:38:37 PM PDT 24
Finished Jul 27 05:38:38 PM PDT 24
Peak memory 200392 kb
Host smart-5ac85ec3-3aa8-40ad-a688-8132ecc5cfbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662829809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.662829809
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.1342038290
Short name T702
Test name
Test status
Simulation time 4335075886 ps
CPU time 26.16 seconds
Started Jul 27 05:38:38 PM PDT 24
Finished Jul 27 05:39:04 PM PDT 24
Peak memory 200840 kb
Host smart-62dece02-68ab-4df7-9c88-991281365074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342038290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.1342038290
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.1132543296
Short name T545
Test name
Test status
Simulation time 13373914225 ps
CPU time 119.22 seconds
Started Jul 27 05:38:35 PM PDT 24
Finished Jul 27 05:40:34 PM PDT 24
Peak memory 217268 kb
Host smart-32aeefb6-2c4d-4f51-ac72-9447f3921583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1132543296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.1132543296
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.424236889
Short name T501
Test name
Test status
Simulation time 66644922 ps
CPU time 0.96 seconds
Started Jul 27 05:38:36 PM PDT 24
Finished Jul 27 05:38:37 PM PDT 24
Peak memory 200456 kb
Host smart-63760210-d7e1-4254-aa77-b5a624d9cd5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424236889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.424236889
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.446290802
Short name T307
Test name
Test status
Simulation time 27223121 ps
CPU time 0.88 seconds
Started Jul 27 05:37:41 PM PDT 24
Finished Jul 27 05:37:42 PM PDT 24
Peak memory 200432 kb
Host smart-2965e069-57b6-425f-a2f7-cd1b4b39d8bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446290802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_alert_test.446290802
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1561315054
Short name T79
Test name
Test status
Simulation time 93950821 ps
CPU time 1.11 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:39 PM PDT 24
Peak memory 200488 kb
Host smart-54fd8e25-3ec2-4219-9578-3db4338f91dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561315054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1561315054
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2064447772
Short name T291
Test name
Test status
Simulation time 16590272 ps
CPU time 0.74 seconds
Started Jul 27 05:37:37 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 200344 kb
Host smart-2f3147a5-c7b4-44a4-9341-e5126501c2e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064447772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2064447772
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.3865783074
Short name T388
Test name
Test status
Simulation time 79638432 ps
CPU time 1.09 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:40 PM PDT 24
Peak memory 200436 kb
Host smart-90b89645-ac41-4a17-84ee-53cc7e6e0139
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865783074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.3865783074
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.4255175302
Short name T193
Test name
Test status
Simulation time 16256998 ps
CPU time 0.79 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:40 PM PDT 24
Peak memory 200464 kb
Host smart-87a2aa2d-f8de-4a82-9e74-e251dda51ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255175302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.4255175302
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.2926304565
Short name T568
Test name
Test status
Simulation time 2241130284 ps
CPU time 12.6 seconds
Started Jul 27 05:37:37 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200784 kb
Host smart-c9722234-de8a-4a79-81d1-7bb974e15c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926304565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2926304565
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.3644805881
Short name T268
Test name
Test status
Simulation time 1258923203 ps
CPU time 5.58 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 200492 kb
Host smart-5b6738bb-68f0-4def-b08b-2a3776b0e476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644805881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.3644805881
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3866512325
Short name T165
Test name
Test status
Simulation time 27527972 ps
CPU time 0.92 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:39 PM PDT 24
Peak memory 200456 kb
Host smart-5860c2f0-42ed-4368-bc6f-035fe5b3cf44
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866512325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.3866512325
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.274602476
Short name T631
Test name
Test status
Simulation time 19461592 ps
CPU time 0.8 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:40 PM PDT 24
Peak memory 200456 kb
Host smart-793e58b7-b783-414f-8b81-f3a1605884ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274602476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_clk_byp_req_intersig_mubi.274602476
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3891969470
Short name T408
Test name
Test status
Simulation time 67577433 ps
CPU time 1.06 seconds
Started Jul 27 05:37:36 PM PDT 24
Finished Jul 27 05:37:37 PM PDT 24
Peak memory 200468 kb
Host smart-18ea68f3-821b-4b1d-adfb-c219ed02fa96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891969470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.3891969470
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.3181748310
Short name T168
Test name
Test status
Simulation time 17501904 ps
CPU time 0.77 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:39 PM PDT 24
Peak memory 200464 kb
Host smart-f9749006-e21c-49aa-b4dc-50605d84a2c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181748310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3181748310
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.3506897925
Short name T315
Test name
Test status
Simulation time 1004055547 ps
CPU time 3.63 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:42 PM PDT 24
Peak memory 200588 kb
Host smart-7036be86-1a46-41a8-b032-e8ec355c6cf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506897925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3506897925
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.1056914701
Short name T42
Test name
Test status
Simulation time 28394479 ps
CPU time 0.85 seconds
Started Jul 27 05:37:40 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 200412 kb
Host smart-0191099a-ffaa-4052-90b4-7a07ed2a07e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056914701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1056914701
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.3536517751
Short name T661
Test name
Test status
Simulation time 2311696725 ps
CPU time 10.78 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 200856 kb
Host smart-c801dff8-1040-4a71-8482-cf19b6a62b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536517751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.3536517751
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.3519569656
Short name T496
Test name
Test status
Simulation time 31809174 ps
CPU time 0.84 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 200456 kb
Host smart-bc3f9815-1bb9-4b8f-90da-12dffb95b38c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519569656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3519569656
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1288530484
Short name T592
Test name
Test status
Simulation time 42033241 ps
CPU time 0.91 seconds
Started Jul 27 05:38:52 PM PDT 24
Finished Jul 27 05:38:53 PM PDT 24
Peak memory 200448 kb
Host smart-91a233ec-c44c-42a7-b2a3-6dc8c112ee7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288530484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1288530484
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.3656307209
Short name T242
Test name
Test status
Simulation time 13814598 ps
CPU time 0.74 seconds
Started Jul 27 05:38:44 PM PDT 24
Finished Jul 27 05:38:45 PM PDT 24
Peak memory 200456 kb
Host smart-662df07a-6796-454c-b35f-84c5dd84e9b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656307209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.3656307209
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.3485041859
Short name T756
Test name
Test status
Simulation time 24981800 ps
CPU time 0.74 seconds
Started Jul 27 05:38:43 PM PDT 24
Finished Jul 27 05:38:44 PM PDT 24
Peak memory 200360 kb
Host smart-8525619f-8ae0-4e5f-9627-37cfe9f17221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485041859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.3485041859
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.648140675
Short name T303
Test name
Test status
Simulation time 201591580 ps
CPU time 1.36 seconds
Started Jul 27 05:38:41 PM PDT 24
Finished Jul 27 05:38:43 PM PDT 24
Peak memory 200420 kb
Host smart-4c4efe79-fa66-4db3-a91b-05e83de26f6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648140675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_div_intersig_mubi.648140675
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.161021422
Short name T598
Test name
Test status
Simulation time 15702229 ps
CPU time 0.81 seconds
Started Jul 27 05:38:43 PM PDT 24
Finished Jul 27 05:38:44 PM PDT 24
Peak memory 200376 kb
Host smart-b8e9fc43-bc0b-4498-81d7-5d8207c6dbbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161021422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.161021422
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.296715977
Short name T499
Test name
Test status
Simulation time 1644754486 ps
CPU time 9.53 seconds
Started Jul 27 05:38:46 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200396 kb
Host smart-a7322f2a-7062-4844-8f9e-fbf6e9735172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296715977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.296715977
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.378158462
Short name T665
Test name
Test status
Simulation time 1359559062 ps
CPU time 6.03 seconds
Started Jul 27 05:38:47 PM PDT 24
Finished Jul 27 05:38:53 PM PDT 24
Peak memory 200516 kb
Host smart-c58c37de-1bda-426b-aeff-3b5291066b3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378158462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_ti
meout.378158462
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2115345094
Short name T604
Test name
Test status
Simulation time 88004956 ps
CPU time 1.12 seconds
Started Jul 27 05:38:48 PM PDT 24
Finished Jul 27 05:38:49 PM PDT 24
Peak memory 200472 kb
Host smart-65bf23e4-f292-4f9e-8334-a6e4c68983e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115345094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.2115345094
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.561320954
Short name T770
Test name
Test status
Simulation time 18924269 ps
CPU time 0.77 seconds
Started Jul 27 05:38:48 PM PDT 24
Finished Jul 27 05:38:49 PM PDT 24
Peak memory 200476 kb
Host smart-67336c85-3ad8-4ba8-889a-9fabed0e751d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561320954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_clk_byp_req_intersig_mubi.561320954
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.2327611624
Short name T224
Test name
Test status
Simulation time 194286498 ps
CPU time 1.52 seconds
Started Jul 27 05:38:48 PM PDT 24
Finished Jul 27 05:38:49 PM PDT 24
Peak memory 200468 kb
Host smart-c26a3faa-d9b7-43fe-8c36-0dc964ed0f96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327611624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.2327611624
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.2024708368
Short name T321
Test name
Test status
Simulation time 40686319 ps
CPU time 0.78 seconds
Started Jul 27 05:38:51 PM PDT 24
Finished Jul 27 05:38:52 PM PDT 24
Peak memory 200388 kb
Host smart-17d3239d-9e6b-43e7-bdae-6b6d94652b96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024708368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2024708368
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.998119847
Short name T698
Test name
Test status
Simulation time 759494541 ps
CPU time 4.58 seconds
Started Jul 27 05:38:48 PM PDT 24
Finished Jul 27 05:38:52 PM PDT 24
Peak memory 200672 kb
Host smart-524f6cdf-af9a-4d3d-a7f7-2604a56f286d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998119847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.998119847
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.3977973525
Short name T401
Test name
Test status
Simulation time 41155949 ps
CPU time 0.88 seconds
Started Jul 27 05:38:52 PM PDT 24
Finished Jul 27 05:38:53 PM PDT 24
Peak memory 200392 kb
Host smart-95815f6c-66d9-4f1e-9289-f1cc3b5e9640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977973525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3977973525
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.19686227
Short name T183
Test name
Test status
Simulation time 48147766 ps
CPU time 0.94 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:38:46 PM PDT 24
Peak memory 200476 kb
Host smart-3c1ca6b5-f2d6-4aed-81fd-a8e5c69a1024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19686227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_stress_all.19686227
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.2283266104
Short name T56
Test name
Test status
Simulation time 21411174375 ps
CPU time 388 seconds
Started Jul 27 05:38:52 PM PDT 24
Finished Jul 27 05:45:21 PM PDT 24
Peak memory 216892 kb
Host smart-53059381-df15-4631-b203-662507da1d44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2283266104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2283266104
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.3999214519
Short name T561
Test name
Test status
Simulation time 22459968 ps
CPU time 0.74 seconds
Started Jul 27 05:38:46 PM PDT 24
Finished Jul 27 05:38:47 PM PDT 24
Peak memory 200460 kb
Host smart-b224327b-7d4d-47fe-a360-2f6b4057e071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999214519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.3999214519
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1545056710
Short name T403
Test name
Test status
Simulation time 240940171 ps
CPU time 1.44 seconds
Started Jul 27 05:38:54 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200468 kb
Host smart-a8f0e3b6-d753-4a24-9e96-8158453a11a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545056710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1545056710
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.818202606
Short name T75
Test name
Test status
Simulation time 52122468 ps
CPU time 0.87 seconds
Started Jul 27 05:38:43 PM PDT 24
Finished Jul 27 05:38:44 PM PDT 24
Peak memory 200492 kb
Host smart-e72133b3-dfc9-4f45-9c24-4c25e5af06f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818202606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.818202606
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.876500235
Short name T158
Test name
Test status
Simulation time 19015367 ps
CPU time 0.72 seconds
Started Jul 27 05:38:51 PM PDT 24
Finished Jul 27 05:38:52 PM PDT 24
Peak memory 200364 kb
Host smart-fca1d01c-1844-4268-be6b-82084261faae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876500235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.876500235
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.3036999341
Short name T364
Test name
Test status
Simulation time 72095103 ps
CPU time 1.08 seconds
Started Jul 27 05:38:47 PM PDT 24
Finished Jul 27 05:38:48 PM PDT 24
Peak memory 200400 kb
Host smart-b894d90c-e238-453f-8b77-8854a730aadd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036999341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.3036999341
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.3343542271
Short name T583
Test name
Test status
Simulation time 28853288 ps
CPU time 0.82 seconds
Started Jul 27 05:38:44 PM PDT 24
Finished Jul 27 05:38:45 PM PDT 24
Peak memory 200392 kb
Host smart-483aa09f-14ef-4412-b0e2-b4b59fa51b11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343542271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3343542271
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.695310556
Short name T371
Test name
Test status
Simulation time 2481397414 ps
CPU time 20.02 seconds
Started Jul 27 05:38:44 PM PDT 24
Finished Jul 27 05:39:04 PM PDT 24
Peak memory 200768 kb
Host smart-8943dda8-100f-4d5e-b05c-ddb70abae4ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695310556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.695310556
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.1943013240
Short name T786
Test name
Test status
Simulation time 393528016 ps
CPU time 2.09 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:38:47 PM PDT 24
Peak memory 200600 kb
Host smart-97da215e-99e0-484c-89a8-49103837fcff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943013240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.1943013240
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1742498407
Short name T189
Test name
Test status
Simulation time 228788073 ps
CPU time 1.34 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:38:46 PM PDT 24
Peak memory 200472 kb
Host smart-e737e813-0a69-4b3e-a75e-d367e2f729e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742498407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1742498407
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.4119454575
Short name T485
Test name
Test status
Simulation time 94772796 ps
CPU time 1.09 seconds
Started Jul 27 05:38:42 PM PDT 24
Finished Jul 27 05:38:44 PM PDT 24
Peak memory 200476 kb
Host smart-45faf304-3e82-44c6-a636-43a2568b8c57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119454575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.4119454575
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.3451466214
Short name T442
Test name
Test status
Simulation time 99569743 ps
CPU time 1.1 seconds
Started Jul 27 05:38:51 PM PDT 24
Finished Jul 27 05:38:52 PM PDT 24
Peak memory 200452 kb
Host smart-0228c9ca-5aad-4d9f-a97f-c4732bce6869
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451466214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.3451466214
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.801263292
Short name T216
Test name
Test status
Simulation time 18468218 ps
CPU time 0.85 seconds
Started Jul 27 05:38:52 PM PDT 24
Finished Jul 27 05:38:53 PM PDT 24
Peak memory 200436 kb
Host smart-004305e8-3e76-48c6-b674-96be9c55e562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801263292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.801263292
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.964019619
Short name T452
Test name
Test status
Simulation time 1094244772 ps
CPU time 6.58 seconds
Started Jul 27 05:38:44 PM PDT 24
Finished Jul 27 05:38:51 PM PDT 24
Peak memory 200588 kb
Host smart-2ae62b1d-59a7-420d-b8fc-e5a3554d5256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964019619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.964019619
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.1018325870
Short name T287
Test name
Test status
Simulation time 20055201 ps
CPU time 0.84 seconds
Started Jul 27 05:38:43 PM PDT 24
Finished Jul 27 05:38:44 PM PDT 24
Peak memory 200372 kb
Host smart-050594a5-8b8b-4f1d-905a-2b921ce625b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018325870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.1018325870
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.691990574
Short name T675
Test name
Test status
Simulation time 6700065655 ps
CPU time 38.01 seconds
Started Jul 27 05:38:45 PM PDT 24
Finished Jul 27 05:39:23 PM PDT 24
Peak memory 200840 kb
Host smart-f5a6498f-55a0-437f-8906-8a539bce738d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691990574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.691990574
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.3419003135
Short name T477
Test name
Test status
Simulation time 87031256890 ps
CPU time 621.42 seconds
Started Jul 27 05:38:48 PM PDT 24
Finished Jul 27 05:49:09 PM PDT 24
Peak memory 213064 kb
Host smart-fdd58f9f-b76a-407c-9170-7b5c96728c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3419003135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3419003135
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.1012618216
Short name T83
Test name
Test status
Simulation time 58038197 ps
CPU time 1.04 seconds
Started Jul 27 05:38:46 PM PDT 24
Finished Jul 27 05:38:47 PM PDT 24
Peak memory 200356 kb
Host smart-15b06e65-11b5-481a-8414-67322e20b749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012618216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1012618216
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.1120829598
Short name T475
Test name
Test status
Simulation time 12968255 ps
CPU time 0.75 seconds
Started Jul 27 05:38:53 PM PDT 24
Finished Jul 27 05:38:54 PM PDT 24
Peak memory 200468 kb
Host smart-42802f3b-d2a5-4bd7-b7e5-762731faf8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120829598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.1120829598
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3005310980
Short name T618
Test name
Test status
Simulation time 39634856 ps
CPU time 0.86 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:57 PM PDT 24
Peak memory 200500 kb
Host smart-e9d8d4c6-dc0c-4544-a5bf-5c442d829dea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005310980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3005310980
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.1352236416
Short name T536
Test name
Test status
Simulation time 14471015 ps
CPU time 0.77 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 199644 kb
Host smart-1b2d06e6-e9a0-4199-9ff5-2e7eb026cffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352236416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1352236416
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2717577098
Short name T111
Test name
Test status
Simulation time 124774042 ps
CPU time 1.22 seconds
Started Jul 27 05:38:59 PM PDT 24
Finished Jul 27 05:39:01 PM PDT 24
Peak memory 200388 kb
Host smart-480e8ce1-8b91-4d61-9b2d-fa344f826731
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717577098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2717577098
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.2753935668
Short name T481
Test name
Test status
Simulation time 24129554 ps
CPU time 0.9 seconds
Started Jul 27 05:38:52 PM PDT 24
Finished Jul 27 05:38:53 PM PDT 24
Peak memory 200448 kb
Host smart-604a3b16-861d-495c-a799-8d518a5f075b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753935668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2753935668
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.547764169
Short name T469
Test name
Test status
Simulation time 289314621 ps
CPU time 1.65 seconds
Started Jul 27 05:38:58 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200428 kb
Host smart-41bd83aa-0610-404a-90e3-8f3e816e15fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547764169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.547764169
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.2314049156
Short name T718
Test name
Test status
Simulation time 619419534 ps
CPU time 5.07 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:39:01 PM PDT 24
Peak memory 200556 kb
Host smart-855f52c8-fbf3-46ed-b8cc-4df5ace6352e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314049156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.2314049156
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.104046248
Short name T600
Test name
Test status
Simulation time 16867192 ps
CPU time 0.81 seconds
Started Jul 27 05:38:57 PM PDT 24
Finished Jul 27 05:38:58 PM PDT 24
Peak memory 200368 kb
Host smart-211d10f3-4974-4b38-be96-39e3ba22a57e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104046248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_idle_intersig_mubi.104046248
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.914926892
Short name T705
Test name
Test status
Simulation time 38415450 ps
CPU time 0.82 seconds
Started Jul 27 05:38:59 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200468 kb
Host smart-e2d9635c-c5d0-43af-8d81-4f8fe4294354
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914926892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_clk_byp_req_intersig_mubi.914926892
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.1967170095
Short name T229
Test name
Test status
Simulation time 57815426 ps
CPU time 0.91 seconds
Started Jul 27 05:38:54 PM PDT 24
Finished Jul 27 05:38:55 PM PDT 24
Peak memory 200452 kb
Host smart-00dcbee3-d2ff-4db3-8fc2-5095e2a9ad19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967170095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.1967170095
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.4217079002
Short name T301
Test name
Test status
Simulation time 13797189 ps
CPU time 0.77 seconds
Started Jul 27 05:38:54 PM PDT 24
Finished Jul 27 05:38:54 PM PDT 24
Peak memory 200348 kb
Host smart-62b35698-84f5-42cc-a04a-1e42c48c8248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217079002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.4217079002
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.3826346120
Short name T7
Test name
Test status
Simulation time 448658789 ps
CPU time 2.8 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:59 PM PDT 24
Peak memory 200644 kb
Host smart-f48d0810-2223-4801-a05e-1318c331b2dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826346120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3826346120
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.954332141
Short name T177
Test name
Test status
Simulation time 65568185 ps
CPU time 1.02 seconds
Started Jul 27 05:38:54 PM PDT 24
Finished Jul 27 05:38:55 PM PDT 24
Peak memory 200460 kb
Host smart-a42f7b86-7f28-4e15-8172-bc544954b05c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954332141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.954332141
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.1942311153
Short name T614
Test name
Test status
Simulation time 8476274222 ps
CPU time 33.97 seconds
Started Jul 27 05:38:53 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200840 kb
Host smart-f46ffd38-9a3d-4be9-8780-772c73087409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942311153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.1942311153
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.3530865885
Short name T223
Test name
Test status
Simulation time 55021659 ps
CPU time 0.91 seconds
Started Jul 27 05:39:00 PM PDT 24
Finished Jul 27 05:39:01 PM PDT 24
Peak memory 200456 kb
Host smart-a3f18af9-284a-4986-96a7-053c82dc04a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530865885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3530865885
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.269957472
Short name T263
Test name
Test status
Simulation time 15093039 ps
CPU time 0.73 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:57 PM PDT 24
Peak memory 200472 kb
Host smart-f7843a96-6c04-4424-9f57-f7373c8c8b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269957472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkm
gr_alert_test.269957472
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.4122416053
Short name T74
Test name
Test status
Simulation time 21277132 ps
CPU time 0.88 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200492 kb
Host smart-f154d0a5-13c7-4ac4-8559-f8899640b667
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122416053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.4122416053
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2854212385
Short name T140
Test name
Test status
Simulation time 16475872 ps
CPU time 0.72 seconds
Started Jul 27 05:38:59 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200380 kb
Host smart-5dcc103b-6eee-473b-97b5-8c069a305e5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854212385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2854212385
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.1216593893
Short name T306
Test name
Test status
Simulation time 19305506 ps
CPU time 0.79 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200432 kb
Host smart-be3c3eac-8e46-4e40-8968-caa158450150
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216593893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.1216593893
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.2767494907
Short name T237
Test name
Test status
Simulation time 26755255 ps
CPU time 0.79 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:57 PM PDT 24
Peak memory 200464 kb
Host smart-bf4df103-eebd-4138-8bc4-544fde6c4b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767494907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2767494907
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.2602511680
Short name T527
Test name
Test status
Simulation time 677217284 ps
CPU time 5.74 seconds
Started Jul 27 05:38:53 PM PDT 24
Finished Jul 27 05:38:59 PM PDT 24
Peak memory 200540 kb
Host smart-c4e3b074-bcb5-46bc-9275-0da426a0b7e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602511680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2602511680
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.2725312659
Short name T437
Test name
Test status
Simulation time 1599488890 ps
CPU time 6.56 seconds
Started Jul 27 05:38:53 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200560 kb
Host smart-b8d4452a-7ff9-4e2b-88d3-ffcd898f846d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725312659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.2725312659
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.2897388064
Short name T239
Test name
Test status
Simulation time 20427626 ps
CPU time 0.84 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:57 PM PDT 24
Peak memory 200416 kb
Host smart-467c3646-7ca9-4d3a-9538-86778bcec861
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897388064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.2897388064
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.565351094
Short name T513
Test name
Test status
Simulation time 46119129 ps
CPU time 0.85 seconds
Started Jul 27 05:38:54 PM PDT 24
Finished Jul 27 05:38:55 PM PDT 24
Peak memory 200492 kb
Host smart-0e33bdf8-17db-4cbf-ab35-d5f9c4dedb9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565351094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.clkmgr_lc_clk_byp_req_intersig_mubi.565351094
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.961693747
Short name T406
Test name
Test status
Simulation time 206538871 ps
CPU time 1.37 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:58 PM PDT 24
Peak memory 200492 kb
Host smart-00a65a6e-902d-41f9-9dd7-9bfc4594443d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961693747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.clkmgr_lc_ctrl_intersig_mubi.961693747
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.244517827
Short name T275
Test name
Test status
Simulation time 39493485 ps
CPU time 0.8 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200348 kb
Host smart-68f2ca0a-eb53-4e23-a9a1-897267ef861c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244517827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.244517827
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.2152787656
Short name T683
Test name
Test status
Simulation time 1052371196 ps
CPU time 4.1 seconds
Started Jul 27 05:39:01 PM PDT 24
Finished Jul 27 05:39:05 PM PDT 24
Peak memory 200560 kb
Host smart-06f578d3-d5c3-4036-977a-48e57131988e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152787656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2152787656
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.4183425730
Short name T314
Test name
Test status
Simulation time 20064620 ps
CPU time 0.84 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200416 kb
Host smart-c5e399d9-bfe5-4951-975b-a7bd2b8e6e7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183425730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4183425730
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.827863611
Short name T106
Test name
Test status
Simulation time 1681884056 ps
CPU time 12.72 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200796 kb
Host smart-ca247f89-268b-4881-a3c2-73547d7c77f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827863611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.827863611
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.2748228712
Short name T220
Test name
Test status
Simulation time 185464675 ps
CPU time 1.43 seconds
Started Jul 27 05:38:53 PM PDT 24
Finished Jul 27 05:38:55 PM PDT 24
Peak memory 200444 kb
Host smart-59c1721a-3cc8-46bb-b552-50c46faffaff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748228712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2748228712
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.404889020
Short name T574
Test name
Test status
Simulation time 246031840 ps
CPU time 1.64 seconds
Started Jul 27 05:39:02 PM PDT 24
Finished Jul 27 05:39:04 PM PDT 24
Peak memory 200464 kb
Host smart-247c5936-fe6a-473b-a89f-4929697e701a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404889020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkm
gr_alert_test.404889020
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3662991062
Short name T642
Test name
Test status
Simulation time 86495821 ps
CPU time 0.98 seconds
Started Jul 27 05:39:00 PM PDT 24
Finished Jul 27 05:39:01 PM PDT 24
Peak memory 200484 kb
Host smart-a3476a92-98d6-48da-88da-60880c2dbcec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662991062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.3662991062
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.143751282
Short name T537
Test name
Test status
Simulation time 123694046 ps
CPU time 0.99 seconds
Started Jul 27 05:38:53 PM PDT 24
Finished Jul 27 05:38:54 PM PDT 24
Peak memory 199668 kb
Host smart-bbe1062d-f261-4ceb-aae3-6e375a464d36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143751282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.143751282
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.2904831111
Short name T387
Test name
Test status
Simulation time 15409602 ps
CPU time 0.8 seconds
Started Jul 27 05:38:58 PM PDT 24
Finished Jul 27 05:38:59 PM PDT 24
Peak memory 200472 kb
Host smart-d9bc6061-0ccc-4b4a-8152-20baa4671a98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904831111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.2904831111
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.2015653146
Short name T495
Test name
Test status
Simulation time 42200251 ps
CPU time 0.85 seconds
Started Jul 27 05:38:57 PM PDT 24
Finished Jul 27 05:38:58 PM PDT 24
Peak memory 200468 kb
Host smart-518809be-4af8-4cfb-8e5d-1c49985444d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015653146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.2015653146
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.1634009492
Short name T232
Test name
Test status
Simulation time 1640484010 ps
CPU time 9.59 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:39:04 PM PDT 24
Peak memory 200528 kb
Host smart-3562fead-0ea7-4d6f-a73a-cc92c068b91b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634009492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.1634009492
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.507789710
Short name T813
Test name
Test status
Simulation time 1000698853 ps
CPU time 4.76 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200584 kb
Host smart-349db1ac-141a-499f-92be-ed9440f92925
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507789710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti
meout.507789710
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.2865627647
Short name T687
Test name
Test status
Simulation time 52664056 ps
CPU time 0.9 seconds
Started Jul 27 05:38:56 PM PDT 24
Finished Jul 27 05:38:57 PM PDT 24
Peak memory 200412 kb
Host smart-a607e064-d5e7-41f2-b88f-2a5c27dbc070
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865627647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.2865627647
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.486407205
Short name T803
Test name
Test status
Simulation time 62307448 ps
CPU time 0.89 seconds
Started Jul 27 05:38:52 PM PDT 24
Finished Jul 27 05:38:53 PM PDT 24
Peak memory 200424 kb
Host smart-f5a425cc-ae7c-4b7f-ac81-5ce0a426143e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486407205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_clk_byp_req_intersig_mubi.486407205
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2448090887
Short name T805
Test name
Test status
Simulation time 91702477 ps
CPU time 1.08 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200488 kb
Host smart-c8791558-aac7-4460-8300-72b98229c622
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448090887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.2448090887
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.2850303812
Short name T139
Test name
Test status
Simulation time 16065552 ps
CPU time 0.83 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200496 kb
Host smart-bbece4f5-ec65-4b38-a6b1-2c55966d7473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850303812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2850303812
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.1371531668
Short name T146
Test name
Test status
Simulation time 1433043667 ps
CPU time 8.19 seconds
Started Jul 27 05:39:03 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200640 kb
Host smart-48ae1d71-d113-4d54-b608-73ad16377356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371531668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1371531668
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.57787418
Short name T132
Test name
Test status
Simulation time 22093693 ps
CPU time 0.85 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200436 kb
Host smart-75735f70-257d-448a-a438-730fb656bf6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57787418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.57787418
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.3634358072
Short name T130
Test name
Test status
Simulation time 53875455 ps
CPU time 1.2 seconds
Started Jul 27 05:38:57 PM PDT 24
Finished Jul 27 05:38:59 PM PDT 24
Peak memory 200488 kb
Host smart-107e1085-a954-4370-a853-b7db193c5d4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634358072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.3634358072
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.3495039225
Short name T708
Test name
Test status
Simulation time 56250889 ps
CPU time 1.05 seconds
Started Jul 27 05:38:53 PM PDT 24
Finished Jul 27 05:38:55 PM PDT 24
Peak memory 200384 kb
Host smart-e56db12a-cbf6-44cc-ae4d-8c7cbe06753f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495039225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.3495039225
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.2080052065
Short name T138
Test name
Test status
Simulation time 15692208 ps
CPU time 0.8 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200432 kb
Host smart-f07c8f70-29cf-46a8-acc9-38115e9f3a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080052065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.2080052065
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.445275414
Short name T254
Test name
Test status
Simulation time 40716790 ps
CPU time 0.87 seconds
Started Jul 27 05:39:11 PM PDT 24
Finished Jul 27 05:39:12 PM PDT 24
Peak memory 200452 kb
Host smart-ea4ea757-8007-4afc-8d90-dbe12bb909e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445275414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.445275414
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.692717239
Short name T39
Test name
Test status
Simulation time 16639689 ps
CPU time 0.76 seconds
Started Jul 27 05:39:03 PM PDT 24
Finished Jul 27 05:39:04 PM PDT 24
Peak memory 200360 kb
Host smart-07001d58-c176-487d-abed-3c8a6fdd4f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692717239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.692717239
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.51353795
Short name T389
Test name
Test status
Simulation time 89991760 ps
CPU time 1.02 seconds
Started Jul 27 05:39:11 PM PDT 24
Finished Jul 27 05:39:12 PM PDT 24
Peak memory 200428 kb
Host smart-27a05577-c5d2-4a5a-a142-ededa501c9c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51353795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.clkmgr_div_intersig_mubi.51353795
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.355668153
Short name T172
Test name
Test status
Simulation time 14753562 ps
CPU time 0.71 seconds
Started Jul 27 05:39:01 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 200428 kb
Host smart-f0e6dc8b-6ec8-4e75-9d85-0d18c8735d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355668153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.355668153
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.1617372329
Short name T107
Test name
Test status
Simulation time 596444741 ps
CPU time 3.16 seconds
Started Jul 27 05:39:03 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200184 kb
Host smart-ca59fd70-a3fa-41c7-9254-b96dbe1d81c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617372329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1617372329
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.1541677835
Short name T288
Test name
Test status
Simulation time 1939546471 ps
CPU time 10.04 seconds
Started Jul 27 05:39:01 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200520 kb
Host smart-6ae3e4f4-872a-4e7b-8bd7-fa0664f262e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541677835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.1541677835
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.1795837239
Short name T534
Test name
Test status
Simulation time 41154685 ps
CPU time 0.88 seconds
Started Jul 27 05:38:59 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200444 kb
Host smart-179c1cdc-6996-4bfb-9d8b-1db81f3a6911
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795837239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.1795837239
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2145050516
Short name T457
Test name
Test status
Simulation time 71232983 ps
CPU time 0.98 seconds
Started Jul 27 05:38:55 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 200472 kb
Host smart-b2e35655-f9d6-4207-b9f5-b62dc39dfbb9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145050516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2145050516
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.2166476149
Short name T560
Test name
Test status
Simulation time 25073871 ps
CPU time 0.89 seconds
Started Jul 27 05:39:01 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 200404 kb
Host smart-b9806ddc-28cc-4fb8-a169-b9ba9f2afb5c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166476149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.2166476149
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.1489358397
Short name T88
Test name
Test status
Simulation time 17024099 ps
CPU time 0.74 seconds
Started Jul 27 05:39:05 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200380 kb
Host smart-93ab3b8e-ba87-4e1f-8f45-ed4b0895959e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489358397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1489358397
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.3684892935
Short name T753
Test name
Test status
Simulation time 325408922 ps
CPU time 2.43 seconds
Started Jul 27 05:39:02 PM PDT 24
Finished Jul 27 05:39:05 PM PDT 24
Peak memory 200464 kb
Host smart-022af18c-c7c2-403e-bfe0-e7818e0f7a51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684892935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3684892935
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.573838871
Short name T680
Test name
Test status
Simulation time 100651469 ps
CPU time 1.16 seconds
Started Jul 27 05:38:59 PM PDT 24
Finished Jul 27 05:39:01 PM PDT 24
Peak memory 200408 kb
Host smart-231ef344-06c4-4bb9-bb0a-0f76c0092e81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573838871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.573838871
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.4253194144
Short name T394
Test name
Test status
Simulation time 7933355426 ps
CPU time 31.64 seconds
Started Jul 27 05:39:03 PM PDT 24
Finished Jul 27 05:39:35 PM PDT 24
Peak memory 200808 kb
Host smart-a871f7ac-1e60-4c6f-9c7b-8c44c5dffaf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253194144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.4253194144
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.2241143281
Short name T297
Test name
Test status
Simulation time 47327946 ps
CPU time 0.98 seconds
Started Jul 27 05:38:58 PM PDT 24
Finished Jul 27 05:38:59 PM PDT 24
Peak memory 200460 kb
Host smart-db75633c-c2e7-4371-a1c1-903636b5ee90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241143281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.2241143281
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3942810864
Short name T341
Test name
Test status
Simulation time 51943022 ps
CPU time 0.87 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 200428 kb
Host smart-20465278-71eb-47cf-9423-48f4077ef25d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942810864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3942810864
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.740006850
Short name T646
Test name
Test status
Simulation time 19974904 ps
CPU time 0.81 seconds
Started Jul 27 05:39:02 PM PDT 24
Finished Jul 27 05:39:03 PM PDT 24
Peak memory 200436 kb
Host smart-7a42d6de-4ecb-4d53-a5c2-8a8bd38a197d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740006850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.740006850
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.1980482985
Short name T40
Test name
Test status
Simulation time 39506324 ps
CPU time 0.78 seconds
Started Jul 27 05:38:59 PM PDT 24
Finished Jul 27 05:38:59 PM PDT 24
Peak memory 199684 kb
Host smart-ef598b91-97b7-4521-9c51-8ca5d81488ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980482985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1980482985
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.63570291
Short name T36
Test name
Test status
Simulation time 95001055 ps
CPU time 1.17 seconds
Started Jul 27 05:38:59 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 200416 kb
Host smart-94ff0e06-8d0b-42b1-b3fa-2400dc934d1c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63570291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.clkmgr_div_intersig_mubi.63570291
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.3419244410
Short name T749
Test name
Test status
Simulation time 20320197 ps
CPU time 0.79 seconds
Started Jul 27 05:38:57 PM PDT 24
Finished Jul 27 05:38:58 PM PDT 24
Peak memory 200504 kb
Host smart-f39ebc01-f8fb-4435-b2c1-f2b3bbefaad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419244410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3419244410
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.2949905644
Short name T644
Test name
Test status
Simulation time 676286109 ps
CPU time 5.72 seconds
Started Jul 27 05:39:00 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200524 kb
Host smart-b4e0e11a-d4d3-41a8-bba0-cb8ae5c3568e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949905644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2949905644
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.3199319227
Short name T610
Test name
Test status
Simulation time 862335022 ps
CPU time 7.19 seconds
Started Jul 27 05:38:58 PM PDT 24
Finished Jul 27 05:39:05 PM PDT 24
Peak memory 200572 kb
Host smart-8a45d693-1d7b-42ce-9662-4d386ab1b659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199319227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.3199319227
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.2884523326
Short name T416
Test name
Test status
Simulation time 140117688 ps
CPU time 1.23 seconds
Started Jul 27 05:39:01 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 200464 kb
Host smart-29948931-b0a7-4088-bde4-583577ce7ed2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884523326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.2884523326
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.98174445
Short name T649
Test name
Test status
Simulation time 234759043 ps
CPU time 1.51 seconds
Started Jul 27 05:39:00 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 200452 kb
Host smart-cc76f553-2381-4bb5-8f57-b19609d64099
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98174445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_lc_clk_byp_req_intersig_mubi.98174445
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.721181370
Short name T305
Test name
Test status
Simulation time 32148814 ps
CPU time 0.81 seconds
Started Jul 27 05:39:02 PM PDT 24
Finished Jul 27 05:39:03 PM PDT 24
Peak memory 200428 kb
Host smart-cf6a52e3-9ec8-481f-9b7e-b32241147c4c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721181370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_ctrl_intersig_mubi.721181370
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.4155664252
Short name T215
Test name
Test status
Simulation time 43992951 ps
CPU time 0.86 seconds
Started Jul 27 05:39:02 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 200452 kb
Host smart-10495171-febc-4a62-8b3b-de669afe7b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155664252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.4155664252
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.3663427596
Short name T208
Test name
Test status
Simulation time 1439677401 ps
CPU time 5.58 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:13 PM PDT 24
Peak memory 200600 kb
Host smart-c37f4689-8874-4bcd-a9cc-1f2847c47d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663427596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.3663427596
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.257354853
Short name T453
Test name
Test status
Simulation time 19275410 ps
CPU time 0.85 seconds
Started Jul 27 05:39:01 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 200408 kb
Host smart-8f337816-f390-4523-9346-32a6b1fa1b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257354853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.257354853
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.1545496327
Short name T733
Test name
Test status
Simulation time 3968903479 ps
CPU time 29.78 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:39 PM PDT 24
Peak memory 200836 kb
Host smart-e6b0d953-1fa5-45cf-8aa8-29fb9505845e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545496327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.1545496327
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1443801530
Short name T601
Test name
Test status
Simulation time 124281782 ps
CPU time 1.3 seconds
Started Jul 27 05:39:03 PM PDT 24
Finished Jul 27 05:39:04 PM PDT 24
Peak memory 200156 kb
Host smart-58635866-92cc-45c0-885f-3855ebff16b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443801530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1443801530
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.35229875
Short name T265
Test name
Test status
Simulation time 17934556 ps
CPU time 0.83 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 200472 kb
Host smart-3bb0277e-82c2-4605-a471-f742e07823ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35229875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmg
r_alert_test.35229875
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.3433591357
Short name T71
Test name
Test status
Simulation time 62397306 ps
CPU time 1 seconds
Started Jul 27 05:39:10 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200476 kb
Host smart-3b2e9272-224f-4373-819a-b125fd4793c3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433591357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.3433591357
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.1812894625
Short name T565
Test name
Test status
Simulation time 33600408 ps
CPU time 0.73 seconds
Started Jul 27 05:39:10 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 199664 kb
Host smart-6b811de5-c063-46e8-a42c-86ad1569042f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812894625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1812894625
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.3197051989
Short name T512
Test name
Test status
Simulation time 53175999 ps
CPU time 0.97 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 200452 kb
Host smart-da4d52bb-fb00-4896-a1ac-41eed3ef289a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197051989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.3197051989
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.554707901
Short name T535
Test name
Test status
Simulation time 59657640 ps
CPU time 0.95 seconds
Started Jul 27 05:39:05 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200464 kb
Host smart-2d8857dd-856e-4046-b8af-1313eab3d9da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554707901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.554707901
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.451111608
Short name T108
Test name
Test status
Simulation time 2375199186 ps
CPU time 10.89 seconds
Started Jul 27 05:39:05 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200752 kb
Host smart-5d5a709d-1118-4035-bd4a-1bd8b6ace38c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451111608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.451111608
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.3648376531
Short name T446
Test name
Test status
Simulation time 1178671032 ps
CPU time 4.18 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:12 PM PDT 24
Peak memory 200580 kb
Host smart-5c3d4cd5-754f-4a80-b0c4-2e2ffdcb3ef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648376531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.3648376531
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.123243216
Short name T289
Test name
Test status
Simulation time 19914825 ps
CPU time 0.82 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200468 kb
Host smart-0331881b-c96c-41a8-a139-cef47aac070b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123243216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.clkmgr_idle_intersig_mubi.123243216
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.704713057
Short name T741
Test name
Test status
Simulation time 26822182 ps
CPU time 0.95 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200448 kb
Host smart-7040501c-6c65-4007-8673-856ac71bfd71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704713057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.clkmgr_lc_clk_byp_req_intersig_mubi.704713057
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1306376280
Short name T350
Test name
Test status
Simulation time 55045281 ps
CPU time 0.87 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200440 kb
Host smart-f07e1604-7d6e-4803-92c1-b3ce6e9a57ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306376280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.1306376280
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.3155673285
Short name T171
Test name
Test status
Simulation time 47482902 ps
CPU time 0.89 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200380 kb
Host smart-4c297188-1f3c-48ce-926b-65cfb0e33c2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155673285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3155673285
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1409211235
Short name T688
Test name
Test status
Simulation time 385575806 ps
CPU time 1.77 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200412 kb
Host smart-dc1207fa-c285-453c-8f51-7297abed9865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409211235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1409211235
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.685365005
Short name T760
Test name
Test status
Simulation time 160661553 ps
CPU time 1.22 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200356 kb
Host smart-4d304252-f889-47e7-a25e-80a8e61cc9a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685365005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.685365005
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.4163017892
Short name T393
Test name
Test status
Simulation time 6894428066 ps
CPU time 28.19 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:34 PM PDT 24
Peak memory 200780 kb
Host smart-1c185754-aa78-47d3-ad83-2a229bdee5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163017892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.4163017892
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.650353466
Short name T340
Test name
Test status
Simulation time 25206504 ps
CPU time 0.9 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200404 kb
Host smart-370cda52-2b10-45cc-822c-1f213e16c44e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650353466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.650353466
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.326925
Short name T636
Test name
Test status
Simulation time 39492549 ps
CPU time 0.88 seconds
Started Jul 27 05:39:13 PM PDT 24
Finished Jul 27 05:39:14 PM PDT 24
Peak memory 200432 kb
Host smart-fbdf3c9b-6422-4937-b5fe-3ebc0f1826bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_
alert_test.326925
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3109335960
Short name T77
Test name
Test status
Simulation time 92330188 ps
CPU time 1.15 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200480 kb
Host smart-499e35ce-6c62-4f50-b36a-3d8a76aafb13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109335960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.3109335960
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.1555956022
Short name T365
Test name
Test status
Simulation time 23087426 ps
CPU time 0.72 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 199608 kb
Host smart-6ccd4da5-8538-42ee-92f5-f34ea2daf54b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555956022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1555956022
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.2070104266
Short name T204
Test name
Test status
Simulation time 30284391 ps
CPU time 0.82 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 200456 kb
Host smart-46536ab0-9d1b-4c56-9f72-234ab38bfc5a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070104266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.2070104266
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.2523454051
Short name T759
Test name
Test status
Simulation time 45350355 ps
CPU time 0.86 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:10 PM PDT 24
Peak memory 200444 kb
Host smart-fbfa0c8b-2259-4c09-bb30-eda582b760b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523454051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2523454051
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.3113882174
Short name T528
Test name
Test status
Simulation time 609873616 ps
CPU time 3.4 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200524 kb
Host smart-f2904520-7c3f-485f-93ff-61a4ac717132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113882174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.3113882174
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.2424562559
Short name T684
Test name
Test status
Simulation time 984176369 ps
CPU time 5.34 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:12 PM PDT 24
Peak memory 200564 kb
Host smart-62870463-eb72-46b3-8884-70800f28d09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424562559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.2424562559
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3406120459
Short name T420
Test name
Test status
Simulation time 15087195 ps
CPU time 0.8 seconds
Started Jul 27 05:39:04 PM PDT 24
Finished Jul 27 05:39:05 PM PDT 24
Peak memory 200472 kb
Host smart-ede64b8f-4a62-4bb4-99e6-cde8e318ec7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406120459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.3406120459
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.3112297186
Short name T654
Test name
Test status
Simulation time 38446159 ps
CPU time 0.82 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 200484 kb
Host smart-59b55666-3a1a-4996-aa81-b0d2f0a18de7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112297186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.3112297186
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.2532116965
Short name T363
Test name
Test status
Simulation time 25169809 ps
CPU time 0.81 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:10 PM PDT 24
Peak memory 200468 kb
Host smart-c19d8755-0c1f-474c-bb46-26cb7bce5a11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532116965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.2532116965
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.833069828
Short name T429
Test name
Test status
Simulation time 29776403 ps
CPU time 0.76 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200400 kb
Host smart-8854a5df-dd8c-4e06-a772-12cfbb63916d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833069828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.833069828
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.1008440555
Short name T657
Test name
Test status
Simulation time 1188257972 ps
CPU time 6.73 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:13 PM PDT 24
Peak memory 200640 kb
Host smart-3f1a629c-b92b-4d05-b977-5702db9abaa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008440555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1008440555
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2629080534
Short name T300
Test name
Test status
Simulation time 31102676 ps
CPU time 0.92 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200676 kb
Host smart-fd6d2dd8-8ed7-4d21-9a31-d43554334630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629080534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2629080534
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.2541813674
Short name T13
Test name
Test status
Simulation time 8808701018 ps
CPU time 63.66 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:40:11 PM PDT 24
Peak memory 200836 kb
Host smart-2a2c15f4-4b93-4391-af67-517916e8e949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541813674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.2541813674
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.3374948163
Short name T494
Test name
Test status
Simulation time 28890062 ps
CPU time 0.77 seconds
Started Jul 27 05:39:10 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200444 kb
Host smart-51616ff0-c05a-4f48-af6a-ef85afaea7e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374948163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3374948163
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.3602292899
Short name T716
Test name
Test status
Simulation time 44762696 ps
CPU time 0.86 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200472 kb
Host smart-5c7d63e5-5cc5-49c1-b11d-eef9fdbc4431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602292899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.3602292899
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.2518017184
Short name T480
Test name
Test status
Simulation time 98389361 ps
CPU time 1.21 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200680 kb
Host smart-2a593e3b-f7cd-4e46-8bab-9b7f0db3ea93
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518017184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.2518017184
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.3961716380
Short name T249
Test name
Test status
Simulation time 30573599 ps
CPU time 0.72 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 199644 kb
Host smart-6afaa045-973e-4ac6-82e2-41e2ed735b17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961716380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3961716380
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.1418174094
Short name T621
Test name
Test status
Simulation time 125959286 ps
CPU time 1.14 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:10 PM PDT 24
Peak memory 200452 kb
Host smart-07b7d946-cb0a-4cff-a09a-a7472d1bf76d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418174094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.1418174094
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.4146717755
Short name T522
Test name
Test status
Simulation time 38625833 ps
CPU time 0.86 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 200420 kb
Host smart-4f25055b-16da-4439-841b-c59ada7b484a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146717755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.4146717755
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.1823476486
Short name T672
Test name
Test status
Simulation time 837140679 ps
CPU time 4.21 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:10 PM PDT 24
Peak memory 200560 kb
Host smart-3b7b3d2e-401c-43ea-a284-408e56570668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823476486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1823476486
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.721921072
Short name T670
Test name
Test status
Simulation time 1531851843 ps
CPU time 6.7 seconds
Started Jul 27 05:39:10 PM PDT 24
Finished Jul 27 05:39:17 PM PDT 24
Peak memory 200584 kb
Host smart-7ade94fa-88d2-410c-aa19-11befc267c39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721921072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_ti
meout.721921072
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1044796671
Short name T700
Test name
Test status
Simulation time 15848592 ps
CPU time 0.75 seconds
Started Jul 27 05:39:05 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200460 kb
Host smart-02aec962-c615-4085-aeea-a79c21c48d28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044796671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.1044796671
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2706234656
Short name T181
Test name
Test status
Simulation time 58051337 ps
CPU time 0.97 seconds
Started Jul 27 05:39:10 PM PDT 24
Finished Jul 27 05:39:11 PM PDT 24
Peak memory 200472 kb
Host smart-aa481545-0a9e-4ae1-b749-8be6b3070d9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706234656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2706234656
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.2713741908
Short name T498
Test name
Test status
Simulation time 119045270 ps
CPU time 1.11 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200440 kb
Host smart-4cdf6119-d2be-4544-b1e4-d0365b6a1426
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713741908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.2713741908
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.1557877521
Short name T345
Test name
Test status
Simulation time 19960474 ps
CPU time 0.76 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200448 kb
Host smart-7fcd3051-3ebb-46f7-a5f9-55bf96b4807c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557877521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1557877521
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1863980957
Short name T63
Test name
Test status
Simulation time 1447127498 ps
CPU time 5.07 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200688 kb
Host smart-3a1da541-6e06-43dd-937c-25d5b7ecdc03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863980957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1863980957
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.1058712890
Short name T299
Test name
Test status
Simulation time 56280655 ps
CPU time 0.99 seconds
Started Jul 27 05:39:04 PM PDT 24
Finished Jul 27 05:39:05 PM PDT 24
Peak memory 200408 kb
Host smart-dfdf70cf-2c62-4bd8-a29a-795a514b2a58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058712890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1058712890
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.1166008321
Short name T251
Test name
Test status
Simulation time 118522024 ps
CPU time 1.4 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:10 PM PDT 24
Peak memory 200472 kb
Host smart-fffa3069-5d73-43d4-9fa7-e9a56b61b8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166008321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.1166008321
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.3708191002
Short name T218
Test name
Test status
Simulation time 55293159 ps
CPU time 1.03 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:10 PM PDT 24
Peak memory 200408 kb
Host smart-df1e509f-74e2-41b0-91ac-a7d88254e9a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708191002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.3708191002
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.2561268792
Short name T808
Test name
Test status
Simulation time 39512800 ps
CPU time 0.82 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 200484 kb
Host smart-cbb9e886-fb3a-4ba1-aac8-5a8ec2e51152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561268792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.2561268792
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.481409301
Short name T660
Test name
Test status
Simulation time 20919228 ps
CPU time 0.83 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:37:35 PM PDT 24
Peak memory 200476 kb
Host smart-246ea54c-7d55-420a-abf5-85fef07e3b7b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481409301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.481409301
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.463418077
Short name T331
Test name
Test status
Simulation time 40239895 ps
CPU time 0.76 seconds
Started Jul 27 05:37:37 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 199608 kb
Host smart-1f5064b7-998b-49c7-b99c-2d95a0623436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463418077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.463418077
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1055653014
Short name T521
Test name
Test status
Simulation time 109803080 ps
CPU time 1.11 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:39 PM PDT 24
Peak memory 200436 kb
Host smart-b005134d-9acf-44e5-953c-972e1f647071
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055653014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1055653014
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.804928144
Short name T486
Test name
Test status
Simulation time 91843782 ps
CPU time 1.09 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 200468 kb
Host smart-9c56ce29-8b0d-4eb0-a1b0-b8f75782073c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804928144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.804928144
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.2438682257
Short name T593
Test name
Test status
Simulation time 1519939129 ps
CPU time 11.85 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:47 PM PDT 24
Peak memory 200520 kb
Host smart-d4cafa9a-9510-4b36-9c5e-df0d4b8775a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438682257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2438682257
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.3958421324
Short name T525
Test name
Test status
Simulation time 2317085868 ps
CPU time 9.52 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200868 kb
Host smart-c984dd05-b34d-4c48-9240-3435e8537b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958421324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.3958421324
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1211694483
Short name T255
Test name
Test status
Simulation time 53250024 ps
CPU time 1.02 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 200416 kb
Host smart-bc7b0b73-93b3-40ab-bbbf-fea628f29baf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211694483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.1211694483
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3712261843
Short name T648
Test name
Test status
Simulation time 38238891 ps
CPU time 0.88 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 200484 kb
Host smart-50bb1ae8-1cf1-421c-83e3-a06c1f600ead
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712261843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.3712261843
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3389643203
Short name T674
Test name
Test status
Simulation time 100195724 ps
CPU time 1.15 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 200460 kb
Host smart-837c0fcb-a0dc-41ca-a9b6-f18c82174be3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389643203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.3389643203
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.3065865897
Short name T343
Test name
Test status
Simulation time 33755862 ps
CPU time 0.75 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:35 PM PDT 24
Peak memory 200456 kb
Host smart-9cb2f33b-b042-411c-af97-e089426ae4ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065865897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3065865897
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.1505662799
Short name T274
Test name
Test status
Simulation time 660807731 ps
CPU time 3.13 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 200644 kb
Host smart-671b0143-5e21-4116-8c92-ca5d28566e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505662799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1505662799
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.1890658385
Short name T44
Test name
Test status
Simulation time 819284819 ps
CPU time 4.22 seconds
Started Jul 27 05:37:37 PM PDT 24
Finished Jul 27 05:37:42 PM PDT 24
Peak memory 221420 kb
Host smart-b6bdf5a7-00d6-4972-95f2-6ea100846e01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890658385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.1890658385
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.1881764124
Short name T758
Test name
Test status
Simulation time 318280299 ps
CPU time 1.73 seconds
Started Jul 27 05:37:36 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 200384 kb
Host smart-47eb8846-3806-4ad9-8420-0fb89f244dc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881764124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1881764124
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.2510502381
Short name T339
Test name
Test status
Simulation time 6649804140 ps
CPU time 26.38 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:38:02 PM PDT 24
Peak memory 200776 kb
Host smart-d8526ff3-8168-4cad-84f6-b1e1d5ca30d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510502381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.2510502381
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.876143997
Short name T736
Test name
Test status
Simulation time 65314709282 ps
CPU time 667.52 seconds
Started Jul 27 05:37:37 PM PDT 24
Finished Jul 27 05:48:45 PM PDT 24
Peak memory 217340 kb
Host smart-21adee04-2385-4c07-9948-2ca255c4df14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=876143997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.876143997
Directory /workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.clkmgr_trans.3689159386
Short name T70
Test name
Test status
Simulation time 168778756 ps
CPU time 1.31 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 200468 kb
Host smart-5f89d7cf-f86e-48b0-9c69-7165b559e12e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689159386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3689159386
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1331562691
Short name T127
Test name
Test status
Simulation time 18251979 ps
CPU time 0.8 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200468 kb
Host smart-6601791c-4259-4de9-ad16-333f0eee1218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331562691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1331562691
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.690284545
Short name T276
Test name
Test status
Simulation time 16305203 ps
CPU time 0.78 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200472 kb
Host smart-41502576-8752-424d-b317-fd847c42b398
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690284545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.690284545
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.530924467
Short name T31
Test name
Test status
Simulation time 21532051 ps
CPU time 0.75 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:10 PM PDT 24
Peak memory 199676 kb
Host smart-633e4ea7-bea7-4ede-8df4-3d174fabf9bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530924467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.530924467
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.389638604
Short name T510
Test name
Test status
Simulation time 53780964 ps
CPU time 1.02 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200676 kb
Host smart-70a242b0-f0ce-45e6-a99c-e85029a36186
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389638604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_div_intersig_mubi.389638604
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.1552504028
Short name T492
Test name
Test status
Simulation time 18908569 ps
CPU time 0.82 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:07 PM PDT 24
Peak memory 200476 kb
Host smart-8eb2f250-ad4e-4ddd-a15f-7b4722273fdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552504028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1552504028
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.1015979051
Short name T10
Test name
Test status
Simulation time 2354799443 ps
CPU time 17.74 seconds
Started Jul 27 05:39:06 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200796 kb
Host smart-f632f711-ca75-47ab-975c-ae77c3233f5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015979051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1015979051
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.3854016670
Short name T450
Test name
Test status
Simulation time 1825546364 ps
CPU time 6.17 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200560 kb
Host smart-3a1debc4-e77b-45f5-8a82-e9e0d2091237
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854016670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.3854016670
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.894036557
Short name T764
Test name
Test status
Simulation time 22070703 ps
CPU time 0.78 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200448 kb
Host smart-1f4da982-4814-42eb-9c52-92c125c34c7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894036557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_idle_intersig_mubi.894036557
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1013509421
Short name T557
Test name
Test status
Simulation time 19665737 ps
CPU time 0.74 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200436 kb
Host smart-6c240de0-bcff-4df0-bbfd-803498fe36f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013509421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1013509421
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.962196244
Short name T390
Test name
Test status
Simulation time 110898121 ps
CPU time 1.08 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200484 kb
Host smart-eac95dd5-29a4-41b8-a52d-b3fefa27b570
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962196244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.clkmgr_lc_ctrl_intersig_mubi.962196244
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2554165399
Short name T293
Test name
Test status
Simulation time 39108095 ps
CPU time 0.81 seconds
Started Jul 27 05:39:08 PM PDT 24
Finished Jul 27 05:39:09 PM PDT 24
Peak memory 200456 kb
Host smart-d5618e56-16f7-47f6-96db-6ae3ac3ef2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554165399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2554165399
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.3310112624
Short name T142
Test name
Test status
Simulation time 630734666 ps
CPU time 3 seconds
Started Jul 27 05:39:09 PM PDT 24
Finished Jul 27 05:39:12 PM PDT 24
Peak memory 200620 kb
Host smart-3a04c081-7a9e-45b8-b637-4d60811829f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310112624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3310112624
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.4291984743
Short name T779
Test name
Test status
Simulation time 16252533 ps
CPU time 0.81 seconds
Started Jul 27 05:39:05 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200372 kb
Host smart-425d3c1b-d717-492e-ae32-ad94c30cae1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291984743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.4291984743
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.446678273
Short name T737
Test name
Test status
Simulation time 141402822 ps
CPU time 2.33 seconds
Started Jul 27 05:39:13 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200676 kb
Host smart-1deb6ace-6fab-40f4-bc7b-cbcaaac26c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446678273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.446678273
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.1298960031
Short name T213
Test name
Test status
Simulation time 15430583 ps
CPU time 0.75 seconds
Started Jul 27 05:39:05 PM PDT 24
Finished Jul 27 05:39:06 PM PDT 24
Peak memory 200440 kb
Host smart-12377524-42b1-4000-afe8-9b49eea41244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298960031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.1298960031
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1062320661
Short name T269
Test name
Test status
Simulation time 52812159 ps
CPU time 0.9 seconds
Started Jul 27 05:39:18 PM PDT 24
Finished Jul 27 05:39:19 PM PDT 24
Peak memory 200464 kb
Host smart-98079f71-819d-4fed-9295-50929cafd35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062320661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1062320661
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.147801676
Short name T503
Test name
Test status
Simulation time 13956508 ps
CPU time 0.78 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200472 kb
Host smart-cdafa793-d168-47a9-a2ea-355109e2652c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147801676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.147801676
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.1476043651
Short name T330
Test name
Test status
Simulation time 17415980 ps
CPU time 0.75 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200396 kb
Host smart-efb8791b-2c74-41d1-af3e-8e9f372aa23e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476043651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.1476043651
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.3408801859
Short name T816
Test name
Test status
Simulation time 36106159 ps
CPU time 0.9 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200480 kb
Host smart-36011282-3161-4b33-9499-67ec5d127365
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408801859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.3408801859
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.454068076
Short name T190
Test name
Test status
Simulation time 20630234 ps
CPU time 0.86 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:08 PM PDT 24
Peak memory 200728 kb
Host smart-b1846ac6-12a6-4832-bd01-70165b25918b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454068076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.454068076
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.3244667625
Short name T699
Test name
Test status
Simulation time 1669408844 ps
CPU time 6.72 seconds
Started Jul 27 05:39:07 PM PDT 24
Finished Jul 27 05:39:13 PM PDT 24
Peak memory 200724 kb
Host smart-64d1334b-c734-4766-af26-14cf213f4637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244667625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.3244667625
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.1120645545
Short name T720
Test name
Test status
Simulation time 1942810592 ps
CPU time 10.62 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:26 PM PDT 24
Peak memory 200568 kb
Host smart-4b2e81a8-fc12-49fc-8f12-c37fbfb33570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120645545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.1120645545
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.3682430860
Short name T714
Test name
Test status
Simulation time 45055598 ps
CPU time 1.16 seconds
Started Jul 27 05:39:16 PM PDT 24
Finished Jul 27 05:39:17 PM PDT 24
Peak memory 200412 kb
Host smart-27ed0bf7-acd2-48c0-8a82-62086c9e8dfd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682430860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.3682430860
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3666159004
Short name T651
Test name
Test status
Simulation time 31056846 ps
CPU time 0.77 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200484 kb
Host smart-cf8b8ec1-17c4-4fc6-aac2-d121f4487129
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666159004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3666159004
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.410282205
Short name T98
Test name
Test status
Simulation time 61922849 ps
CPU time 0.96 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200416 kb
Host smart-c3395db6-1e80-4b26-a4d8-e4ef53b5eb17
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410282205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_ctrl_intersig_mubi.410282205
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.3287366295
Short name T616
Test name
Test status
Simulation time 18021618 ps
CPU time 0.79 seconds
Started Jul 27 05:39:20 PM PDT 24
Finished Jul 27 05:39:21 PM PDT 24
Peak memory 200404 kb
Host smart-7cd8ecae-9444-476a-9967-ab16213f4baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287366295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3287366295
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.196110042
Short name T378
Test name
Test status
Simulation time 799066530 ps
CPU time 4.7 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 200588 kb
Host smart-883213ed-6334-4c59-a9d5-d749272aee07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196110042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.196110042
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.2923536317
Short name T780
Test name
Test status
Simulation time 19639669 ps
CPU time 0.82 seconds
Started Jul 27 05:39:13 PM PDT 24
Finished Jul 27 05:39:14 PM PDT 24
Peak memory 200384 kb
Host smart-417583d8-ab6c-4c5c-af43-408f2b31279e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923536317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2923536317
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.3120909777
Short name T424
Test name
Test status
Simulation time 2428078986 ps
CPU time 14.55 seconds
Started Jul 27 05:39:18 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200724 kb
Host smart-0d0486fd-ed8e-4385-9ce6-d815ac810d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120909777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.3120909777
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.3783778064
Short name T628
Test name
Test status
Simulation time 53238014 ps
CPU time 0.86 seconds
Started Jul 27 05:39:20 PM PDT 24
Finished Jul 27 05:39:20 PM PDT 24
Peak memory 200460 kb
Host smart-10515336-4fa7-4515-a189-ac9bc24eb221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783778064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.3783778064
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.3872598789
Short name T360
Test name
Test status
Simulation time 115779349 ps
CPU time 0.99 seconds
Started Jul 27 05:39:16 PM PDT 24
Finished Jul 27 05:39:17 PM PDT 24
Peak memory 200472 kb
Host smart-c6ae55ae-81f0-4afe-b803-063e0b7073ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872598789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.3872598789
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.3400889001
Short name T738
Test name
Test status
Simulation time 56324050 ps
CPU time 0.91 seconds
Started Jul 27 05:39:13 PM PDT 24
Finished Jul 27 05:39:14 PM PDT 24
Peak memory 200404 kb
Host smart-e0cff8f9-c21c-4298-b13f-6c471e531a27
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400889001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.3400889001
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.1885833693
Short name T137
Test name
Test status
Simulation time 24229109 ps
CPU time 0.74 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 199668 kb
Host smart-86138dd1-f09f-45ba-8ca9-3acfcdc8c96d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885833693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.1885833693
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.4003125843
Short name T347
Test name
Test status
Simulation time 66692347 ps
CPU time 0.99 seconds
Started Jul 27 05:39:17 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 200392 kb
Host smart-09444366-f126-4176-8abe-85bc4c40fd15
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003125843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.4003125843
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.2604004926
Short name T662
Test name
Test status
Simulation time 34016837 ps
CPU time 0.95 seconds
Started Jul 27 05:39:13 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200464 kb
Host smart-f6560a65-f846-4c68-bf49-1ed324d30b8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604004926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2604004926
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.2252263389
Short name T484
Test name
Test status
Simulation time 2113474788 ps
CPU time 16.58 seconds
Started Jul 27 05:39:12 PM PDT 24
Finished Jul 27 05:39:29 PM PDT 24
Peak memory 200740 kb
Host smart-6337fec3-0d22-4458-9068-60d4345fe2b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252263389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.2252263389
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.1488950914
Short name T290
Test name
Test status
Simulation time 634911470 ps
CPU time 2.95 seconds
Started Jul 27 05:39:13 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200532 kb
Host smart-4f27b2b5-c38f-43ac-9475-2bf26f76767e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488950914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.1488950914
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3314904760
Short name T448
Test name
Test status
Simulation time 91874492 ps
CPU time 1.08 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200412 kb
Host smart-34145297-c06a-4dff-be41-f0474e0c3d2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314904760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.3314904760
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3525919402
Short name T563
Test name
Test status
Simulation time 36256622 ps
CPU time 0.87 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200480 kb
Host smart-848efaaa-8730-4b06-a6ca-a77699e1874f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525919402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3525919402
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1582353269
Short name T188
Test name
Test status
Simulation time 37445867 ps
CPU time 0.84 seconds
Started Jul 27 05:39:17 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 200376 kb
Host smart-7a65ad93-ac24-4b07-ab3f-c082b57c4226
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582353269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.1582353269
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.2836991487
Short name T669
Test name
Test status
Simulation time 16667882 ps
CPU time 0.72 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200452 kb
Host smart-493c6e04-1f46-4527-95bc-f59ee7cc91e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836991487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2836991487
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.365996920
Short name T143
Test name
Test status
Simulation time 1028022553 ps
CPU time 5.88 seconds
Started Jul 27 05:39:16 PM PDT 24
Finished Jul 27 05:39:22 PM PDT 24
Peak memory 200644 kb
Host smart-89514d9b-8a10-4e54-949b-3d7804fc7212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365996920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.365996920
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.4274162317
Short name T129
Test name
Test status
Simulation time 44624763 ps
CPU time 0.97 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200440 kb
Host smart-8b4bfb7d-110c-4eda-8254-e24ba14d0fdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274162317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.4274162317
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.2372544970
Short name T524
Test name
Test status
Simulation time 134119961 ps
CPU time 1.98 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200608 kb
Host smart-2a71dd81-0381-4138-83b3-0f70bf31ebd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372544970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.2372544970
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.65997104
Short name T392
Test name
Test status
Simulation time 79486619751 ps
CPU time 1029.27 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:56:24 PM PDT 24
Peak memory 210168 kb
Host smart-606a3f32-ca3c-4a5a-92e7-7de7a3e702ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=65997104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.65997104
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.1718228985
Short name T577
Test name
Test status
Simulation time 101957466 ps
CPU time 1.16 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200460 kb
Host smart-36c4521a-f747-43f8-81a6-a8f3a22c63d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718228985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1718228985
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.1334684429
Short name T197
Test name
Test status
Simulation time 19572120 ps
CPU time 0.82 seconds
Started Jul 27 05:39:13 PM PDT 24
Finished Jul 27 05:39:14 PM PDT 24
Peak memory 200408 kb
Host smart-74e7e50a-4d6e-4c0b-acdf-dc55fa8cd449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334684429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.1334684429
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.771154278
Short name T773
Test name
Test status
Simulation time 95163700 ps
CPU time 1.15 seconds
Started Jul 27 05:39:17 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 200420 kb
Host smart-a3462004-36e3-4025-8787-aca5ae6d0e08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771154278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.771154278
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.336251062
Short name T304
Test name
Test status
Simulation time 14324491 ps
CPU time 0.75 seconds
Started Jul 27 05:39:17 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 200380 kb
Host smart-aae4fcbe-0c84-4d37-befb-8b5c863a7ca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336251062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.336251062
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.275073972
Short name T694
Test name
Test status
Simulation time 19598173 ps
CPU time 0.82 seconds
Started Jul 27 05:39:16 PM PDT 24
Finished Jul 27 05:39:17 PM PDT 24
Peak memory 200456 kb
Host smart-1581df21-bfa4-4f2f-950e-eab72a1a9c77
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275073972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.clkmgr_div_intersig_mubi.275073972
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3638145071
Short name T253
Test name
Test status
Simulation time 84147895 ps
CPU time 0.99 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200372 kb
Host smart-55063288-fb5b-4d62-9bf3-5b3331322e75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638145071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3638145071
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.3343120953
Short name T483
Test name
Test status
Simulation time 516660336 ps
CPU time 2.44 seconds
Started Jul 27 05:39:15 PM PDT 24
Finished Jul 27 05:39:17 PM PDT 24
Peak memory 200512 kb
Host smart-af0da4f4-32c4-46de-b1dc-0c5d90e2469f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343120953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.3343120953
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3491605656
Short name T546
Test name
Test status
Simulation time 1602879864 ps
CPU time 6.59 seconds
Started Jul 27 05:39:18 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200540 kb
Host smart-fe587581-7a11-4f47-b5ea-32af0b2ad6b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491605656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3491605656
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.3750006471
Short name T84
Test name
Test status
Simulation time 15140314 ps
CPU time 0.73 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200428 kb
Host smart-c0aeacb4-1b60-4339-85ce-688e7859729d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750006471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.3750006471
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2797913895
Short name T804
Test name
Test status
Simulation time 72985356 ps
CPU time 1.03 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200484 kb
Host smart-6688392d-fc0b-47dc-8542-37a2abc15682
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797913895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.2797913895
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.1633882225
Short name T101
Test name
Test status
Simulation time 55160893 ps
CPU time 0.92 seconds
Started Jul 27 05:39:18 PM PDT 24
Finished Jul 27 05:39:19 PM PDT 24
Peak memory 200416 kb
Host smart-438c4788-613d-4cc7-a857-809089fd1d9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633882225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.1633882225
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.1238227749
Short name T156
Test name
Test status
Simulation time 35074829 ps
CPU time 0.89 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200408 kb
Host smart-d8b871f6-d7e3-4f83-851e-ebc2940a1990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238227749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.1238227749
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.2303914776
Short name T730
Test name
Test status
Simulation time 1728789598 ps
CPU time 5.87 seconds
Started Jul 27 05:39:17 PM PDT 24
Finished Jul 27 05:39:23 PM PDT 24
Peak memory 200560 kb
Host smart-c4465021-9d13-4dcd-952c-185cc4b46485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303914776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.2303914776
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.1163316062
Short name T126
Test name
Test status
Simulation time 22604310 ps
CPU time 0.87 seconds
Started Jul 27 05:39:17 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 200400 kb
Host smart-6e308238-074a-41ee-a322-8b133c7d35d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163316062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.1163316062
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.2789728214
Short name T458
Test name
Test status
Simulation time 4126286926 ps
CPU time 30.17 seconds
Started Jul 27 05:39:16 PM PDT 24
Finished Jul 27 05:39:46 PM PDT 24
Peak memory 200868 kb
Host smart-48dcb98d-323c-4007-85c6-9d58ba779167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789728214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.2789728214
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.4237348882
Short name T497
Test name
Test status
Simulation time 49037382 ps
CPU time 0.87 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:15 PM PDT 24
Peak memory 200456 kb
Host smart-aee5bea6-cfa9-41d6-b1be-4c3ad1342cfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237348882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.4237348882
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.949993815
Short name T26
Test name
Test status
Simulation time 15923439 ps
CPU time 0.79 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200472 kb
Host smart-7c94a3a3-2642-4cfd-9df5-6bd1fd37beb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949993815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkm
gr_alert_test.949993815
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2936668912
Short name T186
Test name
Test status
Simulation time 44570239 ps
CPU time 0.84 seconds
Started Jul 27 05:39:20 PM PDT 24
Finished Jul 27 05:39:21 PM PDT 24
Peak memory 200460 kb
Host smart-5f9bf2d5-b187-447e-b652-299334d3706e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936668912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.2936668912
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.1307284257
Short name T157
Test name
Test status
Simulation time 34098803 ps
CPU time 0.73 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 199672 kb
Host smart-6c2dcdcd-95cf-4084-8e83-1188c63fccd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307284257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.1307284257
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.2909139243
Short name T612
Test name
Test status
Simulation time 58784580 ps
CPU time 0.91 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:35 PM PDT 24
Peak memory 200392 kb
Host smart-7d062c80-2ab4-45b3-b86a-540ce89f1cb1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909139243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.2909139243
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.4210575964
Short name T173
Test name
Test status
Simulation time 38876184 ps
CPU time 0.85 seconds
Started Jul 27 05:39:17 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 200416 kb
Host smart-e6d5eeaf-6d43-4043-8356-f6033b93fe3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210575964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.4210575964
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.1957211791
Short name T717
Test name
Test status
Simulation time 2486365011 ps
CPU time 13.8 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:28 PM PDT 24
Peak memory 200788 kb
Host smart-fce1d91e-0364-441b-ad8f-ab373ff31311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957211791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.1957211791
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.347939254
Short name T467
Test name
Test status
Simulation time 406046438 ps
CPU time 2.24 seconds
Started Jul 27 05:39:16 PM PDT 24
Finished Jul 27 05:39:19 PM PDT 24
Peak memory 200584 kb
Host smart-ad2d301a-205f-406f-aa81-6e7a7ebd893a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347939254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_ti
meout.347939254
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.2096566117
Short name T221
Test name
Test status
Simulation time 52714810 ps
CPU time 1.05 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200456 kb
Host smart-b54024c2-5c16-4585-b692-ea887bcc76f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096566117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.2096566117
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.2531302742
Short name T362
Test name
Test status
Simulation time 43068051 ps
CPU time 0.84 seconds
Started Jul 27 05:39:24 PM PDT 24
Finished Jul 27 05:39:25 PM PDT 24
Peak memory 200452 kb
Host smart-e48d774e-3b7b-434c-9e07-6c66b671c3ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531302742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.2531302742
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1213701968
Short name T487
Test name
Test status
Simulation time 195178219 ps
CPU time 1.38 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 200408 kb
Host smart-958dc14c-1940-47b9-ad42-7906322f9206
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213701968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.1213701968
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.1813060727
Short name T615
Test name
Test status
Simulation time 14508379 ps
CPU time 0.76 seconds
Started Jul 27 05:39:32 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200360 kb
Host smart-7a5b6850-e37b-40be-9477-4bc204834d4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813060727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.1813060727
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.4286851969
Short name T144
Test name
Test status
Simulation time 516290533 ps
CPU time 3.29 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200580 kb
Host smart-85b4da04-f14a-43aa-b1c9-87ab6ee64a98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286851969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.4286851969
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1846549770
Short name T122
Test name
Test status
Simulation time 68971938 ps
CPU time 1.04 seconds
Started Jul 27 05:39:14 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 200420 kb
Host smart-24698367-22ea-43a8-995b-666bb6847d9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846549770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1846549770
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.1064334633
Short name T3
Test name
Test status
Simulation time 11078230494 ps
CPU time 45.78 seconds
Started Jul 27 05:39:22 PM PDT 24
Finished Jul 27 05:40:08 PM PDT 24
Peak memory 200912 kb
Host smart-b5589aba-3b15-4a43-9f79-1720823f2164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064334633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.1064334633
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.3960872153
Short name T456
Test name
Test status
Simulation time 65196336 ps
CPU time 1.12 seconds
Started Jul 27 05:39:25 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200420 kb
Host smart-4687d878-ce83-400d-989f-a4b600b37ff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960872153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3960872153
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.3165131326
Short name T234
Test name
Test status
Simulation time 106035263 ps
CPU time 0.97 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200456 kb
Host smart-48db0b13-7a4b-43cb-b404-92d0ca21f0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165131326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.3165131326
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.4045121981
Short name T763
Test name
Test status
Simulation time 46896647 ps
CPU time 0.83 seconds
Started Jul 27 05:39:32 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200408 kb
Host smart-0ffdb1d0-b677-403d-8c6d-ef5c9edf7482
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045121981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.4045121981
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.1128912088
Short name T701
Test name
Test status
Simulation time 37170421 ps
CPU time 0.77 seconds
Started Jul 27 05:39:28 PM PDT 24
Finished Jul 27 05:39:29 PM PDT 24
Peak memory 199688 kb
Host smart-590116ad-d3ce-4be1-9720-783f013f514c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128912088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1128912088
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.174699339
Short name T194
Test name
Test status
Simulation time 39987646 ps
CPU time 0.95 seconds
Started Jul 27 05:39:27 PM PDT 24
Finished Jul 27 05:39:28 PM PDT 24
Peak memory 200464 kb
Host smart-1d30ac6f-7f7a-4571-bf25-8baaaffe5aa6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174699339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_div_intersig_mubi.174699339
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.3709692698
Short name T800
Test name
Test status
Simulation time 26225725 ps
CPU time 0.8 seconds
Started Jul 27 05:39:20 PM PDT 24
Finished Jul 27 05:39:21 PM PDT 24
Peak memory 200404 kb
Host smart-62f5a5ef-ec4f-4231-96a4-3d87df299bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709692698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.3709692698
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3507898480
Short name T538
Test name
Test status
Simulation time 1047458758 ps
CPU time 6.12 seconds
Started Jul 27 05:39:24 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200792 kb
Host smart-8a2c5ca6-ed75-4dd0-9265-e0fd60dd193b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507898480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3507898480
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.4029469865
Short name T471
Test name
Test status
Simulation time 2075898662 ps
CPU time 7.74 seconds
Started Jul 27 05:39:32 PM PDT 24
Finished Jul 27 05:39:40 PM PDT 24
Peak memory 200736 kb
Host smart-6076a458-ff6b-4ff8-916e-1073816a5ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029469865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.4029469865
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2089744930
Short name T187
Test name
Test status
Simulation time 20151253 ps
CPU time 0.88 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200460 kb
Host smart-b70afc1b-e26e-441f-b40a-496c0a89ac81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089744930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2089744930
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1634045465
Short name T799
Test name
Test status
Simulation time 32824422 ps
CPU time 0.85 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200480 kb
Host smart-df75bbe1-9368-4d01-a687-9edd574b1c2f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634045465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1634045465
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3212443149
Short name T317
Test name
Test status
Simulation time 42596812 ps
CPU time 0.86 seconds
Started Jul 27 05:39:24 PM PDT 24
Finished Jul 27 05:39:25 PM PDT 24
Peak memory 200456 kb
Host smart-6d8f5a8e-4326-447a-acc8-4bb666c4da9d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212443149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.3212443149
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.1268253506
Short name T250
Test name
Test status
Simulation time 37455623 ps
CPU time 0.86 seconds
Started Jul 27 05:39:31 PM PDT 24
Finished Jul 27 05:39:32 PM PDT 24
Peak memory 200424 kb
Host smart-0ef56a40-c8fb-49a5-a6e5-08848ca513e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268253506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1268253506
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.3849024364
Short name T421
Test name
Test status
Simulation time 271485099 ps
CPU time 1.55 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200412 kb
Host smart-c869552e-7e33-494d-88e2-1bfe1de9237e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849024364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.3849024364
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.3708043478
Short name T409
Test name
Test status
Simulation time 62740268 ps
CPU time 0.96 seconds
Started Jul 27 05:39:22 PM PDT 24
Finished Jul 27 05:39:23 PM PDT 24
Peak memory 200464 kb
Host smart-983e3f7f-4913-4374-b1bd-cd62052ef941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708043478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3708043478
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.2720947110
Short name T653
Test name
Test status
Simulation time 2958316311 ps
CPU time 22.5 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:45 PM PDT 24
Peak memory 200836 kb
Host smart-08047865-186c-4926-a565-fd1cabd2bff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720947110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.2720947110
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.3004332812
Short name T519
Test name
Test status
Simulation time 25297107 ps
CPU time 1 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200460 kb
Host smart-bf8a00f0-9eab-40db-9581-3e4f2d610d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004332812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3004332812
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.609453381
Short name T455
Test name
Test status
Simulation time 52620221 ps
CPU time 0.89 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200452 kb
Host smart-b3f545d7-9d98-4b83-8e36-87f1c2282273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609453381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm
gr_alert_test.609453381
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2896481470
Short name T732
Test name
Test status
Simulation time 18158227 ps
CPU time 0.8 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 200448 kb
Host smart-68536323-86d6-4526-92d3-df685deb16fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896481470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.2896481470
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.2011495165
Short name T613
Test name
Test status
Simulation time 28524413 ps
CPU time 0.74 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:23 PM PDT 24
Peak memory 199700 kb
Host smart-4390bf50-5111-43e8-b6e0-fec58df6033d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011495165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.2011495165
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.2914908608
Short name T664
Test name
Test status
Simulation time 21493208 ps
CPU time 0.87 seconds
Started Jul 27 05:39:20 PM PDT 24
Finished Jul 27 05:39:21 PM PDT 24
Peak memory 200484 kb
Host smart-c3f37e23-41b7-4e4b-a917-48a38ebe6b36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914908608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.2914908608
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.3063178017
Short name T198
Test name
Test status
Simulation time 25564777 ps
CPU time 0.96 seconds
Started Jul 27 05:39:24 PM PDT 24
Finished Jul 27 05:39:25 PM PDT 24
Peak memory 200476 kb
Host smart-55306304-39a5-42c1-a35e-0964251928e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063178017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3063178017
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.3129935328
Short name T8
Test name
Test status
Simulation time 1034746308 ps
CPU time 7.87 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200488 kb
Host smart-cbc63d80-809c-4a38-b41c-b489875e494d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129935328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.3129935328
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.4087511781
Short name T743
Test name
Test status
Simulation time 1713675260 ps
CPU time 7.55 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:34 PM PDT 24
Peak memory 200488 kb
Host smart-d21f1abd-e5b1-4a3c-a298-91bae575f67f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087511781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.4087511781
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.632544920
Short name T338
Test name
Test status
Simulation time 39916189 ps
CPU time 0.81 seconds
Started Jul 27 05:39:27 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200456 kb
Host smart-b0735ab2-e01e-4a03-bb8d-4c99cac540d7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632544920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_idle_intersig_mubi.632544920
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3070455045
Short name T751
Test name
Test status
Simulation time 31556567 ps
CPU time 0.83 seconds
Started Jul 27 05:39:22 PM PDT 24
Finished Jul 27 05:39:23 PM PDT 24
Peak memory 200460 kb
Host smart-61891510-d44e-4716-af04-56aeba63ff1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070455045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.3070455045
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2390205635
Short name T703
Test name
Test status
Simulation time 56465811 ps
CPU time 0.82 seconds
Started Jul 27 05:39:25 PM PDT 24
Finished Jul 27 05:39:26 PM PDT 24
Peak memory 200388 kb
Host smart-a873e51a-659e-471c-adf7-a76bc4f4f759
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390205635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.2390205635
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.955505883
Short name T622
Test name
Test status
Simulation time 21603177 ps
CPU time 0.79 seconds
Started Jul 27 05:39:25 PM PDT 24
Finished Jul 27 05:39:26 PM PDT 24
Peak memory 200412 kb
Host smart-8d8943cf-f8ab-46f2-b681-14b83a87669f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955505883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.955505883
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.803363968
Short name T635
Test name
Test status
Simulation time 1103150194 ps
CPU time 6.1 seconds
Started Jul 27 05:39:25 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200912 kb
Host smart-0f3b611c-6847-4539-979c-a1cc35d4b0c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803363968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.803363968
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.3246684127
Short name T348
Test name
Test status
Simulation time 17644964 ps
CPU time 0.84 seconds
Started Jul 27 05:39:24 PM PDT 24
Finished Jul 27 05:39:25 PM PDT 24
Peak memory 200424 kb
Host smart-0765a252-39e5-44f4-a86a-d3200e39b30d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246684127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3246684127
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.3280446290
Short name T461
Test name
Test status
Simulation time 7174439460 ps
CPU time 24.3 seconds
Started Jul 27 05:39:25 PM PDT 24
Finished Jul 27 05:39:50 PM PDT 24
Peak memory 200804 kb
Host smart-9a6c1b71-8caa-4a75-b637-d0b60c872385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280446290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.3280446290
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.2471498992
Short name T325
Test name
Test status
Simulation time 45398288 ps
CPU time 0.9 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200420 kb
Host smart-3965a0ba-6f17-40e6-a9ce-e4e4c1e98bab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471498992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2471498992
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.1846021049
Short name T154
Test name
Test status
Simulation time 43893803 ps
CPU time 0.88 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200448 kb
Host smart-1a7bd617-050f-46ff-b194-36b7c1f371f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846021049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.1846021049
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3359039000
Short name T539
Test name
Test status
Simulation time 25302147 ps
CPU time 0.79 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 200668 kb
Host smart-829b61e1-17d0-42bc-bd24-bc342fc7eed8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359039000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.3359039000
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.2125595607
Short name T241
Test name
Test status
Simulation time 15338659 ps
CPU time 0.73 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 199676 kb
Host smart-885b0894-441d-4be5-8c11-79452f87cf35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125595607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2125595607
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.522268159
Short name T427
Test name
Test status
Simulation time 37173682 ps
CPU time 0.95 seconds
Started Jul 27 05:39:31 PM PDT 24
Finished Jul 27 05:39:32 PM PDT 24
Peak memory 200476 kb
Host smart-161a0ef3-b622-4057-8718-858d74f2543c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522268159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_div_intersig_mubi.522268159
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.1029768268
Short name T210
Test name
Test status
Simulation time 354819789 ps
CPU time 1.83 seconds
Started Jul 27 05:39:25 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200452 kb
Host smart-121a52ff-1cbd-4d5d-9098-f652415ac221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029768268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1029768268
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.1460406481
Short name T379
Test name
Test status
Simulation time 717067284 ps
CPU time 3.97 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 200512 kb
Host smart-31a901f4-f23d-44a5-817f-286f247bf516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460406481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1460406481
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.1781674975
Short name T517
Test name
Test status
Simulation time 1408640770 ps
CPU time 6.15 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:32 PM PDT 24
Peak memory 200532 kb
Host smart-01c03efa-931f-4109-873a-bedfa6b021ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781674975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.1781674975
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3346317932
Short name T725
Test name
Test status
Simulation time 19201145 ps
CPU time 0.81 seconds
Started Jul 27 05:39:22 PM PDT 24
Finished Jul 27 05:39:23 PM PDT 24
Peak memory 200392 kb
Host smart-bd038a23-9128-4c6f-a15c-3cb01c2e3c98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346317932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.3346317932
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1473128366
Short name T206
Test name
Test status
Simulation time 29247317 ps
CPU time 0.93 seconds
Started Jul 27 05:39:27 PM PDT 24
Finished Jul 27 05:39:28 PM PDT 24
Peak memory 200468 kb
Host smart-855e05e9-7999-4745-894c-54f7b4a91c3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473128366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.1473128366
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.3433819835
Short name T376
Test name
Test status
Simulation time 52946423 ps
CPU time 0.99 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200476 kb
Host smart-dde978cc-7d14-42ad-a725-c5ceaf2f17b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433819835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.3433819835
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.70727314
Short name T170
Test name
Test status
Simulation time 12899939 ps
CPU time 0.72 seconds
Started Jul 27 05:39:23 PM PDT 24
Finished Jul 27 05:39:24 PM PDT 24
Peak memory 200416 kb
Host smart-c0a76aa5-f8c0-4745-a5eb-3d926aabc69b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70727314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.70727314
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.717762206
Short name T167
Test name
Test status
Simulation time 15721939 ps
CPU time 0.8 seconds
Started Jul 27 05:39:28 PM PDT 24
Finished Jul 27 05:39:29 PM PDT 24
Peak memory 200424 kb
Host smart-52a20672-2fa5-4e88-af87-84594f6542cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717762206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.717762206
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.2800829821
Short name T326
Test name
Test status
Simulation time 10987580024 ps
CPU time 57.56 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:40:27 PM PDT 24
Peak memory 200828 kb
Host smart-22d0a563-c7fd-4cf2-8cf1-6b15231bb623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800829821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.2800829821
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.2711591151
Short name T473
Test name
Test status
Simulation time 22079490 ps
CPU time 0.88 seconds
Started Jul 27 05:39:26 PM PDT 24
Finished Jul 27 05:39:27 PM PDT 24
Peak memory 200452 kb
Host smart-a708aad4-1bac-419b-9cd8-06bd25412ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711591151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.2711591151
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.860007329
Short name T395
Test name
Test status
Simulation time 95973932 ps
CPU time 1.04 seconds
Started Jul 27 05:39:33 PM PDT 24
Finished Jul 27 05:39:34 PM PDT 24
Peak memory 200472 kb
Host smart-61a6d303-42d0-41e0-9ef8-da10444177ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860007329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm
gr_alert_test.860007329
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3191723039
Short name T542
Test name
Test status
Simulation time 13594520 ps
CPU time 0.74 seconds
Started Jul 27 05:39:31 PM PDT 24
Finished Jul 27 05:39:32 PM PDT 24
Peak memory 200488 kb
Host smart-fd58db24-e700-412b-abb5-d341b65df841
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191723039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.3191723039
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.2796574681
Short name T298
Test name
Test status
Simulation time 37885846 ps
CPU time 0.84 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200376 kb
Host smart-d998ca83-8dc3-4055-82cd-13694c9cbd36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796574681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.2796574681
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.1898088818
Short name T589
Test name
Test status
Simulation time 15984858 ps
CPU time 0.76 seconds
Started Jul 27 05:39:34 PM PDT 24
Finished Jul 27 05:39:35 PM PDT 24
Peak memory 200384 kb
Host smart-dcea8f2c-c347-4f8e-8901-426e34a1f592
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898088818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.1898088818
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.2513308295
Short name T134
Test name
Test status
Simulation time 125234149 ps
CPU time 1.25 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200416 kb
Host smart-39bd2560-07d6-42ca-89f6-adb6ce81622e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513308295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2513308295
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.2496570715
Short name T277
Test name
Test status
Simulation time 2488986768 ps
CPU time 11.69 seconds
Started Jul 27 05:39:32 PM PDT 24
Finished Jul 27 05:39:43 PM PDT 24
Peak memory 200756 kb
Host smart-82375b5a-dc75-473a-8bd6-ed81bc19527d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496570715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.2496570715
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.3764558246
Short name T530
Test name
Test status
Simulation time 1656811017 ps
CPU time 7.41 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:37 PM PDT 24
Peak memory 200560 kb
Host smart-3958a766-2b30-4379-8812-586dc18c1e56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764558246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.3764558246
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.3269439795
Short name T354
Test name
Test status
Simulation time 105585998 ps
CPU time 1.28 seconds
Started Jul 27 05:39:31 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200464 kb
Host smart-3baf71f1-7e13-4bc4-8305-1448a2a04e16
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269439795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.3269439795
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.4037018331
Short name T692
Test name
Test status
Simulation time 29662837 ps
CPU time 0.85 seconds
Started Jul 27 05:39:35 PM PDT 24
Finished Jul 27 05:39:36 PM PDT 24
Peak memory 200448 kb
Host smart-79500cb0-e62a-4d4a-ba41-dd3569d9c3fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037018331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.4037018331
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1867545311
Short name T793
Test name
Test status
Simulation time 20740349 ps
CPU time 0.78 seconds
Started Jul 27 05:39:34 PM PDT 24
Finished Jul 27 05:39:35 PM PDT 24
Peak memory 200452 kb
Host smart-b651d364-2ddd-487b-93a5-bc2833975e9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867545311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.1867545311
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.3455943433
Short name T374
Test name
Test status
Simulation time 49890127 ps
CPU time 0.83 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 200424 kb
Host smart-bc5e215f-fdd5-47f9-b5ae-c4c35607c915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455943433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3455943433
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.4169139427
Short name T706
Test name
Test status
Simulation time 111328140 ps
CPU time 1.15 seconds
Started Jul 27 05:39:32 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200420 kb
Host smart-b5e2ed6e-9334-48b3-809c-986f34df1d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169139427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.4169139427
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.1476998630
Short name T526
Test name
Test status
Simulation time 48526153 ps
CPU time 0.9 seconds
Started Jul 27 05:39:34 PM PDT 24
Finished Jul 27 05:39:35 PM PDT 24
Peak memory 200328 kb
Host smart-4e0bcc2e-5794-4ed5-a5fc-890aaa2e0a04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476998630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.1476998630
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.1562628498
Short name T440
Test name
Test status
Simulation time 10320895359 ps
CPU time 55.05 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:40:26 PM PDT 24
Peak memory 200888 kb
Host smart-69ec1abc-9ef8-48e8-a61b-ad1ae45981ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562628498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.1562628498
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.40080996
Short name T164
Test name
Test status
Simulation time 314650157243 ps
CPU time 1271.42 seconds
Started Jul 27 05:39:34 PM PDT 24
Finished Jul 27 06:00:46 PM PDT 24
Peak memory 209060 kb
Host smart-7c694458-120c-4799-b04f-7fb6aaf1c727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=40080996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.40080996
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_trans.89237327
Short name T245
Test name
Test status
Simulation time 41130758 ps
CPU time 1.14 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200460 kb
Host smart-750d6601-94b0-4b95-a4e8-4d6be122c871
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89237327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.89237327
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.2749261352
Short name T335
Test name
Test status
Simulation time 79258585 ps
CPU time 0.94 seconds
Started Jul 27 05:39:36 PM PDT 24
Finished Jul 27 05:39:37 PM PDT 24
Peak memory 200508 kb
Host smart-37a43056-20a1-41ea-bb7b-2208aeac2d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749261352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.2749261352
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3835674181
Short name T721
Test name
Test status
Simulation time 102526472 ps
CPU time 1.14 seconds
Started Jul 27 05:39:45 PM PDT 24
Finished Jul 27 05:39:47 PM PDT 24
Peak memory 200480 kb
Host smart-2d4d3335-5c5e-456c-bd50-2a290793c7dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835674181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.3835674181
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.3177691571
Short name T554
Test name
Test status
Simulation time 49832770 ps
CPU time 0.8 seconds
Started Jul 27 05:39:31 PM PDT 24
Finished Jul 27 05:39:32 PM PDT 24
Peak memory 199668 kb
Host smart-d32b2219-fd66-422a-b220-9a2cfc9eb566
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177691571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.3177691571
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2835322765
Short name T801
Test name
Test status
Simulation time 32115866 ps
CPU time 0.78 seconds
Started Jul 27 05:39:37 PM PDT 24
Finished Jul 27 05:39:38 PM PDT 24
Peak memory 200420 kb
Host smart-cd6e7ade-3aa1-4e5b-b667-c1aaa93c0047
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835322765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2835322765
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.2071738859
Short name T214
Test name
Test status
Simulation time 28131093 ps
CPU time 0.75 seconds
Started Jul 27 05:39:28 PM PDT 24
Finished Jul 27 05:39:29 PM PDT 24
Peak memory 200408 kb
Host smart-7ffc7ab7-5bbb-44b6-9515-d2d95631cf7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071738859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2071738859
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.472893088
Short name T357
Test name
Test status
Simulation time 1683966978 ps
CPU time 8.53 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:39 PM PDT 24
Peak memory 200484 kb
Host smart-f8a014ef-0c2c-4f91-922c-414ac3c1db8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472893088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.472893088
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.3120342460
Short name T227
Test name
Test status
Simulation time 636264299 ps
CPU time 3.11 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200584 kb
Host smart-d86547c0-53af-4b1a-a73a-8ada52c7de8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120342460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.3120342460
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2088473469
Short name T761
Test name
Test status
Simulation time 59403443 ps
CPU time 0.94 seconds
Started Jul 27 05:39:32 PM PDT 24
Finished Jul 27 05:39:33 PM PDT 24
Peak memory 200472 kb
Host smart-0c9e22b4-fa5f-4f8a-90a0-14022995ee22
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088473469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.2088473469
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.1514848751
Short name T696
Test name
Test status
Simulation time 27629662 ps
CPU time 0.87 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 200420 kb
Host smart-540db779-abce-4954-a9a6-123346cec46b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514848751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.1514848751
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3682563185
Short name T529
Test name
Test status
Simulation time 41541825 ps
CPU time 0.92 seconds
Started Jul 27 05:39:34 PM PDT 24
Finished Jul 27 05:39:35 PM PDT 24
Peak memory 200452 kb
Host smart-030d37b4-18bf-4097-bca1-801884944a70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682563185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3682563185
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.1288208045
Short name T686
Test name
Test status
Simulation time 18512344 ps
CPU time 0.8 seconds
Started Jul 27 05:39:30 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200408 kb
Host smart-38116057-113e-4455-ace2-d65dcc703f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288208045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1288208045
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.2846315420
Short name T43
Test name
Test status
Simulation time 2134005151 ps
CPU time 6.95 seconds
Started Jul 27 05:39:38 PM PDT 24
Finished Jul 27 05:39:45 PM PDT 24
Peak memory 200600 kb
Host smart-bc24479d-000e-4131-aa1e-d796c5310807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846315420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2846315420
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.979634334
Short name T349
Test name
Test status
Simulation time 28605572 ps
CPU time 0.88 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 200416 kb
Host smart-8d006107-828f-480f-a2bb-4f05596721e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979634334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.979634334
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.3042222751
Short name T667
Test name
Test status
Simulation time 3202998145 ps
CPU time 16.02 seconds
Started Jul 27 05:39:37 PM PDT 24
Finished Jul 27 05:39:53 PM PDT 24
Peak memory 200848 kb
Host smart-200c597e-1e4e-43f8-8078-82604509f00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042222751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.3042222751
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.3452243951
Short name T211
Test name
Test status
Simulation time 85984312 ps
CPU time 1.12 seconds
Started Jul 27 05:39:29 PM PDT 24
Finished Jul 27 05:39:31 PM PDT 24
Peak memory 200400 kb
Host smart-9197560d-ad25-4adf-b3c3-3132b5047faa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452243951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3452243951
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.2742810966
Short name T243
Test name
Test status
Simulation time 57513800 ps
CPU time 0.88 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:39 PM PDT 24
Peak memory 200476 kb
Host smart-39e4ff17-aaa3-4f1f-846b-6f56035a128e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742810966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.2742810966
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2148689186
Short name T185
Test name
Test status
Simulation time 84560323 ps
CPU time 1.12 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:40 PM PDT 24
Peak memory 200444 kb
Host smart-14cfa2e4-e12c-4ffa-9b18-aa142ddc1822
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148689186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.2148689186
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.3874955707
Short name T324
Test name
Test status
Simulation time 18296853 ps
CPU time 0.69 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:37:35 PM PDT 24
Peak memory 200420 kb
Host smart-4ada85ca-cd9a-4b94-a98a-f786a1f4e2c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874955707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.3874955707
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.1898720612
Short name T323
Test name
Test status
Simulation time 16571262 ps
CPU time 0.77 seconds
Started Jul 27 05:37:40 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 200468 kb
Host smart-f8c83d7a-a803-4f52-9a95-5566d678a542
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898720612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.1898720612
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.3056211891
Short name T434
Test name
Test status
Simulation time 26888082 ps
CPU time 0.9 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:40 PM PDT 24
Peak memory 200408 kb
Host smart-51e1c009-73b0-451d-bc49-84b1105fdc21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056211891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.3056211891
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2998241610
Short name T9
Test name
Test status
Simulation time 1860291107 ps
CPU time 8.47 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:47 PM PDT 24
Peak memory 200700 kb
Host smart-5175c3a5-c821-406c-8e51-c451c2c8c59e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998241610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2998241610
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.1138770490
Short name T807
Test name
Test status
Simulation time 1820076625 ps
CPU time 12.92 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:52 PM PDT 24
Peak memory 200584 kb
Host smart-32aac966-718a-4311-a948-41159c96857a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138770490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.1138770490
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.1474732615
Short name T493
Test name
Test status
Simulation time 16452550 ps
CPU time 0.76 seconds
Started Jul 27 05:37:37 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 200472 kb
Host smart-a98decf9-3093-4c36-943f-548431ef968d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474732615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.1474732615
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.956531780
Short name T320
Test name
Test status
Simulation time 19351066 ps
CPU time 0.82 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 200396 kb
Host smart-14eed70c-88ff-494e-9a06-3659ea39b00e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956531780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_ctrl_intersig_mubi.956531780
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3877224136
Short name T279
Test name
Test status
Simulation time 51873472 ps
CPU time 0.82 seconds
Started Jul 27 05:37:40 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 200412 kb
Host smart-513ca6ff-828f-43f2-a87e-e798e41134a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877224136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3877224136
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.1670688854
Short name T599
Test name
Test status
Simulation time 723915373 ps
CPU time 4.18 seconds
Started Jul 27 05:37:34 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 200652 kb
Host smart-05e3f250-9bc2-4dd6-a45a-a6bd0a57ce22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670688854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1670688854
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.3732185713
Short name T147
Test name
Test status
Simulation time 25231016 ps
CPU time 0.89 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:37:39 PM PDT 24
Peak memory 200416 kb
Host smart-f700327f-1f57-4cf6-95a5-a378dc0ba832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732185713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3732185713
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.835339649
Short name T124
Test name
Test status
Simulation time 2558003337 ps
CPU time 12.06 seconds
Started Jul 27 05:37:35 PM PDT 24
Finished Jul 27 05:37:47 PM PDT 24
Peak memory 200824 kb
Host smart-ead3186b-5f4f-48ae-acf1-4a907425d3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835339649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.835339649
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.673718393
Short name T60
Test name
Test status
Simulation time 152680856401 ps
CPU time 1168.54 seconds
Started Jul 27 05:37:38 PM PDT 24
Finished Jul 27 05:57:07 PM PDT 24
Peak memory 217284 kb
Host smart-d8d925c2-3166-402a-a9ae-e8d91b1331ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=673718393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.673718393
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.4063092963
Short name T685
Test name
Test status
Simulation time 108808536 ps
CPU time 1.21 seconds
Started Jul 27 05:37:39 PM PDT 24
Finished Jul 27 05:37:40 PM PDT 24
Peak memory 200428 kb
Host smart-81a2bd43-0546-4df8-aeb8-62ab1d1a60c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063092963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.4063092963
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.1646498952
Short name T757
Test name
Test status
Simulation time 14364680 ps
CPU time 0.74 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200436 kb
Host smart-fce488f0-cc4b-4600-8789-341a14bc27d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646498952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.1646498952
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1776698076
Short name T312
Test name
Test status
Simulation time 19263155 ps
CPU time 0.72 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:43 PM PDT 24
Peak memory 200416 kb
Host smart-99e6bf9f-7191-4859-b2c9-503bd49306c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776698076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.1776698076
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.753171360
Short name T311
Test name
Test status
Simulation time 27358841 ps
CPU time 0.77 seconds
Started Jul 27 05:37:46 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 200344 kb
Host smart-11ba7c49-3472-4fc3-b5ef-a5c4e21f25e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753171360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.753171360
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3419246883
Short name T594
Test name
Test status
Simulation time 43284809 ps
CPU time 0.93 seconds
Started Jul 27 05:37:52 PM PDT 24
Finished Jul 27 05:37:53 PM PDT 24
Peak memory 200456 kb
Host smart-5c3baf35-8a7d-4f79-ac3c-38f5b86ad1d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419246883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3419246883
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.1232071627
Short name T728
Test name
Test status
Simulation time 64583805 ps
CPU time 1.02 seconds
Started Jul 27 05:37:37 PM PDT 24
Finished Jul 27 05:37:38 PM PDT 24
Peak memory 200440 kb
Host smart-efd10128-dada-4d56-a40e-b8c90d203eee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232071627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1232071627
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.4131795982
Short name T308
Test name
Test status
Simulation time 1970172357 ps
CPU time 9.06 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:51 PM PDT 24
Peak memory 200652 kb
Host smart-ed366491-e6be-4dcd-89e5-0042de6255c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131795982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.4131795982
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.657462458
Short name T606
Test name
Test status
Simulation time 239391660 ps
CPU time 1.34 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200636 kb
Host smart-771c4f04-9b7e-4da8-9975-65725e345573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657462458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_tim
eout.657462458
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3428926972
Short name T103
Test name
Test status
Simulation time 62647740 ps
CPU time 0.88 seconds
Started Jul 27 05:37:41 PM PDT 24
Finished Jul 27 05:37:42 PM PDT 24
Peak memory 200472 kb
Host smart-0762e71f-7e8a-4e7d-b329-236f7dafb84b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428926972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.3428926972
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3090731885
Short name T710
Test name
Test status
Simulation time 69661430 ps
CPU time 1 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200452 kb
Host smart-13aff86a-2031-44c6-b674-ac9377a37c09
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090731885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.3090731885
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.4103094743
Short name T666
Test name
Test status
Simulation time 26368479 ps
CPU time 0.94 seconds
Started Jul 27 05:37:46 PM PDT 24
Finished Jul 27 05:37:47 PM PDT 24
Peak memory 200476 kb
Host smart-502fc974-fb92-4dfa-b73b-c2e0a53ec1b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103094743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.4103094743
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.1458729398
Short name T697
Test name
Test status
Simulation time 24798318 ps
CPU time 0.79 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200452 kb
Host smart-902a2721-edfe-440b-9f26-33a0dd458494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458729398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1458729398
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.3480297015
Short name T411
Test name
Test status
Simulation time 1142438533 ps
CPU time 4.26 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 200624 kb
Host smart-2b96b7a1-0b82-49e4-a1d0-768b7731ca06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480297015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3480297015
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1449765608
Short name T104
Test name
Test status
Simulation time 44962392 ps
CPU time 0.91 seconds
Started Jul 27 05:37:36 PM PDT 24
Finished Jul 27 05:37:37 PM PDT 24
Peak memory 200456 kb
Host smart-79a95418-b4f8-4674-8f39-de160b99aae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449765608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1449765608
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_trans.1105664739
Short name T178
Test name
Test status
Simulation time 25369371 ps
CPU time 0.92 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:43 PM PDT 24
Peak memory 200740 kb
Host smart-5307ba9d-e4d3-4fdf-9460-a06f0a2c4d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105664739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1105664739
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3522560309
Short name T722
Test name
Test status
Simulation time 39751265 ps
CPU time 0.77 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200436 kb
Host smart-7620db15-63e0-4639-93cd-f3d9703e7d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522560309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3522560309
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.177217216
Short name T196
Test name
Test status
Simulation time 28567692 ps
CPU time 0.86 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200448 kb
Host smart-b27d81b7-c2c8-42cf-8d03-f54117452d1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177217216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.177217216
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.4042021181
Short name T441
Test name
Test status
Simulation time 17838798 ps
CPU time 0.74 seconds
Started Jul 27 05:37:53 PM PDT 24
Finished Jul 27 05:37:54 PM PDT 24
Peak memory 200360 kb
Host smart-88f9a03c-fec3-41a0-94cb-58ba96196513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042021181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.4042021181
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.1014000413
Short name T230
Test name
Test status
Simulation time 36897542 ps
CPU time 0.92 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200424 kb
Host smart-a2dab617-62bc-4ad1-ae93-5cf816dd7bc4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014000413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.1014000413
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.2631359651
Short name T207
Test name
Test status
Simulation time 20160401 ps
CPU time 0.8 seconds
Started Jul 27 05:37:41 PM PDT 24
Finished Jul 27 05:37:42 PM PDT 24
Peak memory 200448 kb
Host smart-23ab5907-a2e3-4ecf-996a-20c81e319c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631359651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.2631359651
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.3090571525
Short name T270
Test name
Test status
Simulation time 1221733313 ps
CPU time 5.19 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:48 PM PDT 24
Peak memory 200508 kb
Host smart-6383b08c-c7e0-4b86-b265-476f734131ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090571525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3090571525
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.805950626
Short name T336
Test name
Test status
Simulation time 1648759478 ps
CPU time 6.61 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:49 PM PDT 24
Peak memory 200540 kb
Host smart-7b024511-8a0e-4b5a-ba78-f51188e7caff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805950626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_tim
eout.805950626
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.639011512
Short name T398
Test name
Test status
Simulation time 176744316 ps
CPU time 1.41 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:43 PM PDT 24
Peak memory 200464 kb
Host smart-1c38077a-2be2-4190-99a4-ecfc1c54b600
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639011512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_idle_intersig_mubi.639011512
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3527756710
Short name T745
Test name
Test status
Simulation time 18464590 ps
CPU time 0.82 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200460 kb
Host smart-44c6370f-9919-499a-bb43-d4ae9e297cd3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527756710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3527756710
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3463896436
Short name T504
Test name
Test status
Simulation time 25540848 ps
CPU time 0.81 seconds
Started Jul 27 05:37:45 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 200464 kb
Host smart-5e8dd591-b0ac-4ac8-b95a-e6498f84caa0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463896436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3463896436
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.2303495462
Short name T514
Test name
Test status
Simulation time 22353463 ps
CPU time 0.77 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:43 PM PDT 24
Peak memory 200464 kb
Host smart-db719d4f-456a-4d92-a73f-d479a01cf9e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303495462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2303495462
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.3863622106
Short name T713
Test name
Test status
Simulation time 1279938934 ps
CPU time 4.2 seconds
Started Jul 27 05:37:46 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200628 kb
Host smart-ca5e03f3-a912-4e1d-b16f-4da9f04a763b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863622106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3863622106
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.3160656187
Short name T240
Test name
Test status
Simulation time 38911119 ps
CPU time 0.93 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200332 kb
Host smart-02e7e06e-d7c5-4e1b-ab74-445baa24bc75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160656187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3160656187
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.1943768131
Short name T361
Test name
Test status
Simulation time 581768889 ps
CPU time 5.25 seconds
Started Jul 27 05:37:53 PM PDT 24
Finished Jul 27 05:37:59 PM PDT 24
Peak memory 200368 kb
Host smart-06496ec4-b5f2-4ba3-bd52-cff999653090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943768131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.1943768131
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.1488717159
Short name T201
Test name
Test status
Simulation time 78243316 ps
CPU time 1.02 seconds
Started Jul 27 05:37:42 PM PDT 24
Finished Jul 27 05:37:43 PM PDT 24
Peak memory 200500 kb
Host smart-0f1be4c1-33fd-4a52-9106-b1fde1875842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488717159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1488717159
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.4288880269
Short name T782
Test name
Test status
Simulation time 35124327 ps
CPU time 0.85 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200436 kb
Host smart-e11cb6f9-28b8-4f2a-947c-e055b47544b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288880269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.4288880269
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.429919628
Short name T647
Test name
Test status
Simulation time 16953547 ps
CPU time 0.8 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200420 kb
Host smart-5b7c8f1d-eb76-457d-826e-5797ee0d9163
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429919628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.429919628
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.1228279054
Short name T29
Test name
Test status
Simulation time 38650378 ps
CPU time 0.81 seconds
Started Jul 27 05:37:46 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 199612 kb
Host smart-4b45ee5d-fb86-48af-be13-ec3ec3814685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228279054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1228279054
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.19575569
Short name T550
Test name
Test status
Simulation time 66641652 ps
CPU time 0.91 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200456 kb
Host smart-79ace401-1591-4bbf-bb3b-a3d665c0bb3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19575569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
clkmgr_div_intersig_mubi.19575569
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.812731716
Short name T266
Test name
Test status
Simulation time 81429792 ps
CPU time 1.06 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200424 kb
Host smart-53fff700-e9e8-408e-a710-14cadb9ca379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812731716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.812731716
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.3407225489
Short name T454
Test name
Test status
Simulation time 1916936704 ps
CPU time 9.08 seconds
Started Jul 27 05:37:53 PM PDT 24
Finished Jul 27 05:38:02 PM PDT 24
Peak memory 200684 kb
Host smart-bec88647-8121-47ab-b9df-7f13ce278b3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407225489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.3407225489
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.108849399
Short name T296
Test name
Test status
Simulation time 1458548525 ps
CPU time 7.61 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:52 PM PDT 24
Peak memory 200536 kb
Host smart-c93b4915-7fac-4ae4-9941-29da649fe2a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108849399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_tim
eout.108849399
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1931474668
Short name T658
Test name
Test status
Simulation time 22981921 ps
CPU time 0.83 seconds
Started Jul 27 05:37:44 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 200420 kb
Host smart-ce7a7452-6fad-4fd3-bf8e-830f784c09c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931474668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1931474668
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.3030833582
Short name T380
Test name
Test status
Simulation time 15578378 ps
CPU time 0.79 seconds
Started Jul 27 05:37:45 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 200412 kb
Host smart-1361613e-44cd-428a-bb65-2d0a4ab65e75
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030833582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.3030833582
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2605570606
Short name T797
Test name
Test status
Simulation time 16349616 ps
CPU time 0.78 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:43 PM PDT 24
Peak memory 200392 kb
Host smart-59439970-61c7-4a90-84d9-8ed47fcb3dc4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605570606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.2605570606
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.1043909461
Short name T128
Test name
Test status
Simulation time 56665602 ps
CPU time 0.91 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200376 kb
Host smart-0406f224-9d92-45d4-97c5-e98d5fda2650
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043909461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.1043909461
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.2966634299
Short name T638
Test name
Test status
Simulation time 1098686912 ps
CPU time 5 seconds
Started Jul 27 05:37:52 PM PDT 24
Finished Jul 27 05:37:58 PM PDT 24
Peak memory 200628 kb
Host smart-19144ccc-964c-4b44-b240-73bd363cc57b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966634299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2966634299
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.2717265046
Short name T620
Test name
Test status
Simulation time 49880453 ps
CPU time 0.87 seconds
Started Jul 27 05:37:40 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 200420 kb
Host smart-ca30c9e1-26e2-4c95-b153-57bed2817f02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717265046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2717265046
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.1756708769
Short name T734
Test name
Test status
Simulation time 6139240467 ps
CPU time 23.53 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 200856 kb
Host smart-4a9f053e-d2b0-43ef-9718-a1c31cfdcf95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756708769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.1756708769
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.3255989446
Short name T383
Test name
Test status
Simulation time 31315453 ps
CPU time 0.89 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200464 kb
Host smart-9ceb50ae-309a-49a7-8e18-c7423040700a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255989446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3255989446
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.1698936692
Short name T679
Test name
Test status
Simulation time 96875317 ps
CPU time 1.09 seconds
Started Jul 27 05:37:55 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 200420 kb
Host smart-7e4ac0f1-e20c-4dab-80ef-9980d9548d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698936692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.1698936692
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.409291842
Short name T384
Test name
Test status
Simulation time 17508630 ps
CPU time 0.89 seconds
Started Jul 27 05:38:02 PM PDT 24
Finished Jul 27 05:38:03 PM PDT 24
Peak memory 200440 kb
Host smart-19c3b5ae-6ff5-4b60-8de2-8dbdc7a22239
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409291842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.409291842
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.2194051499
Short name T630
Test name
Test status
Simulation time 17533915 ps
CPU time 0.73 seconds
Started Jul 27 05:37:40 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 200376 kb
Host smart-0e6813d8-724c-426b-874f-ee2c25a07aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194051499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.2194051499
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.785703677
Short name T639
Test name
Test status
Simulation time 18976421 ps
CPU time 0.7 seconds
Started Jul 27 05:37:49 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200476 kb
Host smart-e910a021-3087-43f2-a9d9-b90a97d94d9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785703677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_div_intersig_mubi.785703677
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1825387213
Short name T559
Test name
Test status
Simulation time 14740852 ps
CPU time 0.76 seconds
Started Jul 27 05:37:45 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 200436 kb
Host smart-fef390ff-f586-4718-8296-e6289b530b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825387213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1825387213
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.2827212917
Short name T502
Test name
Test status
Simulation time 718011769 ps
CPU time 3.87 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:47 PM PDT 24
Peak memory 200508 kb
Host smart-3b578df3-a125-463c-8800-9d3aaef829cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827212917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2827212917
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.1494129042
Short name T244
Test name
Test status
Simulation time 1157666534 ps
CPU time 5.29 seconds
Started Jul 27 05:37:45 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200540 kb
Host smart-05a4d8f5-3ca3-47a6-8d2c-008eb0a6b0e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494129042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.1494129042
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.4286710955
Short name T585
Test name
Test status
Simulation time 24562842 ps
CPU time 0.74 seconds
Started Jul 27 05:37:47 PM PDT 24
Finished Jul 27 05:37:48 PM PDT 24
Peak memory 200456 kb
Host smart-88af156e-0c41-45b6-8223-f511f90da047
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286710955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.4286710955
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2489227555
Short name T724
Test name
Test status
Simulation time 94572467 ps
CPU time 0.97 seconds
Started Jul 27 05:37:48 PM PDT 24
Finished Jul 27 05:37:49 PM PDT 24
Peak memory 200472 kb
Host smart-a85854fc-ea9d-4fac-a4e3-3d40c9d7826c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489227555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.2489227555
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.572350733
Short name T235
Test name
Test status
Simulation time 26093314 ps
CPU time 0.88 seconds
Started Jul 27 05:37:49 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200488 kb
Host smart-4a8feb0d-47e3-4fbe-bed7-49597a874e7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572350733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_ctrl_intersig_mubi.572350733
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.2090284803
Short name T591
Test name
Test status
Simulation time 40965089 ps
CPU time 0.84 seconds
Started Jul 27 05:37:43 PM PDT 24
Finished Jul 27 05:37:44 PM PDT 24
Peak memory 200408 kb
Host smart-f85b02bc-0bcb-4a86-809d-a6df59d6cbca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090284803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2090284803
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.3804318778
Short name T476
Test name
Test status
Simulation time 244633659 ps
CPU time 1.49 seconds
Started Jul 27 05:37:48 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 200412 kb
Host smart-df3ce52d-767e-496a-bdb6-83342db68c4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804318778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.3804318778
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.1943175952
Short name T709
Test name
Test status
Simulation time 233702769 ps
CPU time 1.41 seconds
Started Jul 27 05:37:53 PM PDT 24
Finished Jul 27 05:37:54 PM PDT 24
Peak memory 200392 kb
Host smart-ab79c91d-0376-4159-bde8-a6f67e327eea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943175952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1943175952
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.2816968369
Short name T322
Test name
Test status
Simulation time 7549176108 ps
CPU time 24.52 seconds
Started Jul 27 05:38:02 PM PDT 24
Finished Jul 27 05:38:27 PM PDT 24
Peak memory 200816 kb
Host smart-25d7407e-ffa9-4b4e-ad55-22af311f3cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816968369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.2816968369
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.2736444095
Short name T28
Test name
Test status
Simulation time 155417569093 ps
CPU time 969.42 seconds
Started Jul 27 05:37:57 PM PDT 24
Finished Jul 27 05:54:07 PM PDT 24
Peak memory 209080 kb
Host smart-8487deea-7bde-4a8d-8156-0e92484ba704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2736444095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2736444095
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.2790335244
Short name T294
Test name
Test status
Simulation time 61753268 ps
CPU time 0.97 seconds
Started Jul 27 05:37:45 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 200432 kb
Host smart-3c3ba3d0-3bec-4669-96b2-a9f44960b887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790335244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2790335244
Directory /workspace/9.clkmgr_trans/latest
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