Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115194892

1

T6

2138

T1

129568

T5

46094

auto[1]

212884

1

T6

118

T17

364

T29

674

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115164078

1

T6

2166

T1

129568

T5

46094

auto[1]

243698

1

T6

90

T17

306

T29

604

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115121124

1

T6

2180

T1

129568

T5

46094

auto[1]

286652

1

T6

76

T17

330

T29

660

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104380356

1

T6

1908

T1

129568

T5

46094

auto[1]

11027420

1

T6

348

T17

1072

T29

4060

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78096990

1

T6

2210

T1

129550

T5

24752

auto[1]

37310786

1

T6

46

T1

18

T5

21342

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

69788358

1

T6

1806

T1

129550

T5

24752

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34361532

1

T6

46

T1

18

T5

21342

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

16270

1

T17

6

T29

6

T39

32

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4286

1

T17

28

T29

2

T10

24

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

7960146

1

T6

230

T17

714

T29

3104

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2892792

1

T17

76

T29

374

T39

292

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

22560

1

T6

36

T17

68

T29

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6314

1

T17

6

T29

40

T9

42

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39250

1

T116

2

T189

8

T11

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

714

1

T11

22

T190

8

T148

24

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8720

1

T116

58

T189

52

T11

42

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1584

1

T13

78

T191

54

T92

70

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

5028

1

T6

26

T17

10

T29

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1120

1

T17

2

T29

4

T39

26

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9732

1

T6

36

T17

44

T29

48

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2718

1

T17

52

T29

86

T90

66

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

34602

1

T6

2

T29

14

T39

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2812

1

T17

10

T39

96

T117

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

18732

1

T6

46

T29

104

T39

106

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4908

1

T17

56

T117

46

T13

58

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

14462

1

T17

66

T29

24

T39

100

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2682

1

T9

48

T114

14

T115

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27402

1

T29

54

T9

96

T10

282

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6220

1

T9

80

T114

54

T11

38

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63230

1

T6

8

T17

38

T39

198

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2698

1

T17

22

T29

46

T10

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25824

1

T17

42

T10

158

T90

36

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6836

1

T17

62

T29

102

T10

64

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20720

1

T6

20

T17

34

T29

80

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4746

1

T29

12

T39

42

T116

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

41954

1

T29

120

T10

422

T90

270

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8824

1

T29

104

T116

58

T11

86