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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80


Total test records in report: 976
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T802 /workspace/coverage/default/19.clkmgr_smoke.929534561 Jul 28 05:10:10 PM PDT 24 Jul 28 05:10:10 PM PDT 24 19638202 ps
T803 /workspace/coverage/default/19.clkmgr_clk_status.1744443780 Jul 28 05:10:30 PM PDT 24 Jul 28 05:10:31 PM PDT 24 27363760 ps
T804 /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1383174578 Jul 28 05:10:52 PM PDT 24 Jul 28 05:10:53 PM PDT 24 33584769 ps
T805 /workspace/coverage/default/49.clkmgr_frequency.1632355761 Jul 28 05:11:19 PM PDT 24 Jul 28 05:11:21 PM PDT 24 208635416 ps
T806 /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2216257878 Jul 28 05:10:48 PM PDT 24 Jul 28 05:10:49 PM PDT 24 32458312 ps
T807 /workspace/coverage/default/17.clkmgr_extclk.1209201300 Jul 28 05:10:11 PM PDT 24 Jul 28 05:10:12 PM PDT 24 27836968 ps
T808 /workspace/coverage/default/8.clkmgr_peri.4222926206 Jul 28 05:10:08 PM PDT 24 Jul 28 05:10:09 PM PDT 24 29749081 ps
T809 /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3762310691 Jul 28 05:10:07 PM PDT 24 Jul 28 05:10:08 PM PDT 24 33259879 ps
T810 /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2257740730 Jul 28 05:10:36 PM PDT 24 Jul 28 05:10:37 PM PDT 24 22213897 ps
T811 /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.226800142 Jul 28 05:10:14 PM PDT 24 Jul 28 05:10:15 PM PDT 24 50924851 ps
T812 /workspace/coverage/default/29.clkmgr_trans.386913717 Jul 28 05:10:48 PM PDT 24 Jul 28 05:10:49 PM PDT 24 23667390 ps
T813 /workspace/coverage/default/33.clkmgr_peri.1424753376 Jul 28 05:10:44 PM PDT 24 Jul 28 05:10:45 PM PDT 24 48668298 ps
T814 /workspace/coverage/default/23.clkmgr_stress_all.585241368 Jul 28 05:10:21 PM PDT 24 Jul 28 05:11:24 PM PDT 24 15812372293 ps
T815 /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.3010197989 Jul 28 05:09:59 PM PDT 24 Jul 28 05:26:09 PM PDT 24 243147336131 ps
T816 /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1283772011 Jul 28 05:10:23 PM PDT 24 Jul 28 05:10:23 PM PDT 24 16443895 ps
T817 /workspace/coverage/default/8.clkmgr_smoke.2997092224 Jul 28 05:10:01 PM PDT 24 Jul 28 05:10:02 PM PDT 24 23528462 ps
T818 /workspace/coverage/default/7.clkmgr_trans.3668254119 Jul 28 05:09:40 PM PDT 24 Jul 28 05:09:41 PM PDT 24 18347122 ps
T819 /workspace/coverage/default/40.clkmgr_stress_all.4044197791 Jul 28 05:10:52 PM PDT 24 Jul 28 05:11:02 PM PDT 24 1912331879 ps
T820 /workspace/coverage/default/36.clkmgr_clk_status.1356342603 Jul 28 05:11:02 PM PDT 24 Jul 28 05:11:03 PM PDT 24 20515965 ps
T821 /workspace/coverage/default/20.clkmgr_div_intersig_mubi.3463407723 Jul 28 05:10:40 PM PDT 24 Jul 28 05:10:41 PM PDT 24 26332777 ps
T822 /workspace/coverage/default/34.clkmgr_frequency.4137551055 Jul 28 05:10:51 PM PDT 24 Jul 28 05:11:02 PM PDT 24 1400382718 ps
T108 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2675024293 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:31 PM PDT 24 48849949 ps
T83 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1775621751 Jul 28 05:09:36 PM PDT 24 Jul 28 05:09:37 PM PDT 24 23311095 ps
T55 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3417628916 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:37 PM PDT 24 224852813 ps
T171 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4001930104 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:28 PM PDT 24 26067477 ps
T823 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2599264007 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:26 PM PDT 24 29802594 ps
T84 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2766847051 Jul 28 05:09:15 PM PDT 24 Jul 28 05:09:16 PM PDT 24 182569952 ps
T824 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3460094884 Jul 28 05:09:37 PM PDT 24 Jul 28 05:09:39 PM PDT 24 278808120 ps
T172 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3727484478 Jul 28 05:09:07 PM PDT 24 Jul 28 05:09:15 PM PDT 24 587790100 ps
T825 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1767624855 Jul 28 05:09:19 PM PDT 24 Jul 28 05:09:20 PM PDT 24 39757430 ps
T85 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2853030087 Jul 28 05:09:17 PM PDT 24 Jul 28 05:09:19 PM PDT 24 359501906 ps
T826 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1124949064 Jul 28 05:09:18 PM PDT 24 Jul 28 05:09:22 PM PDT 24 442372769 ps
T56 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3296114004 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:32 PM PDT 24 60443045 ps
T173 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2329290726 Jul 28 05:09:17 PM PDT 24 Jul 28 05:09:19 PM PDT 24 52416926 ps
T827 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2522223631 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:33 PM PDT 24 125881137 ps
T828 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3926037717 Jul 28 05:09:09 PM PDT 24 Jul 28 05:09:11 PM PDT 24 142984889 ps
T174 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1742227831 Jul 28 05:09:08 PM PDT 24 Jul 28 05:09:12 PM PDT 24 132441187 ps
T86 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3117446843 Jul 28 05:09:26 PM PDT 24 Jul 28 05:09:27 PM PDT 24 16307827 ps
T57 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.671385247 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:30 PM PDT 24 90845046 ps
T63 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3623133775 Jul 28 05:09:05 PM PDT 24 Jul 28 05:09:08 PM PDT 24 217959825 ps
T87 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1141122009 Jul 28 05:09:22 PM PDT 24 Jul 28 05:09:24 PM PDT 24 17288197 ps
T98 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2727159147 Jul 28 05:09:15 PM PDT 24 Jul 28 05:09:18 PM PDT 24 427333652 ps
T61 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3374066907 Jul 28 05:09:08 PM PDT 24 Jul 28 05:09:12 PM PDT 24 286972792 ps
T99 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4181921201 Jul 28 05:09:13 PM PDT 24 Jul 28 05:09:16 PM PDT 24 566376171 ps
T829 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1623590853 Jul 28 05:09:26 PM PDT 24 Jul 28 05:09:29 PM PDT 24 270450418 ps
T58 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3080343129 Jul 28 05:09:11 PM PDT 24 Jul 28 05:09:13 PM PDT 24 201051237 ps
T830 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3148976091 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:26 PM PDT 24 52220699 ps
T831 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1581249611 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:36 PM PDT 24 31000346 ps
T59 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2465953615 Jul 28 05:09:11 PM PDT 24 Jul 28 05:09:14 PM PDT 24 186792054 ps
T88 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.47303234 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:35 PM PDT 24 37873829 ps
T64 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2547688245 Jul 28 05:09:29 PM PDT 24 Jul 28 05:09:33 PM PDT 24 428378616 ps
T832 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2351390070 Jul 28 05:09:39 PM PDT 24 Jul 28 05:09:40 PM PDT 24 12546617 ps
T833 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.88592160 Jul 28 05:09:51 PM PDT 24 Jul 28 05:09:52 PM PDT 24 60230227 ps
T100 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2665012745 Jul 28 05:09:24 PM PDT 24 Jul 28 05:09:32 PM PDT 24 355197852 ps
T834 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.224737381 Jul 28 05:09:04 PM PDT 24 Jul 28 05:09:06 PM PDT 24 56035683 ps
T835 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1417247 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:38 PM PDT 24 539742824 ps
T836 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.287624476 Jul 28 05:09:14 PM PDT 24 Jul 28 05:09:15 PM PDT 24 17852285 ps
T65 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.966662697 Jul 28 05:09:31 PM PDT 24 Jul 28 05:09:33 PM PDT 24 88055062 ps
T837 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.4204729044 Jul 28 05:09:43 PM PDT 24 Jul 28 05:09:43 PM PDT 24 13502932 ps
T60 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3909878408 Jul 28 05:09:22 PM PDT 24 Jul 28 05:09:24 PM PDT 24 60694779 ps
T838 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.4266955307 Jul 28 05:09:09 PM PDT 24 Jul 28 05:09:11 PM PDT 24 106205252 ps
T184 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.344110181 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:29 PM PDT 24 63963057 ps
T839 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2957805641 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:37 PM PDT 24 26227246 ps
T840 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2032719373 Jul 28 05:09:39 PM PDT 24 Jul 28 05:09:40 PM PDT 24 66933700 ps
T131 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1246534274 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:31 PM PDT 24 510992011 ps
T841 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2690627356 Jul 28 05:09:11 PM PDT 24 Jul 28 05:09:12 PM PDT 24 66837095 ps
T842 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2346195750 Jul 28 05:09:32 PM PDT 24 Jul 28 05:09:33 PM PDT 24 41434189 ps
T843 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1681492346 Jul 28 05:08:58 PM PDT 24 Jul 28 05:08:59 PM PDT 24 85918436 ps
T106 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.454453881 Jul 28 05:09:03 PM PDT 24 Jul 28 05:09:08 PM PDT 24 1187962737 ps
T844 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.458236743 Jul 28 05:09:11 PM PDT 24 Jul 28 05:09:11 PM PDT 24 14120679 ps
T845 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3256506873 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:29 PM PDT 24 28445973 ps
T846 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3745002206 Jul 28 05:09:17 PM PDT 24 Jul 28 05:09:18 PM PDT 24 59901303 ps
T847 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3077601513 Jul 28 05:09:22 PM PDT 24 Jul 28 05:09:24 PM PDT 24 15666224 ps
T848 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.4042516676 Jul 28 05:09:22 PM PDT 24 Jul 28 05:09:25 PM PDT 24 86834014 ps
T849 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3618791448 Jul 28 05:09:03 PM PDT 24 Jul 28 05:09:04 PM PDT 24 30157875 ps
T850 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1267135167 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:26 PM PDT 24 13988863 ps
T185 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.366121425 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:37 PM PDT 24 117966242 ps
T851 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.3118065195 Jul 28 05:09:18 PM PDT 24 Jul 28 05:09:21 PM PDT 24 627631036 ps
T852 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1061174375 Jul 28 05:09:43 PM PDT 24 Jul 28 05:09:49 PM PDT 24 10781236 ps
T853 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.314844472 Jul 28 05:09:07 PM PDT 24 Jul 28 05:09:09 PM PDT 24 139037554 ps
T186 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1685472028 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:38 PM PDT 24 232212069 ps
T124 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.734512997 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:27 PM PDT 24 305816535 ps
T62 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3716726386 Jul 28 05:09:26 PM PDT 24 Jul 28 05:09:28 PM PDT 24 189439923 ps
T125 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3929303569 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:38 PM PDT 24 357573947 ps
T854 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2246240749 Jul 28 05:09:20 PM PDT 24 Jul 28 05:09:21 PM PDT 24 28520943 ps
T855 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1527185017 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:36 PM PDT 24 49660142 ps
T856 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1998241789 Jul 28 05:09:15 PM PDT 24 Jul 28 05:09:16 PM PDT 24 13956218 ps
T857 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3836486944 Jul 28 05:09:37 PM PDT 24 Jul 28 05:09:40 PM PDT 24 47707419 ps
T858 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3871092121 Jul 28 05:09:31 PM PDT 24 Jul 28 05:09:32 PM PDT 24 11436619 ps
T859 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1085697686 Jul 28 05:09:05 PM PDT 24 Jul 28 05:09:07 PM PDT 24 27674090 ps
T126 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2220498690 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:32 PM PDT 24 107258325 ps
T860 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1107908870 Jul 28 05:09:21 PM PDT 24 Jul 28 05:09:23 PM PDT 24 30981463 ps
T861 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.288837026 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:26 PM PDT 24 53461744 ps
T127 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3052067475 Jul 28 05:09:05 PM PDT 24 Jul 28 05:09:06 PM PDT 24 71015480 ps
T110 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3569082415 Jul 28 05:09:33 PM PDT 24 Jul 28 05:09:36 PM PDT 24 81436119 ps
T862 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.286737610 Jul 28 05:09:00 PM PDT 24 Jul 28 05:09:01 PM PDT 24 20466911 ps
T863 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2162125684 Jul 28 05:09:04 PM PDT 24 Jul 28 05:09:06 PM PDT 24 95814776 ps
T864 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3858466781 Jul 28 05:09:43 PM PDT 24 Jul 28 05:09:49 PM PDT 24 13963286 ps
T865 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1719241116 Jul 28 05:09:14 PM PDT 24 Jul 28 05:09:16 PM PDT 24 65207205 ps
T866 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1576267061 Jul 28 05:09:32 PM PDT 24 Jul 28 05:09:33 PM PDT 24 58890235 ps
T867 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.142085223 Jul 28 05:09:59 PM PDT 24 Jul 28 05:10:02 PM PDT 24 445007741 ps
T868 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3446879515 Jul 28 05:09:20 PM PDT 24 Jul 28 05:09:21 PM PDT 24 128396227 ps
T869 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.692056243 Jul 28 05:09:20 PM PDT 24 Jul 28 05:09:25 PM PDT 24 277362621 ps
T870 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2318034744 Jul 28 05:09:24 PM PDT 24 Jul 28 05:09:26 PM PDT 24 79028949 ps
T871 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.341233145 Jul 28 05:09:45 PM PDT 24 Jul 28 05:09:47 PM PDT 24 145713839 ps
T872 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.635413726 Jul 28 05:09:17 PM PDT 24 Jul 28 05:09:19 PM PDT 24 142566282 ps
T873 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.845702855 Jul 28 05:08:59 PM PDT 24 Jul 28 05:09:00 PM PDT 24 41037066 ps
T874 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.842965603 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:35 PM PDT 24 16322544 ps
T875 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.616675767 Jul 28 05:09:32 PM PDT 24 Jul 28 05:09:33 PM PDT 24 82183260 ps
T876 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3309397315 Jul 28 05:09:24 PM PDT 24 Jul 28 05:09:25 PM PDT 24 82849403 ps
T877 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.459784893 Jul 28 05:09:18 PM PDT 24 Jul 28 05:09:20 PM PDT 24 31039910 ps
T128 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1638369670 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:32 PM PDT 24 121458288 ps
T878 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.752644630 Jul 28 05:09:23 PM PDT 24 Jul 28 05:09:24 PM PDT 24 14851635 ps
T879 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.826672599 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:28 PM PDT 24 23666618 ps
T880 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3379556055 Jul 28 05:09:40 PM PDT 24 Jul 28 05:09:41 PM PDT 24 74002000 ps
T881 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2835811284 Jul 28 05:09:50 PM PDT 24 Jul 28 05:09:51 PM PDT 24 20872578 ps
T882 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2058354303 Jul 28 05:09:08 PM PDT 24 Jul 28 05:09:09 PM PDT 24 30835152 ps
T883 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.819813466 Jul 28 05:09:54 PM PDT 24 Jul 28 05:09:56 PM PDT 24 27797719 ps
T884 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.774981088 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:26 PM PDT 24 23750923 ps
T187 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1068557429 Jul 28 05:09:08 PM PDT 24 Jul 28 05:09:10 PM PDT 24 243519623 ps
T885 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2455654764 Jul 28 05:09:06 PM PDT 24 Jul 28 05:09:07 PM PDT 24 13799565 ps
T886 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1935921767 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:37 PM PDT 24 556188973 ps
T109 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1158125818 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:30 PM PDT 24 89422523 ps
T887 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.646177985 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:35 PM PDT 24 11635338 ps
T888 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1597514252 Jul 28 05:09:39 PM PDT 24 Jul 28 05:09:40 PM PDT 24 31919360 ps
T889 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.615524448 Jul 28 05:09:01 PM PDT 24 Jul 28 05:09:02 PM PDT 24 36365482 ps
T134 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4235317335 Jul 28 05:09:09 PM PDT 24 Jul 28 05:09:12 PM PDT 24 119498429 ps
T890 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2690617512 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:32 PM PDT 24 256940154 ps
T891 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3725880697 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:35 PM PDT 24 14770184 ps
T892 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1421343059 Jul 28 05:09:17 PM PDT 24 Jul 28 05:09:20 PM PDT 24 43542202 ps
T893 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1876985573 Jul 28 05:09:08 PM PDT 24 Jul 28 05:09:10 PM PDT 24 45143007 ps
T894 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.41685140 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:38 PM PDT 24 448536267 ps
T895 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2070902278 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:36 PM PDT 24 19965158 ps
T896 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2463687329 Jul 28 05:09:36 PM PDT 24 Jul 28 05:09:37 PM PDT 24 15911736 ps
T897 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2171094095 Jul 28 05:09:45 PM PDT 24 Jul 28 05:09:45 PM PDT 24 13607009 ps
T898 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1671546356 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:28 PM PDT 24 14940467 ps
T899 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.236299446 Jul 28 05:09:29 PM PDT 24 Jul 28 05:09:30 PM PDT 24 64141462 ps
T135 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3316683759 Jul 28 05:09:10 PM PDT 24 Jul 28 05:09:12 PM PDT 24 121991678 ps
T900 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2683161065 Jul 28 05:09:41 PM PDT 24 Jul 28 05:09:42 PM PDT 24 30288974 ps
T901 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1929541454 Jul 28 05:09:10 PM PDT 24 Jul 28 05:09:18 PM PDT 24 705023275 ps
T902 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2145948712 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:31 PM PDT 24 23175928 ps
T137 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2740354567 Jul 28 05:09:21 PM PDT 24 Jul 28 05:09:25 PM PDT 24 450426171 ps
T903 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.317831762 Jul 28 05:09:43 PM PDT 24 Jul 28 05:09:44 PM PDT 24 36283186 ps
T904 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1759551815 Jul 28 05:09:15 PM PDT 24 Jul 28 05:09:19 PM PDT 24 448836033 ps
T132 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2901203673 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:36 PM PDT 24 142599834 ps
T905 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.992567579 Jul 28 05:09:15 PM PDT 24 Jul 28 05:09:17 PM PDT 24 158616862 ps
T111 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.4081873821 Jul 28 05:09:29 PM PDT 24 Jul 28 05:09:36 PM PDT 24 128479859 ps
T906 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3970605904 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:37 PM PDT 24 77428589 ps
T907 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2285182748 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:28 PM PDT 24 34382788 ps
T908 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.132549654 Jul 28 05:09:14 PM PDT 24 Jul 28 05:09:16 PM PDT 24 66029154 ps
T909 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.253263093 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:35 PM PDT 24 50593762 ps
T910 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1287613693 Jul 28 05:09:48 PM PDT 24 Jul 28 05:09:49 PM PDT 24 14202628 ps
T911 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.800235640 Jul 28 05:09:26 PM PDT 24 Jul 28 05:09:27 PM PDT 24 23394177 ps
T912 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.888027014 Jul 28 05:09:21 PM PDT 24 Jul 28 05:09:22 PM PDT 24 46986709 ps
T913 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.82446840 Jul 28 05:09:11 PM PDT 24 Jul 28 05:09:12 PM PDT 24 33948355 ps
T914 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3132410424 Jul 28 05:09:33 PM PDT 24 Jul 28 05:09:36 PM PDT 24 167086834 ps
T915 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2097667786 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:32 PM PDT 24 75000748 ps
T916 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1536318935 Jul 28 05:09:20 PM PDT 24 Jul 28 05:09:21 PM PDT 24 34873697 ps
T917 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2695023909 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:36 PM PDT 24 17423791 ps
T918 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2083090827 Jul 28 05:09:15 PM PDT 24 Jul 28 05:09:16 PM PDT 24 29933563 ps
T138 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2041875915 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:32 PM PDT 24 141006525 ps
T919 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.527996266 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:32 PM PDT 24 286383310 ps
T920 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3588520170 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:28 PM PDT 24 12843185 ps
T921 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3691471948 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:27 PM PDT 24 13819156 ps
T922 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3847706136 Jul 28 05:09:07 PM PDT 24 Jul 28 05:09:09 PM PDT 24 41046713 ps
T923 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1690270091 Jul 28 05:09:20 PM PDT 24 Jul 28 05:09:22 PM PDT 24 204141760 ps
T136 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1113768631 Jul 28 05:09:07 PM PDT 24 Jul 28 05:09:10 PM PDT 24 408202106 ps
T924 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2404829789 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:29 PM PDT 24 16745961 ps
T925 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2114522922 Jul 28 05:09:06 PM PDT 24 Jul 28 05:09:06 PM PDT 24 15080601 ps
T926 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.290396413 Jul 28 05:09:09 PM PDT 24 Jul 28 05:09:10 PM PDT 24 112366414 ps
T927 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1394778831 Jul 28 05:09:42 PM PDT 24 Jul 28 05:09:43 PM PDT 24 11841389 ps
T928 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1445800827 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:34 PM PDT 24 132586721 ps
T929 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.3047783124 Jul 28 05:09:48 PM PDT 24 Jul 28 05:09:49 PM PDT 24 11878389 ps
T930 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2301627064 Jul 28 05:09:03 PM PDT 24 Jul 28 05:09:06 PM PDT 24 146220025 ps
T931 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2700843376 Jul 28 05:09:53 PM PDT 24 Jul 28 05:09:54 PM PDT 24 96005408 ps
T932 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1380497824 Jul 28 05:09:47 PM PDT 24 Jul 28 05:09:48 PM PDT 24 14991181 ps
T933 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3619455031 Jul 28 05:08:58 PM PDT 24 Jul 28 05:09:00 PM PDT 24 79443175 ps
T133 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.141054031 Jul 28 05:09:26 PM PDT 24 Jul 28 05:09:29 PM PDT 24 244593966 ps
T934 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1246109697 Jul 28 05:09:31 PM PDT 24 Jul 28 05:09:31 PM PDT 24 60481648 ps
T935 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2106223806 Jul 28 05:09:22 PM PDT 24 Jul 28 05:09:26 PM PDT 24 502126013 ps
T936 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3526686210 Jul 28 05:09:42 PM PDT 24 Jul 28 05:09:44 PM PDT 24 114018052 ps
T129 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2823402851 Jul 28 05:09:18 PM PDT 24 Jul 28 05:09:20 PM PDT 24 103139508 ps
T937 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.295596105 Jul 28 05:09:41 PM PDT 24 Jul 28 05:09:42 PM PDT 24 35017307 ps
T938 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1653894035 Jul 28 05:09:13 PM PDT 24 Jul 28 05:09:14 PM PDT 24 38389395 ps
T939 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2049893796 Jul 28 05:09:21 PM PDT 24 Jul 28 05:09:22 PM PDT 24 18622570 ps
T940 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.87365228 Jul 28 05:09:11 PM PDT 24 Jul 28 05:09:12 PM PDT 24 34977503 ps
T941 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1837256056 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:26 PM PDT 24 63220787 ps
T942 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3704686971 Jul 28 05:09:23 PM PDT 24 Jul 28 05:09:28 PM PDT 24 1038982566 ps
T943 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2537156485 Jul 28 05:09:03 PM PDT 24 Jul 28 05:09:10 PM PDT 24 37673309 ps
T130 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2472986612 Jul 28 05:09:28 PM PDT 24 Jul 28 05:09:31 PM PDT 24 112843304 ps
T944 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3334859128 Jul 28 05:09:23 PM PDT 24 Jul 28 05:09:24 PM PDT 24 48525849 ps
T945 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1530558714 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:36 PM PDT 24 35799622 ps
T946 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.94627380 Jul 28 05:09:10 PM PDT 24 Jul 28 05:09:13 PM PDT 24 127314065 ps
T947 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.251122131 Jul 28 05:09:12 PM PDT 24 Jul 28 05:09:16 PM PDT 24 177205031 ps
T948 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2027138651 Jul 28 05:09:12 PM PDT 24 Jul 28 05:09:15 PM PDT 24 437149101 ps
T949 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.283309661 Jul 28 05:09:17 PM PDT 24 Jul 28 05:09:18 PM PDT 24 15321188 ps
T950 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3840118496 Jul 28 05:09:31 PM PDT 24 Jul 28 05:09:34 PM PDT 24 107682718 ps
T112 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.759406213 Jul 28 05:09:03 PM PDT 24 Jul 28 05:09:05 PM PDT 24 197036203 ps
T951 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2481346205 Jul 28 05:09:01 PM PDT 24 Jul 28 05:09:03 PM PDT 24 59382820 ps
T952 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.392990005 Jul 28 05:09:12 PM PDT 24 Jul 28 05:09:13 PM PDT 24 36009099 ps
T953 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3793782264 Jul 28 05:09:18 PM PDT 24 Jul 28 05:09:27 PM PDT 24 179956523 ps
T954 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1007046464 Jul 28 05:09:30 PM PDT 24 Jul 28 05:09:31 PM PDT 24 21230418 ps
T188 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3515603322 Jul 28 05:09:06 PM PDT 24 Jul 28 05:09:09 PM PDT 24 290626562 ps
T955 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3869663011 Jul 28 05:09:09 PM PDT 24 Jul 28 05:09:10 PM PDT 24 39821962 ps
T956 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.1765468745 Jul 28 05:09:22 PM PDT 24 Jul 28 05:09:24 PM PDT 24 19906748 ps
T957 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.753353007 Jul 28 05:09:24 PM PDT 24 Jul 28 05:09:25 PM PDT 24 16621480 ps
T958 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1174663620 Jul 28 05:09:56 PM PDT 24 Jul 28 05:10:02 PM PDT 24 30345412 ps
T959 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2562933874 Jul 28 05:09:05 PM PDT 24 Jul 28 05:09:07 PM PDT 24 105500677 ps
T960 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.2024295662 Jul 28 05:09:09 PM PDT 24 Jul 28 05:09:10 PM PDT 24 10774600 ps
T961 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1085888533 Jul 28 05:09:20 PM PDT 24 Jul 28 05:09:22 PM PDT 24 70584710 ps
T107 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1026204308 Jul 28 05:09:31 PM PDT 24 Jul 28 05:09:33 PM PDT 24 83665496 ps
T962 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3116021363 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:30 PM PDT 24 558023292 ps
T963 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2459461165 Jul 28 05:09:24 PM PDT 24 Jul 28 05:09:27 PM PDT 24 115950573 ps
T964 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.962955675 Jul 28 05:09:42 PM PDT 24 Jul 28 05:09:43 PM PDT 24 26435683 ps
T965 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.890212044 Jul 28 05:09:35 PM PDT 24 Jul 28 05:09:36 PM PDT 24 19651352 ps
T966 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2756413754 Jul 28 05:09:48 PM PDT 24 Jul 28 05:09:49 PM PDT 24 21785626 ps
T967 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1798152348 Jul 28 05:09:38 PM PDT 24 Jul 28 05:09:39 PM PDT 24 11103274 ps
T968 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.810809122 Jul 28 05:09:22 PM PDT 24 Jul 28 05:09:26 PM PDT 24 332731601 ps
T969 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.225150537 Jul 28 05:09:34 PM PDT 24 Jul 28 05:09:35 PM PDT 24 77865068 ps
T970 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.645185429 Jul 28 05:09:58 PM PDT 24 Jul 28 05:09:59 PM PDT 24 37138637 ps
T971 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4034176384 Jul 28 05:09:05 PM PDT 24 Jul 28 05:09:08 PM PDT 24 224929246 ps
T972 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1905936537 Jul 28 05:09:25 PM PDT 24 Jul 28 05:09:26 PM PDT 24 33005631 ps
T973 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1053695537 Jul 28 05:09:14 PM PDT 24 Jul 28 05:09:16 PM PDT 24 69731658 ps
T974 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2367332623 Jul 28 05:09:27 PM PDT 24 Jul 28 05:09:28 PM PDT 24 12474994 ps
T975 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1387071707 Jul 28 05:09:24 PM PDT 24 Jul 28 05:09:25 PM PDT 24 27479526 ps
T976 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1880031098 Jul 28 05:09:16 PM PDT 24 Jul 28 05:09:17 PM PDT 24 100845531 ps

Test location /workspace/coverage/default/43.clkmgr_stress_all.3317531569
Short name T5
Test name
Test status
Simulation time 1444965772 ps
CPU time 6.21 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 200512 kb
Host smart-2cd34cb7-90da-4d99-b9e0-079c58eb20ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317531569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.3317531569
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.4240644888
Short name T9
Test name
Test status
Simulation time 5974073529 ps
CPU time 44.87 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:59 PM PDT 24
Peak memory 200776 kb
Host smart-3447d9f2-bdd4-4a96-a0e8-ddaf5341a6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240644888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.4240644888
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.3414655991
Short name T11
Test name
Test status
Simulation time 72028840630 ps
CPU time 462.3 seconds
Started Jul 28 05:10:18 PM PDT 24
Finished Jul 28 05:18:01 PM PDT 24
Peak memory 217280 kb
Host smart-38cbda88-2b23-4bd4-9ab9-23e5f2418180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3414655991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.3414655991
Directory /workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2465953615
Short name T59
Test name
Test status
Simulation time 186792054 ps
CPU time 2.06 seconds
Started Jul 28 05:09:11 PM PDT 24
Finished Jul 28 05:09:14 PM PDT 24
Peak memory 209628 kb
Host smart-fd0dba39-e1c6-4e4c-9bdd-47d840b72507
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465953615 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.2465953615
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.1084604244
Short name T154
Test name
Test status
Simulation time 1272884603 ps
CPU time 7.25 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:50 PM PDT 24
Peak memory 200632 kb
Host smart-6ffa90ee-de64-4952-8959-1c03c1382eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084604244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1084604244
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.998317427
Short name T179
Test name
Test status
Simulation time 15212857 ps
CPU time 0.71 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 199728 kb
Host smart-11e163bf-6a0f-44e0-bb41-03c7af0879e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998317427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.998317427
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.3699121115
Short name T41
Test name
Test status
Simulation time 290387617 ps
CPU time 2.43 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 216184 kb
Host smart-8ffd7c5d-502a-4d73-b838-cf49408f0d47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699121115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.3699121115
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.505450496
Short name T89
Test name
Test status
Simulation time 71226156 ps
CPU time 1.01 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200368 kb
Host smart-71050d08-2156-4f10-a2d9-018593b650a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505450496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_idle_intersig_mubi.505450496
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1601030266
Short name T17
Test name
Test status
Simulation time 23320003 ps
CPU time 0.89 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:09 PM PDT 24
Peak memory 200452 kb
Host smart-7acd554a-cedc-42ee-a8db-e4c26768b05a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601030266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.1601030266
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.2801693578
Short name T30
Test name
Test status
Simulation time 17489033 ps
CPU time 0.8 seconds
Started Jul 28 05:09:47 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 200428 kb
Host smart-5fa7958f-ffb5-4fcc-881f-19dca1b736a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801693578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.2801693578
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.734512997
Short name T124
Test name
Test status
Simulation time 305816535 ps
CPU time 2.37 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:27 PM PDT 24
Peak memory 201364 kb
Host smart-49ee8c70-d3cb-4387-97f9-3f5668629e9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734512997 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.clkmgr_shadow_reg_errors.734512997
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4181921201
Short name T99
Test name
Test status
Simulation time 566376171 ps
CPU time 3.6 seconds
Started Jul 28 05:09:13 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 201220 kb
Host smart-89877f1d-135c-4d49-a4a2-75c2d6c62392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181921201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.4181921201
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.3868182991
Short name T14
Test name
Test status
Simulation time 329194329074 ps
CPU time 1451.04 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 213900 kb
Host smart-04209c1a-1a86-4988-9cd8-54bcddcd243f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3868182991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3868182991
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2766847051
Short name T84
Test name
Test status
Simulation time 182569952 ps
CPU time 1.73 seconds
Started Jul 28 05:09:15 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 201184 kb
Host smart-f7d8924c-5b5a-41dc-bd52-f69c7a20c09d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766847051 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.2766847051
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3716726386
Short name T62
Test name
Test status
Simulation time 189439923 ps
CPU time 2.08 seconds
Started Jul 28 05:09:26 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 209680 kb
Host smart-0d1d70ab-ee77-478e-b011-98eb4b11ffa4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716726386 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.3716726386
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.2351055063
Short name T7
Test name
Test status
Simulation time 419274031 ps
CPU time 2.77 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200456 kb
Host smart-278f1154-c1cb-4922-bc37-f1a8da988404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351055063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.2351055063
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.328279641
Short name T4
Test name
Test status
Simulation time 283489136 ps
CPU time 2.11 seconds
Started Jul 28 05:10:34 PM PDT 24
Finished Jul 28 05:10:36 PM PDT 24
Peak memory 200368 kb
Host smart-fc0714d3-927b-4eba-969e-d7ab19e852d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328279641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.328279641
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.344110181
Short name T184
Test name
Test status
Simulation time 63963057 ps
CPU time 1.59 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:29 PM PDT 24
Peak memory 201216 kb
Host smart-b9de0a00-b6a8-456e-afb1-be7da0743870
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344110181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_tl_intg_err.344110181
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.1784056084
Short name T205
Test name
Test status
Simulation time 63430485 ps
CPU time 0.98 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 200472 kb
Host smart-b15eb645-c644-4823-8378-3ff4312132a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784056084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.1784056084
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1568557727
Short name T95
Test name
Test status
Simulation time 42966687 ps
CPU time 1 seconds
Started Jul 28 05:10:11 PM PDT 24
Finished Jul 28 05:10:13 PM PDT 24
Peak memory 200488 kb
Host smart-da32c0fb-4327-45d5-8ce6-e578ec09bcd6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568557727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.1568557727
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2220498690
Short name T126
Test name
Test status
Simulation time 107258325 ps
CPU time 1.94 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 217616 kb
Host smart-1261d9dc-321e-453b-9139-3680ac173c23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220498690 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.2220498690
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2901203673
Short name T132
Test name
Test status
Simulation time 142599834 ps
CPU time 1.8 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 209832 kb
Host smart-578eb902-f4ca-478b-87b9-7e5a1d7a3f95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901203673 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.2901203673
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.4144309678
Short name T34
Test name
Test status
Simulation time 10965410012 ps
CPU time 45.43 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 200900 kb
Host smart-78f32c07-62d8-4ea3-a89b-a7aa8f381581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144309678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.4144309678
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2727159147
Short name T98
Test name
Test status
Simulation time 427333652 ps
CPU time 3.39 seconds
Started Jul 28 05:09:15 PM PDT 24
Finished Jul 28 05:09:18 PM PDT 24
Peak memory 201268 kb
Host smart-4a887219-7040-402c-9ff6-f15c215c74dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727159147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.2727159147
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2665012745
Short name T100
Test name
Test status
Simulation time 355197852 ps
CPU time 3.13 seconds
Started Jul 28 05:09:24 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 201176 kb
Host smart-d6ede11f-0795-4cf6-969c-cbd50d92ef04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665012745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.2665012745
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1026204308
Short name T107
Test name
Test status
Simulation time 83665496 ps
CPU time 1.68 seconds
Started Jul 28 05:09:31 PM PDT 24
Finished Jul 28 05:09:33 PM PDT 24
Peak memory 201204 kb
Host smart-b99ea0cc-9af5-4731-bbf0-36c90d91af2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026204308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.1026204308
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1158125818
Short name T109
Test name
Test status
Simulation time 89422523 ps
CPU time 1.52 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:30 PM PDT 24
Peak memory 201112 kb
Host smart-5f9fac32-6449-4034-849f-359c9f13cb4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158125818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.1158125818
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2562933874
Short name T959
Test name
Test status
Simulation time 105500677 ps
CPU time 1.82 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 201244 kb
Host smart-a3a2bafd-fe13-4c19-ab9b-f73e9b3abd23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562933874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.2562933874
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1935921767
Short name T886
Test name
Test status
Simulation time 556188973 ps
CPU time 8.52 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 201116 kb
Host smart-bcdd22bd-0451-4446-8788-c29cbe6da89d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935921767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.1935921767
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.283309661
Short name T949
Test name
Test status
Simulation time 15321188 ps
CPU time 0.75 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:18 PM PDT 24
Peak memory 200952 kb
Host smart-3e398639-58ae-40c3-8f2d-f90329e24b60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283309661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_hw_reset.283309661
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2058354303
Short name T882
Test name
Test status
Simulation time 30835152 ps
CPU time 0.99 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 201020 kb
Host smart-cdf6f800-0431-4d0c-b7f3-11a399e4f136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058354303 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2058354303
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.845702855
Short name T873
Test name
Test status
Simulation time 41037066 ps
CPU time 0.79 seconds
Started Jul 28 05:08:59 PM PDT 24
Finished Jul 28 05:09:00 PM PDT 24
Peak memory 200980 kb
Host smart-6edeebd2-1806-4390-9c53-e22abc04539f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845702855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.c
lkmgr_csr_rw.845702855
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.2024295662
Short name T960
Test name
Test status
Simulation time 10774600 ps
CPU time 0.65 seconds
Started Jul 28 05:09:09 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 199508 kb
Host smart-53e1ac9b-5e55-4d63-acfb-9fe4b24e0abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024295662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.2024295662
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1681492346
Short name T843
Test name
Test status
Simulation time 85918436 ps
CPU time 1.29 seconds
Started Jul 28 05:08:58 PM PDT 24
Finished Jul 28 05:08:59 PM PDT 24
Peak memory 201196 kb
Host smart-346475ee-f42b-4e16-93bf-c67dc2d7f61b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681492346 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.1681492346
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3909878408
Short name T60
Test name
Test status
Simulation time 60694779 ps
CPU time 1.31 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 201280 kb
Host smart-6ef08f89-3fba-4a19-aa21-fbee106cd0be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909878408 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.3909878408
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2041875915
Short name T138
Test name
Test status
Simulation time 141006525 ps
CPU time 1.94 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 209636 kb
Host smart-2c9de4dc-a0ee-49ba-9a69-81465cf81bb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041875915 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.2041875915
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4034176384
Short name T971
Test name
Test status
Simulation time 224929246 ps
CPU time 2.1 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 201212 kb
Host smart-a1443257-1403-41bb-bbe8-62fdaa4f4055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034176384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.4034176384
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.459784893
Short name T877
Test name
Test status
Simulation time 31039910 ps
CPU time 1.5 seconds
Started Jul 28 05:09:18 PM PDT 24
Finished Jul 28 05:09:20 PM PDT 24
Peak memory 201144 kb
Host smart-7fa118eb-e400-48ab-8567-d32a11c56238
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459784893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_aliasing.459784893
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3727484478
Short name T172
Test name
Test status
Simulation time 587790100 ps
CPU time 8.49 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:15 PM PDT 24
Peak memory 201128 kb
Host smart-1ad1b327-2c7f-42ac-9de6-f08b81e025b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727484478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.3727484478
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3334859128
Short name T944
Test name
Test status
Simulation time 48525849 ps
CPU time 0.89 seconds
Started Jul 28 05:09:23 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 200932 kb
Host smart-194ab85d-4830-4a40-a881-67aacd639de0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334859128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.3334859128
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2083090827
Short name T918
Test name
Test status
Simulation time 29933563 ps
CPU time 1.09 seconds
Started Jul 28 05:09:15 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 201108 kb
Host smart-95597956-f8c1-4b39-b983-9fc245616db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083090827 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.2083090827
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.286737610
Short name T862
Test name
Test status
Simulation time 20466911 ps
CPU time 0.84 seconds
Started Jul 28 05:09:00 PM PDT 24
Finished Jul 28 05:09:01 PM PDT 24
Peak memory 201052 kb
Host smart-aa0f411e-4022-4acd-bb18-5d40ea20e2ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286737610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.c
lkmgr_csr_rw.286737610
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2114522922
Short name T925
Test name
Test status
Simulation time 15080601 ps
CPU time 0.67 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:06 PM PDT 24
Peak memory 199548 kb
Host smart-97fa7a06-dba8-4b4f-bac3-42cd115bd188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114522922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.2114522922
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2537156485
Short name T943
Test name
Test status
Simulation time 37673309 ps
CPU time 1.08 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 201056 kb
Host smart-f9b92601-3425-4c8c-9589-d92a85d9a520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537156485 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.2537156485
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3080343129
Short name T58
Test name
Test status
Simulation time 201051237 ps
CPU time 1.67 seconds
Started Jul 28 05:09:11 PM PDT 24
Finished Jul 28 05:09:13 PM PDT 24
Peak memory 201180 kb
Host smart-51553506-302c-43a6-a39f-c0ef300b0aee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080343129 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.3080343129
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2301627064
Short name T930
Test name
Test status
Simulation time 146220025 ps
CPU time 2.8 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:06 PM PDT 24
Peak memory 209664 kb
Host smart-57349c27-2160-4eee-9056-6bf48a5f42af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301627064 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.2301627064
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3619455031
Short name T933
Test name
Test status
Simulation time 79443175 ps
CPU time 2.03 seconds
Started Jul 28 05:08:58 PM PDT 24
Finished Jul 28 05:09:00 PM PDT 24
Peak memory 201104 kb
Host smart-4f6d8c71-a92b-499e-a104-94d034c69fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619455031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.3619455031
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.4042516676
Short name T848
Test name
Test status
Simulation time 86834014 ps
CPU time 1.62 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:25 PM PDT 24
Peak memory 201228 kb
Host smart-a478d5f0-3be6-43d4-8747-723c9761e3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042516676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.4042516676
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3526686210
Short name T936
Test name
Test status
Simulation time 114018052 ps
CPU time 1.35 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 201036 kb
Host smart-aea0db9e-ab23-4557-a463-926874b8f63f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526686210 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.3526686210
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3117446843
Short name T86
Test name
Test status
Simulation time 16307827 ps
CPU time 0.81 seconds
Started Jul 28 05:09:26 PM PDT 24
Finished Jul 28 05:09:27 PM PDT 24
Peak memory 200924 kb
Host smart-118ae9e4-7b1a-46a3-9bed-6290c29921a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117446843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3117446843
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1998241789
Short name T856
Test name
Test status
Simulation time 13956218 ps
CPU time 0.68 seconds
Started Jul 28 05:09:15 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 199848 kb
Host smart-8834ae1c-4c3c-4dd3-a19f-cb61530ddbdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998241789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1998241789
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.82446840
Short name T913
Test name
Test status
Simulation time 33948355 ps
CPU time 1.18 seconds
Started Jul 28 05:09:11 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 201036 kb
Host smart-48d01b2d-f5f2-40e2-812d-198ee2c53952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82446840 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.clkmgr_same_csr_outstanding.82446840
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2547688245
Short name T64
Test name
Test status
Simulation time 428378616 ps
CPU time 3.65 seconds
Started Jul 28 05:09:29 PM PDT 24
Finished Jul 28 05:09:33 PM PDT 24
Peak memory 209680 kb
Host smart-8b8f3845-9d21-417c-9762-1cfbc81cc992
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547688245 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2547688245
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.3118065195
Short name T851
Test name
Test status
Simulation time 627631036 ps
CPU time 3.26 seconds
Started Jul 28 05:09:18 PM PDT 24
Finished Jul 28 05:09:21 PM PDT 24
Peak memory 201156 kb
Host smart-82a7d3b2-019c-436c-9045-40fd7cfa44af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118065195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.3118065195
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1719241116
Short name T865
Test name
Test status
Simulation time 65207205 ps
CPU time 1.58 seconds
Started Jul 28 05:09:14 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 201404 kb
Host smart-cfed8ea8-03b6-4f2d-b39d-a99f85fa68fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719241116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.1719241116
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3460094884
Short name T824
Test name
Test status
Simulation time 278808120 ps
CPU time 1.85 seconds
Started Jul 28 05:09:37 PM PDT 24
Finished Jul 28 05:09:39 PM PDT 24
Peak memory 201012 kb
Host smart-5344e165-ed86-489b-b3d5-bfec1f57abdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460094884 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3460094884
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2246240749
Short name T854
Test name
Test status
Simulation time 28520943 ps
CPU time 0.88 seconds
Started Jul 28 05:09:20 PM PDT 24
Finished Jul 28 05:09:21 PM PDT 24
Peak memory 200892 kb
Host smart-2babab45-766f-4a04-872a-435b921b983b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246240749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.2246240749
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1536318935
Short name T916
Test name
Test status
Simulation time 34873697 ps
CPU time 0.7 seconds
Started Jul 28 05:09:20 PM PDT 24
Finished Jul 28 05:09:21 PM PDT 24
Peak memory 199508 kb
Host smart-b62898e8-d9bc-4465-8b98-f00fae25e764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536318935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.1536318935
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.392990005
Short name T952
Test name
Test status
Simulation time 36009099 ps
CPU time 1.06 seconds
Started Jul 28 05:09:12 PM PDT 24
Finished Jul 28 05:09:13 PM PDT 24
Peak memory 201048 kb
Host smart-04d113f9-12aa-4bba-b2c6-30c8349d0f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392990005 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 11.clkmgr_same_csr_outstanding.392990005
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2027138651
Short name T948
Test name
Test status
Simulation time 437149101 ps
CPU time 2.68 seconds
Started Jul 28 05:09:12 PM PDT 24
Finished Jul 28 05:09:15 PM PDT 24
Peak memory 201480 kb
Host smart-3a71668e-b2fe-4c39-944c-ebf8a3134b69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027138651 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.2027138651
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3704686971
Short name T942
Test name
Test status
Simulation time 1038982566 ps
CPU time 5.06 seconds
Started Jul 28 05:09:23 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 209836 kb
Host smart-98dadad8-7ba2-4473-a8fd-4d769fc1c2e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704686971 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3704686971
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1124949064
Short name T826
Test name
Test status
Simulation time 442372769 ps
CPU time 4.21 seconds
Started Jul 28 05:09:18 PM PDT 24
Finished Jul 28 05:09:22 PM PDT 24
Peak memory 201068 kb
Host smart-b6334454-922e-4153-8b4b-6403e2df02a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124949064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.1124949064
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1068557429
Short name T187
Test name
Test status
Simulation time 243519623 ps
CPU time 1.91 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 201084 kb
Host smart-24450870-d543-4c60-bc77-7f31791baa94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068557429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.1068557429
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.314844472
Short name T853
Test name
Test status
Simulation time 139037554 ps
CPU time 1.44 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 201072 kb
Host smart-0fc8f53a-c26b-4b6f-8d9b-815fe33230c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314844472 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.314844472
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.87365228
Short name T940
Test name
Test status
Simulation time 34977503 ps
CPU time 0.75 seconds
Started Jul 28 05:09:11 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 200968 kb
Host smart-70675e9f-ab85-450c-8d92-60ac12820c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87365228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.c
lkmgr_csr_rw.87365228
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1387071707
Short name T975
Test name
Test status
Simulation time 27479526 ps
CPU time 0.7 seconds
Started Jul 28 05:09:24 PM PDT 24
Finished Jul 28 05:09:25 PM PDT 24
Peak memory 199688 kb
Host smart-d5560c98-2b5e-4d34-bc13-4aaa0e6940c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387071707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.1387071707
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2070902278
Short name T895
Test name
Test status
Simulation time 19965158 ps
CPU time 0.94 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 200948 kb
Host smart-3d369739-c3cd-41f4-8e5f-99b464abfadb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070902278 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.2070902278
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2690617512
Short name T890
Test name
Test status
Simulation time 256940154 ps
CPU time 3.18 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 209500 kb
Host smart-6ce2aa27-631a-4a9b-839d-6e3d4ada5c7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690617512 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.2690617512
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1421343059
Short name T892
Test name
Test status
Simulation time 43542202 ps
CPU time 2.45 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:20 PM PDT 24
Peak memory 201220 kb
Host smart-6832005a-6f76-4443-be0d-88f12f6482f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421343059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.1421343059
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2957805641
Short name T839
Test name
Test status
Simulation time 26227246 ps
CPU time 0.97 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 201016 kb
Host smart-ecf41e01-4f9e-4faa-8807-45d90b22534a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957805641 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.2957805641
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2145948712
Short name T902
Test name
Test status
Simulation time 23175928 ps
CPU time 0.89 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:31 PM PDT 24
Peak memory 200948 kb
Host smart-5d2b637d-9d0d-452b-b17a-883d0c8b0989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145948712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.2145948712
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1767624855
Short name T825
Test name
Test status
Simulation time 39757430 ps
CPU time 0.74 seconds
Started Jul 28 05:09:19 PM PDT 24
Finished Jul 28 05:09:20 PM PDT 24
Peak memory 199688 kb
Host smart-be2d255a-5c5b-4012-be36-ca4f67d378ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767624855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.1767624855
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3446879515
Short name T868
Test name
Test status
Simulation time 128396227 ps
CPU time 1.27 seconds
Started Jul 28 05:09:20 PM PDT 24
Finished Jul 28 05:09:21 PM PDT 24
Peak memory 201068 kb
Host smart-789ebda0-4b27-4c7b-9e90-cddb300cf4b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446879515 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.3446879515
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2472986612
Short name T130
Test name
Test status
Simulation time 112843304 ps
CPU time 1.99 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:31 PM PDT 24
Peak memory 201452 kb
Host smart-115caf71-f6ef-4911-a8c7-3208e5a3f369
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472986612 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.2472986612
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2106223806
Short name T935
Test name
Test status
Simulation time 502126013 ps
CPU time 3.91 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 201652 kb
Host smart-46e4e731-1783-4a62-a36a-4f6883d0fd3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106223806 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.2106223806
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1623590853
Short name T829
Test name
Test status
Simulation time 270450418 ps
CPU time 3.48 seconds
Started Jul 28 05:09:26 PM PDT 24
Finished Jul 28 05:09:29 PM PDT 24
Peak memory 201256 kb
Host smart-d88eb510-01d9-4fe7-bdaf-bf69983e8003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623590853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.1623590853
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2346195750
Short name T842
Test name
Test status
Simulation time 41434189 ps
CPU time 1.27 seconds
Started Jul 28 05:09:32 PM PDT 24
Finished Jul 28 05:09:33 PM PDT 24
Peak memory 201064 kb
Host smart-77af0bf9-aba3-492e-8631-66dfb4d135f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346195750 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.2346195750
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1267135167
Short name T850
Test name
Test status
Simulation time 13988863 ps
CPU time 0.76 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 200984 kb
Host smart-3a3d4c31-4dcd-4fb3-b7b1-5b9f4110d396
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267135167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.1267135167
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2599264007
Short name T823
Test name
Test status
Simulation time 29802594 ps
CPU time 0.72 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 199616 kb
Host smart-5d6fc95c-51c9-4a45-ab6f-3bc14bcdb733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599264007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.2599264007
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1905936537
Short name T972
Test name
Test status
Simulation time 33005631 ps
CPU time 0.94 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 201028 kb
Host smart-b7f9a416-80e1-4772-a647-4eceb975949b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905936537 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.1905936537
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2823402851
Short name T129
Test name
Test status
Simulation time 103139508 ps
CPU time 1.23 seconds
Started Jul 28 05:09:18 PM PDT 24
Finished Jul 28 05:09:20 PM PDT 24
Peak memory 201208 kb
Host smart-75dc3607-ced8-4466-8136-314f19f6f29a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823402851 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.2823402851
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1759551815
Short name T904
Test name
Test status
Simulation time 448836033 ps
CPU time 3.62 seconds
Started Jul 28 05:09:15 PM PDT 24
Finished Jul 28 05:09:19 PM PDT 24
Peak memory 209644 kb
Host smart-d8e423a6-71d7-47bb-91ff-6c989448e8ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759551815 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.1759551815
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.616675767
Short name T875
Test name
Test status
Simulation time 82183260 ps
CPU time 1.72 seconds
Started Jul 28 05:09:32 PM PDT 24
Finished Jul 28 05:09:33 PM PDT 24
Peak memory 201260 kb
Host smart-5bed7e6f-7c6c-465a-841a-fc3f7d0f9cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616675767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_tl_errors.616675767
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3569082415
Short name T110
Test name
Test status
Simulation time 81436119 ps
CPU time 1.94 seconds
Started Jul 28 05:09:33 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 201208 kb
Host smart-ccd982dc-0685-4205-a520-72a8a6923cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569082415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.3569082415
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2675024293
Short name T108
Test name
Test status
Simulation time 48849949 ps
CPU time 1.35 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:31 PM PDT 24
Peak memory 201052 kb
Host smart-7b310454-4ee3-4405-8e0c-d09043c94293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675024293 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.2675024293
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2463687329
Short name T896
Test name
Test status
Simulation time 15911736 ps
CPU time 0.77 seconds
Started Jul 28 05:09:36 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 200936 kb
Host smart-8c13dec5-6607-4f4c-96e2-81c3440fd9f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463687329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.2463687329
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.225150537
Short name T969
Test name
Test status
Simulation time 77865068 ps
CPU time 0.81 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 199628 kb
Host smart-fdca7248-90a1-40b3-9bcb-eda06bd578d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225150537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk
mgr_intr_test.225150537
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2097667786
Short name T915
Test name
Test status
Simulation time 75000748 ps
CPU time 1.01 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 201052 kb
Host smart-8206e508-3600-4e3c-bb9c-70c5c15edd3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097667786 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.2097667786
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1638369670
Short name T128
Test name
Test status
Simulation time 121458288 ps
CPU time 2.19 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 217816 kb
Host smart-d31a7f2e-f2a2-4ee9-b983-4a8ebe055f41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638369670 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.1638369670
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1246534274
Short name T131
Test name
Test status
Simulation time 510992011 ps
CPU time 3.86 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:31 PM PDT 24
Peak memory 209696 kb
Host smart-4b550595-a6de-47c6-9882-80efb7861c13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246534274 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.1246534274
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3836486944
Short name T857
Test name
Test status
Simulation time 47707419 ps
CPU time 2.94 seconds
Started Jul 28 05:09:37 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 201140 kb
Host smart-6fa5a799-287f-4fb1-8f56-050da974b371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836486944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.3836486944
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1581249611
Short name T831
Test name
Test status
Simulation time 31000346 ps
CPU time 1.08 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 201076 kb
Host smart-61d991c9-b3d4-4d8e-82f1-3f537de53696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581249611 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.1581249611
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.774981088
Short name T884
Test name
Test status
Simulation time 23750923 ps
CPU time 0.78 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 200992 kb
Host smart-d9302f5c-8184-4571-869a-eac48c7da35b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774981088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
clkmgr_csr_rw.774981088
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1061174375
Short name T852
Test name
Test status
Simulation time 10781236 ps
CPU time 0.64 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 199680 kb
Host smart-b04821a3-b857-4929-87bc-d04947c58e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061174375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.1061174375
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1880031098
Short name T976
Test name
Test status
Simulation time 100845531 ps
CPU time 1.12 seconds
Started Jul 28 05:09:16 PM PDT 24
Finished Jul 28 05:09:17 PM PDT 24
Peak memory 201000 kb
Host smart-9cea3de2-7640-4bea-8e12-31191e0aa36f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880031098 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.1880031098
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3296114004
Short name T56
Test name
Test status
Simulation time 60443045 ps
CPU time 1.27 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 201168 kb
Host smart-4aa783e5-3be8-43e0-b43f-39c8f329bf0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296114004 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.3296114004
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.671385247
Short name T57
Test name
Test status
Simulation time 90845046 ps
CPU time 1.85 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:30 PM PDT 24
Peak memory 209680 kb
Host smart-d0849787-53da-48a9-a098-f363885afb98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671385247 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.671385247
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3840118496
Short name T950
Test name
Test status
Simulation time 107682718 ps
CPU time 2.81 seconds
Started Jul 28 05:09:31 PM PDT 24
Finished Jul 28 05:09:34 PM PDT 24
Peak memory 201204 kb
Host smart-901ed02b-d3c6-4a6e-9cfa-37116310efcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840118496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.3840118496
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.4081873821
Short name T111
Test name
Test status
Simulation time 128479859 ps
CPU time 1.6 seconds
Started Jul 28 05:09:29 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 201100 kb
Host smart-1a864f23-62b6-4cb2-864f-c2de60334f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081873821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.4081873821
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.800235640
Short name T911
Test name
Test status
Simulation time 23394177 ps
CPU time 0.94 seconds
Started Jul 28 05:09:26 PM PDT 24
Finished Jul 28 05:09:27 PM PDT 24
Peak memory 200956 kb
Host smart-b958d818-5a75-4fd0-b0c1-c0937bbe7db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800235640 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.800235640
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3148976091
Short name T830
Test name
Test status
Simulation time 52220699 ps
CPU time 0.82 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 200920 kb
Host smart-a4b94568-09a9-43c2-aed7-efc374b0feff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148976091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.3148976091
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2756413754
Short name T966
Test name
Test status
Simulation time 21785626 ps
CPU time 0.67 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 199660 kb
Host smart-354b5cd4-0bf8-43c3-bc43-10069709a8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756413754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2756413754
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1775621751
Short name T83
Test name
Test status
Simulation time 23311095 ps
CPU time 0.94 seconds
Started Jul 28 05:09:36 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 201052 kb
Host smart-58780e08-8ae3-4515-9a5b-3f70a9a1a3c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775621751 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.1775621751
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3929303569
Short name T125
Test name
Test status
Simulation time 357573947 ps
CPU time 2.74 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:38 PM PDT 24
Peak memory 201472 kb
Host smart-0e27e1a2-68a5-4af7-a9ea-820ef7121047
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929303569 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3929303569
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3417628916
Short name T55
Test name
Test status
Simulation time 224852813 ps
CPU time 2.73 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 209720 kb
Host smart-b78959cf-abe6-4647-9bbb-4c1755ac8480
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417628916 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.3417628916
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3970605904
Short name T906
Test name
Test status
Simulation time 77428589 ps
CPU time 2.02 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 201188 kb
Host smart-6783dd57-39b8-4b19-8e7f-b723bc72818f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970605904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3970605904
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1685472028
Short name T186
Test name
Test status
Simulation time 232212069 ps
CPU time 2.53 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:38 PM PDT 24
Peak memory 201232 kb
Host smart-d013af21-26c3-4dd1-9d17-1085f5cfdf41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685472028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.1685472028
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.962955675
Short name T964
Test name
Test status
Simulation time 26435683 ps
CPU time 0.93 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:43 PM PDT 24
Peak memory 201084 kb
Host smart-2ae0885b-3b60-4aee-9a4f-a2698594d79a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962955675 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.962955675
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.47303234
Short name T88
Test name
Test status
Simulation time 37873829 ps
CPU time 0.86 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 200944 kb
Host smart-5a014b4b-2378-41ce-bd81-a56dfad55f76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47303234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.c
lkmgr_csr_rw.47303234
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1671546356
Short name T898
Test name
Test status
Simulation time 14940467 ps
CPU time 0.69 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 199736 kb
Host smart-45db88ae-7208-4b4c-bf6a-23fb2f99ff09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671546356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.1671546356
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.253263093
Short name T909
Test name
Test status
Simulation time 50593762 ps
CPU time 1.31 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 200824 kb
Host smart-3498256d-0b16-4218-99a4-4d86997f6034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253263093 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 18.clkmgr_same_csr_outstanding.253263093
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.966662697
Short name T65
Test name
Test status
Simulation time 88055062 ps
CPU time 1.9 seconds
Started Jul 28 05:09:31 PM PDT 24
Finished Jul 28 05:09:33 PM PDT 24
Peak memory 209640 kb
Host smart-85efafaa-b840-45f1-bacb-65ccd7972ee7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966662697 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.966662697
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1527185017
Short name T855
Test name
Test status
Simulation time 49660142 ps
CPU time 1.64 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 201136 kb
Host smart-8bd36894-3bdd-423a-91a8-e97efb536a68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527185017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.1527185017
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.366121425
Short name T185
Test name
Test status
Simulation time 117966242 ps
CPU time 2.47 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 201180 kb
Host smart-1971e312-0dde-4a11-adaa-ac1c1268c1ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366121425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_tl_intg_err.366121425
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.341233145
Short name T871
Test name
Test status
Simulation time 145713839 ps
CPU time 1.4 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:47 PM PDT 24
Peak memory 200904 kb
Host smart-5420fbb9-a647-4008-8f6f-cc0493492cb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341233145 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.341233145
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.295596105
Short name T937
Test name
Test status
Simulation time 35017307 ps
CPU time 0.85 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200952 kb
Host smart-1123835e-2146-4bdd-a7b2-eaa3405f1eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295596105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.295596105
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2695023909
Short name T917
Test name
Test status
Simulation time 17423791 ps
CPU time 0.67 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 199540 kb
Host smart-b58e91ad-d982-4657-8c2b-e264e0e69244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695023909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2695023909
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.41685140
Short name T894
Test name
Test status
Simulation time 448536267 ps
CPU time 2.14 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:38 PM PDT 24
Peak memory 201120 kb
Host smart-3077e6d0-3913-46aa-8354-a4615ec104fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41685140 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.clkmgr_same_csr_outstanding.41685140
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3132410424
Short name T914
Test name
Test status
Simulation time 167086834 ps
CPU time 2.99 seconds
Started Jul 28 05:09:33 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 201676 kb
Host smart-103f21aa-97ab-4325-b0d4-036425ce59b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132410424 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.3132410424
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3116021363
Short name T962
Test name
Test status
Simulation time 558023292 ps
CPU time 4.37 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:30 PM PDT 24
Peak memory 201144 kb
Host smart-4205e252-bdca-4502-a6d4-c390d4e4acd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116021363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.3116021363
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.142085223
Short name T867
Test name
Test status
Simulation time 445007741 ps
CPU time 3.53 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 201188 kb
Host smart-67798ef0-07cd-497e-8c33-70adb14ec5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142085223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_tl_intg_err.142085223
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1085697686
Short name T859
Test name
Test status
Simulation time 27674090 ps
CPU time 1.52 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 201184 kb
Host smart-84680c0b-7c74-4521-b651-69fd95e5f4c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085697686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1085697686
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1417247
Short name T835
Test name
Test status
Simulation time 539742824 ps
CPU time 8.38 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:38 PM PDT 24
Peak memory 201264 kb
Host smart-0d966fea-85d8-4eae-941f-10117683d6cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.clkmgr_csr_bit_bash.1417247
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3618791448
Short name T849
Test name
Test status
Simulation time 30157875 ps
CPU time 0.82 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:04 PM PDT 24
Peak memory 201036 kb
Host smart-7824b88f-2ae4-4d10-8643-9c95b2f6b505
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618791448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.3618791448
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1576267061
Short name T866
Test name
Test status
Simulation time 58890235 ps
CPU time 0.92 seconds
Started Jul 28 05:09:32 PM PDT 24
Finished Jul 28 05:09:33 PM PDT 24
Peak memory 201084 kb
Host smart-8c8e5be2-8bf9-44a7-b911-4362af7b3373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576267061 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1576267061
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.287624476
Short name T836
Test name
Test status
Simulation time 17852285 ps
CPU time 0.82 seconds
Started Jul 28 05:09:14 PM PDT 24
Finished Jul 28 05:09:15 PM PDT 24
Peak memory 201004 kb
Host smart-9d5262e2-c3f7-46ae-937d-475c5cdd0c3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287624476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.c
lkmgr_csr_rw.287624476
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.615524448
Short name T889
Test name
Test status
Simulation time 36365482 ps
CPU time 0.75 seconds
Started Jul 28 05:09:01 PM PDT 24
Finished Jul 28 05:09:02 PM PDT 24
Peak memory 199604 kb
Host smart-448abfa3-f98c-4663-a6ab-245931db15c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615524448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.615524448
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.635413726
Short name T872
Test name
Test status
Simulation time 142566282 ps
CPU time 1.4 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:19 PM PDT 24
Peak memory 201016 kb
Host smart-f7492a75-6b22-4116-a729-f04a5f05b989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635413726 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.clkmgr_same_csr_outstanding.635413726
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3052067475
Short name T127
Test name
Test status
Simulation time 71015480 ps
CPU time 1.34 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:06 PM PDT 24
Peak memory 201160 kb
Host smart-e4591b63-7693-4605-8e51-e93e83b779d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052067475 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.3052067475
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.251122131
Short name T947
Test name
Test status
Simulation time 177205031 ps
CPU time 3.14 seconds
Started Jul 28 05:09:12 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 201764 kb
Host smart-cc8ef09b-8f20-43e9-ad70-7a9e4f177884
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251122131 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.251122131
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.132549654
Short name T908
Test name
Test status
Simulation time 66029154 ps
CPU time 1.75 seconds
Started Jul 28 05:09:14 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 201196 kb
Host smart-72f8fc65-d069-4cd7-8da3-fe3434024801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132549654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.132549654
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1445800827
Short name T928
Test name
Test status
Simulation time 132586721 ps
CPU time 2.81 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:34 PM PDT 24
Peak memory 201184 kb
Host smart-f95d674f-941e-443d-9d84-04fbc3d286a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445800827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.1445800827
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1597514252
Short name T888
Test name
Test status
Simulation time 31919360 ps
CPU time 0.7 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 199712 kb
Host smart-522fd26b-1668-4c4c-b182-14e1d24602f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597514252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.1597514252
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2700843376
Short name T931
Test name
Test status
Simulation time 96005408 ps
CPU time 0.84 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 199532 kb
Host smart-9b7b5c6b-944d-4c52-a72b-340600e310e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700843376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.2700843376
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3858466781
Short name T864
Test name
Test status
Simulation time 13963286 ps
CPU time 0.65 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 199656 kb
Host smart-ac34bc45-a0ad-4b82-8893-99f23bdbfe45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858466781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.3858466781
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.646177985
Short name T887
Test name
Test status
Simulation time 11635338 ps
CPU time 0.67 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 199532 kb
Host smart-0d6b3295-f72e-4ac2-a0e6-c6af371b2a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646177985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clk
mgr_intr_test.646177985
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.888027014
Short name T912
Test name
Test status
Simulation time 46986709 ps
CPU time 0.69 seconds
Started Jul 28 05:09:21 PM PDT 24
Finished Jul 28 05:09:22 PM PDT 24
Peak memory 199608 kb
Host smart-2fc96445-07a9-4f8b-95ab-d1a1ac614f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888027014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk
mgr_intr_test.888027014
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.890212044
Short name T965
Test name
Test status
Simulation time 19651352 ps
CPU time 0.69 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 199612 kb
Host smart-3de34e42-0f5b-46f1-8934-d59e945e8868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890212044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk
mgr_intr_test.890212044
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1007046464
Short name T954
Test name
Test status
Simulation time 21230418 ps
CPU time 0.68 seconds
Started Jul 28 05:09:30 PM PDT 24
Finished Jul 28 05:09:31 PM PDT 24
Peak memory 199556 kb
Host smart-87dd4634-845f-47ff-abb5-2eaab3228de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007046464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.1007046464
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.4204729044
Short name T837
Test name
Test status
Simulation time 13502932 ps
CPU time 0.69 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:09:43 PM PDT 24
Peak memory 199608 kb
Host smart-867609e8-4f80-41a8-a92b-35d25185517f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204729044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.4204729044
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2367332623
Short name T974
Test name
Test status
Simulation time 12474994 ps
CPU time 0.72 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 199660 kb
Host smart-a4cc7948-aa67-40f1-bc3a-6074de34308a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367332623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.2367332623
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3588520170
Short name T920
Test name
Test status
Simulation time 12843185 ps
CPU time 0.65 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 199576 kb
Host smart-d9150484-b7d4-41be-976b-b850f55f0b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588520170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.3588520170
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.819813466
Short name T883
Test name
Test status
Simulation time 27797719 ps
CPU time 1.43 seconds
Started Jul 28 05:09:54 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 201232 kb
Host smart-bf79243e-7fee-4e11-8d32-eb63bcab1345
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819813466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_aliasing.819813466
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.692056243
Short name T869
Test name
Test status
Simulation time 277362621 ps
CPU time 4.58 seconds
Started Jul 28 05:09:20 PM PDT 24
Finished Jul 28 05:09:25 PM PDT 24
Peak memory 201096 kb
Host smart-da9a0460-5087-49ec-b2e5-f6e0ce86a7ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692056243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_bit_bash.692056243
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2690627356
Short name T841
Test name
Test status
Simulation time 66837095 ps
CPU time 0.92 seconds
Started Jul 28 05:09:11 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 201024 kb
Host smart-9dcfe89d-0b9c-4e98-a854-f5f5561cf7c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690627356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.2690627356
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.4266955307
Short name T838
Test name
Test status
Simulation time 106205252 ps
CPU time 1.97 seconds
Started Jul 28 05:09:09 PM PDT 24
Finished Jul 28 05:09:11 PM PDT 24
Peak memory 201344 kb
Host smart-2119b445-6979-48f6-8b77-202c914c0786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266955307 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.4266955307
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3077601513
Short name T847
Test name
Test status
Simulation time 15666224 ps
CPU time 0.76 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 200972 kb
Host smart-55bf4e80-f816-429e-9923-9e069b9a970c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077601513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.3077601513
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2455654764
Short name T885
Test name
Test status
Simulation time 13799565 ps
CPU time 0.71 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 199592 kb
Host smart-25a14c4a-a993-40da-80ea-a0cea04e0678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455654764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.2455654764
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3745002206
Short name T846
Test name
Test status
Simulation time 59901303 ps
CPU time 1.06 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:18 PM PDT 24
Peak memory 201004 kb
Host smart-533baebe-b3ab-4b8b-919a-43a0f73709c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745002206 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.3745002206
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3316683759
Short name T135
Test name
Test status
Simulation time 121991678 ps
CPU time 1.94 seconds
Started Jul 28 05:09:10 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 209604 kb
Host smart-e69411d7-deb7-48ba-97c8-407e841a5158
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316683759 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.3316683759
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3623133775
Short name T63
Test name
Test status
Simulation time 217959825 ps
CPU time 2.76 seconds
Started Jul 28 05:09:05 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 201772 kb
Host smart-f11097fb-9be1-4902-9bc5-e4474ed1e131
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623133775 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.3623133775
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1742227831
Short name T174
Test name
Test status
Simulation time 132441187 ps
CPU time 3.38 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 201180 kb
Host smart-a8ab30a2-f1f3-40ab-a94a-441bcb61f494
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742227831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.1742227831
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.759406213
Short name T112
Test name
Test status
Simulation time 197036203 ps
CPU time 1.94 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:05 PM PDT 24
Peak memory 201272 kb
Host smart-e66ec34c-851e-447d-87f5-0ec3c00be368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759406213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_tl_intg_err.759406213
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.88592160
Short name T833
Test name
Test status
Simulation time 60230227 ps
CPU time 0.77 seconds
Started Jul 28 05:09:51 PM PDT 24
Finished Jul 28 05:09:52 PM PDT 24
Peak memory 199692 kb
Host smart-7278b93f-45ee-48b7-8369-3f461f3a845c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88592160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkm
gr_intr_test.88592160
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2683161065
Short name T900
Test name
Test status
Simulation time 30288974 ps
CPU time 0.68 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 199668 kb
Host smart-86069ec7-8ab3-4133-bf1e-d9c3359d3539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683161065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.2683161065
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1246109697
Short name T934
Test name
Test status
Simulation time 60481648 ps
CPU time 0.76 seconds
Started Jul 28 05:09:31 PM PDT 24
Finished Jul 28 05:09:31 PM PDT 24
Peak memory 199640 kb
Host smart-287d4be0-7463-4277-8500-8d053bdcf624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246109697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.1246109697
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1530558714
Short name T945
Test name
Test status
Simulation time 35799622 ps
CPU time 0.7 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 199608 kb
Host smart-f8fc0bbc-54d0-4895-a5f9-8dc2f7103606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530558714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.1530558714
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.842965603
Short name T874
Test name
Test status
Simulation time 16322544 ps
CPU time 0.63 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 199680 kb
Host smart-ad8e3b17-2111-48ba-8aa3-edee5769f62c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842965603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk
mgr_intr_test.842965603
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3725880697
Short name T891
Test name
Test status
Simulation time 14770184 ps
CPU time 0.68 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 199632 kb
Host smart-21a5dbc5-0a94-4add-8427-c93da168c5b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725880697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.3725880697
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2351390070
Short name T832
Test name
Test status
Simulation time 12546617 ps
CPU time 0.66 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 199560 kb
Host smart-03a4f77c-64aa-488b-9a3f-a50e03ee0d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351390070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.2351390070
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.317831762
Short name T903
Test name
Test status
Simulation time 36283186 ps
CPU time 0.72 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 199684 kb
Host smart-fe87fbb1-5962-4e3c-ac00-279cb4b7c9cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317831762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk
mgr_intr_test.317831762
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3256506873
Short name T845
Test name
Test status
Simulation time 28445973 ps
CPU time 0.68 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:29 PM PDT 24
Peak memory 199664 kb
Host smart-61f09f17-6f52-4ad2-b2c3-dc9cd0cc4b85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256506873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.3256506873
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1394778831
Short name T927
Test name
Test status
Simulation time 11841389 ps
CPU time 0.67 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:43 PM PDT 24
Peak memory 199696 kb
Host smart-6df79119-731d-402b-a397-0ceaeb248796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394778831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.1394778831
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1107908870
Short name T860
Test name
Test status
Simulation time 30981463 ps
CPU time 1.47 seconds
Started Jul 28 05:09:21 PM PDT 24
Finished Jul 28 05:09:23 PM PDT 24
Peak memory 201160 kb
Host smart-0902ea5b-95cd-47b5-82ae-643593f4ed2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107908870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.1107908870
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1929541454
Short name T901
Test name
Test status
Simulation time 705023275 ps
CPU time 7.72 seconds
Started Jul 28 05:09:10 PM PDT 24
Finished Jul 28 05:09:18 PM PDT 24
Peak memory 201240 kb
Host smart-0be48d09-7ee8-4871-8079-5a6ede21c98f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929541454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1929541454
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1653894035
Short name T938
Test name
Test status
Simulation time 38389395 ps
CPU time 0.8 seconds
Started Jul 28 05:09:13 PM PDT 24
Finished Jul 28 05:09:14 PM PDT 24
Peak memory 200928 kb
Host smart-2ed45bad-5b47-4de6-85d1-cc05266782e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653894035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1653894035
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3869663011
Short name T955
Test name
Test status
Simulation time 39821962 ps
CPU time 0.96 seconds
Started Jul 28 05:09:09 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 200964 kb
Host smart-5c3cb49a-65f0-4f0b-b8a4-8e56f7a2ce16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869663011 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.3869663011
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2049893796
Short name T939
Test name
Test status
Simulation time 18622570 ps
CPU time 0.78 seconds
Started Jul 28 05:09:21 PM PDT 24
Finished Jul 28 05:09:22 PM PDT 24
Peak memory 200928 kb
Host smart-f84a4163-f653-4812-95a0-1818cbc6cd87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049893796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.2049893796
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.752644630
Short name T878
Test name
Test status
Simulation time 14851635 ps
CPU time 0.7 seconds
Started Jul 28 05:09:23 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 199632 kb
Host smart-9c8c7d26-edec-4274-82c3-91ffbc72a474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752644630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkm
gr_intr_test.752644630
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2162125684
Short name T863
Test name
Test status
Simulation time 95814776 ps
CPU time 1.45 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:06 PM PDT 24
Peak memory 201228 kb
Host smart-a496997b-0528-4b2d-9cce-f5eed02c637b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162125684 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.2162125684
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1085888533
Short name T961
Test name
Test status
Simulation time 70584710 ps
CPU time 1.31 seconds
Started Jul 28 05:09:20 PM PDT 24
Finished Jul 28 05:09:22 PM PDT 24
Peak memory 201188 kb
Host smart-7d5bd8fd-617f-4612-98d9-91ea8167d778
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085888533 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.1085888533
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.141054031
Short name T133
Test name
Test status
Simulation time 244593966 ps
CPU time 2.65 seconds
Started Jul 28 05:09:26 PM PDT 24
Finished Jul 28 05:09:29 PM PDT 24
Peak memory 209924 kb
Host smart-6ae6ed48-3be9-4df3-b53b-499f8a7722f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141054031 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.141054031
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3847706136
Short name T922
Test name
Test status
Simulation time 41046713 ps
CPU time 2.22 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 201168 kb
Host smart-80f79a53-4acc-46b0-825b-72f450e3708d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847706136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.3847706136
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3515603322
Short name T188
Test name
Test status
Simulation time 290626562 ps
CPU time 3.15 seconds
Started Jul 28 05:09:06 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 201128 kb
Host smart-f10df180-cbbc-4ef3-8e8f-d23be5e11701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515603322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.3515603322
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2835811284
Short name T881
Test name
Test status
Simulation time 20872578 ps
CPU time 0.68 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 199868 kb
Host smart-ed35dd84-3b01-48ec-b74f-31b6ed7b185d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835811284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.2835811284
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2171094095
Short name T897
Test name
Test status
Simulation time 13607009 ps
CPU time 0.67 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 199796 kb
Host smart-f92e95a7-4aa6-4832-9e1d-92a6534e1fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171094095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2171094095
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1287613693
Short name T910
Test name
Test status
Simulation time 14202628 ps
CPU time 0.68 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 199612 kb
Host smart-ea9fce68-0f69-49bd-aa76-0086bf932e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287613693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.1287613693
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1380497824
Short name T932
Test name
Test status
Simulation time 14991181 ps
CPU time 0.7 seconds
Started Jul 28 05:09:47 PM PDT 24
Finished Jul 28 05:09:48 PM PDT 24
Peak memory 199796 kb
Host smart-8c32ab2d-74eb-44f2-b24e-55d3deb586b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380497824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1380497824
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3379556055
Short name T880
Test name
Test status
Simulation time 74002000 ps
CPU time 0.79 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:09:41 PM PDT 24
Peak memory 199692 kb
Host smart-63808c2a-1a6f-4d76-b7ab-2e4706bd2165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379556055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.3379556055
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1174663620
Short name T958
Test name
Test status
Simulation time 30345412 ps
CPU time 0.68 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 199592 kb
Host smart-8953df22-890b-44ce-af06-1727eb82230b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174663620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.1174663620
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3871092121
Short name T858
Test name
Test status
Simulation time 11436619 ps
CPU time 0.66 seconds
Started Jul 28 05:09:31 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 199604 kb
Host smart-c7cb7e91-25ce-4e60-952c-4217bb84c36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871092121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.3871092121
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.645185429
Short name T970
Test name
Test status
Simulation time 37138637 ps
CPU time 0.72 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:09:59 PM PDT 24
Peak memory 199884 kb
Host smart-5bd9e80a-ffd4-4a23-813e-61e8880af204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645185429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.645185429
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1798152348
Short name T967
Test name
Test status
Simulation time 11103274 ps
CPU time 0.67 seconds
Started Jul 28 05:09:38 PM PDT 24
Finished Jul 28 05:09:39 PM PDT 24
Peak memory 199504 kb
Host smart-0c585857-38f7-4f4b-9433-24f23e652c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798152348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.1798152348
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.3047783124
Short name T929
Test name
Test status
Simulation time 11878389 ps
CPU time 0.65 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 199672 kb
Host smart-28ef688d-8f67-4607-9d35-d413e38694d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047783124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.3047783124
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2032719373
Short name T840
Test name
Test status
Simulation time 66933700 ps
CPU time 1.13 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 200908 kb
Host smart-18e17224-201e-4e94-912d-bff540f6bb1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032719373 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.2032719373
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.753353007
Short name T957
Test name
Test status
Simulation time 16621480 ps
CPU time 0.84 seconds
Started Jul 28 05:09:24 PM PDT 24
Finished Jul 28 05:09:25 PM PDT 24
Peak memory 200948 kb
Host smart-a2200d57-87dc-43ce-8287-c77c2cf00e82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753353007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.c
lkmgr_csr_rw.753353007
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1837256056
Short name T941
Test name
Test status
Simulation time 63220787 ps
CPU time 0.76 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 199592 kb
Host smart-4e742d27-ce25-49d7-ae34-02d2f50b798b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837256056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.1837256056
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.224737381
Short name T834
Test name
Test status
Simulation time 56035683 ps
CPU time 1.38 seconds
Started Jul 28 05:09:04 PM PDT 24
Finished Jul 28 05:09:06 PM PDT 24
Peak memory 201468 kb
Host smart-cc545279-8844-4d94-a6ff-51a5aabce1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224737381 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.clkmgr_same_csr_outstanding.224737381
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2481346205
Short name T951
Test name
Test status
Simulation time 59382820 ps
CPU time 1.3 seconds
Started Jul 28 05:09:01 PM PDT 24
Finished Jul 28 05:09:03 PM PDT 24
Peak memory 201260 kb
Host smart-fd33d843-7911-4137-9bb0-a2636cdb921b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481346205 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.2481346205
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.992567579
Short name T905
Test name
Test status
Simulation time 158616862 ps
CPU time 1.77 seconds
Started Jul 28 05:09:15 PM PDT 24
Finished Jul 28 05:09:17 PM PDT 24
Peak memory 201700 kb
Host smart-718c1584-63b6-4261-b720-9e1a3b3495d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992567579 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.992567579
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.527996266
Short name T919
Test name
Test status
Simulation time 286383310 ps
CPU time 3.32 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:32 PM PDT 24
Peak memory 201256 kb
Host smart-d17a31f6-7dee-440c-9f40-9d0f0fa4b054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527996266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_tl_errors.527996266
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.454453881
Short name T106
Test name
Test status
Simulation time 1187962737 ps
CPU time 5.3 seconds
Started Jul 28 05:09:03 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 201096 kb
Host smart-3ae0f591-a5eb-423d-a765-f483b652a861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454453881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_tl_intg_err.454453881
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.288837026
Short name T861
Test name
Test status
Simulation time 53461744 ps
CPU time 1.11 seconds
Started Jul 28 05:09:25 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 200980 kb
Host smart-479dfe47-7932-4480-a5b2-8a5bc68d2323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288837026 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.288837026
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1141122009
Short name T87
Test name
Test status
Simulation time 17288197 ps
CPU time 0.77 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 200940 kb
Host smart-a11de357-6ff9-48b1-ae22-37bbaa7e0574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141122009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.1141122009
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3691471948
Short name T921
Test name
Test status
Simulation time 13819156 ps
CPU time 0.71 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:27 PM PDT 24
Peak memory 199664 kb
Host smart-5e8017e3-6115-44ca-af1c-271a776d7d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691471948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3691471948
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1690270091
Short name T923
Test name
Test status
Simulation time 204141760 ps
CPU time 1.68 seconds
Started Jul 28 05:09:20 PM PDT 24
Finished Jul 28 05:09:22 PM PDT 24
Peak memory 201232 kb
Host smart-c174cab9-bf70-4865-b86e-fb7cfd4630df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690270091 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1690270091
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2740354567
Short name T137
Test name
Test status
Simulation time 450426171 ps
CPU time 3.65 seconds
Started Jul 28 05:09:21 PM PDT 24
Finished Jul 28 05:09:25 PM PDT 24
Peak memory 209624 kb
Host smart-b1f835dd-2ccb-4127-a2cb-4f6805c138f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740354567 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.2740354567
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2329290726
Short name T173
Test name
Test status
Simulation time 52416926 ps
CPU time 1.5 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:19 PM PDT 24
Peak memory 201188 kb
Host smart-50033be0-34dc-4e4d-b1d3-d699d0a2e302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329290726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.2329290726
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.94627380
Short name T946
Test name
Test status
Simulation time 127314065 ps
CPU time 2.58 seconds
Started Jul 28 05:09:10 PM PDT 24
Finished Jul 28 05:09:13 PM PDT 24
Peak memory 201116 kb
Host smart-5771f7b8-ace1-4aa0-bd61-9e34c6ecc50d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94627380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.clkmgr_tl_intg_err.94627380
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3926037717
Short name T828
Test name
Test status
Simulation time 142984889 ps
CPU time 1.61 seconds
Started Jul 28 05:09:09 PM PDT 24
Finished Jul 28 05:09:11 PM PDT 24
Peak memory 201256 kb
Host smart-1d7ac889-70aa-407d-8b40-0a520ea824e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926037717 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.3926037717
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2404829789
Short name T924
Test name
Test status
Simulation time 16745961 ps
CPU time 0.81 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:29 PM PDT 24
Peak memory 201028 kb
Host smart-dc7058a7-74da-4d07-a339-247cc26a0675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404829789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.2404829789
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.458236743
Short name T844
Test name
Test status
Simulation time 14120679 ps
CPU time 0.67 seconds
Started Jul 28 05:09:11 PM PDT 24
Finished Jul 28 05:09:11 PM PDT 24
Peak memory 199612 kb
Host smart-bcd73d3a-1c83-4b25-90d9-5bf6ae916837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458236743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm
gr_intr_test.458236743
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4235317335
Short name T134
Test name
Test status
Simulation time 119498429 ps
CPU time 1.95 seconds
Started Jul 28 05:09:09 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 217116 kb
Host smart-6a288674-5197-497b-af80-24c1a060387a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235317335 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.4235317335
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3374066907
Short name T61
Test name
Test status
Simulation time 286972792 ps
CPU time 3.42 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:12 PM PDT 24
Peak memory 209692 kb
Host smart-96e0613b-5b6d-4cd6-b79e-db7b895d1b49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374066907 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3374066907
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1876985573
Short name T893
Test name
Test status
Simulation time 45143007 ps
CPU time 1.66 seconds
Started Jul 28 05:09:08 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 201232 kb
Host smart-3ef4dde7-fed3-4142-a305-33dd5b37deab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876985573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.1876985573
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2318034744
Short name T870
Test name
Test status
Simulation time 79028949 ps
CPU time 1.39 seconds
Started Jul 28 05:09:24 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 200988 kb
Host smart-4bea34eb-05b1-45da-a6cd-a29ee27b3d97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318034744 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.2318034744
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4001930104
Short name T171
Test name
Test status
Simulation time 26067477 ps
CPU time 0.79 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 200884 kb
Host smart-10fb4875-3e35-4f68-b42d-05ac3fa36a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001930104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.4001930104
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2285182748
Short name T907
Test name
Test status
Simulation time 34382788 ps
CPU time 0.69 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 199824 kb
Host smart-f377c911-0815-40b6-9cbf-c0c09f5470fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285182748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.2285182748
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.236299446
Short name T899
Test name
Test status
Simulation time 64141462 ps
CPU time 1.52 seconds
Started Jul 28 05:09:29 PM PDT 24
Finished Jul 28 05:09:30 PM PDT 24
Peak memory 201200 kb
Host smart-1e184544-896b-42fc-bab1-9cf9501f3491
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236299446 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.clkmgr_same_csr_outstanding.236299446
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.290396413
Short name T926
Test name
Test status
Simulation time 112366414 ps
CPU time 1.22 seconds
Started Jul 28 05:09:09 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 201224 kb
Host smart-98e14614-5b03-4924-82c4-e7eb580d9290
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290396413 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.clkmgr_shadow_reg_errors.290396413
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2459461165
Short name T963
Test name
Test status
Simulation time 115950573 ps
CPU time 2.56 seconds
Started Jul 28 05:09:24 PM PDT 24
Finished Jul 28 05:09:27 PM PDT 24
Peak memory 209688 kb
Host smart-372993b7-8a71-445f-be45-7ae4194568cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459461165 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2459461165
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.810809122
Short name T968
Test name
Test status
Simulation time 332731601 ps
CPU time 3.3 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:26 PM PDT 24
Peak memory 201188 kb
Host smart-cb3874d5-c564-4944-97ab-ee8abcdd6808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810809122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.810809122
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1053695537
Short name T973
Test name
Test status
Simulation time 69731658 ps
CPU time 1.64 seconds
Started Jul 28 05:09:14 PM PDT 24
Finished Jul 28 05:09:16 PM PDT 24
Peak memory 201440 kb
Host smart-aab1370a-136f-4e4d-92e9-57fc90d357f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053695537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.1053695537
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3309397315
Short name T876
Test name
Test status
Simulation time 82849403 ps
CPU time 1.03 seconds
Started Jul 28 05:09:24 PM PDT 24
Finished Jul 28 05:09:25 PM PDT 24
Peak memory 201080 kb
Host smart-84b90007-e7f5-49ce-87fc-0a69a3f8fb18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309397315 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.3309397315
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.1765468745
Short name T956
Test name
Test status
Simulation time 19906748 ps
CPU time 0.81 seconds
Started Jul 28 05:09:22 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 200976 kb
Host smart-45751dc0-13a7-4dd9-bb61-6decb4c58b0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765468745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.1765468745
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.826672599
Short name T879
Test name
Test status
Simulation time 23666618 ps
CPU time 0.69 seconds
Started Jul 28 05:09:27 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 199584 kb
Host smart-96aa4f61-6805-41b7-9a4b-9005e68fd168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826672599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm
gr_intr_test.826672599
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2853030087
Short name T85
Test name
Test status
Simulation time 359501906 ps
CPU time 1.98 seconds
Started Jul 28 05:09:17 PM PDT 24
Finished Jul 28 05:09:19 PM PDT 24
Peak memory 201244 kb
Host smart-8957b1e4-db39-47b8-b31d-0872f598bf5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853030087 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.2853030087
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1113768631
Short name T136
Test name
Test status
Simulation time 408202106 ps
CPU time 2.59 seconds
Started Jul 28 05:09:07 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 201416 kb
Host smart-0bb13861-abb2-434b-8228-1953615eb12b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113768631 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.1113768631
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3793782264
Short name T953
Test name
Test status
Simulation time 179956523 ps
CPU time 3.18 seconds
Started Jul 28 05:09:18 PM PDT 24
Finished Jul 28 05:09:27 PM PDT 24
Peak memory 201664 kb
Host smart-f3506c32-b9d8-42ae-8cb6-45f04d556eb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793782264 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.3793782264
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2522223631
Short name T827
Test name
Test status
Simulation time 125881137 ps
CPU time 3.76 seconds
Started Jul 28 05:09:28 PM PDT 24
Finished Jul 28 05:09:33 PM PDT 24
Peak memory 201260 kb
Host smart-5c1119fa-6700-4a8b-84d9-57b6b8faad43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522223631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.2522223631
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.2349337287
Short name T597
Test name
Test status
Simulation time 99369311 ps
CPU time 0.96 seconds
Started Jul 28 05:09:49 PM PDT 24
Finished Jul 28 05:09:50 PM PDT 24
Peak memory 200432 kb
Host smart-55dda657-84d5-47df-a7df-a4009b4450f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349337287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.2349337287
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1736371911
Short name T620
Test name
Test status
Simulation time 22390110 ps
CPU time 0.87 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 200432 kb
Host smart-f53237df-af5d-430b-9991-d8c6de22b4de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736371911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.1736371911
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.781857338
Short name T760
Test name
Test status
Simulation time 37226912 ps
CPU time 0.74 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 199684 kb
Host smart-9d7c4d97-89cc-40f1-a5f2-2d07f1022b17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781857338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.781857338
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.547562575
Short name T332
Test name
Test status
Simulation time 246025096 ps
CPU time 1.45 seconds
Started Jul 28 05:09:29 PM PDT 24
Finished Jul 28 05:09:30 PM PDT 24
Peak memory 200388 kb
Host smart-5948d0cb-20c6-49bb-93cd-04cc4ad4eaa4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547562575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_div_intersig_mubi.547562575
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.2711910985
Short name T77
Test name
Test status
Simulation time 15012186 ps
CPU time 0.76 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200392 kb
Host smart-502d2de5-e160-4123-97d4-087333c2cf21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711910985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2711910985
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.3405278568
Short name T555
Test name
Test status
Simulation time 2120704444 ps
CPU time 15.35 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200644 kb
Host smart-caf03525-2f9f-44f5-93ac-b39788237295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405278568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3405278568
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.1190755422
Short name T203
Test name
Test status
Simulation time 742364626 ps
CPU time 4.35 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:39 PM PDT 24
Peak memory 200508 kb
Host smart-f15b80ba-a44b-4cec-99e9-436c9aeb8908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190755422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.1190755422
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.4155798199
Short name T775
Test name
Test status
Simulation time 21850162 ps
CPU time 0.82 seconds
Started Jul 28 05:09:33 PM PDT 24
Finished Jul 28 05:09:34 PM PDT 24
Peak memory 200496 kb
Host smart-cad14b6b-52ca-470c-bca1-0026d6448761
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155798199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.4155798199
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.615883451
Short name T492
Test name
Test status
Simulation time 70911946 ps
CPU time 0.99 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 200488 kb
Host smart-cf9952e1-7641-4ac1-8073-9257402e15d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615883451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.615883451
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.4191617895
Short name T752
Test name
Test status
Simulation time 22457229 ps
CPU time 0.8 seconds
Started Jul 28 05:09:46 PM PDT 24
Finished Jul 28 05:09:46 PM PDT 24
Peak memory 200456 kb
Host smart-b16978bc-7886-4852-a6e4-7b7cc1a95ba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191617895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.4191617895
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.1559353141
Short name T102
Test name
Test status
Simulation time 510469378 ps
CPU time 2.35 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200460 kb
Host smart-2e9ad8ff-c79e-4be6-b177-a5fe129bdf71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559353141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1559353141
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.2959843599
Short name T53
Test name
Test status
Simulation time 319130983 ps
CPU time 2.27 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 220260 kb
Host smart-c90f2039-d610-4815-964b-4455e564864f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959843599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.2959843599
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.2896456482
Short name T432
Test name
Test status
Simulation time 337723886 ps
CPU time 1.73 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200368 kb
Host smart-40547c01-e284-44ff-b119-cba0905584f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896456482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2896456482
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.4169464201
Short name T665
Test name
Test status
Simulation time 2057501926 ps
CPU time 16.12 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 200764 kb
Host smart-9d7043f8-597c-4ced-acba-bc9862261c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169464201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.4169464201
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.2017331677
Short name T195
Test name
Test status
Simulation time 83458460 ps
CPU time 1.13 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 200392 kb
Host smart-c5b13374-5011-4c74-a4e9-866cfe280af3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017331677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2017331677
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.557493463
Short name T490
Test name
Test status
Simulation time 36350360 ps
CPU time 0.85 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200440 kb
Host smart-4097e6dc-a869-45b7-8e05-5063e0f71283
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557493463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.557493463
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.501706972
Short name T322
Test name
Test status
Simulation time 16542225 ps
CPU time 0.72 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 199728 kb
Host smart-5bfcae4a-b1b9-4e5a-910d-851c59f3f332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501706972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.501706972
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.2408725204
Short name T678
Test name
Test status
Simulation time 35370019 ps
CPU time 0.88 seconds
Started Jul 28 05:09:49 PM PDT 24
Finished Jul 28 05:09:50 PM PDT 24
Peak memory 200436 kb
Host smart-e6c496a5-3ade-42d9-b2d4-c2c62f8898e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408725204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.2408725204
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.463898392
Short name T732
Test name
Test status
Simulation time 30023135 ps
CPU time 0.9 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:52 PM PDT 24
Peak memory 200468 kb
Host smart-cf47b817-53c4-421a-88f9-812afde985e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463898392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.463898392
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.1843204632
Short name T23
Test name
Test status
Simulation time 927154607 ps
CPU time 3.99 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:50 PM PDT 24
Peak memory 200420 kb
Host smart-988e0481-efbb-4594-b45e-91c5914c0a44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843204632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1843204632
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.1870211625
Short name T747
Test name
Test status
Simulation time 1459554252 ps
CPU time 10.51 seconds
Started Jul 28 05:09:36 PM PDT 24
Finished Jul 28 05:09:47 PM PDT 24
Peak memory 200616 kb
Host smart-7f1bdecf-bb59-4fe8-bf69-ff9d653f5c0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870211625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.1870211625
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.3566226570
Short name T267
Test name
Test status
Simulation time 73053116 ps
CPU time 0.99 seconds
Started Jul 28 05:09:44 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 200420 kb
Host smart-0d69f9d5-72a2-4545-bd5a-0b3c24ebbfb9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566226570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.3566226570
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2096690661
Short name T275
Test name
Test status
Simulation time 21789484 ps
CPU time 0.83 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:43 PM PDT 24
Peak memory 200424 kb
Host smart-32088a47-d94d-4e77-9a8e-823843cc6011
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096690661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.2096690661
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.822653741
Short name T530
Test name
Test status
Simulation time 19591011 ps
CPU time 0.73 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200484 kb
Host smart-bf13dfea-f57a-49c1-bc1f-fe9e55c703fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822653741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_ctrl_intersig_mubi.822653741
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2768776867
Short name T496
Test name
Test status
Simulation time 15348873 ps
CPU time 0.78 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:43 PM PDT 24
Peak memory 200364 kb
Host smart-af430428-2532-48a5-84f1-ed6f59c536e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768776867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2768776867
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.2302146420
Short name T331
Test name
Test status
Simulation time 149031725 ps
CPU time 1.38 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 200396 kb
Host smart-9eed0805-fcff-419b-828c-8e3c15bd74c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302146420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2302146420
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.424928966
Short name T104
Test name
Test status
Simulation time 18646335 ps
CPU time 0.83 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 200408 kb
Host smart-6677f051-86ef-4d2f-95b0-7e04a04b27ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424928966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.424928966
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.1244557462
Short name T12
Test name
Test status
Simulation time 6536799324 ps
CPU time 34.52 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:10:14 PM PDT 24
Peak memory 200768 kb
Host smart-d6498e52-bfe5-49b8-bf1b-cc36d8212628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244557462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.1244557462
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.2264188776
Short name T28
Test name
Test status
Simulation time 86783973260 ps
CPU time 548.58 seconds
Started Jul 28 05:09:37 PM PDT 24
Finished Jul 28 05:18:45 PM PDT 24
Peak memory 209156 kb
Host smart-5cc7e99c-5fa3-4d5f-b8a2-f436239dd8dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2264188776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.2264188776
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.clkmgr_trans.3048386257
Short name T315
Test name
Test status
Simulation time 24895799 ps
CPU time 0.93 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 200684 kb
Host smart-b630f13a-11a7-4545-a21e-ae9d629ef3b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048386257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3048386257
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.1158428398
Short name T483
Test name
Test status
Simulation time 17987713 ps
CPU time 0.78 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200484 kb
Host smart-430614fd-1ae6-4f8c-b7db-b562ed1d18a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158428398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.1158428398
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.3140393962
Short name T723
Test name
Test status
Simulation time 108107574 ps
CPU time 1.2 seconds
Started Jul 28 05:09:46 PM PDT 24
Finished Jul 28 05:09:48 PM PDT 24
Peak memory 200424 kb
Host smart-67b00528-e985-4ccf-b956-e8b5ebf55cf5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140393962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.3140393962
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.3267511819
Short name T50
Test name
Test status
Simulation time 22192010 ps
CPU time 0.73 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 199644 kb
Host smart-c7935809-6576-4a81-8375-33e688f7ccee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267511819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3267511819
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.161377937
Short name T272
Test name
Test status
Simulation time 35280953 ps
CPU time 0.81 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200404 kb
Host smart-86ef2085-bf4a-45f0-a636-dff6e91118b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161377937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_div_intersig_mubi.161377937
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.1910604118
Short name T284
Test name
Test status
Simulation time 40477856 ps
CPU time 0.96 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200408 kb
Host smart-c2b1d968-6b31-46b2-ae71-81300d8fde43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910604118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1910604118
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.3219595011
Short name T212
Test name
Test status
Simulation time 1874938402 ps
CPU time 13.73 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:15 PM PDT 24
Peak memory 200660 kb
Host smart-8ddf9a00-9b90-4a3a-8869-95ab1038dd9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219595011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3219595011
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.2591196987
Short name T519
Test name
Test status
Simulation time 1406133567 ps
CPU time 6.31 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:13 PM PDT 24
Peak memory 200480 kb
Host smart-1dcb2df3-8686-43e5-a8e9-3dc8649d742d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591196987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.2591196987
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.175321186
Short name T712
Test name
Test status
Simulation time 33685153 ps
CPU time 0.84 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200460 kb
Host smart-f321b2c8-25d2-44b2-9544-65f8ac513b5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175321186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_idle_intersig_mubi.175321186
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1331531498
Short name T163
Test name
Test status
Simulation time 67249688 ps
CPU time 0.94 seconds
Started Jul 28 05:10:12 PM PDT 24
Finished Jul 28 05:10:13 PM PDT 24
Peak memory 200524 kb
Host smart-84f59d3b-819c-4ded-a89b-e3101caad160
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331531498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.1331531498
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1354997736
Short name T303
Test name
Test status
Simulation time 80573685 ps
CPU time 0.99 seconds
Started Jul 28 05:09:52 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 200412 kb
Host smart-e5dfd857-72f5-4c7e-acbb-7f6686d38384
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354997736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.1354997736
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.1454280952
Short name T435
Test name
Test status
Simulation time 15132965 ps
CPU time 0.8 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200392 kb
Host smart-ce6fa2a9-957b-4ab7-9325-012996729471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454280952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.1454280952
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.1234530171
Short name T46
Test name
Test status
Simulation time 355346314 ps
CPU time 1.87 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:55 PM PDT 24
Peak memory 200400 kb
Host smart-5b6fc3a9-6efa-4a5e-8f9b-fcabb9351671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234530171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.1234530171
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.4051175339
Short name T647
Test name
Test status
Simulation time 71650809 ps
CPU time 0.99 seconds
Started Jul 28 05:09:46 PM PDT 24
Finished Jul 28 05:09:47 PM PDT 24
Peak memory 200368 kb
Host smart-03f92d22-5720-4972-805f-93d6353ef433
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051175339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.4051175339
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.1243990753
Short name T556
Test name
Test status
Simulation time 4600887128 ps
CPU time 33.63 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200796 kb
Host smart-30ab44f1-0dcc-4670-898f-fdea1898c82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243990753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.1243990753
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.2369267040
Short name T247
Test name
Test status
Simulation time 101598730 ps
CPU time 1.1 seconds
Started Jul 28 05:09:57 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200468 kb
Host smart-60a71a44-4466-49b6-827a-32f075c12359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369267040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2369267040
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.1589128347
Short name T207
Test name
Test status
Simulation time 30895351 ps
CPU time 0.81 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200400 kb
Host smart-8a2cf273-a56c-4e7d-929a-675ab7d4d159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589128347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.1589128347
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2213675267
Short name T690
Test name
Test status
Simulation time 58487425 ps
CPU time 0.9 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 200444 kb
Host smart-3060676b-1cd2-4e4a-84c8-f3b0fe9e900a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213675267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.2213675267
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.743291124
Short name T305
Test name
Test status
Simulation time 44425887 ps
CPU time 0.84 seconds
Started Jul 28 05:09:57 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200476 kb
Host smart-9b77fd01-a2d9-4c0e-b9b4-7e176b170580
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743291124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.clkmgr_div_intersig_mubi.743291124
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.960183951
Short name T380
Test name
Test status
Simulation time 19835803 ps
CPU time 0.83 seconds
Started Jul 28 05:10:10 PM PDT 24
Finished Jul 28 05:10:11 PM PDT 24
Peak memory 200692 kb
Host smart-131d629a-f14d-43ce-a2d4-3bbd97787ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960183951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.960183951
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.4280375954
Short name T664
Test name
Test status
Simulation time 1762102360 ps
CPU time 9.54 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 200492 kb
Host smart-e1ca19f4-4926-41a4-aadb-a426c1dde298
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280375954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.4280375954
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.1187439125
Short name T400
Test name
Test status
Simulation time 2178848385 ps
CPU time 15.41 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200872 kb
Host smart-c9d25878-068c-48c5-9f1e-138f299854aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187439125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.1187439125
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.1426411971
Short name T316
Test name
Test status
Simulation time 14375838 ps
CPU time 0.77 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200404 kb
Host smart-cef0a056-6187-4bc0-849e-5f9d4fe4fb9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426411971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.1426411971
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.4028437882
Short name T798
Test name
Test status
Simulation time 77036645 ps
CPU time 1 seconds
Started Jul 28 05:10:08 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 200412 kb
Host smart-ec548473-63f5-4383-9b6c-6fda7701ccb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028437882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.4028437882
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1963774247
Short name T378
Test name
Test status
Simulation time 17633774 ps
CPU time 0.81 seconds
Started Jul 28 05:09:57 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200472 kb
Host smart-c30c3075-09bf-42dd-98ec-4d1e1d97f73e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963774247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.1963774247
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.493843102
Short name T48
Test name
Test status
Simulation time 27205798 ps
CPU time 0.76 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200372 kb
Host smart-f3279873-f323-4625-967f-b4a3d74e6408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493843102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.493843102
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.4078978871
Short name T745
Test name
Test status
Simulation time 727419033 ps
CPU time 4.76 seconds
Started Jul 28 05:09:47 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200536 kb
Host smart-b79e6698-7182-49dd-99f2-30cee2ea31ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078978871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.4078978871
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.2425570078
Short name T255
Test name
Test status
Simulation time 64930787 ps
CPU time 0.99 seconds
Started Jul 28 05:09:44 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 200396 kb
Host smart-20079edd-e201-4d9e-8243-94af5dded074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425570078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.2425570078
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.3883066424
Short name T515
Test name
Test status
Simulation time 6800552991 ps
CPU time 28.46 seconds
Started Jul 28 05:10:18 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200828 kb
Host smart-a6371899-7813-4dad-846a-511276c64c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883066424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.3883066424
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.2453411176
Short name T216
Test name
Test status
Simulation time 91498041 ps
CPU time 1.01 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:52 PM PDT 24
Peak memory 200476 kb
Host smart-c9abf4b0-ff7a-4f35-9162-889980e2c13e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453411176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.2453411176
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.273193490
Short name T721
Test name
Test status
Simulation time 25666857 ps
CPU time 0.77 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200460 kb
Host smart-44d7d008-e99a-4a1e-8fa4-c8e4255c3e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273193490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkm
gr_alert_test.273193490
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.405912744
Short name T694
Test name
Test status
Simulation time 20904481 ps
CPU time 0.82 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200444 kb
Host smart-8d9b0705-6ce4-42ff-bc03-08531c6e993a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405912744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.405912744
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.2569204682
Short name T512
Test name
Test status
Simulation time 66100743 ps
CPU time 0.82 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 199636 kb
Host smart-86ffa5f5-3092-4152-a983-3f58916e6ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569204682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.2569204682
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.2154839369
Short name T245
Test name
Test status
Simulation time 13449284 ps
CPU time 0.7 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:09:59 PM PDT 24
Peak memory 200380 kb
Host smart-8767f2e5-68cc-42af-9394-680a06d2238c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154839369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.2154839369
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.3375873574
Short name T318
Test name
Test status
Simulation time 48709925 ps
CPU time 0.9 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 200420 kb
Host smart-fc5a4f8a-04b0-43d7-b55d-17e7a66b0629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375873574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3375873574
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.636192980
Short name T168
Test name
Test status
Simulation time 1999096173 ps
CPU time 15.6 seconds
Started Jul 28 05:10:12 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200724 kb
Host smart-eea7fd6b-48d5-459b-9376-b29cb46af982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636192980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.636192980
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.3743195675
Short name T223
Test name
Test status
Simulation time 1901747565 ps
CPU time 8.43 seconds
Started Jul 28 05:10:04 PM PDT 24
Finished Jul 28 05:10:12 PM PDT 24
Peak memory 200552 kb
Host smart-8c30b240-8d31-49c0-b0ee-072ac4cd08cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743195675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.3743195675
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.4130481256
Short name T421
Test name
Test status
Simulation time 13197501 ps
CPU time 0.71 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200416 kb
Host smart-9d9bf496-e5ca-4079-ade9-09ea96151b00
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130481256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.4130481256
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.357144017
Short name T478
Test name
Test status
Simulation time 22599282 ps
CPU time 0.86 seconds
Started Jul 28 05:10:15 PM PDT 24
Finished Jul 28 05:10:16 PM PDT 24
Peak memory 200684 kb
Host smart-bdcb31cf-5c04-471d-8802-3229073a8763
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357144017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.357144017
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2300607006
Short name T189
Test name
Test status
Simulation time 224471825 ps
CPU time 1.44 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200504 kb
Host smart-e780788b-632c-47cb-817e-0a1e3976593b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300607006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.2300607006
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.792313207
Short name T319
Test name
Test status
Simulation time 15740152 ps
CPU time 0.72 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200408 kb
Host smart-1e4a6bf0-ec32-4161-bb64-d8cefd5b4650
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792313207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.792313207
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.1843844607
Short name T581
Test name
Test status
Simulation time 1712118687 ps
CPU time 5.24 seconds
Started Jul 28 05:10:06 PM PDT 24
Finished Jul 28 05:10:12 PM PDT 24
Peak memory 200616 kb
Host smart-69e6ac7a-f8ab-4981-b9ce-fcce5b96847a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843844607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1843844607
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.2326774213
Short name T569
Test name
Test status
Simulation time 19275480 ps
CPU time 0.8 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 200432 kb
Host smart-c97911d2-fa7d-4818-afd3-19d86c5ecff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326774213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2326774213
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.1164032685
Short name T288
Test name
Test status
Simulation time 3701547802 ps
CPU time 21.7 seconds
Started Jul 28 05:10:02 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200808 kb
Host smart-5c1eda09-724f-4a6c-a777-d5e5dbad64f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164032685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.1164032685
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.1251032731
Short name T165
Test name
Test status
Simulation time 17630597 ps
CPU time 0.76 seconds
Started Jul 28 05:10:37 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 200428 kb
Host smart-72478023-c57e-41b7-809b-3000ea151348
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251032731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1251032731
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.3645071820
Short name T516
Test name
Test status
Simulation time 49884113 ps
CPU time 0.88 seconds
Started Jul 28 05:10:08 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 200420 kb
Host smart-19e1f430-0c10-4d93-8840-be8cf405fe10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645071820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.3645071820
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.4031207705
Short name T97
Test name
Test status
Simulation time 65297631 ps
CPU time 0.93 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200428 kb
Host smart-f1481853-b80f-42b9-bb87-19e90ea9f368
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031207705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.4031207705
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.2432942515
Short name T38
Test name
Test status
Simulation time 17301689 ps
CPU time 0.73 seconds
Started Jul 28 05:09:46 PM PDT 24
Finished Jul 28 05:09:47 PM PDT 24
Peak memory 199732 kb
Host smart-48cfc9d1-a4c2-431f-983c-f6768a328e37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432942515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2432942515
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.1090442226
Short name T333
Test name
Test status
Simulation time 136405593 ps
CPU time 1.15 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200456 kb
Host smart-e91f591d-1329-467c-b88e-32e7c2f3134a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090442226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.1090442226
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.3866004375
Short name T268
Test name
Test status
Simulation time 251504197 ps
CPU time 1.48 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200400 kb
Host smart-bc41e808-2433-4692-9407-3c9b2b5adf4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866004375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3866004375
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3909774871
Short name T246
Test name
Test status
Simulation time 572144225 ps
CPU time 3.73 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:11 PM PDT 24
Peak memory 200496 kb
Host smart-88ff62ee-7386-40ea-92df-9a4a9ebd876b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909774871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3909774871
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.2982112483
Short name T230
Test name
Test status
Simulation time 1246744654 ps
CPU time 4.49 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:04 PM PDT 24
Peak memory 200548 kb
Host smart-6a4fe3b5-cb35-4b0d-aea8-bd87d6a2806c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982112483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.2982112483
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.1473610485
Short name T560
Test name
Test status
Simulation time 33260583 ps
CPU time 0.82 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200424 kb
Host smart-f79e4451-a71a-49b6-bf9b-cef421b788e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473610485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.1473610485
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1103331816
Short name T649
Test name
Test status
Simulation time 78673921 ps
CPU time 0.91 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200480 kb
Host smart-957d32bf-8f61-4ad3-a523-068741b4858e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103331816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.1103331816
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1186328951
Short name T604
Test name
Test status
Simulation time 40180890 ps
CPU time 0.81 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200472 kb
Host smart-267b0f74-e585-4f89-8871-8b142fedc87f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186328951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.1186328951
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.3173172801
Short name T518
Test name
Test status
Simulation time 90707508 ps
CPU time 1.11 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200368 kb
Host smart-f581274c-099d-48ee-8ce3-db178a998ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173172801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.3173172801
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.3255187098
Short name T271
Test name
Test status
Simulation time 661359594 ps
CPU time 2.9 seconds
Started Jul 28 05:10:12 PM PDT 24
Finished Jul 28 05:10:15 PM PDT 24
Peak memory 200584 kb
Host smart-f37f6e9c-977d-4733-8c85-14212043bcb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255187098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3255187098
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.2065981720
Short name T608
Test name
Test status
Simulation time 47012434 ps
CPU time 0.87 seconds
Started Jul 28 05:10:13 PM PDT 24
Finished Jul 28 05:10:14 PM PDT 24
Peak memory 200360 kb
Host smart-c8d9bed1-dc00-4275-b519-a81383242b04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065981720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2065981720
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.3366907430
Short name T683
Test name
Test status
Simulation time 2287006650 ps
CPU time 17.13 seconds
Started Jul 28 05:10:18 PM PDT 24
Finished Jul 28 05:10:35 PM PDT 24
Peak memory 200756 kb
Host smart-9ff05026-3e83-4997-a51b-96ef6e835746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366907430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.3366907430
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.3774957465
Short name T119
Test name
Test status
Simulation time 163555328 ps
CPU time 1.31 seconds
Started Jul 28 05:09:54 PM PDT 24
Finished Jul 28 05:09:55 PM PDT 24
Peak memory 200464 kb
Host smart-76780a28-bfd9-4987-b1c6-ad6a8f4da6fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774957465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3774957465
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.2248378280
Short name T145
Test name
Test status
Simulation time 77903090 ps
CPU time 1.02 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:20 PM PDT 24
Peak memory 200420 kb
Host smart-0b441f4b-69a0-462e-b8b9-83fba473d0b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248378280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.2248378280
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3062457742
Short name T610
Test name
Test status
Simulation time 14673369 ps
CPU time 0.78 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:17 PM PDT 24
Peak memory 200456 kb
Host smart-a461c20c-d4f2-41b5-930d-12b8cea3a441
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062457742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.3062457742
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.1366612536
Short name T406
Test name
Test status
Simulation time 46016721 ps
CPU time 0.78 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 199632 kb
Host smart-34c98c8e-7248-4c74-8582-3dc195552f3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366612536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1366612536
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.2657734141
Short name T291
Test name
Test status
Simulation time 94500049 ps
CPU time 1.14 seconds
Started Jul 28 05:10:08 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 200464 kb
Host smart-d9c65052-d738-4e80-bcde-87b234687b05
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657734141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.2657734141
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.1825400273
Short name T74
Test name
Test status
Simulation time 16758064 ps
CPU time 0.79 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200460 kb
Host smart-b31611cb-d780-4242-9086-0722197537f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825400273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.1825400273
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.2031885950
Short name T394
Test name
Test status
Simulation time 803082451 ps
CPU time 6.65 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200496 kb
Host smart-f38220ff-814d-4015-8ad1-384e74a10658
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031885950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2031885950
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.2619718717
Short name T616
Test name
Test status
Simulation time 736535243 ps
CPU time 5.48 seconds
Started Jul 28 05:09:49 PM PDT 24
Finished Jul 28 05:09:55 PM PDT 24
Peak memory 200580 kb
Host smart-140f2877-74ba-4658-90e4-412cc050c5cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619718717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.2619718717
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2165818820
Short name T663
Test name
Test status
Simulation time 71212851 ps
CPU time 0.99 seconds
Started Jul 28 05:09:57 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200512 kb
Host smart-39357a1e-125b-40f5-98d4-113c202715d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165818820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.2165818820
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.4024206669
Short name T221
Test name
Test status
Simulation time 23325204 ps
CPU time 0.81 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:20 PM PDT 24
Peak memory 200464 kb
Host smart-a57ab773-6bdc-4396-b5ed-a56a659503ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024206669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.4024206669
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3032556135
Short name T724
Test name
Test status
Simulation time 41095282 ps
CPU time 0.95 seconds
Started Jul 28 05:10:04 PM PDT 24
Finished Jul 28 05:10:05 PM PDT 24
Peak memory 200516 kb
Host smart-27a9d180-ea27-49b5-877f-c49deed19b4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032556135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3032556135
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.1217955786
Short name T438
Test name
Test status
Simulation time 15548116 ps
CPU time 0.75 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200408 kb
Host smart-b34f4cd3-bc86-4afd-97e9-5c0d9158137e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217955786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.1217955786
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.1678124321
Short name T157
Test name
Test status
Simulation time 1092741822 ps
CPU time 6.11 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:13 PM PDT 24
Peak memory 200656 kb
Host smart-503931a1-ee7f-4c18-91c0-a21a460172c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678124321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1678124321
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.2875095809
Short name T384
Test name
Test status
Simulation time 38421318 ps
CPU time 0.86 seconds
Started Jul 28 05:10:13 PM PDT 24
Finished Jul 28 05:10:14 PM PDT 24
Peak memory 200388 kb
Host smart-55c5bdeb-338f-408b-8d19-5cf22376cae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875095809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2875095809
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2950198177
Short name T441
Test name
Test status
Simulation time 4576748925 ps
CPU time 35.1 seconds
Started Jul 28 05:10:03 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 200812 kb
Host smart-614b46df-fb8d-4b31-bc55-dc7febeeb0fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950198177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2950198177
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.3029438555
Short name T671
Test name
Test status
Simulation time 15411390 ps
CPU time 0.77 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 200476 kb
Host smart-f1f4d7be-36e8-46ae-98da-76390767abfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029438555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3029438555
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.3635084837
Short name T497
Test name
Test status
Simulation time 21839064 ps
CPU time 0.88 seconds
Started Jul 28 05:10:18 PM PDT 24
Finished Jul 28 05:10:19 PM PDT 24
Peak memory 200408 kb
Host smart-c3b78201-f660-48cd-bcd4-32536eeffa59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635084837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.3635084837
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1656941660
Short name T494
Test name
Test status
Simulation time 40013220 ps
CPU time 0.87 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 200424 kb
Host smart-05915d26-2462-4c86-bfc7-dc02d8310a4c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656941660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.1656941660
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.4131785891
Short name T45
Test name
Test status
Simulation time 21155934 ps
CPU time 0.73 seconds
Started Jul 28 05:10:08 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 200344 kb
Host smart-e715c2cd-5758-4035-a82b-e268c38c1867
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131785891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.4131785891
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.1372667982
Short name T320
Test name
Test status
Simulation time 45089555 ps
CPU time 0.98 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200480 kb
Host smart-e376b7f5-d897-4c96-92ab-8665e50b88df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372667982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.1372667982
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.1462831481
Short name T460
Test name
Test status
Simulation time 33488843 ps
CPU time 0.85 seconds
Started Jul 28 05:10:06 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200408 kb
Host smart-7a90f657-d7ed-4193-b14d-755d1e6cf0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462831481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.1462831481
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.547682555
Short name T308
Test name
Test status
Simulation time 1309143378 ps
CPU time 5.84 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200496 kb
Host smart-79b1164e-cddf-41c5-ab82-706e2730b0e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547682555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.547682555
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.4033843312
Short name T286
Test name
Test status
Simulation time 1460200506 ps
CPU time 8.98 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200644 kb
Host smart-c9ec1b95-1d88-45af-9830-9891196f0faf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033843312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.4033843312
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.868863010
Short name T584
Test name
Test status
Simulation time 53869639 ps
CPU time 1.03 seconds
Started Jul 28 05:10:11 PM PDT 24
Finished Jul 28 05:10:12 PM PDT 24
Peak memory 200316 kb
Host smart-cde973bf-7186-4544-b825-ae265d93c8c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868863010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_idle_intersig_mubi.868863010
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2381959751
Short name T698
Test name
Test status
Simulation time 13918540 ps
CPU time 0.76 seconds
Started Jul 28 05:10:02 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 200444 kb
Host smart-c6cb7958-2a46-4010-98c1-436ff2bb9663
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381959751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2381959751
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1150709566
Short name T785
Test name
Test status
Simulation time 21681084 ps
CPU time 0.82 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200396 kb
Host smart-be352112-a64f-45f9-a49d-4965137cb5f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150709566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1150709566
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.2907934289
Short name T283
Test name
Test status
Simulation time 14821078 ps
CPU time 0.71 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200324 kb
Host smart-77d94cf4-4d01-4c62-9895-3eaddb5e8568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907934289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.2907934289
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.1254994498
Short name T764
Test name
Test status
Simulation time 468955199 ps
CPU time 2.15 seconds
Started Jul 28 05:10:12 PM PDT 24
Finished Jul 28 05:10:14 PM PDT 24
Peak memory 200436 kb
Host smart-6b7fa2c0-6ce2-481e-ace2-a3559f42f4c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254994498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1254994498
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.3831481605
Short name T144
Test name
Test status
Simulation time 44268466 ps
CPU time 0.93 seconds
Started Jul 28 05:10:11 PM PDT 24
Finished Jul 28 05:10:12 PM PDT 24
Peak memory 200388 kb
Host smart-2254ae45-6b36-49b5-858e-824403729369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831481605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.3831481605
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.965383004
Short name T531
Test name
Test status
Simulation time 4263521188 ps
CPU time 31.7 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200796 kb
Host smart-449af46f-2ed9-4653-80f9-4baa78db5c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965383004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.965383004
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.796984208
Short name T338
Test name
Test status
Simulation time 63706135 ps
CPU time 1.09 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:09:59 PM PDT 24
Peak memory 200444 kb
Host smart-3a9a2f8e-1034-4545-9d48-7f34c42b979e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796984208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.796984208
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.553713797
Short name T782
Test name
Test status
Simulation time 20515232 ps
CPU time 0.73 seconds
Started Jul 28 05:10:05 PM PDT 24
Finished Jul 28 05:10:06 PM PDT 24
Peak memory 200672 kb
Host smart-822234bc-ae47-42cd-b5e3-9ee6241139a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553713797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkm
gr_alert_test.553713797
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3547370377
Short name T270
Test name
Test status
Simulation time 130625667 ps
CPU time 1.17 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 200376 kb
Host smart-400e3518-4538-41b6-8786-e75915642c09
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547370377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.3547370377
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2471625543
Short name T342
Test name
Test status
Simulation time 18352126 ps
CPU time 0.72 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 199684 kb
Host smart-92730bdf-3c7c-4b63-8f1e-6d9ad33d8caf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471625543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2471625543
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3649554803
Short name T655
Test name
Test status
Simulation time 18735404 ps
CPU time 0.76 seconds
Started Jul 28 05:10:05 PM PDT 24
Finished Jul 28 05:10:06 PM PDT 24
Peak memory 200408 kb
Host smart-017ddfeb-d15e-436d-9680-6263804015cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649554803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.3649554803
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.299744899
Short name T452
Test name
Test status
Simulation time 27627208 ps
CPU time 0.78 seconds
Started Jul 28 05:10:17 PM PDT 24
Finished Jul 28 05:10:18 PM PDT 24
Peak memory 200424 kb
Host smart-68e5b775-07a4-4223-85b0-7a3724820df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299744899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.299744899
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.3621530465
Short name T238
Test name
Test status
Simulation time 1759769194 ps
CPU time 10.25 seconds
Started Jul 28 05:10:04 PM PDT 24
Finished Jul 28 05:10:15 PM PDT 24
Peak memory 200756 kb
Host smart-6dac0ae9-080d-49af-a0a9-1a5e343fa148
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621530465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3621530465
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.2331143418
Short name T498
Test name
Test status
Simulation time 2035429425 ps
CPU time 8.27 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200500 kb
Host smart-4fd8d6df-b767-48de-9f1a-49fca9597c2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331143418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.2331143418
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2964330552
Short name T780
Test name
Test status
Simulation time 124828493 ps
CPU time 1.3 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200480 kb
Host smart-c0c4c6e7-e01f-4e6f-8258-3fc94d5de14e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964330552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2964330552
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.4102461042
Short name T739
Test name
Test status
Simulation time 24043864 ps
CPU time 0.86 seconds
Started Jul 28 05:10:05 PM PDT 24
Finished Jul 28 05:10:06 PM PDT 24
Peak memory 200484 kb
Host smart-dab621ff-2bf1-4721-9169-d3e1626ceda2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102461042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.4102461042
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3762310691
Short name T809
Test name
Test status
Simulation time 33259879 ps
CPU time 0.78 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 200396 kb
Host smart-65c9f6f6-2328-4127-8605-bca3f7d2fc6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762310691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3762310691
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.988575234
Short name T777
Test name
Test status
Simulation time 14003858 ps
CPU time 0.73 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200412 kb
Host smart-56ded287-c29a-4310-8b4c-4ae03cc0c4d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988575234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.988575234
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.1051110103
Short name T413
Test name
Test status
Simulation time 1277414353 ps
CPU time 4.77 seconds
Started Jul 28 05:10:33 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 200624 kb
Host smart-61c8ceee-38ed-4115-9467-f22f21fa8ab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051110103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1051110103
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.3097041822
Short name T372
Test name
Test status
Simulation time 48164282 ps
CPU time 0.88 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:10:22 PM PDT 24
Peak memory 200356 kb
Host smart-ae8fb3c5-c372-425f-9f36-56b7689c122e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097041822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3097041822
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.3167395746
Short name T328
Test name
Test status
Simulation time 1192525796 ps
CPU time 5.38 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 200708 kb
Host smart-b9e576ab-f7e8-4168-a6a6-54294b742370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167395746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.3167395746
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.3701671591
Short name T789
Test name
Test status
Simulation time 116120242934 ps
CPU time 812.6 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:23:29 PM PDT 24
Peak memory 217372 kb
Host smart-150e5440-ec1f-4638-b9fe-f5cf019b4fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3701671591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3701671591
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.clkmgr_trans.571209721
Short name T786
Test name
Test status
Simulation time 135326858 ps
CPU time 1.32 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200624 kb
Host smart-dd043e8c-5acf-4196-b6b6-fc7ba21fbee2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571209721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.571209721
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.775666468
Short name T350
Test name
Test status
Simulation time 15274142 ps
CPU time 0.74 seconds
Started Jul 28 05:10:06 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200424 kb
Host smart-3881d41f-d2d9-4e4e-acba-401d5c9d9e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775666468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkm
gr_alert_test.775666468
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.608759968
Short name T773
Test name
Test status
Simulation time 73574896 ps
CPU time 1.05 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:21 PM PDT 24
Peak memory 200468 kb
Host smart-a1a46881-1ca0-4144-9282-da2a422806af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608759968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.608759968
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.932654774
Short name T354
Test name
Test status
Simulation time 75307035 ps
CPU time 0.83 seconds
Started Jul 28 05:10:02 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 199616 kb
Host smart-148c48bc-3b8e-4abe-b9fb-85e872266be7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932654774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.932654774
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.63040426
Short name T6
Test name
Test status
Simulation time 71505088 ps
CPU time 0.93 seconds
Started Jul 28 05:10:24 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200376 kb
Host smart-0ee97a78-e98e-49a2-9b5c-d22fe05e5629
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63040426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.clkmgr_div_intersig_mubi.63040426
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.1209201300
Short name T807
Test name
Test status
Simulation time 27836968 ps
CPU time 0.91 seconds
Started Jul 28 05:10:11 PM PDT 24
Finished Jul 28 05:10:12 PM PDT 24
Peak memory 200464 kb
Host smart-b8f98b66-a13a-46de-b12e-4b91cf9b3e5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209201300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1209201300
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1836325556
Short name T8
Test name
Test status
Simulation time 1766553963 ps
CPU time 10.22 seconds
Started Jul 28 05:10:22 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200720 kb
Host smart-29ce8a1c-f603-4f0a-a944-e0fe079788a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836325556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1836325556
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.139338650
Short name T373
Test name
Test status
Simulation time 862004575 ps
CPU time 6.16 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 200528 kb
Host smart-fa1b492e-cf5d-40d4-8d00-6429c26e20c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139338650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_ti
meout.139338650
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3011479923
Short name T349
Test name
Test status
Simulation time 38483380 ps
CPU time 0.77 seconds
Started Jul 28 05:10:06 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200528 kb
Host smart-a6b745f8-08f7-4f0f-a99f-1135352e848d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011479923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.3011479923
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.1645643461
Short name T749
Test name
Test status
Simulation time 195374027 ps
CPU time 1.34 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200488 kb
Host smart-0451d07f-357c-47ad-bdae-608686749144
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645643461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.1645643461
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.44141902
Short name T722
Test name
Test status
Simulation time 21114119 ps
CPU time 0.75 seconds
Started Jul 28 05:10:06 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200468 kb
Host smart-a1e4616b-dc46-4019-9f9b-bd550b51a78a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44141902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_lc_ctrl_intersig_mubi.44141902
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.1879905263
Short name T447
Test name
Test status
Simulation time 102108656 ps
CPU time 0.96 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:28 PM PDT 24
Peak memory 200404 kb
Host smart-2ce93606-cc4f-4ef5-b8e6-b50c7d681c14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879905263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1879905263
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.1207964914
Short name T312
Test name
Test status
Simulation time 1197062813 ps
CPU time 4.04 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200636 kb
Host smart-36b0c760-eb5b-474e-be0f-3ca2ca0238f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207964914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1207964914
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.2906886055
Short name T40
Test name
Test status
Simulation time 42497627 ps
CPU time 0.87 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200356 kb
Host smart-923d07d6-7e5f-4afa-ae94-f9e5c9d4933a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906886055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2906886055
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.1081650928
Short name T687
Test name
Test status
Simulation time 9334579803 ps
CPU time 47.51 seconds
Started Jul 28 05:10:15 PM PDT 24
Finished Jul 28 05:11:03 PM PDT 24
Peak memory 200884 kb
Host smart-b36efb79-0603-44ed-87ff-0cb39e90f73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081650928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.1081650928
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.2757773486
Short name T323
Test name
Test status
Simulation time 58387566 ps
CPU time 0.9 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200456 kb
Host smart-9d7466cc-e0af-4d59-8e11-2b5ea7c07eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757773486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2757773486
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.2798338183
Short name T790
Test name
Test status
Simulation time 28255960 ps
CPU time 0.78 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200480 kb
Host smart-bf9cb7cc-66b8-43d9-80a4-d8dbb21dd9b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798338183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.2798338183
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.3019756133
Short name T735
Test name
Test status
Simulation time 22758409 ps
CPU time 0.7 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:17 PM PDT 24
Peak memory 199612 kb
Host smart-5ffeef99-5be2-4125-845b-654e89ceb34a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019756133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3019756133
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.2033074777
Short name T442
Test name
Test status
Simulation time 60206982 ps
CPU time 0.88 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200468 kb
Host smart-361b5c96-a224-4645-a1c2-17ab1f6343d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033074777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.2033074777
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.4174374466
Short name T209
Test name
Test status
Simulation time 23516714 ps
CPU time 0.83 seconds
Started Jul 28 05:10:05 PM PDT 24
Finished Jul 28 05:10:11 PM PDT 24
Peak memory 200408 kb
Host smart-8342b035-e67b-4537-b6e2-ad0f3f2ba548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174374466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.4174374466
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.71313263
Short name T491
Test name
Test status
Simulation time 674539505 ps
CPU time 6.11 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200544 kb
Host smart-710c4213-6842-4d30-9c41-096a81631fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71313263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.71313263
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.4221088700
Short name T753
Test name
Test status
Simulation time 140369368 ps
CPU time 1.79 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 200768 kb
Host smart-65ba2797-5f07-4904-a82b-3b180774b550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221088700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.4221088700
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2178704674
Short name T239
Test name
Test status
Simulation time 26966981 ps
CPU time 0.92 seconds
Started Jul 28 05:10:03 PM PDT 24
Finished Jul 28 05:10:04 PM PDT 24
Peak memory 200400 kb
Host smart-6e85d8ba-4401-4c5d-8aa6-c18747892083
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178704674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.2178704674
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3099769498
Short name T646
Test name
Test status
Simulation time 55613967 ps
CPU time 0.94 seconds
Started Jul 28 05:10:08 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 200496 kb
Host smart-b43c51f0-c88d-4e3e-9847-3d14cdb94505
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099769498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3099769498
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.238557548
Short name T306
Test name
Test status
Simulation time 35454188 ps
CPU time 0.86 seconds
Started Jul 28 05:10:33 PM PDT 24
Finished Jul 28 05:10:34 PM PDT 24
Peak memory 200436 kb
Host smart-cf477913-98f0-43dc-8539-ed2a84fb6e64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238557548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.clkmgr_lc_ctrl_intersig_mubi.238557548
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.219174986
Short name T389
Test name
Test status
Simulation time 39488217 ps
CPU time 0.77 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 200392 kb
Host smart-06ea3229-a031-46ed-948d-e453a682eda0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219174986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.219174986
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3694575394
Short name T158
Test name
Test status
Simulation time 180118149 ps
CPU time 1.58 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200380 kb
Host smart-df31885f-71c3-43ee-a663-d765d5399331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694575394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3694575394
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.512796553
Short name T706
Test name
Test status
Simulation time 30527157 ps
CPU time 0.89 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200364 kb
Host smart-420c4536-0c70-49af-a57b-35f8d1ff680e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512796553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.512796553
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.3795402571
Short name T423
Test name
Test status
Simulation time 5497884367 ps
CPU time 29.58 seconds
Started Jul 28 05:10:14 PM PDT 24
Finished Jul 28 05:10:44 PM PDT 24
Peak memory 200900 kb
Host smart-7353de0f-2598-4a2f-8d84-adc0136e4323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795402571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.3795402571
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.44482626
Short name T510
Test name
Test status
Simulation time 26969551 ps
CPU time 0.9 seconds
Started Jul 28 05:10:12 PM PDT 24
Finished Jul 28 05:10:13 PM PDT 24
Peak memory 200472 kb
Host smart-2f4257ed-d4d0-491c-b308-79157d1668cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44482626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.44482626
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.1644994871
Short name T596
Test name
Test status
Simulation time 22754538 ps
CPU time 0.79 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200452 kb
Host smart-6444ca29-57b8-4d01-bb3b-44f6c75fde6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644994871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.1644994871
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1156978155
Short name T582
Test name
Test status
Simulation time 14300708 ps
CPU time 0.72 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:21 PM PDT 24
Peak memory 200412 kb
Host smart-049da1c9-736a-4407-8f4d-1fa930382ee7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156978155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.1156978155
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.1744443780
Short name T803
Test name
Test status
Simulation time 27363760 ps
CPU time 0.74 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200384 kb
Host smart-adc957c7-15cb-477d-a02f-9cc15db616f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744443780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1744443780
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1572450737
Short name T638
Test name
Test status
Simulation time 22095617 ps
CPU time 0.8 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:09:59 PM PDT 24
Peak memory 200368 kb
Host smart-87bcdcde-0b60-4d53-ac0e-141a20b08507
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572450737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.1572450737
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.590400859
Short name T600
Test name
Test status
Simulation time 51299100 ps
CPU time 0.97 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:17 PM PDT 24
Peak memory 200368 kb
Host smart-919923a4-9a6e-4d3c-b823-532e1c821cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590400859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.590400859
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.2925449359
Short name T82
Test name
Test status
Simulation time 1364602002 ps
CPU time 6.42 seconds
Started Jul 28 05:10:15 PM PDT 24
Finished Jul 28 05:10:22 PM PDT 24
Peak memory 200456 kb
Host smart-3069cd9d-0513-40f2-a14b-115adeb7e7b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925449359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2925449359
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.2587560736
Short name T623
Test name
Test status
Simulation time 2310316536 ps
CPU time 10.16 seconds
Started Jul 28 05:10:22 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200756 kb
Host smart-40332492-5645-441b-ae59-563663d73682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587560736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.2587560736
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.3388945503
Short name T639
Test name
Test status
Simulation time 36190965 ps
CPU time 0.85 seconds
Started Jul 28 05:10:22 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 200420 kb
Host smart-0d92db58-ff79-4a39-832a-cbc9b4436bf4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388945503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.3388945503
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2773488923
Short name T381
Test name
Test status
Simulation time 31506832 ps
CPU time 0.86 seconds
Started Jul 28 05:10:02 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 200380 kb
Host smart-d4f5b6d2-64ad-4130-ad79-dbadc3fb24a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773488923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2773488923
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2361854008
Short name T783
Test name
Test status
Simulation time 43522891 ps
CPU time 0.84 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:20 PM PDT 24
Peak memory 200476 kb
Host smart-3e7df552-246d-4204-a74e-a197ff48684c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361854008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.2361854008
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.1944167616
Short name T409
Test name
Test status
Simulation time 27180724 ps
CPU time 0.79 seconds
Started Jul 28 05:10:07 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 200412 kb
Host smart-3748f8ae-9ed3-4f17-afe2-48c1dde78a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944167616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1944167616
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.2265378622
Short name T590
Test name
Test status
Simulation time 1395617986 ps
CPU time 4.92 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200648 kb
Host smart-b3ed62f2-6c27-4fc1-a333-1e96e84569b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265378622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2265378622
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.929534561
Short name T802
Test name
Test status
Simulation time 19638202 ps
CPU time 0.83 seconds
Started Jul 28 05:10:10 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200472 kb
Host smart-95d64d21-7999-4da6-a8e0-55d65fe1a504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929534561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.929534561
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.1664421155
Short name T549
Test name
Test status
Simulation time 5625861909 ps
CPU time 30.25 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200756 kb
Host smart-46bcbf34-623b-49ba-8e77-770eca113394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664421155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.1664421155
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.1220354269
Short name T340
Test name
Test status
Simulation time 44455566 ps
CPU time 0.79 seconds
Started Jul 28 05:10:31 PM PDT 24
Finished Jul 28 05:10:32 PM PDT 24
Peak memory 200468 kb
Host smart-39d901e3-d9d9-4cd1-81f5-4f3f151e7688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220354269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1220354269
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.1688112626
Short name T612
Test name
Test status
Simulation time 15893427 ps
CPU time 0.75 seconds
Started Jul 28 05:09:37 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 200484 kb
Host smart-1da57c7a-98ac-40ce-ba67-bf3730542fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688112626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.1688112626
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2972114277
Short name T296
Test name
Test status
Simulation time 57336568 ps
CPU time 0.93 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200512 kb
Host smart-fdfecfe0-02fe-4adf-917c-b8e20f10c240
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972114277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.2972114277
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.1207594848
Short name T180
Test name
Test status
Simulation time 23121631 ps
CPU time 0.72 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:09:41 PM PDT 24
Peak memory 199740 kb
Host smart-83eee73c-3038-4ff5-8841-e3ea436aa601
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207594848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1207594848
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.600435035
Short name T414
Test name
Test status
Simulation time 22791257 ps
CPU time 0.75 seconds
Started Jul 28 05:09:38 PM PDT 24
Finished Jul 28 05:09:39 PM PDT 24
Peak memory 200500 kb
Host smart-b3b9a1b0-68c0-42c9-b3bb-b1782c852383
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600435035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_div_intersig_mubi.600435035
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.618758398
Short name T191
Test name
Test status
Simulation time 64703965 ps
CPU time 0.93 seconds
Started Jul 28 05:09:52 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 200676 kb
Host smart-c02a4410-f24a-41f6-aca3-0f72501090c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618758398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.618758398
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.2074531798
Short name T277
Test name
Test status
Simulation time 1039095028 ps
CPU time 8.63 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200488 kb
Host smart-53d092ca-176f-4982-be6b-70cdf1e45075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074531798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2074531798
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.1984797136
Short name T258
Test name
Test status
Simulation time 1128547780 ps
CPU time 5.22 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200516 kb
Host smart-cf24e261-6d75-4f2d-9d66-7f8018e47378
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984797136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.1984797136
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.3241828101
Short name T626
Test name
Test status
Simulation time 124490193 ps
CPU time 1.27 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 200464 kb
Host smart-b79bd5f2-0c7f-4981-a3ca-add07d54928f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241828101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.3241828101
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.874233408
Short name T621
Test name
Test status
Simulation time 21253708 ps
CPU time 0.86 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200476 kb
Host smart-9970642f-dbea-404c-a47f-bd43f82cc91e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874233408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_clk_byp_req_intersig_mubi.874233408
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3752706184
Short name T507
Test name
Test status
Simulation time 27279610 ps
CPU time 0.83 seconds
Started Jul 28 05:09:36 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 200356 kb
Host smart-53468b95-23e8-49a5-921d-1d7bf0b115fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752706184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.3752706184
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.1182167205
Short name T300
Test name
Test status
Simulation time 25088087 ps
CPU time 0.88 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200424 kb
Host smart-46cd0f27-0dfe-494f-8d29-7524ac97246a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182167205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1182167205
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.1598677181
Short name T155
Test name
Test status
Simulation time 686142545 ps
CPU time 3.08 seconds
Started Jul 28 05:09:46 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200624 kb
Host smart-0e6052df-0f9b-4418-8e98-12ef39e55bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598677181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1598677181
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.3255155955
Short name T42
Test name
Test status
Simulation time 292444865 ps
CPU time 3.24 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 217336 kb
Host smart-5de2b32f-03e8-4415-8f60-b1d965e9d3cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255155955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.3255155955
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.2348105025
Short name T588
Test name
Test status
Simulation time 17897020 ps
CPU time 0.83 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:09:41 PM PDT 24
Peak memory 200404 kb
Host smart-d32d4c68-2b16-464c-aa3d-edbbe659d293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348105025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2348105025
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.3298037608
Short name T142
Test name
Test status
Simulation time 3676453985 ps
CPU time 21.26 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 200832 kb
Host smart-5e10c1bf-e45c-4920-8f39-2b8fa814d597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298037608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.3298037608
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.83843720
Short name T375
Test name
Test status
Simulation time 28969836 ps
CPU time 0.98 seconds
Started Jul 28 05:09:33 PM PDT 24
Finished Jul 28 05:09:34 PM PDT 24
Peak memory 200448 kb
Host smart-e99cf877-e918-426f-b23c-6971efc891ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83843720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.83843720
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.743167168
Short name T487
Test name
Test status
Simulation time 26233952 ps
CPU time 0.79 seconds
Started Jul 28 05:10:17 PM PDT 24
Finished Jul 28 05:10:18 PM PDT 24
Peak memory 200372 kb
Host smart-dbcb436a-8e5f-4afd-9c97-3610d0dfc4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743167168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkm
gr_alert_test.743167168
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.1137046759
Short name T96
Test name
Test status
Simulation time 100165714 ps
CPU time 1.17 seconds
Started Jul 28 05:10:24 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200436 kb
Host smart-c4ecdad9-75cd-410b-80c4-5e490f08cf55
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137046759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.1137046759
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.66630071
Short name T178
Test name
Test status
Simulation time 17590078 ps
CPU time 0.72 seconds
Started Jul 28 05:10:35 PM PDT 24
Finished Jul 28 05:10:36 PM PDT 24
Peak memory 199712 kb
Host smart-a3cb766d-1cb3-486e-91f7-02ede0b37cf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66630071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.66630071
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.3463407723
Short name T821
Test name
Test status
Simulation time 26332777 ps
CPU time 0.73 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200436 kb
Host smart-44581fae-ce1b-4629-aed8-429f61991be0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463407723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.3463407723
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.145307940
Short name T167
Test name
Test status
Simulation time 23875442 ps
CPU time 0.76 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:10:22 PM PDT 24
Peak memory 200440 kb
Host smart-bcabe1a8-21c7-480b-bb11-4ecbe13d04c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145307940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.145307940
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1672875591
Short name T274
Test name
Test status
Simulation time 2363507785 ps
CPU time 18.49 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200716 kb
Host smart-476a600e-6652-434a-a834-007a06682d9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672875591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1672875591
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.1337230023
Short name T499
Test name
Test status
Simulation time 173156152 ps
CPU time 1.24 seconds
Started Jul 28 05:10:18 PM PDT 24
Finished Jul 28 05:10:19 PM PDT 24
Peak memory 200512 kb
Host smart-1260d9bf-e9fb-45d6-b4c3-ffdf2a1f6676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337230023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.1337230023
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.226800142
Short name T811
Test name
Test status
Simulation time 50924851 ps
CPU time 1.09 seconds
Started Jul 28 05:10:14 PM PDT 24
Finished Jul 28 05:10:15 PM PDT 24
Peak memory 200460 kb
Host smart-948f4ff5-26b5-4736-9191-2ca57d1107ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226800142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_idle_intersig_mubi.226800142
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.483516849
Short name T266
Test name
Test status
Simulation time 16907431 ps
CPU time 0.73 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200464 kb
Host smart-77c433bd-f239-4f73-9f57-b4d4a9086ed1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483516849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_clk_byp_req_intersig_mubi.483516849
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.144896120
Short name T231
Test name
Test status
Simulation time 23647628 ps
CPU time 0.85 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:17 PM PDT 24
Peak memory 200456 kb
Host smart-540284a9-9563-445d-9112-e48b6a6ae18b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144896120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_ctrl_intersig_mubi.144896120
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.4123053963
Short name T465
Test name
Test status
Simulation time 32297013 ps
CPU time 0.79 seconds
Started Jul 28 05:10:17 PM PDT 24
Finished Jul 28 05:10:18 PM PDT 24
Peak memory 200404 kb
Host smart-2a903a15-58ed-42b5-8d8c-6e359c99b554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123053963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.4123053963
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.993155385
Short name T356
Test name
Test status
Simulation time 163673592 ps
CPU time 1.48 seconds
Started Jul 28 05:10:33 PM PDT 24
Finished Jul 28 05:10:39 PM PDT 24
Peak memory 200424 kb
Host smart-fdad78cf-8a7b-4a09-b0a8-8ecc5613797d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993155385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.993155385
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.2647885440
Short name T574
Test name
Test status
Simulation time 27395563 ps
CPU time 0.89 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200316 kb
Host smart-d474b805-65ca-4938-9639-b282b8a6b1a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647885440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.2647885440
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.3502580624
Short name T143
Test name
Test status
Simulation time 9015065995 ps
CPU time 57.82 seconds
Started Jul 28 05:10:35 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 200824 kb
Host smart-1bc56ff2-b5a6-45b7-87e0-e7ca6a5b6273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502580624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.3502580624
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.1859531829
Short name T73
Test name
Test status
Simulation time 27417725 ps
CPU time 0.94 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 200412 kb
Host smart-741eac97-20cd-4ab5-a84a-79246ba793bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859531829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1859531829
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.273239904
Short name T49
Test name
Test status
Simulation time 34044961 ps
CPU time 0.8 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 200452 kb
Host smart-66dced58-36c8-42b5-a204-dcfe26027738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273239904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkm
gr_alert_test.273239904
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.1444868844
Short name T304
Test name
Test status
Simulation time 114296397 ps
CPU time 1.2 seconds
Started Jul 28 05:10:22 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200536 kb
Host smart-80e0f53e-5eca-454a-a0bf-7385763ce62c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444868844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.1444868844
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.4098995360
Short name T368
Test name
Test status
Simulation time 14928290 ps
CPU time 0.72 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 199608 kb
Host smart-31add6f5-0014-4c20-8d4f-49a7e60d56fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098995360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.4098995360
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1676827176
Short name T150
Test name
Test status
Simulation time 21922319 ps
CPU time 0.85 seconds
Started Jul 28 05:10:35 PM PDT 24
Finished Jul 28 05:10:36 PM PDT 24
Peak memory 200460 kb
Host smart-d8db53ce-b097-4a30-94a0-d24bae05f55f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676827176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1676827176
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.2903934919
Short name T462
Test name
Test status
Simulation time 16116219 ps
CPU time 0.72 seconds
Started Jul 28 05:10:17 PM PDT 24
Finished Jul 28 05:10:17 PM PDT 24
Peak memory 200396 kb
Host smart-dd79dca7-db84-4b88-90f3-516e4182b53c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903934919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2903934919
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.3497979248
Short name T586
Test name
Test status
Simulation time 2263080896 ps
CPU time 10.14 seconds
Started Jul 28 05:10:06 PM PDT 24
Finished Jul 28 05:10:16 PM PDT 24
Peak memory 200748 kb
Host smart-829a41d3-0530-4999-ab0a-ea9990581516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497979248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3497979248
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.1285717241
Short name T281
Test name
Test status
Simulation time 139845206 ps
CPU time 1.6 seconds
Started Jul 28 05:10:11 PM PDT 24
Finished Jul 28 05:10:13 PM PDT 24
Peak memory 200552 kb
Host smart-34a0fbc1-7329-4d83-9a3f-cc63851c6915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285717241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.1285717241
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1752522361
Short name T18
Test name
Test status
Simulation time 76296070 ps
CPU time 1.03 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:20 PM PDT 24
Peak memory 200440 kb
Host smart-ac5dca7e-c4b3-496e-b3da-eec65f94c22b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752522361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.1752522361
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1601872123
Short name T456
Test name
Test status
Simulation time 15479178 ps
CPU time 0.78 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:21 PM PDT 24
Peak memory 200436 kb
Host smart-7f295867-ff5c-456c-844c-60e19f038a2f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601872123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.1601872123
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3740357539
Short name T264
Test name
Test status
Simulation time 64634131 ps
CPU time 0.95 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 200452 kb
Host smart-3b253eb1-b7f7-40fa-9547-c03b807625e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740357539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.3740357539
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.3121422774
Short name T719
Test name
Test status
Simulation time 19980865 ps
CPU time 0.76 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200392 kb
Host smart-b68c22db-25f2-4c17-90f2-2153f6cf7abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121422774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3121422774
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.1765385142
Short name T658
Test name
Test status
Simulation time 21327350 ps
CPU time 0.84 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:21 PM PDT 24
Peak memory 200344 kb
Host smart-c7241978-32e3-46c3-b066-b23d09297955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765385142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1765385142
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.1357389585
Short name T572
Test name
Test status
Simulation time 92874184 ps
CPU time 1.34 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200408 kb
Host smart-80994935-8c34-4e8e-aa9c-e55f7ec171d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357389585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.1357389585
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.1283176083
Short name T446
Test name
Test status
Simulation time 61892043 ps
CPU time 0.89 seconds
Started Jul 28 05:10:08 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 200452 kb
Host smart-bb91c20b-ac7b-4681-a21e-5786edb2c155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283176083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.1283176083
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.583147485
Short name T293
Test name
Test status
Simulation time 39694449 ps
CPU time 0.89 seconds
Started Jul 28 05:10:11 PM PDT 24
Finished Jul 28 05:10:12 PM PDT 24
Peak memory 200388 kb
Host smart-93cbf7ff-83ee-4aaa-81ce-bdbea419ef42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583147485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkm
gr_alert_test.583147485
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.438482712
Short name T269
Test name
Test status
Simulation time 44763099 ps
CPU time 0.92 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:21 PM PDT 24
Peak memory 200528 kb
Host smart-86bc84ed-4ae0-4cd6-94d6-3aaafb371882
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438482712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.438482712
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.215473848
Short name T656
Test name
Test status
Simulation time 40211680 ps
CPU time 0.8 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200412 kb
Host smart-5fc87d35-9e69-4760-bd19-1ce2eca3b9a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215473848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.215473848
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.3035259625
Short name T585
Test name
Test status
Simulation time 14393607 ps
CPU time 0.74 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:10:22 PM PDT 24
Peak memory 200412 kb
Host smart-01fb1bb2-b4a9-4610-ac09-3dbf43376ce4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035259625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.3035259625
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.3411205603
Short name T237
Test name
Test status
Simulation time 19175569 ps
CPU time 0.72 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200440 kb
Host smart-5876e1bb-9078-406d-ac64-176edfa06d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411205603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.3411205603
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.3162062289
Short name T625
Test name
Test status
Simulation time 200398101 ps
CPU time 2.09 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200576 kb
Host smart-6c8e410a-3331-41f7-89bc-a8509408fa84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162062289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3162062289
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.795864574
Short name T210
Test name
Test status
Simulation time 2082324998 ps
CPU time 8.55 seconds
Started Jul 28 05:10:16 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200756 kb
Host smart-995cd88a-2822-4f14-9067-c515437c4183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795864574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti
meout.795864574
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.2210211466
Short name T396
Test name
Test status
Simulation time 19607408 ps
CPU time 0.82 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200452 kb
Host smart-7f227543-3925-4355-8a09-f474c6a6e396
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210211466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.2210211466
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3785696104
Short name T149
Test name
Test status
Simulation time 23191009 ps
CPU time 0.78 seconds
Started Jul 28 05:10:03 PM PDT 24
Finished Jul 28 05:10:04 PM PDT 24
Peak memory 200472 kb
Host smart-06fdce63-c81d-4983-b435-24ead5036877
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785696104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3785696104
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2257740730
Short name T810
Test name
Test status
Simulation time 22213897 ps
CPU time 0.8 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 200468 kb
Host smart-87334ebb-e207-4027-93cd-280263152b74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257740730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.2257740730
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3992861242
Short name T717
Test name
Test status
Simulation time 18010656 ps
CPU time 0.82 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200468 kb
Host smart-525252f4-7216-4da3-8c36-51f12428945e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992861242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3992861242
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2313671103
Short name T667
Test name
Test status
Simulation time 1021710132 ps
CPU time 4.88 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200644 kb
Host smart-8dfdf8a6-47c9-447b-88a3-419652f8e896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313671103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2313671103
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.715807391
Short name T522
Test name
Test status
Simulation time 16428072 ps
CPU time 0.81 seconds
Started Jul 28 05:10:32 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200420 kb
Host smart-f900bacb-afec-41b7-a70e-e1ab00cf5d25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715807391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.715807391
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.3135021161
Short name T405
Test name
Test status
Simulation time 3681525779 ps
CPU time 15.17 seconds
Started Jul 28 05:10:33 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 201044 kb
Host smart-04dfe268-e3ee-4bef-a461-907055b8ffad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135021161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.3135021161
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.2961094866
Short name T765
Test name
Test status
Simulation time 18224595 ps
CPU time 0.76 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200424 kb
Host smart-3a769c43-4930-4f47-bdd2-a8beff382127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961094866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2961094866
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.1314570590
Short name T31
Test name
Test status
Simulation time 54212254 ps
CPU time 0.84 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:21 PM PDT 24
Peak memory 200432 kb
Host smart-bc177c4b-b851-43c3-b20b-4c53d1d5a93b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314570590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.1314570590
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2963467113
Short name T448
Test name
Test status
Simulation time 216756065 ps
CPU time 1.35 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 200436 kb
Host smart-8c40d04b-8a0e-4430-985e-64f3917c16c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963467113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.2963467113
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.4027583761
Short name T699
Test name
Test status
Simulation time 15125970 ps
CPU time 0.71 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:28 PM PDT 24
Peak memory 199664 kb
Host smart-36f749c5-5112-4e73-bd24-5d99a476b3a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027583761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.4027583761
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.3660922683
Short name T613
Test name
Test status
Simulation time 31262517 ps
CPU time 0.94 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:28 PM PDT 24
Peak memory 200452 kb
Host smart-b0afc059-cb4f-41cc-bb48-1a50dfbb89ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660922683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.3660922683
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.567672966
Short name T682
Test name
Test status
Simulation time 39355669 ps
CPU time 0.78 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200424 kb
Host smart-a06119ae-fd6a-467f-8c21-42e9e8de9ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567672966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.567672966
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.3623716093
Short name T228
Test name
Test status
Simulation time 328866430 ps
CPU time 2.36 seconds
Started Jul 28 05:10:41 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200488 kb
Host smart-df46b2bd-98a6-446d-8b5e-381387e8a614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623716093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3623716093
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.2297780047
Short name T458
Test name
Test status
Simulation time 1475279597 ps
CPU time 6.3 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200564 kb
Host smart-6983a807-a768-4f69-a371-47775de489db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297780047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.2297780047
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.1702670299
Short name T697
Test name
Test status
Simulation time 28536852 ps
CPU time 0.96 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 200352 kb
Host smart-a8c35243-f271-428f-9f8c-5e96491d71d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702670299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.1702670299
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.2410375545
Short name T634
Test name
Test status
Simulation time 32951246 ps
CPU time 0.84 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200424 kb
Host smart-83fb7614-f6eb-4def-ad35-5393b34ab95b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410375545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.2410375545
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3911988860
Short name T693
Test name
Test status
Simulation time 58817101 ps
CPU time 0.92 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200508 kb
Host smart-66a236d5-30c0-446c-b55e-fbc5ef93fcf3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911988860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.3911988860
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.2568931689
Short name T324
Test name
Test status
Simulation time 46246786 ps
CPU time 0.79 seconds
Started Jul 28 05:10:32 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200448 kb
Host smart-6ae4487e-5cda-48f2-9e04-13bdb2b59a79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568931689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.2568931689
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.2408565010
Short name T445
Test name
Test status
Simulation time 555864416 ps
CPU time 2.43 seconds
Started Jul 28 05:10:31 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200452 kb
Host smart-cfd65d43-7199-49ac-9666-a7f567e3e572
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408565010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2408565010
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.342983934
Short name T169
Test name
Test status
Simulation time 21677671 ps
CPU time 0.82 seconds
Started Jul 28 05:10:35 PM PDT 24
Finished Jul 28 05:10:36 PM PDT 24
Peak memory 200428 kb
Host smart-362b4902-876f-4ef5-a680-c70b680bc29e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342983934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.342983934
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.585241368
Short name T814
Test name
Test status
Simulation time 15812372293 ps
CPU time 62.95 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 200884 kb
Host smart-0add8d1e-bad3-4c13-b53d-4a3e38920184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585241368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.585241368
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.289825711
Short name T196
Test name
Test status
Simulation time 35660930 ps
CPU time 0.78 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200416 kb
Host smart-b8546c7e-7f5e-48de-bf3a-544aa8a19d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289825711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.289825711
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.4158647719
Short name T761
Test name
Test status
Simulation time 16087586 ps
CPU time 0.79 seconds
Started Jul 28 05:10:18 PM PDT 24
Finished Jul 28 05:10:19 PM PDT 24
Peak memory 200452 kb
Host smart-fae819d6-02a0-4493-bce6-8accb4bf9185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158647719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.4158647719
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3848596362
Short name T651
Test name
Test status
Simulation time 31626736 ps
CPU time 0.77 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:20 PM PDT 24
Peak memory 200496 kb
Host smart-5f03f35f-e870-46bb-8b23-025a8a62d44f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848596362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3848596362
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.2414833950
Short name T715
Test name
Test status
Simulation time 17710110 ps
CPU time 0.73 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:28 PM PDT 24
Peak memory 200372 kb
Host smart-70c97f6a-2a8a-4cdd-aa2c-26536b2655ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414833950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2414833950
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.3101842233
Short name T759
Test name
Test status
Simulation time 30612133 ps
CPU time 0.85 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200408 kb
Host smart-9a0cac70-6d48-4924-b971-ea4943a80162
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101842233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.3101842233
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.3549945789
Short name T500
Test name
Test status
Simulation time 67140581 ps
CPU time 0.95 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200444 kb
Host smart-3e8fe12d-5921-4d5e-b0dd-017570d40f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549945789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3549945789
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3305367004
Short name T559
Test name
Test status
Simulation time 1187715708 ps
CPU time 6.08 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200492 kb
Host smart-767007a6-c048-4e9a-9e01-202da2686123
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305367004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3305367004
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.1620375094
Short name T397
Test name
Test status
Simulation time 512355898 ps
CPU time 2.53 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:32 PM PDT 24
Peak memory 200560 kb
Host smart-8a38002e-2a7a-4a4f-b9ec-0ef61cb90a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620375094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.1620375094
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.1632144342
Short name T488
Test name
Test status
Simulation time 29009209 ps
CPU time 0.95 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200356 kb
Host smart-d0b8b77b-2766-4c77-940b-7de6928d5a0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632144342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.1632144342
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1757697401
Short name T589
Test name
Test status
Simulation time 53128264 ps
CPU time 0.84 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200468 kb
Host smart-b3460c8a-9194-4675-898a-694b3a9e09b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757697401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1757697401
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.3337657821
Short name T648
Test name
Test status
Simulation time 25361631 ps
CPU time 0.91 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 200416 kb
Host smart-8752d094-66d2-40e7-9d3d-5d33636cd0f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337657821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.3337657821
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.4074811235
Short name T696
Test name
Test status
Simulation time 23304816 ps
CPU time 0.76 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:28 PM PDT 24
Peak memory 200400 kb
Host smart-80b7f033-3692-4229-8eda-93bee96f81d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074811235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.4074811235
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.814657575
Short name T321
Test name
Test status
Simulation time 58703353 ps
CPU time 0.94 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:24 PM PDT 24
Peak memory 200396 kb
Host smart-340282b8-c81a-47d7-8c5c-8b541f06b047
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814657575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.814657575
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.1408618272
Short name T704
Test name
Test status
Simulation time 73345636 ps
CPU time 0.98 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200376 kb
Host smart-dfe3e800-72a1-4007-9d82-7b430dfe1026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408618272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.1408618272
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.45855171
Short name T10
Test name
Test status
Simulation time 3286216418 ps
CPU time 24.82 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200752 kb
Host smart-9485b147-ca9f-4071-9825-719d0bf4258f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45855171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.clkmgr_stress_all.45855171
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2010330403
Short name T120
Test name
Test status
Simulation time 19233840 ps
CPU time 0.82 seconds
Started Jul 28 05:10:19 PM PDT 24
Finished Jul 28 05:10:20 PM PDT 24
Peak memory 200460 kb
Host smart-9d7fb409-4051-487a-9245-37e46343bdbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010330403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2010330403
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3664295774
Short name T751
Test name
Test status
Simulation time 59193034 ps
CPU time 0.96 seconds
Started Jul 28 05:10:21 PM PDT 24
Finished Jul 28 05:10:22 PM PDT 24
Peak memory 200480 kb
Host smart-d6e0339a-9629-4290-a8b4-9174988b3399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664295774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3664295774
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.3729186986
Short name T472
Test name
Test status
Simulation time 25353180 ps
CPU time 0.92 seconds
Started Jul 28 05:10:34 PM PDT 24
Finished Jul 28 05:10:35 PM PDT 24
Peak memory 200492 kb
Host smart-45067d19-50af-4cad-b887-13d5aec5a407
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729186986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.3729186986
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.3367418327
Short name T800
Test name
Test status
Simulation time 12446275 ps
CPU time 0.69 seconds
Started Jul 28 05:10:32 PM PDT 24
Finished Jul 28 05:10:33 PM PDT 24
Peak memory 200396 kb
Host smart-cd7a58eb-e577-49b9-bdb7-05553518aa56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367418327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3367418327
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.4038132795
Short name T548
Test name
Test status
Simulation time 15453167 ps
CPU time 0.73 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200452 kb
Host smart-fd4054c2-545f-43fa-a90e-5ea03d80f702
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038132795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.4038132795
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3279063122
Short name T674
Test name
Test status
Simulation time 15155404 ps
CPU time 0.73 seconds
Started Jul 28 05:10:38 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 200392 kb
Host smart-25688763-a1a5-4f84-9913-7d5e9e3700b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279063122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3279063122
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.3460896241
Short name T784
Test name
Test status
Simulation time 2086789810 ps
CPU time 7.64 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200724 kb
Host smart-63fed699-247b-4c40-a753-cc77fb3c08cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460896241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3460896241
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.1205578064
Short name T528
Test name
Test status
Simulation time 2301001706 ps
CPU time 16.51 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:11:02 PM PDT 24
Peak memory 200796 kb
Host smart-3830ab5b-a30e-49a2-9885-49a471405995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205578064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.1205578064
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2507241051
Short name T603
Test name
Test status
Simulation time 35597133 ps
CPU time 0.78 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 200396 kb
Host smart-b54c4587-11ad-4c2f-8ebf-a33325afaa1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507241051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.2507241051
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.734129212
Short name T364
Test name
Test status
Simulation time 115448211 ps
CPU time 1.04 seconds
Started Jul 28 05:10:43 PM PDT 24
Finished Jul 28 05:10:44 PM PDT 24
Peak memory 200460 kb
Host smart-88a5d378-56a0-416d-805c-d9752620b656
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734129212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_ctrl_intersig_mubi.734129212
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.4134427983
Short name T211
Test name
Test status
Simulation time 27860446 ps
CPU time 0.8 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 200356 kb
Host smart-cc30a67a-9758-446c-ae48-807e46649e25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134427983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.4134427983
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.858531254
Short name T101
Test name
Test status
Simulation time 1284781182 ps
CPU time 4.72 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:34 PM PDT 24
Peak memory 200692 kb
Host smart-60d9eab0-f583-42b7-893e-3fdb4477a5ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858531254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.858531254
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.3364234492
Short name T508
Test name
Test status
Simulation time 16949508 ps
CPU time 0.8 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200408 kb
Host smart-ed3aba97-0fbb-4849-ab08-dc6110923b85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364234492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3364234492
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.3614325799
Short name T602
Test name
Test status
Simulation time 6476029685 ps
CPU time 21.79 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200872 kb
Host smart-1ab78d0f-3b13-46f9-b32c-05f4889e8df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614325799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.3614325799
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.724007922
Short name T774
Test name
Test status
Simulation time 24811361 ps
CPU time 0.87 seconds
Started Jul 28 05:10:37 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 200424 kb
Host smart-d202c231-1ab5-47b6-bdcc-b476a9467f1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724007922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.724007922
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.3412555401
Short name T606
Test name
Test status
Simulation time 36538079 ps
CPU time 0.78 seconds
Started Jul 28 05:10:34 PM PDT 24
Finished Jul 28 05:10:35 PM PDT 24
Peak memory 200452 kb
Host smart-e44ffd74-2b6a-4a7f-b07b-c9a3cacf5d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412555401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.3412555401
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3557778378
Short name T411
Test name
Test status
Simulation time 66302793 ps
CPU time 0.9 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200716 kb
Host smart-0befb559-96ff-4d63-b3ae-4cffe9310912
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557778378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.3557778378
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.1535728653
Short name T36
Test name
Test status
Simulation time 17942969 ps
CPU time 0.68 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 199684 kb
Host smart-10612767-a1fa-463d-857e-098896df3b69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535728653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1535728653
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.1061812584
Short name T640
Test name
Test status
Simulation time 38824213 ps
CPU time 1.01 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:28 PM PDT 24
Peak memory 200472 kb
Host smart-701a4aa5-c8b9-477a-b025-ffdfcc4d65a1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061812584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.1061812584
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.1924957156
Short name T726
Test name
Test status
Simulation time 29858364 ps
CPU time 0.9 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 200460 kb
Host smart-60f71675-f7a5-498d-a2b7-159f67e9d17d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924957156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1924957156
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.2148768818
Short name T415
Test name
Test status
Simulation time 2003189722 ps
CPU time 15.93 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200740 kb
Host smart-a4d718cd-b94a-4bad-bd56-1831c9a6f788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148768818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.2148768818
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.2711310764
Short name T19
Test name
Test status
Simulation time 2299794955 ps
CPU time 16.53 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200720 kb
Host smart-8ef17bf2-a6ec-483d-a37f-89ad44bf0172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711310764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.2711310764
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.4263508867
Short name T260
Test name
Test status
Simulation time 51148441 ps
CPU time 0.97 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200456 kb
Host smart-9b09b80e-c65f-4081-b84b-43d5d63e029c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263508867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.4263508867
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3521274408
Short name T117
Test name
Test status
Simulation time 31586270 ps
CPU time 0.82 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200484 kb
Host smart-bc69aad4-c79d-4b2c-8fae-a20b76bb976c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521274408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3521274408
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1633650384
Short name T252
Test name
Test status
Simulation time 120526994 ps
CPU time 1.13 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200464 kb
Host smart-6c192c38-05a9-4821-b6f2-fa657ec53608
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633650384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.1633650384
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.2662165277
Short name T146
Test name
Test status
Simulation time 47828047 ps
CPU time 0.82 seconds
Started Jul 28 05:10:55 PM PDT 24
Finished Jul 28 05:10:56 PM PDT 24
Peak memory 200352 kb
Host smart-0d66a0af-3906-4950-9ecc-ea58ea5b65e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662165277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2662165277
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.1408036644
Short name T525
Test name
Test status
Simulation time 1237369596 ps
CPU time 5.17 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200704 kb
Host smart-440ec589-38ca-431c-9596-15eaf4979498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408036644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1408036644
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.260418583
Short name T689
Test name
Test status
Simulation time 21781290 ps
CPU time 0.84 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200348 kb
Host smart-29389467-c10f-428f-8389-54c88ae08eb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260418583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.260418583
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.3081272703
Short name T261
Test name
Test status
Simulation time 8773300050 ps
CPU time 33.96 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200880 kb
Host smart-7f27dfa0-87a9-4fa5-874d-0f6cb6d3d173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081272703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.3081272703
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1845680178
Short name T301
Test name
Test status
Simulation time 125859172 ps
CPU time 1.17 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200464 kb
Host smart-c0187dcf-e8ef-4794-abb4-47122c940646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845680178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1845680178
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.3735394908
Short name T201
Test name
Test status
Simulation time 19075886 ps
CPU time 0.84 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 200408 kb
Host smart-c67cef7e-ee69-4585-9314-080a41ddad7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735394908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.3735394908
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1558910250
Short name T539
Test name
Test status
Simulation time 50672613 ps
CPU time 0.87 seconds
Started Jul 28 05:10:38 PM PDT 24
Finished Jul 28 05:10:39 PM PDT 24
Peak memory 200484 kb
Host smart-eaee06c9-d0b3-4e9a-bac7-5717885609e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558910250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.1558910250
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.652354866
Short name T37
Test name
Test status
Simulation time 35866695 ps
CPU time 0.74 seconds
Started Jul 28 05:10:27 PM PDT 24
Finished Jul 28 05:10:28 PM PDT 24
Peak memory 199676 kb
Host smart-46c115f1-0eec-4bd8-ba8c-1b5873d17281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652354866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.652354866
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.623431479
Short name T382
Test name
Test status
Simulation time 43543935 ps
CPU time 0.82 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200508 kb
Host smart-77073f23-b165-4f18-84fe-09a1b2be4337
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623431479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_div_intersig_mubi.623431479
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.747039761
Short name T326
Test name
Test status
Simulation time 51377564 ps
CPU time 0.9 seconds
Started Jul 28 05:10:25 PM PDT 24
Finished Jul 28 05:10:26 PM PDT 24
Peak memory 200392 kb
Host smart-7e898f3a-8dce-412c-ae9e-f74d3d00710a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747039761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.747039761
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.1560494956
Short name T455
Test name
Test status
Simulation time 219691742 ps
CPU time 1.56 seconds
Started Jul 28 05:10:35 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 200464 kb
Host smart-3c8cc770-c9cc-42b4-a7e3-4376ec22247e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560494956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1560494956
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.3256727568
Short name T416
Test name
Test status
Simulation time 137228427 ps
CPU time 1.54 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200520 kb
Host smart-30db5130-cb5d-41a8-a670-248dc9a09361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256727568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.3256727568
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.2066500950
Short name T241
Test name
Test status
Simulation time 273570938 ps
CPU time 1.61 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200464 kb
Host smart-bbbbc933-cc5d-4b3a-9f0b-05c270e15f33
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066500950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.2066500950
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.1874633440
Short name T217
Test name
Test status
Simulation time 46260334 ps
CPU time 0.81 seconds
Started Jul 28 05:10:24 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200420 kb
Host smart-05d1c443-52b2-42ac-8c59-7757bc9f5639
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874633440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.1874633440
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2971035470
Short name T393
Test name
Test status
Simulation time 33324385 ps
CPU time 0.96 seconds
Started Jul 28 05:10:37 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 200424 kb
Host smart-95186e47-c02b-455a-9e4e-25bfcecddeb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971035470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.2971035470
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.968849618
Short name T571
Test name
Test status
Simulation time 16258020 ps
CPU time 0.72 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 200312 kb
Host smart-3ba06b54-e6e7-4c58-8625-0d61bd83ac74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968849618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.968849618
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.3948331974
Short name T235
Test name
Test status
Simulation time 53920561 ps
CPU time 0.97 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200344 kb
Host smart-b7098a2e-1c25-4d19-9ff9-5f621b9dd962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948331974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3948331974
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.871465482
Short name T526
Test name
Test status
Simulation time 5099450319 ps
CPU time 37.6 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 200836 kb
Host smart-6db0df3d-0d7c-4e58-b2ca-fc7ff4954a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871465482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.871465482
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.682872604
Short name T762
Test name
Test status
Simulation time 24077061 ps
CPU time 0.84 seconds
Started Jul 28 05:10:22 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 200460 kb
Host smart-bb321804-b00f-4b58-a242-4f6cc7e175d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682872604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.682872604
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.1172730524
Short name T362
Test name
Test status
Simulation time 39394092 ps
CPU time 0.92 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200432 kb
Host smart-f21c1e2f-d361-4e08-91b1-321b78426051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172730524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.1172730524
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.829289313
Short name T660
Test name
Test status
Simulation time 137165202 ps
CPU time 1.25 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:44 PM PDT 24
Peak memory 200488 kb
Host smart-3f3213f9-4ced-46e6-90eb-46dddd1083cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829289313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.829289313
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.2412484720
Short name T182
Test name
Test status
Simulation time 27569339 ps
CPU time 0.73 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 199632 kb
Host smart-26d277c1-3ebd-4d18-9cc2-ea4d15a11432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412484720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2412484720
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.1322111406
Short name T479
Test name
Test status
Simulation time 64673467 ps
CPU time 0.95 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200384 kb
Host smart-e0153067-c14c-49de-8de1-eb86398405e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322111406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.1322111406
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.3706036581
Short name T399
Test name
Test status
Simulation time 20722574 ps
CPU time 0.83 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200432 kb
Host smart-f9484fc9-92b8-413a-b903-b3fd99a71c59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706036581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.3706036581
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.2144924393
Short name T249
Test name
Test status
Simulation time 563842192 ps
CPU time 3.59 seconds
Started Jul 28 05:10:31 PM PDT 24
Finished Jul 28 05:10:35 PM PDT 24
Peak memory 200500 kb
Host smart-3b9d9a24-9b2a-4d0c-9d1f-be106db73aa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144924393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2144924393
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.93222937
Short name T80
Test name
Test status
Simulation time 737323192 ps
CPU time 5.77 seconds
Started Jul 28 05:10:32 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 200536 kb
Host smart-da187073-4601-429b-b20b-28c41c63f891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93222937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_tim
eout.93222937
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1383174578
Short name T804
Test name
Test status
Simulation time 33584769 ps
CPU time 0.98 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200396 kb
Host smart-96080a17-645a-4a71-bbde-22f944841f70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383174578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.1383174578
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.305078923
Short name T439
Test name
Test status
Simulation time 42589003 ps
CPU time 0.92 seconds
Started Jul 28 05:10:57 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200488 kb
Host smart-ff9f1021-0923-4157-8f68-ba1ab2228467
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305078923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.clkmgr_lc_clk_byp_req_intersig_mubi.305078923
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2313597
Short name T313
Test name
Test status
Simulation time 24764926 ps
CPU time 0.88 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200436 kb
Host smart-275c165e-9544-436c-98df-c6c08cbecc32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_lc_ctrl_intersig_mubi.2313597
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.840509344
Short name T370
Test name
Test status
Simulation time 14539583 ps
CPU time 0.78 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200424 kb
Host smart-a85bb640-de79-4e75-b9c2-9ee77004857a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840509344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.840509344
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.2728008754
Short name T253
Test name
Test status
Simulation time 119216356 ps
CPU time 1.06 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200408 kb
Host smart-15c87e0f-b624-4e45-aad9-5230a9678756
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728008754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2728008754
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.3204737268
Short name T741
Test name
Test status
Simulation time 39583950 ps
CPU time 0.86 seconds
Started Jul 28 05:10:26 PM PDT 24
Finished Jul 28 05:10:27 PM PDT 24
Peak memory 200340 kb
Host smart-c1d3b016-2784-4ec3-89cc-06d3bf9f9ef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204737268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3204737268
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.678654760
Short name T628
Test name
Test status
Simulation time 995328165 ps
CPU time 7.54 seconds
Started Jul 28 05:10:34 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200636 kb
Host smart-ead8e926-7e17-4e57-aec3-c4d39c48e930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678654760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.678654760
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3506460154
Short name T431
Test name
Test status
Simulation time 24777199 ps
CPU time 0.86 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 200684 kb
Host smart-d30909cf-7525-4ff7-8302-e8dbdfef34e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506460154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3506460154
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.2431669714
Short name T727
Test name
Test status
Simulation time 28189858 ps
CPU time 0.75 seconds
Started Jul 28 05:10:33 PM PDT 24
Finished Jul 28 05:10:34 PM PDT 24
Peak memory 200464 kb
Host smart-631199a2-bb83-44ba-809c-3fc8bd577ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431669714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.2431669714
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3831936096
Short name T420
Test name
Test status
Simulation time 13587754 ps
CPU time 0.71 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 200364 kb
Host smart-f1388784-ffae-467e-88d5-59c32308d7e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831936096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.3831936096
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.1295816556
Short name T793
Test name
Test status
Simulation time 26122113 ps
CPU time 0.69 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 199664 kb
Host smart-37388182-2a63-4d78-8a9f-46478db91016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295816556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.1295816556
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.3493339405
Short name T564
Test name
Test status
Simulation time 14003728 ps
CPU time 0.76 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200400 kb
Host smart-1d7c09b8-2392-4639-9a75-8799eeae81c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493339405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.3493339405
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.2654329777
Short name T344
Test name
Test status
Simulation time 39769213 ps
CPU time 0.98 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 200520 kb
Host smart-9db0f7d1-2573-414b-aa3f-9ce478c5b20c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654329777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.2654329777
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.99458209
Short name T652
Test name
Test status
Simulation time 1693951455 ps
CPU time 7.65 seconds
Started Jul 28 05:10:50 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200564 kb
Host smart-8eb02bc0-d960-4096-b883-2168522cd9c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99458209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.99458209
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.2159198846
Short name T26
Test name
Test status
Simulation time 621282889 ps
CPU time 4.79 seconds
Started Jul 28 05:10:37 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200792 kb
Host smart-1ce889c6-765f-4532-80a8-81594d7b17c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159198846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.2159198846
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.1446176690
Short name T388
Test name
Test status
Simulation time 30579303 ps
CPU time 0.94 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:50 PM PDT 24
Peak memory 200372 kb
Host smart-b57da8f7-5dfc-4bdf-8362-ee659d9dbca1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446176690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.1446176690
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.11270674
Short name T76
Test name
Test status
Simulation time 14025721 ps
CPU time 0.77 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200468 kb
Host smart-b0382711-7134-4531-ab0b-2b9bc4b9de37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_lc_clk_byp_req_intersig_mubi.11270674
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.1988795764
Short name T208
Test name
Test status
Simulation time 54686890 ps
CPU time 0.89 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200508 kb
Host smart-be042eda-2926-4feb-a295-686097343991
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988795764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.1988795764
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.2786875098
Short name T204
Test name
Test status
Simulation time 29904874 ps
CPU time 0.72 seconds
Started Jul 28 05:10:31 PM PDT 24
Finished Jul 28 05:10:32 PM PDT 24
Peak memory 200364 kb
Host smart-7043a4a3-c9eb-4beb-895d-bbb4fab17bc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786875098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2786875098
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.1528731663
Short name T716
Test name
Test status
Simulation time 606450422 ps
CPU time 3.89 seconds
Started Jul 28 05:10:57 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200572 kb
Host smart-c02d94e2-06cf-456d-9673-15ef102e18ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528731663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.1528731663
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.4190912820
Short name T335
Test name
Test status
Simulation time 44191231 ps
CPU time 0.86 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200376 kb
Host smart-dbff7662-20de-4bf7-863c-931f1b124a32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190912820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.4190912820
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.1277322555
Short name T170
Test name
Test status
Simulation time 74466242788 ps
CPU time 373.53 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 217364 kb
Host smart-2643810b-c702-4170-a8c7-c1359023b9f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1277322555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.1277322555
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.386913717
Short name T812
Test name
Test status
Simulation time 23667390 ps
CPU time 0.86 seconds
Started Jul 28 05:10:48 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200508 kb
Host smart-0ce9eaab-0d55-419c-9548-e999befe288a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386913717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.386913717
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.1350761233
Short name T695
Test name
Test status
Simulation time 37013222 ps
CPU time 0.88 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 200376 kb
Host smart-d5d3de61-8a77-4832-b342-66acddbec58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350761233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.1350761233
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.2794637079
Short name T385
Test name
Test status
Simulation time 32725745 ps
CPU time 0.86 seconds
Started Jul 28 05:09:49 PM PDT 24
Finished Jul 28 05:09:55 PM PDT 24
Peak memory 200416 kb
Host smart-717b6747-3ebb-4f8e-9983-26851410189a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794637079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.2794637079
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.187182811
Short name T622
Test name
Test status
Simulation time 26417179 ps
CPU time 0.72 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200368 kb
Host smart-b8d023aa-89d8-471d-ac7c-5d126d3b71d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187182811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.187182811
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.3031467561
Short name T461
Test name
Test status
Simulation time 31724469 ps
CPU time 0.98 seconds
Started Jul 28 05:09:47 PM PDT 24
Finished Jul 28 05:09:48 PM PDT 24
Peak memory 200476 kb
Host smart-4c62b6a3-81b1-489f-9159-2f7eb85563f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031467561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.3031467561
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.950962928
Short name T215
Test name
Test status
Simulation time 154915817 ps
CPU time 1.18 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200472 kb
Host smart-c1f7b264-d982-4809-bb26-dc6d610da476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950962928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.950962928
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.649962623
Short name T21
Test name
Test status
Simulation time 1282470775 ps
CPU time 10.19 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:52 PM PDT 24
Peak memory 200532 kb
Host smart-59d12980-6fb4-4dab-82f5-51f900b51b3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649962623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.649962623
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.2005402113
Short name T468
Test name
Test status
Simulation time 741927447 ps
CPU time 6.18 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:47 PM PDT 24
Peak memory 200560 kb
Host smart-53bf14e4-0fc3-41f9-8e9b-2d2bf6aba2e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005402113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.2005402113
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.1250093816
Short name T371
Test name
Test status
Simulation time 101547319 ps
CPU time 1.16 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:09:36 PM PDT 24
Peak memory 200308 kb
Host smart-3c515267-ed91-450a-b977-65304e622eb8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250093816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.1250093816
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.616332053
Short name T541
Test name
Test status
Simulation time 15952283 ps
CPU time 0.83 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:46 PM PDT 24
Peak memory 200396 kb
Host smart-e970bb25-eb08-4c13-a57a-d3d3ab4eecf8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616332053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_clk_byp_req_intersig_mubi.616332053
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3538372500
Short name T347
Test name
Test status
Simulation time 32872027 ps
CPU time 0.82 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 200412 kb
Host smart-86e91da8-10f3-49d7-85ce-f2412fab2460
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538372500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.3538372500
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.2704824275
Short name T15
Test name
Test status
Simulation time 15842262 ps
CPU time 0.79 seconds
Started Jul 28 05:09:47 PM PDT 24
Finished Jul 28 05:09:48 PM PDT 24
Peak memory 200360 kb
Host smart-2f017be9-cad3-4f2c-ae76-ad98b3044aec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704824275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2704824275
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.2657433811
Short name T434
Test name
Test status
Simulation time 439600857 ps
CPU time 2.79 seconds
Started Jul 28 05:09:46 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 200380 kb
Host smart-6e3e49ea-adb5-4260-9faa-6ab7ffe454f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657433811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.2657433811
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.3490954898
Short name T43
Test name
Test status
Simulation time 156693048 ps
CPU time 1.92 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 215964 kb
Host smart-fafdcdc2-92b6-41fe-8ec9-fc3970a35d43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490954898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.3490954898
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.1249576500
Short name T443
Test name
Test status
Simulation time 21479813 ps
CPU time 0.84 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200396 kb
Host smart-c6cd71b3-727a-4a09-8a89-ff6ce5f20044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249576500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1249576500
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.4010540910
Short name T377
Test name
Test status
Simulation time 9980225098 ps
CPU time 67.54 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 201048 kb
Host smart-e39b2d8a-1c34-4763-8e99-1c7ec3fb9382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010540910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.4010540910
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.3528484730
Short name T599
Test name
Test status
Simulation time 104910399900 ps
CPU time 704.34 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:21:42 PM PDT 24
Peak memory 217264 kb
Host smart-697a6877-f091-48da-a163-2a720a253a3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3528484730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.3528484730
Directory /workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.clkmgr_trans.2189838176
Short name T657
Test name
Test status
Simulation time 315883099 ps
CPU time 1.87 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200412 kb
Host smart-6460bbdb-1306-4878-897c-35df213c55c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189838176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2189838176
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.2760194837
Short name T361
Test name
Test status
Simulation time 61306787 ps
CPU time 0.9 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200432 kb
Host smart-4ad83b08-12e4-4791-b5dc-6461f28cd9a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760194837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.2760194837
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.3785292111
Short name T691
Test name
Test status
Simulation time 21814532 ps
CPU time 0.86 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200416 kb
Host smart-2e02f2a1-0191-48b2-a099-e9da3030d105
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785292111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.3785292111
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.1756246608
Short name T181
Test name
Test status
Simulation time 17827170 ps
CPU time 0.72 seconds
Started Jul 28 05:10:34 PM PDT 24
Finished Jul 28 05:10:34 PM PDT 24
Peak memory 200300 kb
Host smart-992945d9-f9bb-4fb0-b308-2b72558823ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756246608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1756246608
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.3254930966
Short name T346
Test name
Test status
Simulation time 17553590 ps
CPU time 0.79 seconds
Started Jul 28 05:10:41 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200408 kb
Host smart-24841f87-63fe-4ac1-8f6c-622cc1db3bf3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254930966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.3254930966
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.1278827776
Short name T242
Test name
Test status
Simulation time 18575274 ps
CPU time 0.8 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200420 kb
Host smart-85bcc396-28d1-4cc3-a2da-228da17e6806
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278827776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1278827776
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.3808655120
Short name T538
Test name
Test status
Simulation time 320583013 ps
CPU time 2.67 seconds
Started Jul 28 05:10:48 PM PDT 24
Finished Jul 28 05:10:50 PM PDT 24
Peak memory 200500 kb
Host smart-75729506-86b7-4c70-8514-a8e38ed7ae2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808655120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3808655120
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.1989415427
Short name T254
Test name
Test status
Simulation time 1107099629 ps
CPU time 6.38 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200584 kb
Host smart-09cd049d-847c-4146-adea-cee5c367418f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989415427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.1989415427
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2516271236
Short name T197
Test name
Test status
Simulation time 103199867 ps
CPU time 1.14 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200460 kb
Host smart-b30f8585-282c-4aa9-a9c2-5e84cf700114
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516271236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.2516271236
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.3881538984
Short name T151
Test name
Test status
Simulation time 19056867 ps
CPU time 0.81 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200460 kb
Host smart-8d4926d5-6b3f-4c12-8825-b0d1b771fccb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881538984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.3881538984
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3556691867
Short name T276
Test name
Test status
Simulation time 19141385 ps
CPU time 0.8 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 200364 kb
Host smart-a95c2716-1585-4827-bc29-393ba839218d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556691867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3556691867
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.1032596865
Short name T153
Test name
Test status
Simulation time 18492347 ps
CPU time 0.79 seconds
Started Jul 28 05:10:43 PM PDT 24
Finished Jul 28 05:10:44 PM PDT 24
Peak memory 200360 kb
Host smart-7c49188c-b26e-4822-905c-abb445d5605d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032596865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.1032596865
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.906285702
Short name T605
Test name
Test status
Simulation time 76223535 ps
CPU time 0.97 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200472 kb
Host smart-9ce7eaa6-3a58-44e6-b319-b8a45b9cfd46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906285702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.906285702
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.42693219
Short name T756
Test name
Test status
Simulation time 26014739 ps
CPU time 0.83 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 200404 kb
Host smart-c8df4917-8c32-4279-9059-1d0500f61add
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42693219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.42693219
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.3256671021
Short name T791
Test name
Test status
Simulation time 406711764 ps
CPU time 3.96 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:44 PM PDT 24
Peak memory 200556 kb
Host smart-5af220d3-d94d-48d6-b1ab-5007ceefd617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256671021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.3256671021
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.812439939
Short name T509
Test name
Test status
Simulation time 20111150 ps
CPU time 0.82 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200448 kb
Host smart-731ea8f7-8cc0-4669-83ca-94e049576a66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812439939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.812439939
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.4046518575
Short name T51
Test name
Test status
Simulation time 16097596 ps
CPU time 0.74 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200480 kb
Host smart-27dbaef4-7eff-4d27-a616-8b7e23bb6f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046518575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.4046518575
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.4216102504
Short name T598
Test name
Test status
Simulation time 91388080 ps
CPU time 0.95 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200472 kb
Host smart-50e3a65a-4be3-42b1-9bb1-c0cc0da393a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216102504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.4216102504
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.1881552921
Short name T351
Test name
Test status
Simulation time 15733017 ps
CPU time 0.72 seconds
Started Jul 28 05:10:43 PM PDT 24
Finished Jul 28 05:10:44 PM PDT 24
Peak memory 200340 kb
Host smart-491323ba-1ca5-4d78-923a-51fa03e56039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881552921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.1881552921
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.2785436406
Short name T758
Test name
Test status
Simulation time 27287637 ps
CPU time 0.81 seconds
Started Jul 28 05:10:41 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200516 kb
Host smart-7ca76523-e4ea-4378-9c1f-7b500a0acb76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785436406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.2785436406
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.1067064240
Short name T206
Test name
Test status
Simulation time 35719482 ps
CPU time 0.77 seconds
Started Jul 28 05:10:41 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200412 kb
Host smart-355462f9-297e-4ca5-a25e-1637aecaa314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067064240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.1067064240
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.4250362146
Short name T1
Test name
Test status
Simulation time 683194711 ps
CPU time 5.92 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:09 PM PDT 24
Peak memory 200508 kb
Host smart-d4c1e724-c975-4a0e-8484-2be4218d44c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250362146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.4250362146
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.659367479
Short name T259
Test name
Test status
Simulation time 1275623669 ps
CPU time 5.72 seconds
Started Jul 28 05:10:41 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200548 kb
Host smart-0e68a726-f6cd-4ef2-a0f6-7fd5ea71a192
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659367479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_ti
meout.659367479
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1267001530
Short name T248
Test name
Test status
Simulation time 338286562 ps
CPU time 1.88 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:51 PM PDT 24
Peak memory 200412 kb
Host smart-61403bb5-4e14-4792-9f3e-275734070d0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267001530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1267001530
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3218554371
Short name T710
Test name
Test status
Simulation time 40232723 ps
CPU time 0.82 seconds
Started Jul 28 05:10:57 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200444 kb
Host smart-16163e60-46ad-4ec4-adfb-8ee65d08d234
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218554371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3218554371
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.566430703
Short name T583
Test name
Test status
Simulation time 19996819 ps
CPU time 0.79 seconds
Started Jul 28 05:10:40 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200408 kb
Host smart-7a237947-f359-4dd7-b094-743e7faab2b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566430703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.clkmgr_lc_ctrl_intersig_mubi.566430703
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.1552647230
Short name T459
Test name
Test status
Simulation time 36298074 ps
CPU time 0.79 seconds
Started Jul 28 05:10:50 PM PDT 24
Finished Jul 28 05:10:51 PM PDT 24
Peak memory 200448 kb
Host smart-8b4d6091-4db9-47f0-8892-d24f312c2d21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552647230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1552647230
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.484627418
Short name T466
Test name
Test status
Simulation time 57914067 ps
CPU time 0.93 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200412 kb
Host smart-2ac1bf5a-c3f7-4b9d-a0cf-2069f457124e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484627418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.484627418
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.611356907
Short name T139
Test name
Test status
Simulation time 227116468 ps
CPU time 1.39 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200316 kb
Host smart-f1c901ec-50a2-4eb1-9b85-4f39ec3ac519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611356907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.611356907
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.422337517
Short name T141
Test name
Test status
Simulation time 7450202205 ps
CPU time 38.89 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 200868 kb
Host smart-b271b278-e6a2-42ca-8e1c-efd337ec20f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422337517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.422337517
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.3786526410
Short name T310
Test name
Test status
Simulation time 83161695 ps
CPU time 1.05 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200384 kb
Host smart-b521d071-b5d4-4847-b32f-eeea44e34712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786526410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3786526410
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.539937707
Short name T627
Test name
Test status
Simulation time 54359463 ps
CPU time 0.91 seconds
Started Jul 28 05:10:59 PM PDT 24
Finished Jul 28 05:11:00 PM PDT 24
Peak memory 200412 kb
Host smart-e154d709-07c3-4246-8d3a-b4d7c5193208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539937707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkm
gr_alert_test.539937707
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3059209935
Short name T469
Test name
Test status
Simulation time 12598727 ps
CPU time 0.7 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200456 kb
Host smart-090ae9d6-38c9-40aa-ad26-9d7463ec7b51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059209935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3059209935
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.3526572753
Short name T637
Test name
Test status
Simulation time 26540114 ps
CPU time 0.72 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 199700 kb
Host smart-5a0da356-8a2b-4d6c-a6c7-fdc1cc3b85d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526572753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3526572753
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.3464859125
Short name T709
Test name
Test status
Simulation time 130676155 ps
CPU time 1.18 seconds
Started Jul 28 05:10:37 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 200476 kb
Host smart-a043a772-6182-4733-bc18-5744e022e655
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464859125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.3464859125
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.672420323
Short name T562
Test name
Test status
Simulation time 44826131 ps
CPU time 0.93 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200492 kb
Host smart-cc257eb8-778b-4f0e-8a66-f28fc81d4fcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672420323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.672420323
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.1754550385
Short name T578
Test name
Test status
Simulation time 2018223004 ps
CPU time 9.21 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200652 kb
Host smart-8287af53-0635-42a6-bbca-833e21792638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754550385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1754550385
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.646881119
Short name T105
Test name
Test status
Simulation time 670865934 ps
CPU time 2.91 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:12 PM PDT 24
Peak memory 200576 kb
Host smart-02ead04e-fb4c-4041-a534-40eec9e51e91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646881119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti
meout.646881119
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.1932307730
Short name T160
Test name
Test status
Simulation time 19848971 ps
CPU time 0.81 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200472 kb
Host smart-61e8eb95-684e-46e2-819f-c6ff3607b584
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932307730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.1932307730
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1292980547
Short name T677
Test name
Test status
Simulation time 25290005 ps
CPU time 0.87 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 200448 kb
Host smart-c65fa433-b10f-4686-a2c4-54ba12c795d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292980547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.1292980547
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3756967372
Short name T662
Test name
Test status
Simulation time 33315450 ps
CPU time 0.83 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200484 kb
Host smart-deded8b4-f833-4dc3-9dfe-5103dd599557
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756967372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.3756967372
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.2571623436
Short name T426
Test name
Test status
Simulation time 44995557 ps
CPU time 0.84 seconds
Started Jul 28 05:10:30 PM PDT 24
Finished Jul 28 05:10:31 PM PDT 24
Peak memory 200424 kb
Host smart-916b1893-65b6-49b1-a9c7-06d4dbaec0d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571623436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.2571623436
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.4223982527
Short name T643
Test name
Test status
Simulation time 986173962 ps
CPU time 5.46 seconds
Started Jul 28 05:10:43 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200724 kb
Host smart-c6ee6583-142a-4bb1-97d8-b67e5ec6b33a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223982527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.4223982527
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.2765177286
Short name T619
Test name
Test status
Simulation time 102158264 ps
CPU time 1.05 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200372 kb
Host smart-a71de070-018b-4045-b9ba-12bffa57cc3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765177286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.2765177286
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.2723604365
Short name T22
Test name
Test status
Simulation time 266210050 ps
CPU time 3.06 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200576 kb
Host smart-66accef2-cfcb-4d0e-8e57-e2b8ad3d63d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723604365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.2723604365
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.68540680
Short name T464
Test name
Test status
Simulation time 70864198 ps
CPU time 1 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 200420 kb
Host smart-b4dd2a61-81c9-4984-b400-50b91096d4ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68540680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.68540680
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1803195477
Short name T718
Test name
Test status
Simulation time 205232084 ps
CPU time 1.33 seconds
Started Jul 28 05:10:29 PM PDT 24
Finished Jul 28 05:10:35 PM PDT 24
Peak memory 200528 kb
Host smart-f5db513a-e96e-4244-b594-57dd0e2a46e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803195477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1803195477
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.4244202474
Short name T714
Test name
Test status
Simulation time 58916867 ps
CPU time 0.91 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:41 PM PDT 24
Peak memory 200504 kb
Host smart-1b5da32a-2223-41d5-8c2b-ceba02cc8e4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244202474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.4244202474
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.1403678223
Short name T554
Test name
Test status
Simulation time 27676592 ps
CPU time 0.75 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 199656 kb
Host smart-87eb3d7d-a822-4622-8169-4b6d85649164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403678223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1403678223
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3184698635
Short name T337
Test name
Test status
Simulation time 36585053 ps
CPU time 0.81 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200392 kb
Host smart-f57adc58-cc11-4445-bb4c-0b722e58fa20
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184698635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.3184698635
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.2746125519
Short name T353
Test name
Test status
Simulation time 16684682 ps
CPU time 0.79 seconds
Started Jul 28 05:10:50 PM PDT 24
Finished Jul 28 05:10:51 PM PDT 24
Peak memory 200472 kb
Host smart-4386b42c-90fb-4fbf-9bf2-980c4ec124a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746125519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2746125519
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.4265423609
Short name T565
Test name
Test status
Simulation time 1799899939 ps
CPU time 6.99 seconds
Started Jul 28 05:10:43 PM PDT 24
Finished Jul 28 05:10:51 PM PDT 24
Peak memory 200712 kb
Host smart-e2fd6880-d235-40f2-92f8-c329136c0f57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265423609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.4265423609
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.3194123259
Short name T24
Test name
Test status
Simulation time 2425785149 ps
CPU time 12.94 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200812 kb
Host smart-244c428d-edee-4560-a004-d6f1ab453a0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194123259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.3194123259
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.1611447790
Short name T72
Test name
Test status
Simulation time 31030098 ps
CPU time 0.85 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 200384 kb
Host smart-02f3b4ac-0241-4e97-8f3b-9a6a6f4b8ceb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611447790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.1611447790
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3467222626
Short name T776
Test name
Test status
Simulation time 15889505 ps
CPU time 0.75 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:46 PM PDT 24
Peak memory 200380 kb
Host smart-c7e99b20-291c-413f-8aa1-0c2cba3405da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467222626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3467222626
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1357325585
Short name T659
Test name
Test status
Simulation time 23625019 ps
CPU time 0.81 seconds
Started Jul 28 05:10:36 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 200404 kb
Host smart-09859892-1f69-4e79-8bc7-7193dd9f40d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357325585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1357325585
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.1424753376
Short name T813
Test name
Test status
Simulation time 48668298 ps
CPU time 0.85 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 200452 kb
Host smart-74202e2a-1ac1-457f-b9ef-4ce4cf8d9f0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424753376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1424753376
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.854905436
Short name T547
Test name
Test status
Simulation time 213760686 ps
CPU time 1.66 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 200404 kb
Host smart-66ca32f4-fc57-42f1-93b7-64d0336a13f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854905436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.854905436
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.1346064377
Short name T52
Test name
Test status
Simulation time 17015135 ps
CPU time 0.81 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200412 kb
Host smart-e7f72b97-7ed7-4b04-a51a-84d2cfd8c320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346064377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.1346064377
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.2772310385
Short name T35
Test name
Test status
Simulation time 5468550489 ps
CPU time 22.62 seconds
Started Jul 28 05:10:38 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200868 kb
Host smart-ef7af2c6-a025-4098-bb0a-0c8c6bd88c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772310385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.2772310385
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.2929611846
Short name T733
Test name
Test status
Simulation time 22855737 ps
CPU time 0.83 seconds
Started Jul 28 05:10:57 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200456 kb
Host smart-4621ec25-4c70-438c-a3b0-ac1b67ca4331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929611846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2929611846
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.2246944942
Short name T568
Test name
Test status
Simulation time 31058691 ps
CPU time 0.79 seconds
Started Jul 28 05:10:41 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200428 kb
Host smart-a8382b6b-0fa5-4295-91b4-047a48da6036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246944942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.2246944942
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3846873663
Short name T408
Test name
Test status
Simulation time 102325512 ps
CPU time 1.17 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200432 kb
Host smart-2de8497b-84ab-4e5d-b42e-33d1df456c37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846873663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.3846873663
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.2851766438
Short name T769
Test name
Test status
Simulation time 39951428 ps
CPU time 0.75 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200376 kb
Host smart-2d42c51e-cb06-425b-a21e-86344789eda4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851766438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2851766438
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.3782496017
Short name T595
Test name
Test status
Simulation time 19624848 ps
CPU time 0.72 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200464 kb
Host smart-9b33b284-7cf6-44c0-9dae-8a69161c2959
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782496017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.3782496017
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.1867505152
Short name T376
Test name
Test status
Simulation time 214126069 ps
CPU time 1.42 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200440 kb
Host smart-a61e0ea9-392f-428e-9351-6512f25a6108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867505152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.1867505152
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.4137551055
Short name T822
Test name
Test status
Simulation time 1400382718 ps
CPU time 10.81 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:11:02 PM PDT 24
Peak memory 200512 kb
Host smart-f33bbdcd-e5e6-4eed-984c-d79a7cc57ad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137551055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.4137551055
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.3126064084
Short name T553
Test name
Test status
Simulation time 1949473382 ps
CPU time 10.52 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200476 kb
Host smart-2fd02ab4-eff8-42a3-82cd-6b535dd36af5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126064084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.3126064084
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.619809841
Short name T679
Test name
Test status
Simulation time 55765893 ps
CPU time 1.02 seconds
Started Jul 28 05:10:41 PM PDT 24
Finished Jul 28 05:10:42 PM PDT 24
Peak memory 200432 kb
Host smart-4efe9176-ba01-4020-b19b-23dd3de5a691
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619809841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_idle_intersig_mubi.619809841
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1243160496
Short name T587
Test name
Test status
Simulation time 280104971 ps
CPU time 1.57 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200436 kb
Host smart-5189a3bf-e176-4364-b280-f937634fc2f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243160496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.1243160496
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2770338991
Short name T653
Test name
Test status
Simulation time 21194308 ps
CPU time 0.79 seconds
Started Jul 28 05:10:57 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200460 kb
Host smart-66f8e66c-ce14-4498-a745-ce1b84b8ede4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770338991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.2770338991
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.3690816340
Short name T198
Test name
Test status
Simulation time 51220502 ps
CPU time 0.85 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200412 kb
Host smart-fe2725fe-fec5-4764-ad37-0ca2e767d899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690816340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.3690816340
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2628187921
Short name T799
Test name
Test status
Simulation time 299532147 ps
CPU time 1.48 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200404 kb
Host smart-83a56f9e-b653-408d-b79a-8bbbb1bbed79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628187921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2628187921
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.3426172745
Short name T746
Test name
Test status
Simulation time 57235832 ps
CPU time 0.94 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200312 kb
Host smart-c9e63c7d-1a30-4520-b5da-2c7102430609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426172745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.3426172745
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.3700669013
Short name T768
Test name
Test status
Simulation time 1773295545 ps
CPU time 7.97 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200708 kb
Host smart-70dde5ed-76a2-4649-a363-80ce29749d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700669013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.3700669013
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.73729437
Short name T624
Test name
Test status
Simulation time 446087773569 ps
CPU time 1885.81 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:42:13 PM PDT 24
Peak memory 217344 kb
Host smart-c6df93f3-5d8b-46f4-b479-ab0b13a02f64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=73729437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.73729437
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.clkmgr_trans.4054455142
Short name T563
Test name
Test status
Simulation time 54773660 ps
CPU time 0.86 seconds
Started Jul 28 05:11:17 PM PDT 24
Finished Jul 28 05:11:18 PM PDT 24
Peak memory 200424 kb
Host smart-8cf3f2c3-81e0-48fd-8462-4a0142da4609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054455142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.4054455142
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3094456604
Short name T544
Test name
Test status
Simulation time 122213847 ps
CPU time 1.03 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200424 kb
Host smart-2b6ec83b-aca9-45d3-a728-385a79ac03fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094456604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3094456604
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3129066188
Short name T29
Test name
Test status
Simulation time 26016435 ps
CPU time 0.9 seconds
Started Jul 28 05:10:43 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 200468 kb
Host smart-057bdb47-eccd-4a0e-bba7-d29a27acb1e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129066188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.3129066188
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.201289850
Short name T410
Test name
Test status
Simulation time 28821435 ps
CPU time 0.76 seconds
Started Jul 28 05:10:39 PM PDT 24
Finished Jul 28 05:10:40 PM PDT 24
Peak memory 200336 kb
Host smart-eb98d9cd-7f55-41bc-8c97-781ac441ba6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201289850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.201289850
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.2026179789
Short name T325
Test name
Test status
Simulation time 50845564 ps
CPU time 0.89 seconds
Started Jul 28 05:11:06 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 200416 kb
Host smart-1013131c-397e-4bae-8d61-1ce0ac56e634
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026179789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.2026179789
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3037915813
Short name T740
Test name
Test status
Simulation time 16205183 ps
CPU time 0.74 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200392 kb
Host smart-ecc75688-57de-43a7-8770-1806925f2be2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037915813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3037915813
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.1984297952
Short name T417
Test name
Test status
Simulation time 236453900 ps
CPU time 1.64 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:04 PM PDT 24
Peak memory 200528 kb
Host smart-ddfb0e37-3a70-4c2e-9701-861209c0e13d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984297952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1984297952
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.234456640
Short name T473
Test name
Test status
Simulation time 399994529 ps
CPU time 2.22 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200536 kb
Host smart-c8460ef8-3f3b-4818-a700-a162b5339290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234456640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_ti
meout.234456640
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3867581516
Short name T451
Test name
Test status
Simulation time 51290288 ps
CPU time 0.89 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200296 kb
Host smart-b2b70efe-0b6c-41d6-adcf-c53cfb206409
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867581516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3867581516
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.203058721
Short name T365
Test name
Test status
Simulation time 61726983 ps
CPU time 0.91 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200712 kb
Host smart-76836c67-88e0-4bf1-9404-94f884fffce6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203058721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.clkmgr_lc_clk_byp_req_intersig_mubi.203058721
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.2093011932
Short name T359
Test name
Test status
Simulation time 18836413 ps
CPU time 0.74 seconds
Started Jul 28 05:10:42 PM PDT 24
Finished Jul 28 05:10:43 PM PDT 24
Peak memory 200452 kb
Host smart-ae5d5635-59e7-464c-9c9d-6bf7ceeb82b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093011932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.2093011932
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.526459794
Short name T240
Test name
Test status
Simulation time 20374294 ps
CPU time 0.78 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200448 kb
Host smart-3d307565-6640-4263-82f0-ed9a724f75d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526459794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.526459794
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.836443566
Short name T748
Test name
Test status
Simulation time 1522389967 ps
CPU time 5.16 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200552 kb
Host smart-fba67bc9-55a1-46b4-8e9d-3971c6680002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836443566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.836443566
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.2886363196
Short name T661
Test name
Test status
Simulation time 15720384 ps
CPU time 0.78 seconds
Started Jul 28 05:10:54 PM PDT 24
Finished Jul 28 05:10:55 PM PDT 24
Peak memory 200348 kb
Host smart-0a308f7e-0955-4dbb-a3eb-18930a7a5af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886363196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2886363196
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.4216279365
Short name T778
Test name
Test status
Simulation time 209588083 ps
CPU time 2.12 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:13 PM PDT 24
Peak memory 200448 kb
Host smart-d9cc8ab1-4b56-4780-b7f6-d48571c0013f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216279365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.4216279365
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.371673509
Short name T630
Test name
Test status
Simulation time 33814729 ps
CPU time 0.99 seconds
Started Jul 28 05:10:58 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 200676 kb
Host smart-60e6b1f7-8d4e-479f-b009-5193ddd09ca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371673509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.371673509
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.844521593
Short name T514
Test name
Test status
Simulation time 18024071 ps
CPU time 0.75 seconds
Started Jul 28 05:10:50 PM PDT 24
Finished Jul 28 05:10:51 PM PDT 24
Peak memory 200368 kb
Host smart-35d9edfd-0641-4464-932b-c3ece6273f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844521593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkm
gr_alert_test.844521593
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.2541523578
Short name T93
Test name
Test status
Simulation time 22735981 ps
CPU time 0.87 seconds
Started Jul 28 05:10:50 PM PDT 24
Finished Jul 28 05:10:51 PM PDT 24
Peak memory 200468 kb
Host smart-300b13c3-82c3-4116-9534-55cf3788d0c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541523578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.2541523578
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.1356342603
Short name T820
Test name
Test status
Simulation time 20515965 ps
CPU time 0.77 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:03 PM PDT 24
Peak memory 199652 kb
Host smart-94035e1c-fdbe-4248-8168-aa693fa16e2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356342603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1356342603
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2119125631
Short name T148
Test name
Test status
Simulation time 60725698 ps
CPU time 0.96 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200676 kb
Host smart-fde27a5b-8e69-412a-9677-4bc2497aec6b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119125631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.2119125631
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.2102331183
Short name T358
Test name
Test status
Simulation time 23501948 ps
CPU time 0.85 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200416 kb
Host smart-4c2a800f-fcf1-4d80-a255-f2b4e55788af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102331183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2102331183
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.862196472
Short name T317
Test name
Test status
Simulation time 2309022499 ps
CPU time 9.99 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:55 PM PDT 24
Peak memory 200560 kb
Host smart-e42535c6-6e41-40ce-a2c2-3ff621d0c006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862196472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.862196472
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.809906919
Short name T329
Test name
Test status
Simulation time 2352343203 ps
CPU time 9.69 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200708 kb
Host smart-c457e436-878f-4a2b-bfa1-876f7011e982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809906919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_ti
meout.809906919
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.4166482526
Short name T298
Test name
Test status
Simulation time 40488473 ps
CPU time 1.05 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200424 kb
Host smart-1ebbd6d0-1d5c-4bbd-beed-ba3591d1dc9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166482526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.4166482526
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.2257958077
Short name T529
Test name
Test status
Simulation time 40887320 ps
CPU time 0.89 seconds
Started Jul 28 05:10:59 PM PDT 24
Finished Jul 28 05:11:00 PM PDT 24
Peak memory 200480 kb
Host smart-a1ab946a-7599-46c8-8525-e126f7bc53fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257958077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.2257958077
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3377699975
Short name T225
Test name
Test status
Simulation time 34755391 ps
CPU time 0.76 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200416 kb
Host smart-a0a92ecf-c85c-4978-bd76-43496522c46f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377699975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.3377699975
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.187540780
Short name T294
Test name
Test status
Simulation time 71409335 ps
CPU time 0.91 seconds
Started Jul 28 05:10:55 PM PDT 24
Finished Jul 28 05:10:56 PM PDT 24
Peak memory 200456 kb
Host smart-e302fcf3-eb6e-43ee-bdd9-d9c8cc82a422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187540780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.187540780
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.42479298
Short name T156
Test name
Test status
Simulation time 405365535 ps
CPU time 2.79 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:09 PM PDT 24
Peak memory 200468 kb
Host smart-b256e553-28af-41f5-8992-ba6568fb4a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42479298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.42479298
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.557305577
Short name T343
Test name
Test status
Simulation time 27253065 ps
CPU time 0.84 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200420 kb
Host smart-6971e428-e91c-499f-b424-df68a4834082
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557305577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.557305577
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.3328533108
Short name T282
Test name
Test status
Simulation time 33351858 ps
CPU time 0.81 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200384 kb
Host smart-b41ea2a2-9329-430f-835d-fc6398a0fdf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328533108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.3328533108
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.2848347255
Short name T69
Test name
Test status
Simulation time 153807044146 ps
CPU time 632.31 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:21:23 PM PDT 24
Peak memory 209208 kb
Host smart-8ce5b157-4fcd-4b08-87c1-756509c28992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2848347255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2848347255
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1555702666
Short name T642
Test name
Test status
Simulation time 31697213 ps
CPU time 0.89 seconds
Started Jul 28 05:10:54 PM PDT 24
Finished Jul 28 05:10:55 PM PDT 24
Peak memory 200264 kb
Host smart-0a81257d-ce0c-45f2-b9d7-9f6880e43707
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555702666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1555702666
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.1156189060
Short name T552
Test name
Test status
Simulation time 145426292 ps
CPU time 1.14 seconds
Started Jul 28 05:11:05 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200432 kb
Host smart-b8b18730-e2dd-464d-9e1d-7f58d2d30131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156189060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.1156189060
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1860255124
Short name T383
Test name
Test status
Simulation time 47934724 ps
CPU time 0.86 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:11:04 PM PDT 24
Peak memory 200380 kb
Host smart-ad0db6d4-5897-4c3b-9648-89d8d4b5731e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860255124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.1860255124
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2410034010
Short name T436
Test name
Test status
Simulation time 45152717 ps
CPU time 0.74 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200320 kb
Host smart-1965d634-4c9c-44b8-ae45-4b52bb58b6a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410034010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2410034010
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.2600421062
Short name T450
Test name
Test status
Simulation time 29954316 ps
CPU time 0.81 seconds
Started Jul 28 05:10:57 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200400 kb
Host smart-c92533b1-557d-4880-8e17-35f77bcf4e90
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600421062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.2600421062
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.2930765295
Short name T540
Test name
Test status
Simulation time 69938135 ps
CPU time 1 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200368 kb
Host smart-472a46ff-7775-4f53-aca3-2e1ff56ef533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930765295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2930765295
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.1229526293
Short name T262
Test name
Test status
Simulation time 329159988 ps
CPU time 2.32 seconds
Started Jul 28 05:10:45 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200464 kb
Host smart-a3bb620b-24cb-4b13-9f00-3f124545f10c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229526293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1229526293
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.89501370
Short name T536
Test name
Test status
Simulation time 194053501 ps
CPU time 1.34 seconds
Started Jul 28 05:11:05 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200544 kb
Host smart-71c7c7e3-c402-4207-826b-d5329b0150e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89501370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_tim
eout.89501370
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.1449626223
Short name T429
Test name
Test status
Simulation time 24315252 ps
CPU time 0.87 seconds
Started Jul 28 05:10:51 PM PDT 24
Finished Jul 28 05:10:52 PM PDT 24
Peak memory 200468 kb
Host smart-08524caa-c3c6-4d6e-90c1-353bf3780fe1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449626223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.1449626223
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1824030474
Short name T427
Test name
Test status
Simulation time 73442533 ps
CPU time 0.99 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200364 kb
Host smart-470308ea-78eb-4238-b30b-b8d161269da3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824030474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1824030474
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1196587428
Short name T486
Test name
Test status
Simulation time 82347681 ps
CPU time 0.89 seconds
Started Jul 28 05:10:55 PM PDT 24
Finished Jul 28 05:10:56 PM PDT 24
Peak memory 200460 kb
Host smart-806c995b-efb7-4ae3-9eba-49184af315b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196587428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.1196587428
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.779525159
Short name T307
Test name
Test status
Simulation time 41662686 ps
CPU time 0.8 seconds
Started Jul 28 05:11:05 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200412 kb
Host smart-518ccf78-1e08-4cd1-9588-ff3ca82f25c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779525159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.779525159
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.462979320
Short name T506
Test name
Test status
Simulation time 675524183 ps
CPU time 2.91 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 200864 kb
Host smart-c28e8f66-dd1a-4f2c-8997-604eb6a21ba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462979320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.462979320
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.2513568422
Short name T482
Test name
Test status
Simulation time 73239329 ps
CPU time 0.97 seconds
Started Jul 28 05:10:48 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200412 kb
Host smart-65dd21dd-592a-4184-9b96-b1e5c0866b64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513568422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.2513568422
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.1457790133
Short name T123
Test name
Test status
Simulation time 2295519779 ps
CPU time 8.82 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200752 kb
Host smart-2d933ff9-c1a6-4021-9594-013ca7333bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457790133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.1457790133
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.3194944972
Short name T348
Test name
Test status
Simulation time 16856108 ps
CPU time 0.73 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:11:04 PM PDT 24
Peak memory 200460 kb
Host smart-77ade27e-2cc0-4611-91bb-6cfe57d46ad9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194944972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.3194944972
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.2905627211
Short name T224
Test name
Test status
Simulation time 14940371 ps
CPU time 0.72 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200472 kb
Host smart-3d6d77d1-4b0d-494e-a9e7-8cd1dbc386c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905627211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.2905627211
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1918826316
Short name T90
Test name
Test status
Simulation time 46794756 ps
CPU time 0.96 seconds
Started Jul 28 05:11:04 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200480 kb
Host smart-71ee46cb-2528-4bb5-8a1a-f1146bde8536
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918826316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.1918826316
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.3156663674
Short name T557
Test name
Test status
Simulation time 41694672 ps
CPU time 0.77 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 199664 kb
Host smart-d1b33906-578d-41af-950d-3a37a4b772c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156663674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3156663674
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.3056758892
Short name T725
Test name
Test status
Simulation time 17774616 ps
CPU time 0.8 seconds
Started Jul 28 05:11:11 PM PDT 24
Finished Jul 28 05:11:12 PM PDT 24
Peak memory 200436 kb
Host smart-3d8755ed-8159-43fa-a5b8-fdb531ab2857
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056758892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.3056758892
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.154217081
Short name T75
Test name
Test status
Simulation time 24549796 ps
CPU time 0.86 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:03 PM PDT 24
Peak memory 200416 kb
Host smart-e95f82c0-ade2-4e57-903b-d6960cb8d89a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154217081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.154217081
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.3124941374
Short name T513
Test name
Test status
Simulation time 2299935099 ps
CPU time 8.64 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 200708 kb
Host smart-7940d09c-40dd-45ec-a677-608a9b176d7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124941374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.3124941374
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.2945520157
Short name T767
Test name
Test status
Simulation time 137706311 ps
CPU time 1.28 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:50 PM PDT 24
Peak memory 200572 kb
Host smart-88bc4c02-e3f8-4626-a5f3-b7fb9a998307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945520157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.2945520157
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.916577828
Short name T534
Test name
Test status
Simulation time 29529233 ps
CPU time 0.99 seconds
Started Jul 28 05:10:57 PM PDT 24
Finished Jul 28 05:10:58 PM PDT 24
Peak memory 200428 kb
Host smart-36ad631e-189f-46ea-b95c-7dde482ea2b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916577828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_idle_intersig_mubi.916577828
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2761703532
Short name T495
Test name
Test status
Simulation time 41322550 ps
CPU time 0.77 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200424 kb
Host smart-ade3894d-f367-4bc3-88cc-75181630ad7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761703532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2761703532
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.4251403503
Short name T754
Test name
Test status
Simulation time 95075264 ps
CPU time 1.09 seconds
Started Jul 28 05:11:01 PM PDT 24
Finished Jul 28 05:11:03 PM PDT 24
Peak memory 200468 kb
Host smart-a500c482-139c-4839-926c-353a3ab1bc91
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251403503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.4251403503
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.634954362
Short name T766
Test name
Test status
Simulation time 16719871 ps
CPU time 0.73 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200436 kb
Host smart-8648c19a-b99d-4c9d-b883-cc8236ded96c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634954362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.634954362
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.475320347
Short name T159
Test name
Test status
Simulation time 88827617 ps
CPU time 0.92 seconds
Started Jul 28 05:10:59 PM PDT 24
Finished Jul 28 05:11:00 PM PDT 24
Peak memory 200384 kb
Host smart-d9a3710e-44a1-415b-a184-c43e6e484f46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475320347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.475320347
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.858070367
Short name T20
Test name
Test status
Simulation time 17060975 ps
CPU time 0.82 seconds
Started Jul 28 05:11:04 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200316 kb
Host smart-24796d4e-6cec-4815-8006-256214fd4e1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858070367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.858070367
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.365326671
Short name T419
Test name
Test status
Simulation time 9464569428 ps
CPU time 66.29 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:12:14 PM PDT 24
Peak memory 200856 kb
Host smart-be4d4cdd-62b3-4439-a5d2-dd705ed62313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365326671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.365326671
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.2761215702
Short name T493
Test name
Test status
Simulation time 43061530 ps
CPU time 0.96 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200476 kb
Host smart-8fccd181-c1f8-44c1-897b-35189658ec3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761215702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2761215702
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.2352169661
Short name T257
Test name
Test status
Simulation time 139850514 ps
CPU time 1.05 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200472 kb
Host smart-9196f2aa-1709-442c-97fa-c3cd5ae07cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352169661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.2352169661
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.2495472085
Short name T94
Test name
Test status
Simulation time 29206510 ps
CPU time 0.92 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:11:17 PM PDT 24
Peak memory 200484 kb
Host smart-7ae3bd6e-1ddc-4ccc-931b-9f10438dfecb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495472085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.2495472085
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.2494979031
Short name T176
Test name
Test status
Simulation time 15596340 ps
CPU time 0.74 seconds
Started Jul 28 05:10:58 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 199676 kb
Host smart-37d5ca80-02b6-4a82-aa12-35dd0957d211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494979031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2494979031
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.948084117
Short name T222
Test name
Test status
Simulation time 21112675 ps
CPU time 0.81 seconds
Started Jul 28 05:11:12 PM PDT 24
Finished Jul 28 05:11:13 PM PDT 24
Peak memory 200424 kb
Host smart-4125612a-21d1-4173-bdb1-c4e8116f0102
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948084117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_div_intersig_mubi.948084117
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.2734147989
Short name T728
Test name
Test status
Simulation time 17162036 ps
CPU time 0.72 seconds
Started Jul 28 05:10:54 PM PDT 24
Finished Jul 28 05:10:55 PM PDT 24
Peak memory 200424 kb
Host smart-5d9e8535-3b33-4b88-9878-5ddae691c43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734147989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2734147989
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.1284104271
Short name T3
Test name
Test status
Simulation time 928256033 ps
CPU time 4.17 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 200528 kb
Host smart-9fa4ceea-2c7c-4028-a4a3-c718c9940117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284104271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1284104271
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.2089785627
Short name T779
Test name
Test status
Simulation time 1722545920 ps
CPU time 7.22 seconds
Started Jul 28 05:10:58 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200544 kb
Host smart-4fbb805a-0d29-403a-b4c2-189014f744b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089785627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.2089785627
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1941335324
Short name T527
Test name
Test status
Simulation time 14740478 ps
CPU time 0.75 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200508 kb
Host smart-8707d84b-5d46-489b-876e-9e012b6b3e7c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941335324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.1941335324
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1698961240
Short name T44
Test name
Test status
Simulation time 37864226 ps
CPU time 0.81 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:09 PM PDT 24
Peak memory 200440 kb
Host smart-e5988e04-a6a1-4f49-bf95-4c61624836df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698961240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1698961240
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1841202324
Short name T736
Test name
Test status
Simulation time 19698030 ps
CPU time 0.78 seconds
Started Jul 28 05:10:48 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200376 kb
Host smart-afabc3e3-c0c6-4753-ac4e-468ff2f7e7b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841202324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.1841202324
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.3815766003
Short name T250
Test name
Test status
Simulation time 17644755 ps
CPU time 0.69 seconds
Started Jul 28 05:10:58 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 200412 kb
Host smart-da0426f7-5e16-497a-bb65-c69506c1736b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815766003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3815766003
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.112350534
Short name T236
Test name
Test status
Simulation time 53572061 ps
CPU time 0.9 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200424 kb
Host smart-7aaae230-3061-47a5-bd91-41dd63e4b26a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112350534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.112350534
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.1182100429
Short name T214
Test name
Test status
Simulation time 3512605909 ps
CPU time 19.84 seconds
Started Jul 28 05:10:48 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200844 kb
Host smart-7d48df11-c506-402e-9d83-9e350f06a43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182100429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.1182100429
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.2778060989
Short name T218
Test name
Test status
Simulation time 228752314 ps
CPU time 1.4 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200696 kb
Host smart-a82791e5-de46-4c0d-a4a6-7c238d743250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778060989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2778060989
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.1900876087
Short name T475
Test name
Test status
Simulation time 66473892 ps
CPU time 0.92 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:46 PM PDT 24
Peak memory 200404 kb
Host smart-76360103-6022-4ca2-87f8-24527d649011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900876087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.1900876087
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1393327036
Short name T273
Test name
Test status
Simulation time 25858563 ps
CPU time 0.92 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:46 PM PDT 24
Peak memory 200464 kb
Host smart-c7cc6009-8aa0-45f9-b6f5-7b7db1ae7f07
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393327036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1393327036
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.1284504360
Short name T635
Test name
Test status
Simulation time 27063140 ps
CPU time 0.72 seconds
Started Jul 28 05:09:37 PM PDT 24
Finished Jul 28 05:09:38 PM PDT 24
Peak memory 199684 kb
Host smart-1e70f026-3412-4ade-8fc8-698fd3aba991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284504360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1284504360
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1791949033
Short name T116
Test name
Test status
Simulation time 30391405 ps
CPU time 0.96 seconds
Started Jul 28 05:09:36 PM PDT 24
Finished Jul 28 05:09:37 PM PDT 24
Peak memory 200356 kb
Host smart-4a55bf43-3bd3-4371-b938-56cbfbdc9a15
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791949033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1791949033
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.1126454079
Short name T787
Test name
Test status
Simulation time 18624174 ps
CPU time 0.86 seconds
Started Jul 28 05:10:04 PM PDT 24
Finished Jul 28 05:10:05 PM PDT 24
Peak memory 200400 kb
Host smart-300ec086-ac6a-4765-8be3-a0a8b5d461c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126454079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1126454079
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.685335082
Short name T636
Test name
Test status
Simulation time 1428159403 ps
CPU time 6.73 seconds
Started Jul 28 05:09:46 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 200504 kb
Host smart-998db596-2c5e-41a0-bfd0-6db521251547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685335082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.685335082
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.3175877275
Short name T750
Test name
Test status
Simulation time 1002614577 ps
CPU time 4.46 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 200544 kb
Host smart-84d4476f-e24a-495a-82c4-03c2b4696ca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175877275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.3175877275
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1811415557
Short name T292
Test name
Test status
Simulation time 57860124 ps
CPU time 0.91 seconds
Started Jul 28 05:09:51 PM PDT 24
Finished Jul 28 05:09:52 PM PDT 24
Peak memory 200356 kb
Host smart-852470b5-a206-4078-945b-775e44239e80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811415557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.1811415557
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3258539826
Short name T363
Test name
Test status
Simulation time 22207358 ps
CPU time 0.85 seconds
Started Jul 28 05:09:44 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 200420 kb
Host smart-3309cde4-fd21-47aa-9faa-e4d9a147aedb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258539826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.3258539826
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3925683051
Short name T796
Test name
Test status
Simulation time 97606181 ps
CPU time 1.01 seconds
Started Jul 28 05:09:54 PM PDT 24
Finished Jul 28 05:09:55 PM PDT 24
Peak memory 200408 kb
Host smart-7383879e-b647-4d82-b831-d056119b23f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925683051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.3925683051
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.1078469076
Short name T199
Test name
Test status
Simulation time 27779891 ps
CPU time 0.75 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 200412 kb
Host smart-5d3e5b90-a6fc-4d63-abb3-274be654dbde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078469076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.1078469076
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.1309229674
Short name T570
Test name
Test status
Simulation time 416804150 ps
CPU time 2.74 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 200376 kb
Host smart-654c729c-0180-4281-8f6d-722303cafb18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309229674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1309229674
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.4010734902
Short name T54
Test name
Test status
Simulation time 337133003 ps
CPU time 2.48 seconds
Started Jul 28 05:10:20 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 215956 kb
Host smart-fb910aed-f142-4c5e-9e6b-2f28e8b68411
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010734902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.4010734902
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.51814449
Short name T700
Test name
Test status
Simulation time 29325847 ps
CPU time 0.82 seconds
Started Jul 28 05:09:42 PM PDT 24
Finished Jul 28 05:09:43 PM PDT 24
Peak memory 200316 kb
Host smart-9055a6bf-cf5e-4940-a418-3b56c2bf04ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51814449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.51814449
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.1055367456
Short name T632
Test name
Test status
Simulation time 42701423 ps
CPU time 0.98 seconds
Started Jul 28 05:09:49 PM PDT 24
Finished Jul 28 05:09:50 PM PDT 24
Peak memory 200480 kb
Host smart-fabfac8c-8a8c-4dbd-949e-ea224c389fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055367456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.1055367456
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.252893253
Short name T70
Test name
Test status
Simulation time 29915963276 ps
CPU time 176.26 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:12:52 PM PDT 24
Peak memory 217264 kb
Host smart-00bc9f8d-5b13-498e-ad72-23e561769023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=252893253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.252893253
Directory /workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1540141412
Short name T591
Test name
Test status
Simulation time 43943954 ps
CPU time 0.89 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 200456 kb
Host smart-75d8807a-cbf8-47ee-86dd-5e740e481b02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540141412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1540141412
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.3379975130
Short name T480
Test name
Test status
Simulation time 103702034 ps
CPU time 0.99 seconds
Started Jul 28 05:10:50 PM PDT 24
Finished Jul 28 05:10:51 PM PDT 24
Peak memory 200520 kb
Host smart-b7e16d05-5ac7-4361-8466-2b3446494f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379975130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.3379975130
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1030632023
Short name T202
Test name
Test status
Simulation time 19310272 ps
CPU time 0.82 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:11:04 PM PDT 24
Peak memory 200456 kb
Host smart-4d742b63-354e-42b3-bdbd-2c9e51984a65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030632023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.1030632023
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1425202198
Short name T580
Test name
Test status
Simulation time 16208416 ps
CPU time 0.7 seconds
Started Jul 28 05:10:53 PM PDT 24
Finished Jul 28 05:10:54 PM PDT 24
Peak memory 199668 kb
Host smart-7889ee47-384e-45dc-a758-249fe7c69e97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425202198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1425202198
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.197572020
Short name T355
Test name
Test status
Simulation time 27291820 ps
CPU time 0.91 seconds
Started Jul 28 05:11:05 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200456 kb
Host smart-54f321b3-3114-428e-be9b-a367b2bce6ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197572020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_div_intersig_mubi.197572020
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.2444617687
Short name T114
Test name
Test status
Simulation time 14032419 ps
CPU time 0.7 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:50 PM PDT 24
Peak memory 200304 kb
Host smart-40f9650b-a23b-4f32-ba4a-33f839f552c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444617687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.2444617687
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.617239438
Short name T476
Test name
Test status
Simulation time 782322877 ps
CPU time 3.3 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:12 PM PDT 24
Peak memory 200480 kb
Host smart-664b90c9-5f38-4d1d-ab86-b69d7945f208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617239438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.617239438
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.1821703850
Short name T27
Test name
Test status
Simulation time 2211187289 ps
CPU time 7.08 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 200664 kb
Host smart-d8855089-a85f-484e-a463-8fb64eb641c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821703850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.1821703850
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1916424642
Short name T402
Test name
Test status
Simulation time 40021963 ps
CPU time 0.94 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:11:14 PM PDT 24
Peak memory 200320 kb
Host smart-39d53105-5361-4a81-bbcf-29636e151ba6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916424642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1916424642
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2386823350
Short name T470
Test name
Test status
Simulation time 17966855 ps
CPU time 0.8 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200484 kb
Host smart-3bfd920d-0635-4b0a-8a41-df6f06dcc322
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386823350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.2386823350
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2551441648
Short name T797
Test name
Test status
Simulation time 29446234 ps
CPU time 0.8 seconds
Started Jul 28 05:11:17 PM PDT 24
Finished Jul 28 05:11:18 PM PDT 24
Peak memory 200448 kb
Host smart-7c899bfd-7653-4873-a31d-5a7f818a0eb9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551441648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.2551441648
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.4222022776
Short name T243
Test name
Test status
Simulation time 36751404 ps
CPU time 0.77 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200380 kb
Host smart-03b6162a-d183-4fe3-8ac2-e2b152f870d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222022776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.4222022776
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.3727275299
Short name T601
Test name
Test status
Simulation time 104195972 ps
CPU time 1.03 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200336 kb
Host smart-f507283b-093c-4d0b-a826-df6fbee1d5b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727275299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3727275299
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.3152377761
Short name T566
Test name
Test status
Simulation time 49156453 ps
CPU time 0.93 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200316 kb
Host smart-918ccab9-a239-4548-b57e-2e50932fe45d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152377761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.3152377761
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.4044197791
Short name T819
Test name
Test status
Simulation time 1912331879 ps
CPU time 10.4 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:11:02 PM PDT 24
Peak memory 200772 kb
Host smart-baccff7f-fe50-4901-82d8-6049956e9124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044197791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.4044197791
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.2604370040
Short name T192
Test name
Test status
Simulation time 281511809169 ps
CPU time 1166.22 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:30:30 PM PDT 24
Peak memory 212368 kb
Host smart-bb6da471-aa93-425e-9635-b66fab437a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2604370040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.2604370040
Directory /workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.clkmgr_trans.56784152
Short name T535
Test name
Test status
Simulation time 67055279 ps
CPU time 0.93 seconds
Started Jul 28 05:10:49 PM PDT 24
Finished Jul 28 05:10:50 PM PDT 24
Peak memory 200416 kb
Host smart-91eb625d-1bf3-43a8-92ed-1d529770ee0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56784152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.56784152
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1678551955
Short name T771
Test name
Test status
Simulation time 89030580 ps
CPU time 0.98 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200612 kb
Host smart-b11169c2-4f5d-4c90-a86c-88f9c23dadbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678551955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1678551955
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.215570576
Short name T788
Test name
Test status
Simulation time 26673324 ps
CPU time 0.83 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200476 kb
Host smart-0966b31e-cfbe-4d3f-a878-a674f6f89170
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215570576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.215570576
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.2126751031
Short name T449
Test name
Test status
Simulation time 47649492 ps
CPU time 0.76 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:00 PM PDT 24
Peak memory 199628 kb
Host smart-b8f48608-6ef5-4e7d-bd22-0c6ffbb1bbf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126751031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2126751031
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.4188591392
Short name T164
Test name
Test status
Simulation time 24505110 ps
CPU time 0.86 seconds
Started Jul 28 05:11:06 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 200444 kb
Host smart-a82e4170-a196-4b7f-ba12-68fb5f2dda8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188591392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.4188591392
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.831615921
Short name T299
Test name
Test status
Simulation time 12830056 ps
CPU time 0.77 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200380 kb
Host smart-d287ad3f-2672-467e-8f24-0c0bf7c8ab24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831615921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.831615921
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.2716276872
Short name T703
Test name
Test status
Simulation time 1166093749 ps
CPU time 7.99 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:17 PM PDT 24
Peak memory 200484 kb
Host smart-dfdd5d7e-43d7-47b9-a83b-78d8f00f9686
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716276872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2716276872
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.772982169
Short name T297
Test name
Test status
Simulation time 1573636004 ps
CPU time 11.29 seconds
Started Jul 28 05:10:59 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200552 kb
Host smart-6232f57b-fa7f-4636-bc7b-3f20df88515a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772982169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti
meout.772982169
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.2797178782
Short name T233
Test name
Test status
Simulation time 43217041 ps
CPU time 1.12 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200384 kb
Host smart-648199cc-377b-4af7-9d16-a1f17dbf9e30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797178782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.2797178782
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3457613128
Short name T190
Test name
Test status
Simulation time 49974005 ps
CPU time 0.87 seconds
Started Jul 28 05:11:06 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 200484 kb
Host smart-c9127c1f-25c4-4493-b315-eac077aab804
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457613128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3457613128
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.4287742116
Short name T280
Test name
Test status
Simulation time 32670324 ps
CPU time 0.81 seconds
Started Jul 28 05:11:11 PM PDT 24
Finished Jul 28 05:11:12 PM PDT 24
Peak memory 200700 kb
Host smart-b59c127b-aff7-4151-8293-b822b5b33a8a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287742116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.4287742116
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.2915106983
Short name T594
Test name
Test status
Simulation time 39862138 ps
CPU time 0.8 seconds
Started Jul 28 05:10:58 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 200372 kb
Host smart-499c3ba0-8971-4f07-a08a-15136930cc06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915106983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2915106983
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.3519846805
Short name T685
Test name
Test status
Simulation time 588038746 ps
CPU time 2.96 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:03 PM PDT 24
Peak memory 200484 kb
Host smart-f7f19de9-a594-461f-9171-6f200319fea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519846805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3519846805
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.2687636283
Short name T430
Test name
Test status
Simulation time 37243432 ps
CPU time 0.87 seconds
Started Jul 28 05:11:04 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200368 kb
Host smart-2acb48e9-6bcc-4a78-9e5e-6a2c2a92254a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687636283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2687636283
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.3187517801
Short name T633
Test name
Test status
Simulation time 6844256760 ps
CPU time 27.48 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 200904 kb
Host smart-04c2f27b-0401-498b-994e-d9e197aebd12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187517801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.3187517801
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.309534937
Short name T309
Test name
Test status
Simulation time 32787061 ps
CPU time 0.79 seconds
Started Jul 28 05:10:58 PM PDT 24
Finished Jul 28 05:10:59 PM PDT 24
Peak memory 200416 kb
Host smart-703773ea-c0ff-462e-bd3e-5cb7179be168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309534937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.309534937
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.1253447749
Short name T32
Test name
Test status
Simulation time 18038634 ps
CPU time 0.77 seconds
Started Jul 28 05:10:44 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 200328 kb
Host smart-5f24b378-c30d-4151-9929-b65e8ff9208c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253447749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.1253447749
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.2263027302
Short name T794
Test name
Test status
Simulation time 16393759 ps
CPU time 0.72 seconds
Started Jul 28 05:10:54 PM PDT 24
Finished Jul 28 05:11:00 PM PDT 24
Peak memory 199532 kb
Host smart-d338fee1-15c3-41d9-a5df-1cacf8a835b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263027302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2263027302
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1197372030
Short name T78
Test name
Test status
Simulation time 18240514 ps
CPU time 0.76 seconds
Started Jul 28 05:10:47 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200664 kb
Host smart-a37ce4a2-bc13-4407-8c23-7998e1304fb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197372030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.1197372030
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.2123228195
Short name T200
Test name
Test status
Simulation time 28717407 ps
CPU time 0.9 seconds
Started Jul 28 05:11:06 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 200452 kb
Host smart-e17f01f5-d8b3-45b2-ae07-89387d92c481
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123228195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2123228195
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.898733302
Short name T278
Test name
Test status
Simulation time 1572051084 ps
CPU time 7.02 seconds
Started Jul 28 05:11:05 PM PDT 24
Finished Jul 28 05:11:12 PM PDT 24
Peak memory 200324 kb
Host smart-8a650608-d6c4-49f7-8d8f-45d2e2d41db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898733302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.898733302
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.2387697833
Short name T263
Test name
Test status
Simulation time 136922527 ps
CPU time 1.71 seconds
Started Jul 28 05:11:05 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200520 kb
Host smart-80afd980-e79a-4c58-a80d-01577e544c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387697833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.2387697833
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3147303315
Short name T792
Test name
Test status
Simulation time 14628085 ps
CPU time 0.75 seconds
Started Jul 28 05:11:22 PM PDT 24
Finished Jul 28 05:11:23 PM PDT 24
Peak memory 200464 kb
Host smart-bf5255d7-e619-4dc7-ada5-ca857e693d74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147303315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.3147303315
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.774199388
Short name T47
Test name
Test status
Simulation time 26901412 ps
CPU time 0.87 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200428 kb
Host smart-559ffbe1-2e97-4727-90c5-dc694a55e228
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774199388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.clkmgr_lc_clk_byp_req_intersig_mubi.774199388
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3676920264
Short name T511
Test name
Test status
Simulation time 53844404 ps
CPU time 0.85 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:11:17 PM PDT 24
Peak memory 200432 kb
Host smart-6dba69e6-09d1-4ef3-9411-2533b1dcd3c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676920264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.3676920264
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.1251613638
Short name T244
Test name
Test status
Simulation time 16383533 ps
CPU time 0.76 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200456 kb
Host smart-b8a7fe52-48d7-4e0e-9459-550a7f844193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251613638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1251613638
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.1330418254
Short name T289
Test name
Test status
Simulation time 1082101865 ps
CPU time 6 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:17 PM PDT 24
Peak memory 200600 kb
Host smart-4523363a-a247-49b6-9001-07947dbb2407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330418254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1330418254
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.648198029
Short name T770
Test name
Test status
Simulation time 63750569 ps
CPU time 1 seconds
Started Jul 28 05:10:52 PM PDT 24
Finished Jul 28 05:10:53 PM PDT 24
Peak memory 200348 kb
Host smart-325220a6-fa9a-4302-a2e4-5e1771eb766f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648198029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.648198029
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.934452908
Short name T654
Test name
Test status
Simulation time 4880669908 ps
CPU time 24.97 seconds
Started Jul 28 05:11:11 PM PDT 24
Finished Jul 28 05:11:36 PM PDT 24
Peak memory 200864 kb
Host smart-624fcd7b-7cd3-4b87-96b8-9843ee4a7147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934452908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.934452908
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_trans.2214211667
Short name T407
Test name
Test status
Simulation time 93091687 ps
CPU time 1.12 seconds
Started Jul 28 05:10:59 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200356 kb
Host smart-deb413b4-60c1-4fec-9740-dc507470e0a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214211667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2214211667
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.958639796
Short name T617
Test name
Test status
Simulation time 18401999 ps
CPU time 0.76 seconds
Started Jul 28 05:11:01 PM PDT 24
Finished Jul 28 05:11:02 PM PDT 24
Peak memory 200480 kb
Host smart-3372923a-e60a-4b93-a0c8-8e4f2dbbc875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958639796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkm
gr_alert_test.958639796
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3849267512
Short name T504
Test name
Test status
Simulation time 59563414 ps
CPU time 0.9 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:15 PM PDT 24
Peak memory 200412 kb
Host smart-2790c809-fe5a-4587-b834-6fd576aa3b62
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849267512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.3849267512
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.1338249307
Short name T579
Test name
Test status
Simulation time 33885400 ps
CPU time 0.73 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 199652 kb
Host smart-7db81a29-27ad-4470-9a6c-8c78f80c4897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338249307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1338249307
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.3353987984
Short name T213
Test name
Test status
Simulation time 17771691 ps
CPU time 0.83 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:11:14 PM PDT 24
Peak memory 200372 kb
Host smart-56c11acc-53a6-40bf-821a-347cf4392bfb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353987984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.3353987984
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3418529845
Short name T501
Test name
Test status
Simulation time 77852592 ps
CPU time 1.07 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200404 kb
Host smart-ab29b8ae-d585-42b7-a857-84b554b61f41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418529845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3418529845
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.1987449821
Short name T395
Test name
Test status
Simulation time 1158626525 ps
CPU time 9.15 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 200488 kb
Host smart-91b600fc-25ab-4fae-a295-c43acb35c14c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987449821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1987449821
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.2781174668
Short name T311
Test name
Test status
Simulation time 501122002 ps
CPU time 4 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:11:07 PM PDT 24
Peak memory 200592 kb
Host smart-0085cc57-b848-4cca-953a-d3d8ab1a61cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781174668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.2781174668
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1428237819
Short name T795
Test name
Test status
Simulation time 28389897 ps
CPU time 0.8 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200292 kb
Host smart-35bdeb8a-93ad-439f-98ae-a0180a7f398b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428237819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1428237819
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3838674356
Short name T369
Test name
Test status
Simulation time 30262525 ps
CPU time 0.91 seconds
Started Jul 28 05:11:04 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200428 kb
Host smart-299b14a8-d936-4fd7-aa8b-a22c16ff884e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838674356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.3838674356
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3951895484
Short name T166
Test name
Test status
Simulation time 16971634 ps
CPU time 0.7 seconds
Started Jul 28 05:11:04 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200480 kb
Host smart-d3f59451-fd8f-4691-a3fd-1326eb2bb129
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951895484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.3951895484
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.2529011331
Short name T743
Test name
Test status
Simulation time 47284563 ps
CPU time 0.82 seconds
Started Jul 28 05:11:06 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200436 kb
Host smart-c0705a90-c155-4655-9466-b4f946eec124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529011331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2529011331
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.672665749
Short name T730
Test name
Test status
Simulation time 411414622 ps
CPU time 2.57 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:05 PM PDT 24
Peak memory 200420 kb
Host smart-558cd42b-5662-455a-91a8-0f040a55b4f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672665749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.672665749
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.299048547
Short name T537
Test name
Test status
Simulation time 32613763 ps
CPU time 0.84 seconds
Started Jul 28 05:10:46 PM PDT 24
Finished Jul 28 05:10:48 PM PDT 24
Peak memory 200348 kb
Host smart-40dd2d3d-4821-4632-b59b-69d611008d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299048547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.299048547
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_trans.1766196419
Short name T614
Test name
Test status
Simulation time 86669340 ps
CPU time 1.16 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200476 kb
Host smart-f04e2ab7-e117-4c58-b4f8-0ffc9a81ff55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766196419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1766196419
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.317167185
Short name T546
Test name
Test status
Simulation time 16019899 ps
CPU time 0.73 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200396 kb
Host smart-4a858e5c-f6d4-4912-9e37-eec5e95ce9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317167185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkm
gr_alert_test.317167185
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1071754845
Short name T302
Test name
Test status
Simulation time 119863630 ps
CPU time 1.18 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200712 kb
Host smart-b82bda86-e1e1-4e7c-9bec-e0d98c376afa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071754845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.1071754845
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.3919280564
Short name T707
Test name
Test status
Simulation time 15334094 ps
CPU time 0.69 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 199624 kb
Host smart-689d6c63-2b6d-4cde-a47c-44ee538084e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919280564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3919280564
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.724539466
Short name T453
Test name
Test status
Simulation time 21689113 ps
CPU time 0.84 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:11:04 PM PDT 24
Peak memory 200420 kb
Host smart-fbfcfd92-ff5a-413c-a1a9-444b04e97401
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724539466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_div_intersig_mubi.724539466
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.769319202
Short name T401
Test name
Test status
Simulation time 28369654 ps
CPU time 0.92 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200472 kb
Host smart-4e6d5348-60de-46da-92a1-78389f16267c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769319202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.769319202
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2077589128
Short name T734
Test name
Test status
Simulation time 319976616 ps
CPU time 2.41 seconds
Started Jul 28 05:10:58 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200740 kb
Host smart-3ea1d641-c4af-4609-9b8b-c97c4a839cee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077589128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2077589128
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.3305084754
Short name T162
Test name
Test status
Simulation time 882474229 ps
CPU time 3.75 seconds
Started Jul 28 05:11:12 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200560 kb
Host smart-3e98fe33-4ec5-4510-9af9-39c368fdfdb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305084754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.3305084754
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.2765360157
Short name T161
Test name
Test status
Simulation time 36689445 ps
CPU time 1.01 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:11:17 PM PDT 24
Peak memory 200412 kb
Host smart-41a7833b-b808-4c74-8278-915b137e6fce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765360157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.2765360157
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.212015094
Short name T576
Test name
Test status
Simulation time 46685558 ps
CPU time 0.83 seconds
Started Jul 28 05:11:03 PM PDT 24
Finished Jul 28 05:11:04 PM PDT 24
Peak memory 200380 kb
Host smart-d2f7df53-a5a8-4970-a07b-03c230393b76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212015094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_clk_byp_req_intersig_mubi.212015094
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2216257878
Short name T806
Test name
Test status
Simulation time 32458312 ps
CPU time 0.91 seconds
Started Jul 28 05:10:48 PM PDT 24
Finished Jul 28 05:10:49 PM PDT 24
Peak memory 200444 kb
Host smart-b0998ee4-b118-480b-81b1-0f9e88874e70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216257878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.2216257878
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.2417838064
Short name T265
Test name
Test status
Simulation time 33197199 ps
CPU time 0.85 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200408 kb
Host smart-e9335870-0a63-46ca-b01c-8dbd4ce0c6f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417838064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2417838064
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.2439746794
Short name T234
Test name
Test status
Simulation time 458027187 ps
CPU time 2.01 seconds
Started Jul 28 05:11:17 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 200408 kb
Host smart-51b2254e-e46d-45a3-8bcd-e8607f2b8310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439746794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.2439746794
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.2404720012
Short name T641
Test name
Test status
Simulation time 21972708 ps
CPU time 0.85 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200332 kb
Host smart-ded7ad07-0beb-4bbe-9ff5-57dd8350f5b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404720012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.2404720012
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.1851469900
Short name T81
Test name
Test status
Simulation time 13008437939 ps
CPU time 92.74 seconds
Started Jul 28 05:10:59 PM PDT 24
Finished Jul 28 05:12:32 PM PDT 24
Peak memory 200792 kb
Host smart-14de8133-5110-447f-90e8-cd741e73c961
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851469900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.1851469900
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.1785456488
Short name T33
Test name
Test status
Simulation time 125487795707 ps
CPU time 1003.79 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:28:03 PM PDT 24
Peak memory 217284 kb
Host smart-6cc060b7-6b42-42ad-b575-16ffb14f370d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1785456488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.1785456488
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.clkmgr_trans.3953673359
Short name T686
Test name
Test status
Simulation time 64651469 ps
CPU time 0.94 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:15 PM PDT 24
Peak memory 200408 kb
Host smart-c6b3f827-8b42-49fa-b37b-8f6ea3c155bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953673359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3953673359
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.402205823
Short name T672
Test name
Test status
Simulation time 16088565 ps
CPU time 0.8 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200424 kb
Host smart-6304577e-ad53-4517-be87-231d00a5dce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402205823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkm
gr_alert_test.402205823
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.1217188641
Short name T668
Test name
Test status
Simulation time 30002308 ps
CPU time 0.93 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200364 kb
Host smart-28bb6f7a-8b7c-411a-a99e-5adfe6076592
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217188641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.1217188641
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3953981329
Short name T711
Test name
Test status
Simulation time 17192050 ps
CPU time 0.72 seconds
Started Jul 28 05:10:56 PM PDT 24
Finished Jul 28 05:10:57 PM PDT 24
Peak memory 200440 kb
Host smart-e509c405-97f0-4c74-9ea0-aa0c27b37434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953981329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3953981329
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2020319932
Short name T440
Test name
Test status
Simulation time 52313561 ps
CPU time 1 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200468 kb
Host smart-09e9fb0c-406b-4f2b-8ea6-4f03ba2ff6f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020319932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2020319932
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.144710395
Short name T314
Test name
Test status
Simulation time 106608877 ps
CPU time 1.11 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200476 kb
Host smart-60d469dc-0b94-469d-9b78-0b64c0819836
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144710395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.144710395
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3511529951
Short name T692
Test name
Test status
Simulation time 2001551867 ps
CPU time 15.63 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 200636 kb
Host smart-b3fd7680-bd10-4263-9038-00d01dafdb4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511529951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3511529951
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.3586148982
Short name T339
Test name
Test status
Simulation time 978688122 ps
CPU time 7.75 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 200444 kb
Host smart-30edf8f3-93a7-40f8-ad53-997506a58ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586148982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.3586148982
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.1557162357
Short name T341
Test name
Test status
Simulation time 39699371 ps
CPU time 0.8 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200416 kb
Host smart-69ff31c4-e88a-476f-8815-477c42efa1dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557162357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.1557162357
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1011720444
Short name T118
Test name
Test status
Simulation time 60504606 ps
CPU time 0.95 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:04 PM PDT 24
Peak memory 200456 kb
Host smart-ec514c39-8a5d-4a19-8db6-e9c586baa4ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011720444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1011720444
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.323654356
Short name T428
Test name
Test status
Simulation time 13660166 ps
CPU time 0.75 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200408 kb
Host smart-e2f57e2b-e9f2-4eef-897b-23bb11c923c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323654356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_ctrl_intersig_mubi.323654356
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.266593642
Short name T463
Test name
Test status
Simulation time 18619082 ps
CPU time 0.77 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:01 PM PDT 24
Peak memory 200424 kb
Host smart-603a91af-f101-499b-9872-2ff381f92049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266593642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.266593642
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2734127
Short name T702
Test name
Test status
Simulation time 689248459 ps
CPU time 3.17 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:18 PM PDT 24
Peak memory 200596 kb
Host smart-4ee6fb80-88d0-424c-a4ee-4616340df94d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2734127
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.1444883134
Short name T701
Test name
Test status
Simulation time 44188726 ps
CPU time 0.86 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200352 kb
Host smart-def1c241-fc16-42d2-85dd-118450ed91b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444883134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1444883134
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.129737299
Short name T433
Test name
Test status
Simulation time 4038597935 ps
CPU time 20.41 seconds
Started Jul 28 05:11:00 PM PDT 24
Finished Jul 28 05:11:20 PM PDT 24
Peak memory 200844 kb
Host smart-c8293ac7-0733-4435-aad5-7d4e89db9a44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129737299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.129737299
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.3485108763
Short name T71
Test name
Test status
Simulation time 64465405425 ps
CPU time 839.37 seconds
Started Jul 28 05:11:01 PM PDT 24
Finished Jul 28 05:25:01 PM PDT 24
Peak memory 209088 kb
Host smart-3cbc4afa-f45f-4ae7-bc8b-136a06d5b2b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3485108763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.3485108763
Directory /workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.clkmgr_trans.3769935357
Short name T575
Test name
Test status
Simulation time 21725305 ps
CPU time 0.77 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:20 PM PDT 24
Peak memory 200408 kb
Host smart-651eee23-bab0-494e-a32b-fbea371ce1de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769935357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3769935357
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3187259264
Short name T551
Test name
Test status
Simulation time 16219562 ps
CPU time 0.79 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:09 PM PDT 24
Peak memory 200476 kb
Host smart-fd69699d-0a97-4469-ac09-c67d9cde87eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187259264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3187259264
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.3202636285
Short name T523
Test name
Test status
Simulation time 19297108 ps
CPU time 0.83 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200416 kb
Host smart-1590ddb0-a34e-46e0-8d24-cdde0e7c58eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202636285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.3202636285
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.299649613
Short name T609
Test name
Test status
Simulation time 43919471 ps
CPU time 0.79 seconds
Started Jul 28 05:11:12 PM PDT 24
Finished Jul 28 05:11:13 PM PDT 24
Peak memory 199620 kb
Host smart-165a4b0b-b69b-4f76-b2e8-ff6d6e4b82a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299649613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.299649613
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.781122601
Short name T256
Test name
Test status
Simulation time 16139155 ps
CPU time 0.77 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200448 kb
Host smart-63c30b95-7e9a-450b-88c9-a0954e0db810
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781122601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_div_intersig_mubi.781122601
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.4083261388
Short name T517
Test name
Test status
Simulation time 29562677 ps
CPU time 0.8 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:09 PM PDT 24
Peak memory 200464 kb
Host smart-f76d44dc-604e-484f-a70d-478cff80e631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083261388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.4083261388
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.2244438731
Short name T379
Test name
Test status
Simulation time 437882903 ps
CPU time 4.09 seconds
Started Jul 28 05:11:17 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200556 kb
Host smart-01339199-6a59-4b76-ab94-409600afbdfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244438731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.2244438731
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.2825840817
Short name T781
Test name
Test status
Simulation time 2323750101 ps
CPU time 8.83 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 200760 kb
Host smart-86cd574a-a26f-431d-ab6e-8e400281bc94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825840817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.2825840817
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.3786731012
Short name T708
Test name
Test status
Simulation time 27279689 ps
CPU time 0.95 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:14 PM PDT 24
Peak memory 200484 kb
Host smart-f26c4878-a4c2-407f-99d4-f82a5c7cc189
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786731012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.3786731012
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.4165967460
Short name T287
Test name
Test status
Simulation time 23028131 ps
CPU time 0.85 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200404 kb
Host smart-85f69087-9171-459e-8444-e6105069ce0c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165967460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.4165967460
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.623502678
Short name T567
Test name
Test status
Simulation time 41066309 ps
CPU time 0.94 seconds
Started Jul 28 05:11:11 PM PDT 24
Finished Jul 28 05:11:12 PM PDT 24
Peak memory 200420 kb
Host smart-567e8d19-4739-4448-af5f-44811382bf0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623502678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_ctrl_intersig_mubi.623502678
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.1776178014
Short name T742
Test name
Test status
Simulation time 29197665 ps
CPU time 0.79 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200424 kb
Host smart-f4c0c961-4f34-445f-945e-20d252131b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776178014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.1776178014
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.2976087473
Short name T279
Test name
Test status
Simulation time 1529922063 ps
CPU time 5.56 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200884 kb
Host smart-0915b48f-ca99-4834-9afc-7c0b136dddab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976087473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2976087473
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.3086731684
Short name T398
Test name
Test status
Simulation time 39747364 ps
CPU time 0.95 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 200260 kb
Host smart-abede6d9-2b42-44a4-8d8c-e8e2e07f161e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086731684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3086731684
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.914575408
Short name T13
Test name
Test status
Simulation time 5386987302 ps
CPU time 23.16 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 200824 kb
Host smart-62ed3222-d3f8-48a8-84bf-f4248f5ac547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914575408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.914575408
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.3988228412
Short name T705
Test name
Test status
Simulation time 70414269 ps
CPU time 1.02 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:11:17 PM PDT 24
Peak memory 200420 kb
Host smart-955bc4ec-602b-4f76-84ef-9c25ced56641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988228412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3988228412
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.1662375403
Short name T772
Test name
Test status
Simulation time 107924951 ps
CPU time 1.11 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 200392 kb
Host smart-71a988ff-f004-4f0b-8672-2e6e1dd64f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662375403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.1662375403
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3543157148
Short name T611
Test name
Test status
Simulation time 42865454 ps
CPU time 0.92 seconds
Started Jul 28 05:11:18 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 200420 kb
Host smart-889f89c7-0ffe-471e-a687-0b76084d6d2c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543157148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.3543157148
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.2097516836
Short name T386
Test name
Test status
Simulation time 17680832 ps
CPU time 0.73 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 199608 kb
Host smart-ea46733d-81fb-4b6b-ad48-51d66f25d18f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097516836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2097516836
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.106882471
Short name T152
Test name
Test status
Simulation time 15680029 ps
CPU time 0.82 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 200396 kb
Host smart-7a79e992-1a63-4a0d-baa5-a718603d4741
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106882471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_div_intersig_mubi.106882471
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.1079300482
Short name T543
Test name
Test status
Simulation time 114196328 ps
CPU time 0.99 seconds
Started Jul 28 05:11:02 PM PDT 24
Finished Jul 28 05:11:03 PM PDT 24
Peak memory 200688 kb
Host smart-b9d7753f-6367-4e51-bf13-14b6ae270001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079300482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1079300482
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.2563339288
Short name T502
Test name
Test status
Simulation time 1405807028 ps
CPU time 8.61 seconds
Started Jul 28 05:11:11 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 200464 kb
Host smart-429525a0-6aef-496c-9cb7-0fb2a7955ab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563339288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2563339288
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.1862110168
Short name T631
Test name
Test status
Simulation time 2319962295 ps
CPU time 9.85 seconds
Started Jul 28 05:11:12 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200804 kb
Host smart-e3c56297-05d1-46a8-8530-446bbe48cc74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862110168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.1862110168
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3482870854
Short name T16
Test name
Test status
Simulation time 35013690 ps
CPU time 0.92 seconds
Started Jul 28 05:11:05 PM PDT 24
Finished Jul 28 05:11:06 PM PDT 24
Peak memory 200412 kb
Host smart-dfc5062e-bc12-49f2-a359-b94342f30bbf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482870854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.3482870854
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1760772902
Short name T545
Test name
Test status
Simulation time 54804562 ps
CPU time 0.87 seconds
Started Jul 28 05:11:11 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200492 kb
Host smart-d7ea8516-74af-437a-8192-18ce2a8eb62a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760772902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.1760772902
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.394179772
Short name T673
Test name
Test status
Simulation time 102672342 ps
CPU time 1.07 seconds
Started Jul 28 05:10:55 PM PDT 24
Finished Jul 28 05:10:56 PM PDT 24
Peak memory 200464 kb
Host smart-b2f419fa-511a-4f62-ba79-5402e4c1d590
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394179772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.clkmgr_lc_ctrl_intersig_mubi.394179772
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.6468275
Short name T25
Test name
Test status
Simulation time 12705758 ps
CPU time 0.73 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200432 kb
Host smart-89393bbb-1c5c-471f-b2ea-2eafe2da2985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6468275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.6468275
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.3457012496
Short name T113
Test name
Test status
Simulation time 1118635766 ps
CPU time 6.73 seconds
Started Jul 28 05:11:17 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 200644 kb
Host smart-31ce2345-7a05-4b1e-a10c-e9c03feb62cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457012496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.3457012496
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.3828960374
Short name T558
Test name
Test status
Simulation time 20026852 ps
CPU time 0.85 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200424 kb
Host smart-0ea36149-a92c-4c0d-beb7-41d9711acd8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828960374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.3828960374
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.3092260090
Short name T607
Test name
Test status
Simulation time 36224231 ps
CPU time 0.82 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:15 PM PDT 24
Peak memory 200464 kb
Host smart-50ae1f20-97cc-45e0-acc1-7f8cfe7d07e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092260090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.3092260090
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.94306366
Short name T121
Test name
Test status
Simulation time 30082062 ps
CPU time 0.8 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200416 kb
Host smart-6dcc5fcf-174b-470f-bc5b-5ff54a50edf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94306366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.94306366
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.1106951307
Short name T676
Test name
Test status
Simulation time 23061630 ps
CPU time 0.76 seconds
Started Jul 28 05:11:34 PM PDT 24
Finished Jul 28 05:11:35 PM PDT 24
Peak memory 200476 kb
Host smart-860ea6e3-4ffd-4969-ab77-4d47cf44286d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106951307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.1106951307
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3774402636
Short name T92
Test name
Test status
Simulation time 40230965 ps
CPU time 0.81 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200504 kb
Host smart-d130c7e1-4473-450b-a0f8-5c3fe60b31d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774402636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.3774402636
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.1847323630
Short name T177
Test name
Test status
Simulation time 18697457 ps
CPU time 0.71 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 200340 kb
Host smart-f130507c-c86a-4ed8-b99c-79be132124c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847323630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.1847323630
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.810857704
Short name T79
Test name
Test status
Simulation time 67135865 ps
CPU time 0.96 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 200428 kb
Host smart-cd9a67b3-e7a1-4be8-b01e-f3ab61861a29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810857704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.810857704
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.2465901740
Short name T391
Test name
Test status
Simulation time 60410012 ps
CPU time 0.94 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 200468 kb
Host smart-1c4805db-e26e-4bed-b79c-42c03de35c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465901740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2465901740
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.1849898444
Short name T485
Test name
Test status
Simulation time 1275029792 ps
CPU time 10.65 seconds
Started Jul 28 05:11:10 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 200432 kb
Host smart-3278845e-40a7-446f-926d-66b53849eb72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849898444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1849898444
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.3788509376
Short name T521
Test name
Test status
Simulation time 263987612 ps
CPU time 2.04 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 200564 kb
Host smart-6b494c77-00fc-4c6b-8613-a604a1394478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788509376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.3788509376
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.789533132
Short name T650
Test name
Test status
Simulation time 55412272 ps
CPU time 1.09 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 200444 kb
Host smart-3124b54a-8eb5-4833-b456-c1d137b82214
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789533132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_idle_intersig_mubi.789533132
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.4283731643
Short name T327
Test name
Test status
Simulation time 61881567 ps
CPU time 0.94 seconds
Started Jul 28 05:11:25 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 200472 kb
Host smart-691667a7-1c2d-48a6-9b15-5d0156412d03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283731643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.4283731643
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2981061312
Short name T474
Test name
Test status
Simulation time 105684774 ps
CPU time 1.16 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:15 PM PDT 24
Peak memory 200520 kb
Host smart-641afd41-7ace-4e4d-b76d-ad511dc1be09
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981061312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.2981061312
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.2382671772
Short name T334
Test name
Test status
Simulation time 101355854 ps
CPU time 1.03 seconds
Started Jul 28 05:11:07 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200416 kb
Host smart-86078c7a-4ff6-49a9-b4f5-a06877e20e00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382671772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2382671772
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.1522603282
Short name T424
Test name
Test status
Simulation time 1060308329 ps
CPU time 5.65 seconds
Started Jul 28 05:11:18 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 200588 kb
Host smart-313e0453-4f72-409b-8619-bdfa3714061f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522603282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1522603282
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.3728297642
Short name T403
Test name
Test status
Simulation time 74047780 ps
CPU time 0.98 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:20 PM PDT 24
Peak memory 200356 kb
Host smart-ea62e8b9-4514-4658-b8b1-0239b2eb2932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728297642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.3728297642
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.986181263
Short name T67
Test name
Test status
Simulation time 54695914489 ps
CPU time 590.24 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:21:03 PM PDT 24
Peak memory 211592 kb
Host smart-6f3375c4-a7e3-4c7d-b0d8-5ecc9cb9b31e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=986181263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.986181263
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3786558657
Short name T352
Test name
Test status
Simulation time 115975475 ps
CPU time 1.26 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200464 kb
Host smart-bb5983e7-ad35-4d1b-aafa-173254d2d3c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786558657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3786558657
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.2353096667
Short name T285
Test name
Test status
Simulation time 18694665 ps
CPU time 0.75 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 200472 kb
Host smart-3eed444e-9fa6-40de-847e-206091dc8195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353096667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.2353096667
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.4086315910
Short name T550
Test name
Test status
Simulation time 196668463 ps
CPU time 1.34 seconds
Started Jul 28 05:11:17 PM PDT 24
Finished Jul 28 05:11:18 PM PDT 24
Peak memory 200400 kb
Host smart-eefc8bd0-adac-4e8a-964e-31908e117ce1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086315910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.4086315910
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.1830737894
Short name T390
Test name
Test status
Simulation time 15982939 ps
CPU time 0.71 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 199676 kb
Host smart-51dfcf5a-ef10-4307-9c54-dfbd2e2d98e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830737894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.1830737894
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.376646374
Short name T232
Test name
Test status
Simulation time 43404862 ps
CPU time 0.85 seconds
Started Jul 28 05:11:30 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 200424 kb
Host smart-14e9d13b-dee5-4225-b852-7c64078c062d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376646374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_div_intersig_mubi.376646374
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.489511167
Short name T374
Test name
Test status
Simulation time 24359803 ps
CPU time 0.86 seconds
Started Jul 28 05:11:12 PM PDT 24
Finished Jul 28 05:11:13 PM PDT 24
Peak memory 200520 kb
Host smart-aaeb3643-bb00-48c5-bbdb-d1bf7c7ced61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489511167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.489511167
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.1632355761
Short name T805
Test name
Test status
Simulation time 208635416 ps
CPU time 1.71 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 200524 kb
Host smart-0e14b8a3-16e6-42d6-aeda-db1588687838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632355761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.1632355761
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.384508652
Short name T731
Test name
Test status
Simulation time 1463648889 ps
CPU time 7.63 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 200612 kb
Host smart-04f3aae8-4397-47de-b41c-3fd7b9100aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384508652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_ti
meout.384508652
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.3839006921
Short name T532
Test name
Test status
Simulation time 52577058 ps
CPU time 0.89 seconds
Started Jul 28 05:11:14 PM PDT 24
Finished Jul 28 05:11:15 PM PDT 24
Peak memory 200364 kb
Host smart-11a687f7-614e-417f-ae1d-07833483fa1a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839006921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.3839006921
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.410813892
Short name T573
Test name
Test status
Simulation time 37338680 ps
CPU time 0.83 seconds
Started Jul 28 05:11:09 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200376 kb
Host smart-6e021da9-92c9-4adc-bb9c-53d572e8e9e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410813892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.clkmgr_lc_clk_byp_req_intersig_mubi.410813892
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3439203307
Short name T295
Test name
Test status
Simulation time 297591145 ps
CPU time 1.62 seconds
Started Jul 28 05:11:08 PM PDT 24
Finished Jul 28 05:11:10 PM PDT 24
Peak memory 200508 kb
Host smart-f93ea04f-1f43-4978-8acc-1dbfeb23c4ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439203307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3439203307
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.1940871248
Short name T183
Test name
Test status
Simulation time 18084778 ps
CPU time 0.74 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 200416 kb
Host smart-bef61f01-9943-4284-9eec-61fd4db615d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940871248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1940871248
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.3226428926
Short name T103
Test name
Test status
Simulation time 460028105 ps
CPU time 2.93 seconds
Started Jul 28 05:11:25 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 200460 kb
Host smart-a32713a9-2adb-4883-858b-7388bc02e820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226428926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3226428926
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.2468380794
Short name T360
Test name
Test status
Simulation time 38406886 ps
CPU time 0.92 seconds
Started Jul 28 05:11:06 PM PDT 24
Finished Jul 28 05:11:08 PM PDT 24
Peak memory 200344 kb
Host smart-8160c9e9-aca8-45d5-895f-0765d68f1e32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468380794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.2468380794
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.2171134880
Short name T140
Test name
Test status
Simulation time 6303948972 ps
CPU time 49.26 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:12:06 PM PDT 24
Peak memory 200820 kb
Host smart-bb7c38b2-0acb-4e3c-92b9-36b469b1b208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171134880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.2171134880
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.3204331276
Short name T66
Test name
Test status
Simulation time 35959646817 ps
CPU time 214.79 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:14:48 PM PDT 24
Peak memory 209176 kb
Host smart-363c7cab-f3e7-467c-a555-425e7ebffd5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3204331276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.3204331276
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.clkmgr_trans.133181303
Short name T194
Test name
Test status
Simulation time 96013270 ps
CPU time 1.17 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:20 PM PDT 24
Peak memory 200380 kb
Host smart-a53d1ba6-e9d1-4921-8539-13145b770d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133181303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.133181303
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.1842541827
Short name T542
Test name
Test status
Simulation time 16995271 ps
CPU time 0.76 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 200408 kb
Host smart-95ea7757-c4dc-4b6a-8977-c7b6c6984505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842541827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.1842541827
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.4264198718
Short name T418
Test name
Test status
Simulation time 35185850 ps
CPU time 0.84 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 200440 kb
Host smart-9b82ab5c-f274-44ff-9922-ef7cafe71259
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264198718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.4264198718
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.2915405514
Short name T422
Test name
Test status
Simulation time 41931568 ps
CPU time 0.75 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:46 PM PDT 24
Peak memory 199668 kb
Host smart-919fcc7a-fa63-4195-8925-d5e9167a166b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915405514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2915405514
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.1048692527
Short name T219
Test name
Test status
Simulation time 40072717 ps
CPU time 0.82 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 200376 kb
Host smart-7b0b1d47-392d-4cff-a315-d4a4f9176666
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048692527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.1048692527
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.3866524526
Short name T729
Test name
Test status
Simulation time 47386711 ps
CPU time 0.94 seconds
Started Jul 28 05:09:44 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 200408 kb
Host smart-ef3f24ff-8dd5-4008-81ee-54045feebb05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866524526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.3866524526
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.4083733518
Short name T645
Test name
Test status
Simulation time 1999003510 ps
CPU time 15.22 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200692 kb
Host smart-c9f85d7f-709a-41c6-9e70-af569b9f2f15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083733518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.4083733518
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.79790938
Short name T720
Test name
Test status
Simulation time 2471922330 ps
CPU time 8.82 seconds
Started Jul 28 05:09:38 PM PDT 24
Finished Jul 28 05:09:46 PM PDT 24
Peak memory 200768 kb
Host smart-766e2520-53ac-49ed-a139-4f91bf10e7db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79790938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_time
out.79790938
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3025892011
Short name T122
Test name
Test status
Simulation time 178747693 ps
CPU time 1.43 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200416 kb
Host smart-1f42f159-45b0-4178-9733-eaac028e0841
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025892011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.3025892011
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.1518656790
Short name T39
Test name
Test status
Simulation time 38577789 ps
CPU time 0.92 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 200420 kb
Host smart-f8a03a7a-3c1f-43af-bca9-369f0c824cda
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518656790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.1518656790
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.1119554650
Short name T227
Test name
Test status
Simulation time 16536898 ps
CPU time 0.74 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200464 kb
Host smart-271dea52-002a-4da5-82a5-d1ad01993ab6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119554650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.1119554650
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.2260945754
Short name T644
Test name
Test status
Simulation time 17118776 ps
CPU time 0.76 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200416 kb
Host smart-527a7164-13dd-4ff4-bfbf-803686a6b93d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260945754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2260945754
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.1351634033
Short name T757
Test name
Test status
Simulation time 561042423 ps
CPU time 3.36 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 200600 kb
Host smart-98bcf4d7-022d-40d7-9f7d-d662d81b640c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351634033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1351634033
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.4018648502
Short name T147
Test name
Test status
Simulation time 112481736 ps
CPU time 1.11 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200352 kb
Host smart-ce5b1e37-8b9c-432f-b846-f004850fef40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018648502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.4018648502
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.4096963681
Short name T738
Test name
Test status
Simulation time 65534420 ps
CPU time 1.31 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:50 PM PDT 24
Peak memory 200540 kb
Host smart-65da6aca-4fa5-43bb-9508-73d00843e3ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096963681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.4096963681
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.3010197989
Short name T815
Test name
Test status
Simulation time 243147336131 ps
CPU time 970.07 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:26:09 PM PDT 24
Peak memory 209132 kb
Host smart-b777cc9d-e843-4fd6-8df1-076c1cbbfe61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3010197989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.3010197989
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.2359170792
Short name T330
Test name
Test status
Simulation time 23187959 ps
CPU time 0.82 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:50 PM PDT 24
Peak memory 200400 kb
Host smart-7832aff8-b021-48eb-b57d-ee8605e1c6fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359170792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2359170792
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.4058007313
Short name T763
Test name
Test status
Simulation time 17381559 ps
CPU time 0.78 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200480 kb
Host smart-e817ef3d-e124-4840-b053-2867b07dbd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058007313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.4058007313
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1629421692
Short name T444
Test name
Test status
Simulation time 245261802 ps
CPU time 1.68 seconds
Started Jul 28 05:09:44 PM PDT 24
Finished Jul 28 05:09:46 PM PDT 24
Peak memory 200456 kb
Host smart-bcfb36b8-c4a2-43be-ae8a-d2dd4f468cde
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629421692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.1629421692
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.2900706709
Short name T366
Test name
Test status
Simulation time 79107461 ps
CPU time 0.85 seconds
Started Jul 28 05:10:02 PM PDT 24
Finished Jul 28 05:10:08 PM PDT 24
Peak memory 199632 kb
Host smart-44ccace1-1386-4ec6-b15f-be7e1de14da9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900706709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2900706709
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.4084290914
Short name T505
Test name
Test status
Simulation time 38721740 ps
CPU time 0.85 seconds
Started Jul 28 05:09:51 PM PDT 24
Finished Jul 28 05:09:52 PM PDT 24
Peak memory 200460 kb
Host smart-2f4b17a6-acd6-4cd5-ba97-eeabe7fd5921
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084290914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.4084290914
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.1685665919
Short name T251
Test name
Test status
Simulation time 61391057 ps
CPU time 0.88 seconds
Started Jul 28 05:09:41 PM PDT 24
Finished Jul 28 05:09:42 PM PDT 24
Peak memory 200424 kb
Host smart-1309762d-793b-4c3a-8852-945ae2cb7e68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685665919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1685665919
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.2527049499
Short name T2
Test name
Test status
Simulation time 1282596985 ps
CPU time 10.08 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 200424 kb
Host smart-461694fe-3ab7-4a21-86fd-a3ec168dbeb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527049499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2527049499
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.2152845417
Short name T336
Test name
Test status
Simulation time 2419736007 ps
CPU time 12.67 seconds
Started Jul 28 05:09:52 PM PDT 24
Finished Jul 28 05:10:04 PM PDT 24
Peak memory 200768 kb
Host smart-3527321a-bbad-4ae2-9ba7-ec535e1753ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152845417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.2152845417
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.2533138228
Short name T524
Test name
Test status
Simulation time 32724294 ps
CPU time 0.77 seconds
Started Jul 28 05:10:05 PM PDT 24
Finished Jul 28 05:10:06 PM PDT 24
Peak memory 200420 kb
Host smart-e4fb38eb-f90a-4b5c-932d-e1505722f91b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533138228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.2533138228
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3731829164
Short name T357
Test name
Test status
Simulation time 33362328 ps
CPU time 0.76 seconds
Started Jul 28 05:09:48 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 200428 kb
Host smart-aa908d75-bc0d-442a-8a29-03c60f41af9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731829164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.3731829164
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.559830736
Short name T755
Test name
Test status
Simulation time 18962085 ps
CPU time 0.78 seconds
Started Jul 28 05:09:54 PM PDT 24
Finished Jul 28 05:09:55 PM PDT 24
Peak memory 200460 kb
Host smart-4bba2fcd-1b42-491b-ae95-097b8551907f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559830736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_ctrl_intersig_mubi.559830736
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.2438341332
Short name T484
Test name
Test status
Simulation time 15152643 ps
CPU time 0.73 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200400 kb
Host smart-2290ded8-d162-442e-87e1-274d0cd9400b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438341332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2438341332
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.316562765
Short name T713
Test name
Test status
Simulation time 148505497 ps
CPU time 1.35 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200364 kb
Host smart-7fed46d6-d867-41cf-8e51-853ccf26311a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316562765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.316562765
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.40386136
Short name T489
Test name
Test status
Simulation time 15995865 ps
CPU time 0.8 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200404 kb
Host smart-a0a4a92b-355f-40e2-8851-51731f2b424f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40386136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.40386136
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.3994893272
Short name T737
Test name
Test status
Simulation time 8956382019 ps
CPU time 31.75 seconds
Started Jul 28 05:09:35 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200848 kb
Host smart-c91f395a-8929-48d9-aa5c-3fa131fa8868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994893272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.3994893272
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.447391990
Short name T68
Test name
Test status
Simulation time 288484637151 ps
CPU time 1023.69 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:27:02 PM PDT 24
Peak memory 217320 kb
Host smart-6d9b9655-28ee-4bf4-96ef-f8f651ef3ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=447391990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.447391990
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.3303209555
Short name T193
Test name
Test status
Simulation time 101416663 ps
CPU time 1.16 seconds
Started Jul 28 05:09:39 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 200408 kb
Host smart-5e72f8d1-62a4-4142-8a26-a88843d09a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303209555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3303209555
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3775210760
Short name T561
Test name
Test status
Simulation time 19063556 ps
CPU time 0.75 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200456 kb
Host smart-d2b9f670-9b81-467b-9aeb-e1bad93141d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775210760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3775210760
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1287106525
Short name T471
Test name
Test status
Simulation time 53509336 ps
CPU time 0.92 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200468 kb
Host smart-d5f8442e-5907-4f98-bdf1-42e2abc2e019
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287106525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1287106525
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.2710622520
Short name T801
Test name
Test status
Simulation time 16063398 ps
CPU time 0.72 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200320 kb
Host smart-183aece1-10dc-4320-971a-6712a3856777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710622520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2710622520
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3818995687
Short name T175
Test name
Test status
Simulation time 140619776 ps
CPU time 1.15 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 200412 kb
Host smart-bf13c1f9-cbfd-4f06-b9bc-cfca4df13562
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818995687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.3818995687
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.2949057051
Short name T615
Test name
Test status
Simulation time 41463722 ps
CPU time 0.92 seconds
Started Jul 28 05:10:09 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200440 kb
Host smart-38de2ee7-f810-4c1c-bb6c-c17790bfb35e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949057051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.2949057051
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.4178723095
Short name T437
Test name
Test status
Simulation time 1175359450 ps
CPU time 5.55 seconds
Started Jul 28 05:09:34 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 200352 kb
Host smart-f32b46b0-fb19-40ee-86ce-58be4edd8972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178723095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.4178723095
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.4066540581
Short name T681
Test name
Test status
Simulation time 1357934099 ps
CPU time 5.97 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:06 PM PDT 24
Peak memory 200524 kb
Host smart-b9ff3235-4269-4f11-ae62-4452ceeb47e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066540581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.4066540581
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.66405126
Short name T520
Test name
Test status
Simulation time 44992501 ps
CPU time 1.03 seconds
Started Jul 28 05:10:11 PM PDT 24
Finished Jul 28 05:10:12 PM PDT 24
Peak memory 200464 kb
Host smart-1e9701be-cacd-477a-8aaf-ed98b9aa5ded
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66405126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
clkmgr_idle_intersig_mubi.66405126
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.2236644032
Short name T115
Test name
Test status
Simulation time 13859077 ps
CPU time 0.71 seconds
Started Jul 28 05:09:51 PM PDT 24
Finished Jul 28 05:09:52 PM PDT 24
Peak memory 200432 kb
Host smart-7b3338e0-0e3b-4034-b18d-ac474ab61a43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236644032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.2236644032
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3808152185
Short name T457
Test name
Test status
Simulation time 28603985 ps
CPU time 0.94 seconds
Started Jul 28 05:09:47 PM PDT 24
Finished Jul 28 05:09:48 PM PDT 24
Peak memory 200460 kb
Host smart-282ef00b-300d-43f3-9038-54cd31230c81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808152185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3808152185
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.3304369101
Short name T593
Test name
Test status
Simulation time 15219654 ps
CPU time 0.72 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:09:59 PM PDT 24
Peak memory 200436 kb
Host smart-8c8f6e22-9983-4c9b-9153-7d9b0b02d376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304369101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3304369101
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.4144937986
Short name T367
Test name
Test status
Simulation time 881988494 ps
CPU time 5.16 seconds
Started Jul 28 05:10:02 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200640 kb
Host smart-6530241d-fb5e-4ee6-90b8-fc96cb61662a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144937986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.4144937986
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.1373585142
Short name T345
Test name
Test status
Simulation time 160154623 ps
CPU time 1.22 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200352 kb
Host smart-a001e2a1-f617-454a-a7ad-9491f9fb9be7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373585142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.1373585142
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.3011791001
Short name T412
Test name
Test status
Simulation time 3948658977 ps
CPU time 23.35 seconds
Started Jul 28 05:09:43 PM PDT 24
Finished Jul 28 05:10:07 PM PDT 24
Peak memory 200740 kb
Host smart-72eaddcf-81ba-48b2-8243-3aca30cbf014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011791001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.3011791001
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.3668254119
Short name T818
Test name
Test status
Simulation time 18347122 ps
CPU time 0.81 seconds
Started Jul 28 05:09:40 PM PDT 24
Finished Jul 28 05:09:41 PM PDT 24
Peak memory 200380 kb
Host smart-29e4ba76-5d70-4d10-887e-8f141f62cb7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668254119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.3668254119
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.2835850724
Short name T392
Test name
Test status
Simulation time 39588952 ps
CPU time 0.79 seconds
Started Jul 28 05:10:04 PM PDT 24
Finished Jul 28 05:10:05 PM PDT 24
Peak memory 200408 kb
Host smart-cbeb517e-c105-4391-bbee-a71c1725879c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835850724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.2835850724
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1179192634
Short name T91
Test name
Test status
Simulation time 29180411 ps
CPU time 0.83 seconds
Started Jul 28 05:09:57 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200536 kb
Host smart-93282d55-71fb-43b1-833b-5f550b1b2125
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179192634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.1179192634
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.3805589616
Short name T675
Test name
Test status
Simulation time 13255938 ps
CPU time 0.72 seconds
Started Jul 28 05:10:28 PM PDT 24
Finished Jul 28 05:10:29 PM PDT 24
Peak memory 199616 kb
Host smart-760c00db-a65b-4a52-928c-5a0d8a8b6dfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805589616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.3805589616
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.3432325036
Short name T425
Test name
Test status
Simulation time 100798639 ps
CPU time 1.11 seconds
Started Jul 28 05:09:56 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200456 kb
Host smart-5964a4a2-d96a-4a1e-aa92-7c1bc01ef3f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432325036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.3432325036
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.4163210886
Short name T404
Test name
Test status
Simulation time 42456738 ps
CPU time 0.87 seconds
Started Jul 28 05:09:55 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 200372 kb
Host smart-6f6b0cc6-f38b-410a-a32f-f57dd093e8fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163210886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.4163210886
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.801814622
Short name T592
Test name
Test status
Simulation time 2482227402 ps
CPU time 19.37 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:18 PM PDT 24
Peak memory 200760 kb
Host smart-1cad4d06-fac5-4fb6-aef1-e79b8ed6a45b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801814622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.801814622
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.538315612
Short name T577
Test name
Test status
Simulation time 1493316312 ps
CPU time 5.68 seconds
Started Jul 28 05:09:45 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200508 kb
Host smart-f7f19526-1c92-4e66-9264-b78ba247a958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538315612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_tim
eout.538315612
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1009794767
Short name T680
Test name
Test status
Simulation time 29378555 ps
CPU time 0.79 seconds
Started Jul 28 05:10:04 PM PDT 24
Finished Jul 28 05:10:10 PM PDT 24
Peak memory 200468 kb
Host smart-22040088-51d5-4d62-9bf0-cbf37c2111eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009794767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1009794767
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.3872866578
Short name T670
Test name
Test status
Simulation time 34262321 ps
CPU time 0.83 seconds
Started Jul 28 05:09:59 PM PDT 24
Finished Jul 28 05:10:00 PM PDT 24
Peak memory 200488 kb
Host smart-652d6fd8-ce75-4633-a036-7afbebbec802
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872866578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.3872866578
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2939229167
Short name T744
Test name
Test status
Simulation time 17570258 ps
CPU time 0.77 seconds
Started Jul 28 05:10:04 PM PDT 24
Finished Jul 28 05:10:05 PM PDT 24
Peak memory 200412 kb
Host smart-2859d667-c02f-44fe-b56f-0c73ce05059b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939229167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.2939229167
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.4222926206
Short name T808
Test name
Test status
Simulation time 29749081 ps
CPU time 0.73 seconds
Started Jul 28 05:10:08 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 200400 kb
Host smart-469b1462-19ea-41fb-a863-7073e42b4163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222926206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.4222926206
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.4213344163
Short name T688
Test name
Test status
Simulation time 1293384328 ps
CPU time 4.55 seconds
Started Jul 28 05:10:13 PM PDT 24
Finished Jul 28 05:10:18 PM PDT 24
Peak memory 200660 kb
Host smart-16a07207-4e19-4500-be3a-8c6af83bf499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213344163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.4213344163
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.2997092224
Short name T817
Test name
Test status
Simulation time 23528462 ps
CPU time 0.85 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200404 kb
Host smart-c4de12b9-a8c0-48de-9b7b-8416d36ba921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997092224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2997092224
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.3232333672
Short name T229
Test name
Test status
Simulation time 5821102591 ps
CPU time 24.61 seconds
Started Jul 28 05:10:12 PM PDT 24
Finished Jul 28 05:10:37 PM PDT 24
Peak memory 200756 kb
Host smart-1abba6d2-59fb-4133-80bb-f8ee33d75c53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232333672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.3232333672
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.4134586621
Short name T387
Test name
Test status
Simulation time 54990373 ps
CPU time 0.92 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200472 kb
Host smart-d99a193e-5260-458b-8cff-10701ead4a52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134586621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.4134586621
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.3791308381
Short name T220
Test name
Test status
Simulation time 14486854 ps
CPU time 0.79 seconds
Started Jul 28 05:09:52 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 200428 kb
Host smart-b33385c6-8ecd-439b-8071-23622671157b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791308381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.3791308381
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2180056858
Short name T481
Test name
Test status
Simulation time 25136413 ps
CPU time 0.94 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:54 PM PDT 24
Peak memory 200432 kb
Host smart-4afb77f9-0aab-4677-afdd-4ddb4a8762f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180056858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.2180056858
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.1335427099
Short name T454
Test name
Test status
Simulation time 150717573 ps
CPU time 1.03 seconds
Started Jul 28 05:09:47 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 199632 kb
Host smart-30d9f835-5a4e-43e3-b618-4c1d229e8825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335427099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1335427099
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.1225892851
Short name T290
Test name
Test status
Simulation time 22325029 ps
CPU time 0.75 seconds
Started Jul 28 05:09:58 PM PDT 24
Finished Jul 28 05:09:59 PM PDT 24
Peak memory 200412 kb
Host smart-cd3380f9-143c-4d96-8012-00b61961dde3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225892851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.1225892851
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1382174290
Short name T467
Test name
Test status
Simulation time 24417365 ps
CPU time 0.77 seconds
Started Jul 28 05:09:57 PM PDT 24
Finished Jul 28 05:09:58 PM PDT 24
Peak memory 200408 kb
Host smart-f46208a4-539a-4918-bba3-6ae9d758cc57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382174290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1382174290
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.1969433089
Short name T533
Test name
Test status
Simulation time 2244393764 ps
CPU time 12.57 seconds
Started Jul 28 05:09:52 PM PDT 24
Finished Jul 28 05:10:04 PM PDT 24
Peak memory 200712 kb
Host smart-ad5ba58e-3366-4464-961c-4daad56210d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969433089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1969433089
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.1878372498
Short name T618
Test name
Test status
Simulation time 2413310339 ps
CPU time 10.12 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:10:03 PM PDT 24
Peak memory 200768 kb
Host smart-9b5ef9fa-1071-41b8-8a3a-8d3db56d58aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878372498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.1878372498
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.2014247451
Short name T666
Test name
Test status
Simulation time 55338849 ps
CPU time 0.89 seconds
Started Jul 28 05:10:00 PM PDT 24
Finished Jul 28 05:10:01 PM PDT 24
Peak memory 200468 kb
Host smart-99ea7a1f-0a92-4b6c-82cb-346aee15d835
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014247451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.2014247451
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1283772011
Short name T816
Test name
Test status
Simulation time 16443895 ps
CPU time 0.79 seconds
Started Jul 28 05:10:23 PM PDT 24
Finished Jul 28 05:10:23 PM PDT 24
Peak memory 200464 kb
Host smart-2f432869-6884-4fe4-ae4e-1e9d2a5a0a79
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283772011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1283772011
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.2285964787
Short name T629
Test name
Test status
Simulation time 52106216 ps
CPU time 0.96 seconds
Started Jul 28 05:09:50 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 200424 kb
Host smart-497f29bf-9daf-4140-aed6-3e4212d669cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285964787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.2285964787
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.2533426463
Short name T226
Test name
Test status
Simulation time 17207431 ps
CPU time 0.76 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:02 PM PDT 24
Peak memory 200368 kb
Host smart-e3307824-e20c-4adb-9f7f-657808cd6fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533426463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2533426463
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1694793431
Short name T477
Test name
Test status
Simulation time 1124136572 ps
CPU time 4.34 seconds
Started Jul 28 05:09:52 PM PDT 24
Finished Jul 28 05:09:56 PM PDT 24
Peak memory 200624 kb
Host smart-e82bb8ea-6011-423b-b9d6-09fb42e27ed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694793431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1694793431
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.1981105667
Short name T669
Test name
Test status
Simulation time 16532714 ps
CPU time 0.79 seconds
Started Jul 28 05:09:53 PM PDT 24
Finished Jul 28 05:09:53 PM PDT 24
Peak memory 200424 kb
Host smart-865d8b84-02a0-4e03-b60a-ef7f7e8371eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981105667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1981105667
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.2681091404
Short name T503
Test name
Test status
Simulation time 2297614226 ps
CPU time 18.32 seconds
Started Jul 28 05:10:01 PM PDT 24
Finished Jul 28 05:10:25 PM PDT 24
Peak memory 200820 kb
Host smart-6bfef809-68d3-497e-946a-f0d6fcde0c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681091404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.2681091404
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_trans.4070362583
Short name T684
Test name
Test status
Simulation time 59779524 ps
CPU time 1.04 seconds
Started Jul 28 05:09:51 PM PDT 24
Finished Jul 28 05:09:57 PM PDT 24
Peak memory 200420 kb
Host smart-2ed916c2-b4b7-4948-81dc-8bc8ee1fdd7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070362583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.4070362583
Directory /workspace/9.clkmgr_trans/latest
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