Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 181003886 1 T6 1574 T7 1940 T8 2748
auto[1] 300544 1 T25 120 T26 730 T27 160


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 181004748 1 T6 1574 T7 1940 T8 2748
auto[1] 299682 1 T25 148 T26 678 T27 616


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 180933190 1 T6 1574 T7 1940 T8 2748
auto[1] 371240 1 T25 208 T26 626 T27 578


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 174178468 1 T6 1574 T7 1940 T8 2748
auto[1] 7125962 1 T25 3360 T26 150 T27 4224


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 121665632 1 T6 1574 T7 50 T8 2748
auto[1] 59638798 1 T7 1890 T25 2610 T5 22


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 116059816 1 T6 1574 T7 50 T8 2748
auto[0] auto[0] auto[0] auto[0] auto[1] 57859150 1 T7 1890 T25 78 T5 22
auto[0] auto[0] auto[0] auto[1] auto[0] 22966 1 T26 46 T38 30 T1 50
auto[0] auto[0] auto[0] auto[1] auto[1] 6112 1 T26 2 T38 26 T23 20
auto[0] auto[0] auto[1] auto[0] auto[0] 5167664 1 T25 652 T26 76 T27 3316
auto[0] auto[0] auto[1] auto[0] auto[1] 1695920 1 T25 2484 T27 266 T120 144
auto[0] auto[0] auto[1] auto[1] auto[0] 35678 1 T26 26 T27 18 T38 32
auto[0] auto[0] auto[1] auto[1] auto[1] 9244 1 T3 48 T149 66 T16 110
auto[0] auto[1] auto[0] auto[0] auto[0] 33604 1 T26 28 T27 70 T38 48
auto[0] auto[1] auto[0] auto[0] auto[1] 896 1 T119 18 T121 8 T150 42
auto[0] auto[1] auto[0] auto[1] auto[0] 9098 1 T26 98 T38 76 T122 56
auto[0] auto[1] auto[0] auto[1] auto[1] 1858 1 T32 58 T168 76 T94 72
auto[0] auto[1] auto[1] auto[0] auto[0] 9026 1 T25 32 T26 2 T27 76
auto[0] auto[1] auto[1] auto[0] auto[1] 2588 1 T25 8 T149 2 T13 28
auto[0] auto[1] auto[1] auto[1] auto[0] 15818 1 T26 46 T27 78 T33 44
auto[0] auto[1] auto[1] auto[1] auto[1] 3752 1 T149 82 T17 96 T31 90
auto[1] auto[0] auto[0] auto[0] auto[0] 40596 1 T25 8 T26 36 T27 38
auto[1] auto[0] auto[0] auto[0] auto[1] 3758 1 T38 44 T1 8 T23 2
auto[1] auto[0] auto[0] auto[1] auto[0] 24504 1 T26 86 T38 98 T33 50
auto[1] auto[0] auto[0] auto[1] auto[1] 5762 1 T38 74 T1 60 T23 54
auto[1] auto[0] auto[1] auto[0] auto[0] 22852 1 T25 24 T27 68 T38 26
auto[1] auto[0] auto[1] auto[0] auto[1] 4032 1 T25 8 T27 80 T121 16
auto[1] auto[0] auto[1] auto[1] auto[0] 38488 1 T25 60 T38 44 T22 84
auto[1] auto[0] auto[1] auto[1] auto[1] 8206 1 T3 38 T17 288 T31 68
auto[1] auto[1] auto[0] auto[0] auto[0] 59062 1 T25 8 T26 58 T27 70
auto[1] auto[1] auto[0] auto[0] auto[1] 4140 1 T25 8 T26 20 T38 4
auto[1] auto[1] auto[0] auto[1] auto[0] 36482 1 T26 336 T38 68 T122 78
auto[1] auto[1] auto[0] auto[1] auto[1] 10664 1 T26 90 T38 68 T121 56
auto[1] auto[1] auto[1] auto[0] auto[0] 32698 1 T25 8 T27 196 T38 2
auto[1] auto[1] auto[1] auto[0] auto[1] 8084 1 T25 24 T27 62 T120 42
auto[1] auto[1] auto[1] auto[1] auto[0] 57280 1 T25 60 T27 64 T38 56
auto[1] auto[1] auto[1] auto[1] auto[1] 14632 1 T121 64 T3 54 T13 184

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